A semiconductor device structure and a method for manufacturing the same

Abstract

The present invention provides a semiconductor device structure and a method for preparing the same, wherein a composite passivation layer is formed on a semiconductor layer including an aluminum-containing barrier layer, wherein the composite passivation layer includes a first passivation layer and a second passivation layer. The first passivation layer is patterned to form an opening exposing the aluminum-containing barrier layer, and the second passivation layer covers the first passivation layer and fills the opening. One of the first passivation layer and the second passivation layer includes aluminum elements, and the other includes silicon elements, and the gate electrode is formed in the area where the passivation layer including silicon elements is in direct contact with the aluminum-containing barrier layer. The design of this composite passivation layer effectively reduces dangling bonds and surface states on the surface of the aluminum-containing barrier layer, thereby achieving efficient passivation of the semiconductor device structure. At the same time, it effectively avoids damage to the aluminum-containing barrier layer during the subsequent preparation of gate electrode through holes and source contact holes, significantly reduces the risk of leakage, and improves the electrical performance and reliability of the semiconductor device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to a semiconductor device structure and a preparation method thereof. Background Art

[0002] With the development of semiconductor technology, GaN (gallium nitride)-based HEMTs (High Electron Mobility Transistors) have shown great potential in high-frequency, high-power applications due to their high electron mobility, high breakdown voltage, and good thermal stability. However, the growth process of GaN materials inevitably introduces a large number of dislocations and defects. These defects not only affect device performance but also lead to gate electrode leakage, which in turn causes current collapse, limiting the application of GaN HEMTs in high-performance electronic devices.

[0003] Gate leakage is primarily caused by charge recombination on the GaN material surface. These surface states interact with the gate electrode, causing current to flow in unintended paths beyond the control of the gate voltage. This phenomenon is known as gate leakage. Gate leakage not only reduces device switching speed but also increases power consumption, impacting overall device performance and reliability. To address this issue, researchers have explored various approaches, including using dielectric materials such as Al2O3, Si3N4, and SiO2 as passivation layers to mitigate the impact of surface states and suppress gate leakage. While these dielectric passivation layers have made some progress in reducing gate leakage, existing solutions still have limitations. The dielectric layer fabrication process requires precise control to ensure uniformity and integrity; any non-uniformity or defects can lead to leakage. Mismatched interface properties can lead to the formation of charge traps, compromising passivation effectiveness and further exacerbating leakage. Furthermore, the chemical and thermal stability of the dielectric layer are key factors affecting its long-term performance.

[0004] Therefore, how to enhance the passivation effect while reducing gate electrode leakage, thereby improving the performance and reliability of GaN HEMT, has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device structure and a method for manufacturing the same, so as to solve the problems of gate electrode leakage and insufficient passivation layer performance in GaN HEMT in the prior art.

[0007] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a semiconductor device structure, comprising the following steps:

[0008] providing a semiconductor layer, the semiconductor layer including an aluminum-containing barrier layer;

[0009] forming a composite passivation layer above the semiconductor layer, the composite passivation layer comprising a first passivation layer and a second passivation layer formed sequentially, the first passivation layer being patterned to form an opening exposing the aluminum-containing barrier layer, the second passivation layer covering the patterned first passivation layer and filling the opening, one of the first passivation layer and the second passivation layer comprising aluminum and the other comprising silicon;

[0010] forming a source electrode and a drain electrode spaced apart from each other, wherein the source electrode and the drain electrode both vertically penetrate the composite passivation layer;

[0011] forming a first dielectric layer above the composite passivation layer;

[0012] forming a gate electrode through-hole, the gate electrode through-hole vertically penetrating the first dielectric layer and the composite passivation layer, the gate electrode through-hole being formed in a region where the passivation layer including silicon elements directly contacts the aluminum-containing barrier layer;

[0013] A gate electrode is formed, wherein the gate electrode at least fills the gate electrode through hole.

[0014] Optionally, the first passivation layer includes aluminum, the second passivation layer includes silicon, and the gate electrode through hole is located in the area where the opening is located.

[0015] Optionally, both the source electrode and the drain electrode avoid the opening area, or the source electrode is located in the area where the opening is located, and the drain electrode avoids the opening area.

[0016] Optionally, the first passivation layer includes silicon, the second passivation layer includes aluminum, and the gate electrode through hole avoids the area where the opening is located.

[0017] Optionally, the source electrode and the drain electrode are both located in the opening area, or the source electrode avoids the area where the opening is located, and the drain electrode is located in the opening area.

[0018] Optionally, the composite passivation layer further includes a third passivation layer, and the third passivation layer covers the second passivation layer.

[0019] Optionally, the method further includes the following steps:

[0020] forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the gate electrode;

[0021] patterning the second dielectric layer to form a through-hole structure, wherein the through-hole structure exposes the tops of the source electrode, the drain electrode, and the gate electrode;

[0022] forming an interconnection metal layer, wherein the interconnection metal layer covers the second dielectric layer and fills the through-hole structure;

[0023] The interconnect metal layer is patterned to form a lead structure.

[0024] Optionally, the semiconductor layer further includes a substrate, a buffer layer, and a channel layer stacked sequentially from bottom to top and located below the aluminum-containing barrier layer, and a side of the channel layer facing the aluminum-containing barrier layer has a two-dimensional electron gas.

[0025] Optionally, a material of one of the first passivation layer and the second passivation layer includes at least one of aluminum nitride, aluminum oxide, and aluminum oxide nitride, and a material of the other one includes at least one of silicon nitride and silicon dioxide.

[0026] The present invention also provides a semiconductor device structure, comprising:

[0027] a semiconductor layer, the semiconductor layer including an aluminum-containing barrier layer;

[0028] a composite passivation layer located above the semiconductor layer, the composite passivation layer comprising a first passivation layer and a second passivation layer formed sequentially, the first passivation layer being patterned to form an opening exposing the aluminum-containing barrier layer, the second passivation layer covering the patterned first passivation layer and filling the opening, one of the first passivation layer and the second passivation layer comprising aluminum, and the other comprising silicon;

[0029] a source electrode and a drain electrode, wherein the source electrode and the drain electrode are spaced apart from each other and both the source electrode and the drain electrode vertically penetrate the composite passivation layer;

[0030] a first dielectric layer, located above the composite passivation layer;

[0031] A gate electrode vertically penetrates the first dielectric layer and the composite passivation layer, and is located in a region where the passivation layer including silicon elements directly contacts the aluminum-containing barrier layer.

[0032] As described above, the semiconductor device structure and preparation method of the present invention are formed by forming a composite passivation layer on a semiconductor layer including an aluminum-containing barrier layer, wherein the composite passivation layer includes a first passivation layer and a second passivation layer. The first passivation layer is patterned to form an opening that exposes the aluminum-containing barrier layer, and the second passivation layer covers the first passivation layer and fills the opening. One of the first passivation layer and the second passivation layer includes aluminum elements, and the other includes silicon elements, and the gate electrode is formed in the area where the passivation layer including silicon elements is in direct contact with the aluminum-containing barrier layer. The design of this composite passivation layer effectively reduces the dangling bonds and surface states on the surface of the aluminum-containing barrier layer, thereby achieving efficient passivation of the semiconductor device structure. At the same time, it effectively avoids damage to the aluminum-containing barrier layer during the subsequent preparation of the gate electrode through hole and the source contact hole, significantly reduces the risk of leakage, and improves the electrical performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shown is a flowchart of the steps of the method for preparing the semiconductor device structure of the present invention.

[0034] Figure 2 It is a schematic cross-sectional view of a structure obtained after executing step S1 in the method for preparing a semiconductor device structure of the present invention.

[0035] Figure 3 It is a schematic cross-sectional view of a structure obtained after executing step S2 in the method for preparing a semiconductor device structure of the present invention.

[0036] Figure 4 It is a cross-sectional schematic diagram of the structure obtained after forming the source contact hole and the drain contact hole in the method for manufacturing the semiconductor device structure of the present invention in Example 1.

[0037] Figure 5 FIG. 1 is a schematic cross-sectional view of a structure obtained after executing step S3 in the method for manufacturing a semiconductor device structure of the present invention in Example 1. FIG.

[0038] Figure 6 FIG. 1 is a schematic cross-sectional view of a structure obtained after executing step S4 in the method for manufacturing a semiconductor device structure of the present invention in Example 1. FIG.

[0039] Figure 7 FIG. 1 is a schematic cross-sectional view of a structure obtained after executing step S5 in the method for manufacturing a semiconductor device structure of the present invention in the first embodiment.

[0040] Figure 8 FIG. 1 is a schematic cross-sectional view of a structure obtained after executing step S6 in the method for manufacturing a semiconductor device structure of the present invention in the first embodiment.

[0041] Figure 9It is a cross-sectional schematic diagram of the structure obtained after forming the second dielectric layer in the method for preparing the semiconductor device structure of the present invention in Example 1.

[0042] Figure 10 It is a schematic cross-sectional view of a structure obtained after forming a through-hole structure in the method for preparing a semiconductor device structure of the present invention in Example 1.

[0043] Figure 11 It is a cross-sectional schematic diagram of the structure obtained after forming the interconnection metal layer in the method for preparing the semiconductor device structure of the present invention in Example 1.

[0044] Figure 12 It is a cross-sectional schematic diagram of the structure obtained after forming the lead structure in the method for preparing the semiconductor device structure of the present invention in Example 1.

[0045] Figure 13 It is a cross-sectional schematic diagram of the structure obtained after forming the gate electrode through hole in the method for manufacturing the semiconductor device structure of the present invention in Example 2.

[0046] Figure 14 It is a cross-sectional schematic diagram of the structure obtained after forming the lead structure in the method for preparing the semiconductor device structure of the present invention in Example 2.

[0047] Component number description

[0048] 10 Semiconductor layer

[0049] 101 substrate

[0050] 102 buffer layer

[0051] 103 channel layer

[0052] 104 Aluminum-containing barrier layer

[0053] 11 Composite passivation layer

[0054] 111 First passivation layer

[0055] 112 second passivation layer

[0056] 113 Third passivation layer

[0057] 114 Opening

[0058] 12 Source electrode

[0059] 121 Source contact hole

[0060] 13 Drain electrode

[0061] 131 drain contact hole

[0062] 14. First dielectric layer

[0063] 15 Gate electrode through hole

[0064] 16 Gate electrode

[0065] 17 Second dielectric layer

[0066] 18 through-hole structure

[0067] 19 Interconnect Metal Layer

[0068] 20 lead structure

[0069] 201 gate lead

[0070] 202 source lead

[0071] 203 drain lead

[0072] Steps S1 to S6 DETAILED DESCRIPTION

[0073] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0074] See also Figures 1 to 14 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0075] Example 1

[0076] This embodiment provides a method for preparing a semiconductor device structure. Figure 1 , which is a flow chart showing the steps of the preparation method, comprising the following steps:

[0077] S1: providing a semiconductor layer, wherein the semiconductor layer includes an aluminum-containing barrier layer;

[0078] S2: forming a composite passivation layer on the semiconductor layer, the composite passivation layer comprising a first passivation layer and a second passivation layer formed sequentially, the first passivation layer being patterned to form an opening exposing the aluminum-containing barrier layer, the second passivation layer covering the patterned first passivation layer and filling the opening, one of the first passivation layer and the second passivation layer comprising aluminum, and the other comprising silicon;

[0079] S3: forming a source electrode and a drain electrode spaced apart from each other, wherein the source electrode and the drain electrode both vertically penetrate the composite passivation layer;

[0080] S4: forming a first dielectric layer above the composite passivation layer;

[0081] S5: forming a gate electrode through-hole, wherein the gate electrode through-hole vertically penetrates the first dielectric layer and the composite passivation layer, and the gate electrode through-hole is formed in a region where the passivation layer including silicon elements directly contacts the aluminum-containing barrier layer;

[0082] S6: forming a gate electrode, wherein the gate electrode at least fills the gate electrode through hole.

[0083] The above steps are described in detail below with reference to the structural diagram.

[0084] First see Figure 2 , performing the step S1: providing a semiconductor layer 10 , wherein the semiconductor layer 10 includes an aluminum-containing barrier layer 104 .

[0085] As an example, the semiconductor layer 10 further includes a substrate 101, a buffer layer 102, and a channel layer 103 stacked sequentially from bottom to top, located below the aluminum-containing barrier layer 104. The channel layer 103 has a two-dimensional electron gas on the side facing the aluminum-containing barrier layer 104. That is, the fabrication method of this embodiment is applied to the fabrication of HEMT devices. However, in other embodiments, this fabrication method can also be applied to the fabrication of other device structures requiring improved gate electrode leakage and device structures requiring improved passivation layer performance.

[0086] As an example, the substrate 101 includes any one of a silicon-based substrate, a silicon carbide substrate, a gallium nitride substrate, and a sapphire substrate; the buffer layer 102 includes at least one of an AlGaN buffer layer and a GaN buffer layer; and the channel layer 103 includes at least one of a GaN layer and a GaAs layer. The buffer layer 102 is used to reduce lattice mismatch generated when the channel layer 103 is directly epitaxially grown on the substrate 101. The buffer layer 102 helps reduce crystal defects such as dislocations, improves the film quality of the channel layer 103, and enhances device performance.

[0087] As an example, the aluminum-containing barrier layer 104 includes at least one of an AlGaN layer, an AlN layer, an InAlGaN layer, and an InAlN layer. In this embodiment, the aluminum-containing barrier layer 104 is preferably an AlGaN layer. By adjusting the molar percentage of aluminum in the aluminum-containing barrier layer 104, the interface characteristics between the aluminum-containing barrier layer 104 and the channel layer 103 can be optimized, effectively regulating the two-dimensional electron gas density in the channel layer 103, and improving the breakdown voltage and overall performance of the device.

[0088] See also Figure 3 , perform the step S2: forming a composite passivation layer 11 above the semiconductor layer 10, the composite passivation layer 11 includes a first passivation layer 111 and a second passivation layer 112 formed successively, the first passivation layer 111 is patterned to form an opening 114 exposing the aluminum-containing barrier layer 104, the second passivation layer 112 covers the patterned first passivation layer 111 and fills the opening 114, one of the first passivation layer 111 and the second passivation layer 112 includes aluminum element, and the other includes silicon element.

[0089] Specifically, this embodiment uses atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or other suitable methods to form the first passivation layer 111, and then uses a photolithography-etching process to pattern the first passivation layer 111 to form the opening 114, and then uses ALD, LPCVD, PECVD or other suitable methods to form the second passivation layer 112.

[0090] As an example, a material of one of the first passivation layer 111 and the second passivation layer 112 includes at least one of aluminum nitride, aluminum oxide, and aluminum oxide nitride, and a material of the other includes at least one of silicon nitride and silicon dioxide.

[0091] See also Figure 4 and Figure 5 , performing the step S3: forming a source electrode 12 and a drain electrode 13 that are spaced apart, wherein the source electrode 12 and the drain electrode 13 both vertically penetrate the composite passivation layer 11 .

[0092] Specifically, forming the source electrode 12 and the drain electrode 13 includes the following steps:

[0093] (1) Figure 4 As shown, the composite passivation layer 11 is patterned by a photolithography-etching process to form a source contact hole 121 and a drain contact hole 131 vertically penetrating the composite passivation layer 11 .

[0094] (2) forming a contact metal layer on the composite passivation layer 11, wherein the contact metal layer covers and fills the source contact hole 121 and the drain contact hole 131 (not shown);

[0095] (3) Figure 5 As shown, the contact metal layer is planarized to form the source electrode 12 and the drain electrode 13 .

[0096] Specifically, the depths of the source contact hole 121 and the drain contact hole 131 can be set according to specific performance requirements of the device.

[0097] In some embodiments, the source contact hole 121 and the drain contact hole 131 penetrate the composite passivation layer 11, and the bottoms of the source electrode 12 and the drain electrode 13 are both in contact and electrically connected to the aluminum-containing barrier layer 104. This structure helps reduce contact resistance and promotes current flow from the source to the drain, making it suitable for semiconductor devices that require high current density and low power consumption.

[0098] In other embodiments, the source contact hole 121 and the drain contact hole 131 penetrate the composite passivation layer 11 and extend into the aluminum-containing barrier layer 104 or the channel layer 103. The bottom of the source electrode 12 and the bottom of the drain electrode 13 are in electrical contact with the aluminum-containing barrier layer 104 or the channel layer 103. This structure is suitable for applications with specific requirements for increasing threshold voltage or reducing on-resistance, such as high-power or high-frequency HEMT devices.

[0099] This embodiment is described by taking as an example that the source contact hole 121 and the drain contact hole 131 penetrate the composite passivation layer 11, and the bottom of the source electrode 12 and the bottom of the drain electrode 13 are in contact and electrically connected to the aluminum-containing barrier layer 104. However, the connection between the source electrode 12 and the drain electrode 13 and the specific layer in the semiconductor layer 10 can be flexibly adjusted according to different device performance requirements, and is not limited to this.

[0100] See also Figure 6 , performing step S4: forming a first dielectric layer 14 on the composite passivation layer 11 .

[0101] Specifically, the material of the first dielectric layer 14 includes at least one of silicon nitride and silicon dioxide, and the method of forming the first dielectric layer 14 includes ALD, LPCVD, PECVD or other appropriate methods.

[0102] See also Figure 7, perform the step S5: form a gate electrode through hole 15, the gate electrode through hole 15 vertically penetrates the first dielectric layer 14 and the composite passivation layer 11, and the gate electrode through hole 15 is formed in the area where the passivation layer including silicon elements directly contacts the aluminum-containing barrier layer 104.

[0103] As an example, the first passivation layer 111 includes aluminum, the second passivation layer 112 includes silicon, and the gate electrode through hole 15 is located in the area where the opening 114 is located.

[0104] Specifically, in this embodiment, the first passivation layer 111 is formed using atomic layer deposition, and the second passivation layer 112 is formed using PECVD. The first passivation layer 111 is preferably an AlN layer, and the second passivation layer 112 is preferably a Si3N4 layer. The lattice matching between the first passivation layer 111 and the aluminum-containing barrier layer 104 effectively reduces the interface state density and increases the breakdown voltage of the device. The second passivation layer 112 provides further protection and electrical isolation for the device, effectively enhancing its reliability and durability.

[0105] Specifically, the gate electrode through hole 15 is formed in the area where the second passivation layer 112 is in direct contact with the aluminum-containing barrier layer 104, and the gate electrode through hole 15 vertically penetrates the first dielectric layer 14 and the second passivation layer 112. In the process of forming the gate electrode through hole 15 using a dry etching process, this embodiment uses a fluorine-based gas (such as carbon tetrafluoride CF4 or hexafluoroethane C2F6) for plasma etching. These gases have high reactivity with the silicon element in the first dielectric layer 14 and the second passivation layer 112, but have extremely low reactivity with the aluminum-containing barrier layer 104. This difference in chemical properties ensures high selectivity of etching. By combining precisely controlled etching conditions, etching can be stopped precisely when contacting the aluminum-containing barrier layer 104, avoiding unnecessary damage to the aluminum-containing barrier layer 104, reducing the risk of current leakage, and ensuring the precise formation of the gate electrode through hole 15, thereby improving the overall performance of the device.

[0106] See also Figure 8 , performing step S6: forming a gate electrode 16 , wherein the gate electrode 16 at least fills the gate electrode through hole 15 .

[0107] As an example, the gate electrode 16 forms a Schottky contact with the aluminum-containing barrier layer 104 .

[0108] As an example, both the source electrode 12 and the drain electrode 13 avoid the opening 114 area (not shown), or the source electrode 12 is located in the area where the opening 114 is located, and the drain electrode 13 avoids the opening 114 area.

[0109] Specifically, in this embodiment, the source electrode 12 is preferably located in the region where the opening 114 is located, and the source electrode 12 and the gate electrode 16 are spaced apart within the same region. When the source contact hole 121 is formed using a dry etching process, the structural design of the composite passivation layer 11 can also avoid damage or defects to the aluminum-containing barrier layer 104, effectively reducing the risk of leakage and ensuring efficient electrical connection between the source electrode 12 and the aluminum-containing barrier layer 104.

[0110] As an example, see Figures 9-14 After forming the gate electrode 16, the following steps are further included:

[0111] (1) Figure 9 As shown, a second dielectric layer 17 is formed on the first dielectric layer 14 by using ALD, LPCVD, PECVD or other suitable methods, and the second dielectric layer 17 covers the gate electrode 16;

[0112] (2) Figure 10 As shown, the second dielectric layer 17 is patterned by a photolithography-etching process to form a through-hole structure 18 , wherein the through-hole structure 18 exposes the tops of the source electrode 12 , the drain electrode 13 and the gate electrode 16 ;

[0113] (3) Figure 11 As shown, an interconnection metal layer 19 is formed by sputtering, evaporation or other suitable methods, and the interconnection metal layer 19 covers the second dielectric layer 17 and fills the through-hole structure 18;

[0114] (4) Figure 12 As shown, the interconnect metal layer 19 is patterned by a photolithography-etching process to form a lead structure 20, and the lead structure 20 includes a gate lead 201 connected to the gate electrode 16, a source lead 202 connected to the source electrode 12, and a drain lead 203 connected to the drain electrode 13. The lead structure 20 is used to lead out the gate electrode 16, the source electrode 12 and the drain electrode 13.

[0115] In the method for fabricating the semiconductor device structure of this embodiment, a composite passivation layer is formed on a semiconductor layer including an aluminum-containing barrier layer, significantly optimizing device performance. The composite passivation layer comprises a first aluminum-containing passivation layer and a second silicon-containing passivation layer, formed sequentially. The first passivation layer is patterned to form an opening that exposes the aluminum-containing barrier layer; the second passivation layer covers the first passivation layer and the opening, forming a continuous protective layer. This composite passivation layer design not only effectively reduces dangling bonds and surface states on the surface of the aluminum-containing barrier layer, but also achieves efficient passivation of the semiconductor device structure. Furthermore, the composite passivation layer of this embodiment can effectively prevent damage to the aluminum-containing barrier layer during the subsequent fabrication of gate electrode vias and source contact holes, thereby effectively reducing the risk of leakage caused by damage or defects at the interface between the aluminum-containing barrier layer and the gate and source electrodes, and effectively suppressing the current collapse effect. The composite passivation layer of this embodiment not only enhances the electrical isolation performance of the device but also ensures the long-term stability and reliability of the device under high-frequency and high-power conditions.

[0116] Example 2

[0117] The present embodiment provides a method for preparing a semiconductor device structure. The preparation method of this embodiment adopts basically the same technical solution as the preparation method of Example 1, and the main difference is that the first passivation layer 111 formed in Example 1 includes aluminum elements, and the second passivation layer 112 includes silicon elements. The first passivation layer 111 formed in this embodiment includes silicon elements, and the second passivation layer 112 includes aluminum elements. More specifically, in this embodiment, the first passivation layer 111 is formed by a PECVD method, and the first passivation layer 111 is patterned by a photolithography-etching process to form an opening 114 that exposes the aluminum-containing barrier layer 104, and then the second passivation layer 112 is formed by an atomic layer deposition method. Among them, the first passivation layer 111 is preferably a Si3N4 layer, and the second passivation layer 112 is preferably an AlN layer.

[0118] As an example, see Figure 13 , which is a schematic cross-sectional view of the structure obtained after the gate electrode through hole 15 is formed in this embodiment, wherein the first passivation layer 111 includes silicon elements, the second passivation layer 112 includes aluminum elements, and the gate electrode through hole 15 avoids the area where the opening 114 is located.

[0119] As an example, the composite passivation layer 11 further includes a third passivation layer 113, which covers the second passivation layer 112. The third passivation layer 113 can be formed by ALD, LPCVD, PECVD, or other suitable methods. The material of the third passivation layer 113 includes at least one of aluminum nitride, aluminum oxide, aluminum oxide nitride, silicon nitride, and silicon dioxide. In this embodiment, the third passivation layer 113 is formed by PECVD, and the third passivation layer 113 is preferably a Si3N4 layer.

[0120] Specifically, in this embodiment, the gate electrode through hole 15 is formed in the region where the first passivation layer 111 directly contacts the aluminum-containing barrier layer 104. During the dry etching process to form the gate electrode through hole 15, the etching sequentially penetrates the first dielectric layer 14, the third passivation layer 113, the second passivation layer 112, and the first passivation layer 111. More specifically, in this embodiment, a fluorine-based etching gas (such as CF4 or C2F6) is used to etch the first passivation layer 111. These etching gases react with the first passivation layer 111 to achieve efficient etching. However, when the etching gas contacts the aluminum-containing barrier layer 104, an etching reaction hardly occurs. This selective etching characteristic enables the etching process to automatically stop after penetrating the first passivation layer 111, thereby avoiding damage to the aluminum-containing barrier layer 104, ensuring the integrity of the contact interface between the aluminum-containing barrier layer 104 and the first passivation layer 111, and effectively preventing current leakage or other performance degradation problems caused by damage to the aluminum-containing barrier layer 104, thereby improving the performance and reliability of the semiconductor device.

[0121] As an example, the source electrode 12 and the drain electrode 13 are both located in the opening 114 area (not shown), or the source electrode 12 avoids the area where the opening 114 is located, and the drain electrode 13 is located in the opening 114 area.

[0122] Specifically, the source electrode 12 preferably avoids the area where the opening 114 is located, and the source electrode 12 and the gate electrode through hole 15 are spaced apart and arranged in the same area. The structural design of the composite passivation layer 11 in this embodiment can also avoid damage or defects to the aluminum-containing barrier layer 104 when using a dry etching process to form a contact hole to fill the source electrode 12, ensuring that the source electrode 12 and the aluminum-containing barrier layer 104 are efficiently electrically connected.

[0123] As an example, see Figure 14 , which is a schematic cross-sectional view of the structure obtained after forming the lead structure 20 in this embodiment. In this embodiment, the preparation methods of other structural layers are the same as those in the first embodiment. For details, please refer to the introduction of the first embodiment, which will not be repeated for the purpose of brevity.

[0124] In the preparation method of the semiconductor device structure of the present embodiment, a composite passivation layer is formed on the semiconductor layer including the aluminum-containing barrier layer, thereby achieving significant optimization of the device performance. The composite passivation layer includes a first silicon-containing and patterned passivation layer, a second aluminum-containing passivation layer, and a third passivation layer formed in sequence. The design of this composite passivation layer not only effectively reduces the dangling bonds and surface states on the surface of the aluminum-containing barrier layer, but also effectively suppresses the current collapse effect, thereby achieving efficient passivation of the semiconductor device structure. Furthermore, the composite passivation layer of the present embodiment can effectively avoid damage to the aluminum-containing barrier layer during the subsequent preparation of the gate electrode through hole and the source contact hole, thereby effectively reducing the risk of leakage caused by defects in the interface between the aluminum-containing barrier layer and the gate electrode and the source electrode. The composite passivation layer of the present embodiment not only enhances the electrical isolation performance of the device, but also ensures the long-term stability and reliability of the device under high frequency and high power conditions.

[0125] Example 3

[0126] This embodiment provides a semiconductor device structure. Figure 12 The semiconductor device structure can be obtained by the preparation method described in the first embodiment or other suitable preparation methods. The semiconductor device structure includes a semiconductor layer 10, a composite passivation layer 11, a source electrode 12, a drain electrode 13, a first dielectric layer 14 and a gate electrode 16, wherein the semiconductor layer 10 includes an aluminum-containing barrier layer 104; the composite passivation layer 11 is located above the semiconductor layer 10, and the composite passivation layer 11 includes a first passivation layer 111 and a second passivation layer 112 formed successively, the first passivation layer 111 is patterned to form an opening 114 exposing the aluminum-containing barrier layer 104, and the second passivation layer 112 is patterned to form an opening 114 exposing the aluminum-containing barrier layer 104. 2 covers the patterned first passivation layer 111 and fills the opening 114, one of the first passivation layer 111 and the second passivation layer 112 includes aluminum and the other includes silicon; the source electrode 12 and the drain electrode 13 are spaced apart, and both the source electrode 12 and the drain electrode 13 vertically penetrate the composite passivation layer 11; the first dielectric layer 14 is located above the composite passivation layer 11; the gate electrode 16 vertically penetrates the first dielectric layer 14 and the composite passivation layer 11, and the gate electrode 16 is located in a region where the passivation layer including silicon directly contacts the aluminum-containing barrier layer 104.

[0127] As an example, the semiconductor layer 10 further includes a substrate 101 , a buffer layer 102 and a channel layer 103 stacked in order from bottom to top below the aluminum-containing barrier layer 104 . The channel layer 103 has a two-dimensional electron gas on a side facing the aluminum-containing barrier layer 104 .

[0128] As an example, the aluminum-containing barrier layer 104 includes at least one of an AlGaN layer, an AlN layer, an InAlGaN layer, and an InAlN layer. In this embodiment, the aluminum-containing barrier layer 104 is preferably an AlGaN layer.

[0129] As an example, the first passivation layer 111 includes aluminum, the second passivation layer 112 includes silicon, and the gate electrode 16 is located in the region where the opening 114 is located.

[0130] Specifically, in this embodiment, the gate electrode 16 is located at an interface region where the second passivation layer 112 directly contacts the aluminum-containing barrier layer 104 .

[0131] As an example, both the source electrode 12 and the drain electrode 13 avoid the opening 114 area (not shown), or the source electrode 12 is located in the area where the opening 114 is located, and the drain electrode 13 avoids the opening 114 area.

[0132] As an example, the semiconductor device structure also includes a second dielectric layer 17 and a lead structure 20, the second dielectric layer 17 is located on the first dielectric layer 14, and the second dielectric layer 17 covers the gate electrode 16; the lead structure 20 includes a gate lead 201 connected to the gate electrode 16, a source lead 202 connected to the source electrode 12, and a drain lead 203 connected to the drain electrode 13, and the lead structure 20 is used to lead out the gate electrode 16, the source electrode 12 and the drain electrode 13.

[0133] The semiconductor device structure of this embodiment significantly enhances device performance by forming a composite passivation layer on the semiconductor layer. The composite passivation layer includes a patterned first aluminum-containing passivation layer and a second silicon-containing passivation layer. The density and uniformity of the film effectively reduce dangling bonds and surface states on the surface of the aluminum-containing barrier layer, thereby enhancing the passivation effect. In addition, the introduction of the composite passivation layer reduces interface damage between the aluminum-containing barrier layer and the gate and source electrodes, effectively improving gate electrode leakage, suppressing the current collapse effect, and improving the electrical performance and reliability of the device.

[0134] Example 4

[0135] This embodiment provides a semiconductor device structure, which can be obtained using the fabrication method described in Example 2 or other suitable fabrication methods. The main difference between the semiconductor device structure of this embodiment and the semiconductor device structure of Example 3 is that the gate electrode 16 formed in Example 3 is located in the region of the opening 114 formed after the first passivation layer 111 is patterned. In this embodiment, however, the gate electrode 16 is formed away from the region where the opening 114 is located.

[0136] As an example, see Figure 14 , which is a schematic cross-sectional view of the semiconductor device structure in this embodiment, wherein the first passivation layer 111 includes silicon, the second passivation layer 112 includes aluminum, and the gate electrode 16 avoids the area where the opening 114 is located.

[0137] Specifically, in this embodiment, the gate electrode 16 is located at an interface region where the first passivation layer 111 directly contacts the aluminum-containing barrier layer 104 .

[0138] As an example, the source electrode 12 and the drain electrode 13 are both located in the opening 114 area (not shown), or the source electrode 12 avoids the area where the opening 114 is located, and the drain electrode 13 is located in the opening 114 area.

[0139] As an example, the composite passivation layer 11 further includes a third passivation layer 113 , and the third passivation layer 113 covers the second passivation layer 112 .

[0140] The semiconductor device structure of this embodiment, through a composite passivation layer structure consisting of a patterned first silicon-containing passivation layer, a second aluminum-containing passivation layer, and a third passivation layer, effectively reduces dangling bonds and surface states on the surface of the aluminum-containing barrier layer, thereby enhancing the passivation effect. Furthermore, it reduces interface damage between the aluminum-containing barrier layer and the gate and source electrodes, effectively improving gate leakage, suppressing the current collapse effect, and further enhancing the electrical performance and reliability of the device.

[0141] In summary, the present invention provides a semiconductor device structure and a method for preparing the same, which significantly enhances device performance by forming a composite passivation layer on a semiconductor layer including an aluminum-containing barrier layer. The composite passivation layer includes a first passivation layer and a second passivation layer. The first passivation layer is patterned to form an opening that exposes the aluminum-containing barrier layer, and the second passivation layer covers the first passivation layer and fills the opening. One of the first passivation layer and the second passivation layer includes aluminum elements, and the other includes silicon elements, and the gate electrode is formed in the area where the passivation layer including silicon elements is in direct contact with the aluminum-containing barrier layer. The design of this composite passivation layer, on the one hand, effectively reduces the dangling bonds and surface states on the surface of the aluminum-containing barrier layer, thereby achieving efficient passivation of the semiconductor device structure. On the other hand, it can effectively avoid damage to the aluminum-containing barrier layer during the subsequent preparation of the gate electrode through hole and the source contact hole, thereby effectively reducing the leakage risk caused by defects in the contact interface between the aluminum-containing barrier layer and the gate electrode and the source electrode, and effectively suppressing the current collapse effect. By introducing a composite passivation layer into the semiconductor device structure, the present invention not only enhances the device's electrical isolation performance but also ensures long-term stability and reliability under high-frequency and high-power conditions. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and possesses high industrial value.

[0142] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor device structure, characterized in that: The following steps are involved: providing a semiconductor layer, the semiconductor layer including an aluminum-containing barrier layer; forming a composite passivation layer above the semiconductor layer, the composite passivation layer comprising a first passivation layer and a second passivation layer formed sequentially, the first passivation layer being patterned to form an opening exposing the aluminum-containing barrier layer, the second passivation layer covering the patterned first passivation layer and filling the opening, the first passivation layer comprising aluminum, and the second passivation layer comprising silicon; forming a source electrode and a drain electrode spaced apart from each other, wherein the source electrode and the drain electrode both vertically penetrate the composite passivation layer; forming a first dielectric layer above the composite passivation layer; forming a gate electrode through-hole, wherein the gate electrode through-hole vertically penetrates the first dielectric layer and the composite passivation layer, and the gate electrode through-hole is located in the area where the opening is located; A gate electrode is formed, wherein the gate electrode at least fills the gate electrode through hole.

2. The method for preparing a semiconductor device structure according to claim 1, wherein: The source electrode and the drain electrode both avoid the opening area, or the source electrode is located in the area where the opening is located, and the drain electrode avoids the opening area.

3. The method for preparing a semiconductor device structure according to claim 1, wherein: The following steps are also included: forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the gate electrode; patterning the second dielectric layer to form a through-hole structure, wherein the through-hole structure exposes the tops of the source electrode, the drain electrode, and the gate electrode; forming an interconnect metal layer, wherein the interconnect metal layer covers the second dielectric layer and fills the through-hole structure; The interconnect metal layer is patterned to form a lead structure.

4. The method for preparing a semiconductor device structure according to claim 1, wherein: The semiconductor layer further includes a substrate, a buffer layer, and a channel layer which are stacked in sequence from bottom to top and are located below the aluminum-containing barrier layer. A two-dimensional electron gas is formed on a side of the channel layer facing the aluminum-containing barrier layer.

5. The method for preparing a semiconductor device structure according to claim 1, wherein: The material of the first passivation layer includes at least one of aluminum nitride, aluminum oxide, and aluminum oxide nitride, and the material of the second passivation layer includes at least one of silicon nitride and silicon dioxide.

6. A semiconductor device structure, characterized in that: include: a semiconductor layer, the semiconductor layer comprising an aluminum-containing barrier layer; a composite passivation layer located above the semiconductor layer, the composite passivation layer comprising a first passivation layer and a second passivation layer formed sequentially, the first passivation layer being patterned to form an opening exposing the aluminum-containing barrier layer, the second passivation layer covering the patterned first passivation layer and filling the opening, the first passivation layer comprising aluminum, and the second passivation layer comprising silicon; a source electrode and a drain electrode, wherein the source electrode and the drain electrode are spaced apart from each other and both the source electrode and the drain electrode vertically penetrate the composite passivation layer; a first dielectric layer, located above the composite passivation layer; A gate electrode is provided, wherein the gate electrode vertically penetrates the first dielectric layer and the composite passivation layer, and the gate electrode through hole is located in the area where the opening is located.

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