Semiconductor structure and manufacturing method thereof

Abstract

Disclosed are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: a substrate, a stacked structure located on the substrate, and a support structure. The stacked structure includes a plurality of active layers spaced apart along a vertical direction, the active layers including a plurality of first active portions extending along a first direction and spaced apart along a second direction, wherein the second direction intersects the first direction and is parallel to the substrate plane. The support structure includes a first through portion and a first protruding portion. The first through portion extends along the vertical direction and covers the sidewalls of the plurality of first active portions. The first protruding portion is located below the first through portion and embedded in the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the development and advancement of technology, semiconductor devices are becoming increasingly smaller, with a continuous trend towards miniaturization and high integration. Dynamic random access memory (DRAM), a semiconductor device that allows for high-speed, random data write and read operations, is widely used in data storage devices and equipment. However, in practice, DRAM still faces many challenges that require improvement. Summary of the Invention

[0003] An embodiment of the present disclosure provides a semiconductor structure, comprising:

[0004] substrate;

[0005] a stacked structure located on the substrate, the stacked structure comprising a plurality of active layers spaced apart along a vertical direction, the active layer comprising a plurality of first active portions extending along a first direction and spaced apart along a second direction, wherein the second direction intersects the first direction and is parallel to the substrate plane;

[0006] The support structure includes a first through portion and a first protruding portion, wherein the first through portion extends in a vertical direction and covers the sidewalls of the plurality of first active portions, and the first protruding portion is located below the first through portion and embedded in the substrate.

[0007] In some embodiments, in the second direction, the maximum width of the first protruding portion is greater than the width of the first through portion.

[0008] In some embodiments, the substrate includes a first semiconductor layer, an insulating layer covering the first semiconductor layer, and a second semiconductor layer covering the insulating layer, the first through-portion penetrates the second semiconductor layer and connects to a first protrusion located in the insulating layer, and in the second direction, the width of the first protrusion located in the insulating layer is greater than the width of the first through-portion.

[0009] In some embodiments, the number of the first through-portions and the first protrusions of the support structure is multiple, and the multiple first through-portions and the multiple first protrusions are arranged at intervals along the second direction, and in the first direction, the first protrusions are at least partially located in the substrate below the first active portion.

[0010] In some embodiments, the support structure further includes a horizontal portion extending along the second direction and intersecting the first through portion, wherein the horizontal portion covers an upper surface and a lower surface of the first active portion.

[0011] In some embodiments, the semiconductor structure further includes an adhesion layer located between the first protrusion and the substrate.

[0012] In some embodiments, the active layer further includes a second active portion extending along the second direction and connected to ends of the plurality of first active portions;

[0013] There are multiple support structures, and the multiple support structures include a first support structure, a second support structure and a third support structure arranged at intervals along a first direction, the first support structure covers the end of the first active part close to the second active part and is arranged adjacent to the second active part, the third support structure covers the end of the first active part away from the second active part, and the second support structure is located between the first support structure and the third support structure.

[0014] In some embodiments, the substrate includes a core area and a peripheral area surrounding the core area, and the stacked structure is located in the core area; the semiconductor structure also includes an isolation structure located in the peripheral area, and the isolation structure includes a second through-portion extending in a vertical direction and a second protrusion located below the second through-portion and embedded in the substrate.

[0015] The present disclosure also provides a method for manufacturing a semiconductor structure, including:

[0016] Providing a substrate, and forming an initial stacking structure on the substrate, wherein the initial stacking structure includes sacrificial layers and active layers alternately stacked in sequence along a vertical direction;

[0017] Patterning the initial stacked structure to form an isolation trench and a stacked structure, wherein the stacked structure includes first sacrificial portions and first active portions alternately stacked in a vertical direction, wherein a plurality of the first sacrificial portions and a plurality of the first active portions extend along a first direction and are spaced apart along a second direction; wherein the second direction intersects the first direction and is parallel to the substrate plane;

[0018] forming a filling layer in the isolation trench;

[0019] removing a portion of the filling layer and a portion of the substrate to form a first trench extending in a vertical direction and exposing a sidewall of the stacked structure, and a first recess located below the first trench and formed in the substrate;

[0020] Insulating material is filled in the first groove and the first recess to form a first through portion and a first protruding portion respectively, and the first through portion and the first protruding portion constitute a supporting structure.

[0021] In some embodiments, removing a portion of the filling layer and a portion of the substrate to form the first trench and the first recess includes:

[0022] forming a patterned mask layer on the stacked structure and the filling layer, wherein the patterned mask layer includes a first opening pattern extending along the second direction;

[0023] removing the filling layer below the first opening pattern to form the first trench, wherein the bottom of the first trench exposes the substrate;

[0024] The substrate exposed by the first trench is etched to form the first recess.

[0025] In some embodiments, after forming the first trench, the method further includes:

[0026] Laterally etching the first sacrificial portion below the first opening pattern using the first trench as an opening to form a gap exposing the upper surface and the lower surface of the first active portion;

[0027] While filling the first groove and the first recess with insulating material to form a first through portion and a first protruding portion respectively, it also includes: filling the insulating material in the gap to form a horizontal portion covering the upper surface and the lower surface of the first active portion, the horizontal portion extending along the second direction and intersecting with the first through portion, the first through portion, the first protruding portion and the horizontal portion together constitute the support structure.

[0028] In some embodiments, before etching the substrate exposed by the first trench to form the first recess, the method further includes:

[0029] forming a protection layer, the protection layer covering a bottom surface of the first trench and a surface of the first active portion exposed by the first trench;

[0030] The protection layer at the bottom of the first trench is removed to expose the substrate.

[0031] In some embodiments, after forming the first recess, the method further includes:

[0032] The substrate exposed by the first recess is laterally etched so that a maximum width of the first recess in the second direction is greater than a width of the first trench.

[0033] In some embodiments, the substrate includes a first semiconductor layer, an insulating layer covering the first semiconductor layer, and a second semiconductor layer covering the insulating layer; the first trench at least penetrates the second semiconductor layer and exposes the insulating layer; and etching the substrate exposed by the first trench to form the first recess includes:

[0034] The insulating layer exposed by the first trench is etched to form the first recess, and the etching rate of the insulating layer is greater than the etching rate of the first semiconductor layer and the second semiconductor layer, so that the width of the first recess formed in the insulating layer in the second direction is greater than the width of the first trench in the second direction.

[0035] In some embodiments, before filling the first recess with the insulating material, the method further includes: forming an adhesion layer on an inner wall of the first recess.

[0036] The present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes: a substrate; a stacked structure located on the substrate, the stacked structure including a plurality of active layers spaced apart in a vertical direction, the active layers including a plurality of first active portions extending in a first direction and spaced apart in a second direction, the second direction intersecting the first direction and both being parallel to the plane of the substrate; and a support structure including a first through portion and a first protrusion, the first through portion extending in a vertical direction and covering the sidewalls of the plurality of first active portions, the first protrusion being located below the first through portion and embedded in the substrate. The present disclosure provides a semiconductor structure including a stacked structure and a support structure for supporting the stacked structure, the support structure including a first through portion and a first protrusion located below the first through portion, wherein the first protrusion is embedded in the substrate, which can enhance the firmness of the bonding between the support structure and the substrate, prevent or mitigate the support structure from falling off the substrate, thereby improving the mechanical stability of the support structure, thereby improving the support effect of the support structure on the stacked structure, and preventing the stacked structure from collapsing when subsequent processes are performed on the stacked structure.

[0037] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1a A perspective view of a semiconductor structure provided in accordance with an embodiment of the present disclosure, Figure 1b For the Figure 1a The cross-sectional structure diagram taken along the lines A-A' and B-B' is shown in FIG. Figure 1c for Figure 1a Omit the perspective view of the fill layer, Figure 1d for Figure 1a A perspective view of the stacked structure;

[0040] Figure 2a A perspective view of a semiconductor structure provided in accordance with another embodiment of the present disclosure is provided. Figure 2b For the Figure 2a A schematic diagram of the cross-sectional structure taken along lines A-A' and B-B';

[0041] Figure 3a A perspective view of a semiconductor structure provided in accordance with another embodiment of the present disclosure is provided. Figure 3b For the Figure 3a A schematic diagram of the cross-sectional structure taken along lines A-A' and B-B';

[0042] Figure 4a A perspective view of a semiconductor structure provided in accordance with another embodiment of the present disclosure is provided. Figure 4b For the Figure 4a A schematic diagram of the cross-sectional structure taken along lines A-A' and B-B';

[0043] Figure 5a A perspective view of a semiconductor structure provided in accordance with another embodiment of the present disclosure is provided. Figure 5b For the Figure 5a The cross-sectional structure diagram taken along the lines A-A' and B-B' is shown in FIG. Figure 5c for Figure 5a A perspective view omitting the filling layer and sacrificial layer;

[0044] Figure 6 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0045] Figures 7 to 13b A process flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0046] Figures 14a to 14b A process flow chart of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure;

[0047] Figures 15a to 16b A process flow chart of a method for manufacturing a semiconductor structure provided in yet another embodiment of the present disclosure;

[0048] Figures 17a to 17b A process flow chart of a method for manufacturing a semiconductor structure provided in yet another embodiment of the present disclosure;

[0049] Figures 18a to 18b A process flow chart of a method for manufacturing a semiconductor structure provided in yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0051] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0052] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0053] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0054] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0055] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] Dynamic random access memory (DRAM), a semiconductor device that allows for high-speed, random data write and read operations, is widely used in data storage devices or apparatuses. Typically, increasing the level of integration can effectively increase the information storage capacity of the memory. In practice, the memory structure is often formed by first stacking multiple transistors on a substrate and then forming capacitors on the side of the transistor structure away from the substrate. However, in actual processes, when multiple transistors are formed on a substrate, the transistors are prone to collapse.

[0057] Based on this, the following technical solutions of the embodiments of the present disclosure are proposed. The specific implementation methods of the present disclosure are described in detail below with reference to the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present disclosure.

[0058] Figure 1a A perspective view of a semiconductor structure provided in accordance with an embodiment of the present disclosure, Figure 1b For the Figure 1a The cross-sectional structure diagram taken along the lines A-A' and B-B' is shown in FIG. Figure 1c for Figure 1a Omit the perspective view of the fill layer, Figure 1d for Figure 1a A perspective view of the stacked structure; Figure 2a A perspective view of a semiconductor structure provided in accordance with another embodiment of the present disclosure is provided. Figure 2b For the Figure 2a A schematic diagram of the cross-sectional structure taken along lines A-A' and B-B'; Figure 3a A perspective view of a semiconductor structure provided in accordance with another embodiment of the present disclosure is provided. Figure 3b For the Figure 3a A schematic diagram of the cross-sectional structure taken along lines A-A' and B-B'; Figure 4a A perspective view of a semiconductor structure provided in accordance with another embodiment of the present disclosure is provided. Figure 4b For the Figure 4a A schematic diagram of the cross-sectional structure taken along lines A-A' and B-B'; Figure 5a A perspective view of a semiconductor structure provided in accordance with another embodiment of the present disclosure is provided. Figure 5b For the Figure 5a The cross-sectional structure diagram taken along the lines A-A' and B-B' is shown in FIG. Figure 5c for Figure 5a The perspective view of the filling layer and the sacrificial layer is omitted. Figures 1a to 5c The semiconductor structure provided by the embodiment of the present disclosure is further described.

[0059] like Figures 1a to 1d As shown, the semiconductor structure includes: a substrate 10; a stacked structure ST located on the substrate 10, the stacked structure ST including a plurality of active layers 12 spaced apart along a vertical direction, the active layer 12 including a plurality of first active portions 121 extending along a first direction and spaced apart along a second direction, the second direction intersecting with the first direction and both being parallel to the plane of the substrate 10; a support structure 21, the support structure 21 including a first through portion 211 and a first protruding portion 212, the first through portion 211 extending along a vertical direction and covering side walls of the plurality of first active portions 121, the first protruding portion 212 being located below the first through portion 211 and embedded in the substrate 10.

[0060] In actual operation, the semiconductor structure provided by the embodiment of the present disclosure may be a three-dimensional dynamic random access memory (3DDRAM), but is not limited thereto and may be any semiconductor structure.

[0061] In one embodiment, the substrate 10 may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate or a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate 10 is a silicon substrate, which may be doped or undoped.

[0062] In one embodiment, the substrate 10 includes a core region R1 and a peripheral region R2 surrounding the core region R1 , and the stacked structure ST is located in the core region R1 .

[0063] like Figure 1d As shown, in one embodiment, the active layer 12 further includes a second active portion 122, which extends along the second direction and is connected to the ends of the plurality of first active portions 121. The material of the active layer 12 can be a doped or undoped semiconductor material, such as silicon. However, the active layer 12 is not limited thereto. The material of the active layer 12 can also be an oxide semiconductor material, such as at least one of indium oxide, tin oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide, or a combination thereof. In actual operation, the semiconductor structure can be a three-dimensional dynamic random access memory, the first active portion 121 can be used to form a transistor, and the second active portion 122 can be used as a bit line of the memory. Subsequently, a metallization process can be performed on the second active portion 122 to improve the conductivity of the second active portion 122.

[0064] In one embodiment, the stacked structure ST further includes a plurality of sacrificial layers 11, which are arranged alternately with the plurality of active layers 12 in a vertical direction. The sacrificial layers 11 include a second sacrificial portion 112 and a plurality of first sacrificial portions 111. The plurality of first sacrificial portions 111 extend in a first direction and are arranged at intervals in a second direction. The second sacrificial portions 112 extend in the second direction and connect to the ends of the plurality of first sacrificial portions 111. More specifically, the stacked structure ST includes a plurality of second active portions 122 and a plurality of second sacrificial portions 112. In a direction perpendicular to the plane of the substrate 10, the plurality of first sacrificial portions 111 are arranged alternately with the plurality of first active portions 121, and the plurality of second sacrificial portions 112 are arranged alternately with the plurality of second active portions 122. Here, the first direction and the second direction are perpendicular or oblique to each other. The material of the sacrificial layer 11 includes, but is not limited to, silicon germanium, which may be doped or undoped.

[0065] In one embodiment, the semiconductor structure further includes an isolation trench T4 , and the plurality of first sacrificial portions 111 and the plurality of first active portions 121 arranged along the second direction are separated by the isolation trench T4 .

[0066] In one embodiment, the bottom layer of the stacked structure ST is a sacrificial layer 11 . In subsequent processes, the sacrificial layer 11 may be removed, and a dielectric material may be filled in the space where the sacrificial layer 11 is removed to prevent electrical connection between the active layer 12 and the substrate 10 .

[0067] In practice, the sacrificial layer 11 and the active layer 12 can be formed by a selective epitaxial process. The thickness of the sacrificial layer 11 ranges from 50 nm to 70 nm (inclusive), for example, 60 nm; the thickness of the active layer 12 ranges from 20 nm to 40 nm (inclusive), for example, 30 nm.

[0068] In one embodiment, the stacked structure ST further includes a capping layer 14, which is located at the top layer of the stacked structure ST and covers at least the first active portion 121 or the first sacrificial portion 111. However, this is not limiting. In some other embodiments, the capping layer 14 also covers the second active portion 122 and the second sacrificial portion 112, and the orthographic projection of the capping layer 14 on the plane of the substrate 10 overlaps with the orthographic projections of the sacrificial layer 11 and the active layer 12 on the plane of the substrate 10. In some embodiments, the semiconductor structure further includes a spacer layer 13 located below the capping layer 14. The capping layer 14 protects the stacked structure ST and isolates the capping layer 14 from other structures located below the capping layer 14. Materials for the capping layer 14 include, but are not limited to, nitrides, such as silicon nitride; materials for the spacer layer 13 include, but are not limited to, oxides, such as silicon oxide. However, this is not limiting, and the spacer layer 13 and / or the capping layer 14 may also be omitted.

[0069] In one embodiment, the semiconductor structure further includes a filling layer 17, which covers the substrate 10 in the core region R1 and the peripheral region R2 and fills the isolation trench T4. The material of the filling layer 17 includes but is not limited to insulating materials such as tetraethylorthosilicate (TEOS) and silicon dioxide.

[0070] The support structure 21 provided in the present disclosure is used to support the stacked structure ST located on the substrate 10, wherein the support structure 21 includes a first through portion 211 and a first protruding portion 212, the first through portion 211 extends in the vertical direction in the filling layer 17 and covers the side walls of the first active portion 121 and the first sacrificial portion 111, the first protruding portion 212 is located below the first through portion 211 and embedded in the substrate 10, the first protruding portion 212 can enhance the firmness of the combination of the support structure 21 and the substrate 10, avoid or alleviate the support structure 21 from falling off the substrate 10, thereby improving the mechanical stability of the support structure 21, and further improving the support effect on the stacked structure ST; in addition, in subsequent processes, the filling layer 17 and the sacrificial layer 11 can be removed to perform subsequent processing on the active layer 12, and each active layer 12 will be suspended and spaced apart on the substrate 10. The support structure 21 with the first protruding portion 212 provided in the embodiment of the present disclosure plays a good supporting role for multiple active layers 12, and can avoid the collapse of the active layer 12.

[0071] like Figures 1a to 1cAs shown, in one embodiment, the support structure 21 includes a plurality of first through-portions 211 and a plurality of first protruding portions 212, each of which is spaced apart along the second direction. In some embodiments, the first through-portions 211 also cover the sidewalls of the cover layer 14. The plurality of first through-portions 211 arranged along the second direction are interconnected with the cover layer 14 to jointly support other structures on the substrate 10. This further enhances the mechanical stability of the support structure 21 and the supporting effect of the support structure 21.

[0072] The materials of the first through portion 211 and the first protruding portion 212 can be the same or different. In practice, the first through portion 211 and the first protruding portion 212 can be integrally formed and made of the same material, including but not limited to insulating materials such as nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride), and oxynitride carbide (e.g., silicon oxynitride carbide).

[0073] In one embodiment, there are multiple support structures 21, including a first support structure SS1, a second support structure SS2, and a third support structure SS3, spaced apart along a first direction. The first support structure SS1 covers the end of the first active portion 121 near the second active portion 122 and is disposed adjacent to the second active portion 122. The third support structure SS3 covers the end of the first active portion 121 away from the second active portion 122. The second support structure SS2 is located between the first support structure SS1 and the third support structure SS3. The provision of multiple support structures 21 can further enhance the support for the stacked structure ST or the active layer 12 after the filler layer 17 and the sacrificial layer 11 are removed. In some embodiments, the cap layer 14 is simultaneously connected to the first support structure SS1, the second support structure SS2, and the third support structure SS3, further enhancing the mechanical stability and support effectiveness of the support structure 21.

[0074] In one embodiment, the third support structure SS3 further includes a connecting portion 214 extending along the second direction. The connecting portion 214 is disposed adjacent to the end of the first active portion 121 away from the second active portion 122 and is connected to a plurality of first through-portions 211 spaced apart along the second direction. A first protrusion 212 is also formed below the connecting portion 214. The first protrusion 212 below the connecting portion 214 is connected to the plurality of first protrusions 212 below the first through-portions 211. This provides the third support structure SS3 with greater mechanical stability, further enhancing the supporting effect of the third support structure SS3. In actual operation, the first through-portions 211 and the connecting portion 214 of the third support structure SS3 are integrally formed and made of the same material.

[0075] like Figures 1a to 1cAs shown, in one embodiment, the semiconductor structure further includes an adhesion layer 23, which is located between the first protrusion 212 and the substrate 10 to enhance the adhesion between the first protrusion 212 and the substrate 10, further improving the firmness of the bond between the first protrusion 212 and the substrate 10, and thereby enhancing the support effect of the support structure 21. The material of the adhesion layer 23 includes, but is not limited to, oxides (e.g., silicon oxide), oxynitrides (e.g., silicon oxynitride), oxynitride carbides (e.g., silicon oxynitride carbide), etc., and the material of the adhesion layer 23 can be different from the material of the first protrusion 212. In one specific embodiment, the material of the adhesion layer 23 is an oxide (e.g., silicon oxide), which can be formed by a deposition process or by performing a thermal oxidation process on the substrate 10.

[0076] In one embodiment, the semiconductor structure further includes an isolation structure 22 located in the peripheral region R2. The isolation structure 22 includes a second through-portion 221 extending in a vertical direction and a second protrusion 222 located below the second through-portion 221 and embedded in the substrate 10. In some embodiments, the isolation structure 22 further extends in a direction parallel to the plane of the substrate 10 and is disposed around the core region R1. The isolation structure 22 isolates and supports the structures located in the core region R1. In the disclosed embodiment, the second protrusion 222 embedded in the substrate 10 is disposed below the second through-portion 221, thereby enhancing the secure connection between the isolation structure 22 and the substrate 10, thereby improving the support provided by the isolation structure 22 to the core region R1. In actual operation, the isolation structure 22 and the support structure 21 can be formed in the same step to save process steps.

[0077] In one embodiment, an adhesive layer 23 is further disposed between the second protrusion 222 and the substrate 10 to improve adhesion between the second protrusion 222 and the substrate 10 .

[0078] like Figure 1b As shown, in one embodiment, the semiconductor structure further includes a protective layer 24, which covers the sidewalls of the first through portion 211 and the second through portion 221 to protect the active layer 12. The material of the protective layer 24 includes but is not limited to oxides, such as silicon oxide. It should be noted that in order to better illustrate the positional relationship of the various structural layers in the semiconductor structure, Figure 1a 、 Figure 1c The protective layer 24 is omitted.

[0079] Figures 1a to 1c In the semiconductor structure shown, in the second direction, the width of the first protrusion 212 is the same as or similar to the width of the first through portion 211. Figure 2a to Figure 2b As shown, in another embodiment of the present disclosure, in the second direction, the maximum width of the first protruding portion 212 is greater than the width of the first penetrating portion 211; further, as shown Figure 2b Middle Edge Figure 2a As shown in the schematic diagram of the cross-sectional structure taken along the center line BB′, in the first direction, the first protrusion 212 is at least partially located in the substrate 10 below the first active portion 121, thereby further increasing the firmness of the connection between the support structure 21 and the substrate 10 and enhancing the mechanical stability of the support structure 21.

[0080] In one embodiment, in the second direction, the width of the top of the first protrusion 212 is smaller than the maximum width of the first protrusion 212 , so that the first protrusion 212 can be better embedded in the substrate 10 . Figure 2a to Figure 2b The cross section of the first protrusion 212 in the vertical direction shown in FIG has an arc-shaped profile. However, the present invention is not limited thereto. In some embodiments, the cross section of the first protrusion 212 in the vertical direction may also be a trapezoidal, step-shaped, comb-tooth-shaped, etc.

[0081] Continue to see Figure 2a to Figure 2b In one embodiment, in the extension direction of the second through portion 221 parallel to the plane of the substrate 10, the width of the second protrusion 222 of the isolation structure 22 is greater than the width of the second through portion 221, further improving the firmness of the combination between the isolation structure 22 and the substrate 10.

[0082] In the embodiment of the present disclosure, the substrate 10 may also be a SOI (Silicon On Insulator) substrate. Figure 3a to Figure 3b As shown, the substrate 10 includes a first semiconductor layer 101, an insulating layer 102 covering the first semiconductor layer 101, and a second semiconductor layer 103 covering the insulating layer 102. The first penetrating portion 211 penetrates the second semiconductor layer 103 and connects to the first protruding portion 212 located in the insulating layer 102. The first protruding portion 212 may penetrate or partially penetrate the insulating layer 102. The materials of the first semiconductor layer 101 and the second semiconductor layer 103 include, but are not limited to, silicon, and the material of the insulating layer 102 includes, but is not limited to, oxide (e.g., silicon oxide).

[0083] Further, such as Figures 4a to 4b As shown, in yet another embodiment of the present disclosure, in the second direction, the width of the first protruding portion 212 located in the insulating layer 102 is greater than the width of the first through portion 211, and in the first direction, the width of the first protruding portion 212 located in the insulating layer 102 is greater than the width of the first through portion 211. In some embodiments, in the first direction, the first protruding portion 212 is at least partially located in the substrate 10 below the first active portion 121.

[0084] In actual operation, when the substrate 10 includes an insulating layer 102, the method for forming the support structure 21 can be: first, the filling layer 17 and the second semiconductor layer 103 are etched to form a first trench T1 exposing the insulating layer 102, then the insulating layer 102 is etched to form a first recess S1, and then the first trench T1 and the first recess S1 are filled with insulating material to form a first through portion 211 and a first protrusion 212, respectively. The substrate 10 provided in the embodiment of the present disclosure includes an insulating layer 102. Thus, when forming the first recess S1, the etching rate of the insulating layer 102 can be controlled to be greater than the etching rates of the first semiconductor layer 101 and the second semiconductor layer 103, so that the width of the first recess S1 formed in the insulating layer 102 in the second direction is greater than the width of the first trench T1 in the second direction, thereby making the width of the formed first protrusion 212 in the second direction greater than the width of the first through portion 211 in the second direction, thereby reducing the process difficulty of forming the first protrusion 212 with a larger width, and reducing damage to the substrate 10 and the second active portion 122 during the formation of the first recess S1.

[0085] In one embodiment, when the substrate 10 includes the insulating layer 102, the second through portion 221 of the isolation structure 22 penetrates the second semiconductor layer 103, and the second protruding portion 222 is located within the insulating layer 102. The second protruding portion 222 may or may not penetrate the insulating layer 102. In some embodiments, in a direction in which the second through portion 221 extends parallel to the substrate 10, the width of the second protruding portion 222 located within the insulating layer 102 is greater than the width of the second through portion 221.

[0086] like Figures 5a to 5c As shown, in another embodiment of the present disclosure, the support structure 21 further includes a horizontal portion 213 extending along the second direction and intersecting the first through portion 211. The horizontal portion 213 covers the upper and lower surfaces of the first active portion 121. In practice, the horizontal portion 213 can be formed by removing a portion of the first sacrificial portion 111 to form a gap exposing the upper and lower surfaces of the first active portion 121, and then filling the gap with an insulating material. The horizontal portion 213 and the first through portion 211 can be formed integrally, and the two can be made of the same material.

[0087] In one embodiment, there are multiple horizontal portions 213, and the multiple horizontal portions 213 are arranged in a direction perpendicular to the plane of the substrate 10, and the multiple first through portions 211 and the multiple horizontal portions 213 cross and connect with each other to form a structure extending along the second direction and surrounding the multiple first active portions 121, further improving the supporting effect of the support structure 21.

[0088] It should be noted that although Figures 2a to 5c The adhesive layer 23 is not shown in the figure, but in actual operation, it can also be Figures 2a to 5cAn adhesive layer 23 is formed between the first protrusion 212 , the second protrusion 222 and the substrate 10 to improve adhesion between the first protrusion 212 , the second protrusion 222 and the substrate 10 .

[0089] The present disclosure also provides a method for manufacturing a semiconductor structure. Figure 6 As shown, the method includes the following steps:

[0090] Step S101: providing a substrate, and forming an initial stacking structure on the substrate, wherein the initial stacking structure includes sacrificial layers and active layers alternately stacked in a vertical direction;

[0091] Step S102: patterning the initial stack structure to form an isolation trench and a stack structure, wherein the stack structure includes first sacrificial portions and first active portions alternately stacked in a vertical direction, wherein the plurality of first sacrificial portions and the plurality of first active portions extend along a first direction and are spaced apart along a second direction; the second direction intersects the first direction and is parallel to the substrate plane;

[0092] Step S103: forming a filling layer in the isolation trench;

[0093] Step S104: removing a portion of the filling layer and a portion of the substrate to form a first trench extending in a vertical direction and exposing a sidewall of the stacked structure, and a first recess located below the first trench and formed in the substrate;

[0094] Step S105 : Filling the first trench and the first recess with insulating material to form a first through portion and a first protruding portion, respectively. The first through portion and the first protruding portion constitute a supporting structure.

[0095] Next, combine Figures 7 to 18b The manufacturing method of the semiconductor structure of the embodiment of the present disclosure is further described in detail; wherein, Figure 9a 、 Figure 10a 、 Figure 11a 、 Figure 12a 、 Figure 13a 、 Figure 14a 、 Figure 15a 、 Figure 16a 、 Figure 17a 、 Figure 18a A perspective view of a method for manufacturing a semiconductor structure in different process steps provided by an embodiment of the present disclosure, Figure 9b 、 Figure 10b 、 Figure 11b 、 Figure 12b 、 Figure 13b 、 Figure 14b 、 Figure 15b 、 Figure 16b 、 Figure 17b 、 Figure 18b Along Figure 9a 、 Figure 10a 、 Figure 11a 、 Figure 12a 、 Figure 13a 、 Figure 14a 、 Figure 15a 、 Figure 16a 、 Figure 17a 、 Figure 18a Schematic diagram of the cross-sectional structure taken along lines AA' and BB'.

[0096] First, execute step S101, as Figure 7 As shown, a substrate 10 is provided, and an initial stacked structure ST′ is formed on the substrate 10 . The initial stacked structure ST′ includes sacrificial layers 11 and active layers 12 that are alternately stacked in sequence along a vertical direction.

[0097] In one embodiment, the substrate 10 may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate or a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate 10 is a silicon substrate, which may be doped or undoped.

[0098] In one embodiment, the substrate 10 includes a core region R1 and a peripheral region R2 surrounding the core region R1 , and the initial stacked structure ST′ covers the core region R1 and the peripheral region R2 .

[0099] In one embodiment, the bottom layer of the initial stacked structure ST' is a sacrificial layer 11. In subsequent processes, the sacrificial layer 11 can be removed, and the space left by the sacrificial layer 11 can be filled with a dielectric material to prevent electrical connection between the active layer 12 and the substrate 10. In some embodiments, there are multiple sacrificial layers 11 and multiple active layers 12, and the multiple sacrificial layers 11 and the multiple active layers 12 are alternately stacked in a vertical direction.

[0100] In actual operation, the sacrificial layer 11 and the active layer 12 can be formed by a selective epitaxial growth process. The material of the active layer 12 can be a doped or undoped semiconductor material, such as silicon. However, the material of the active layer 12 can also be an oxide semiconductor material, such as at least one of indium oxide, tin oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide, or a combination thereof. The material of the sacrificial layer 11 includes, but is not limited to, silicon germanium, which can be doped or undoped. The thickness of the sacrificial layer 11 ranges from 50 nm to 70 nm (inclusive), for example, 60 nm; the thickness of the active layer 12 ranges from 20 nm to 40 nm (inclusive), for example, 30 nm.

[0101] In one embodiment, the initial stacked structure ST′ further includes a capping layer 14, which is located on the top of the initial stacked structure ST′ and covers the sacrificial layer 11 and active layer 12 located thereunder. In some embodiments, the semiconductor structure further includes a spacer layer 13 located below the capping layer 14. The capping layer 14 protects other structures located thereunder, and the spacer layer 13 isolates the capping layer 14 from the sacrificial layer 11 and active layer 12 located thereunder. Materials for the capping layer 14 include, but are not limited to, nitrides, such as silicon nitride; materials for the spacer layer 13 include, but are not limited to, oxides, such as silicon oxide. However, this is not limiting, and the spacer layer 13 and / or the capping layer 14 may be omitted.

[0102] Next, execute step S102, as shown in FIG. Figures 8 to 9b As shown, the initial stacking structure ST′ is patterned to form an isolation trench T4 and a stacking structure ST. The stacking structure ST includes first sacrificial portions 111 and first active portions 121 that are alternately stacked in a vertical direction. Multiple first sacrificial portions 111 and multiple first active portions 121 extend along the first direction and are arranged at intervals along the second direction. The second direction intersects the first direction and is parallel to the plane of the substrate 10.

[0103] Specifically, patterning the initial stacked structure ST′ to form the isolation trench T4 and the stacked structure ST includes: first, forming a first mask layer 15 on the initial stacked structure ST′, and forming a stacked pattern mask layer 16 on the first mask layer 15; then, etching the initial stacked structure ST′ using the stacked pattern mask layer 16 as a mask to form the isolation trench T4 and the stacked structure ST, wherein the plurality of first sacrificial portions 111 and the plurality of first active portions 121 arranged along the second direction are separated by the isolation trench T4. In some embodiments, the stacked pattern mask layer 16 is located in the core region R1, and the stacked structure ST is formed in the core region R1. Here, the first mask layer 15 can be a single-layer or multi-layer structure including a spin-on hard mask layer, wherein the spin-on hard mask layer includes an amorphous carbon layer or an amorphous silicon layer, etc. The stacked pattern mask layer 16 can be a photoresist layer.

[0104] like Figures 9a to 9b As shown, in some embodiments, the patterned active layer 12 further includes a second active portion 122, which extends along the second direction and connects to the ends of the plurality of first active portions 121 arranged along the second direction; the patterned sacrificial layer 11 further includes a second sacrificial portion 112, which extends along the second direction and connects to the ends of the plurality of first sacrificial portions 111 arranged along the second direction. More specifically, the stacked structure ST includes a plurality of sacrificial layers 11 and a plurality of active layers 12. In a direction perpendicular to the plane of the substrate 10, the first sacrificial portions 111 of the plurality of sacrificial layers 11 are arranged alternately with the first active portions 121 of the plurality of active layers 12, and the second sacrificial portions 112 of the plurality of sacrificial layers 11 are arranged alternately with the second active portions 122 of the plurality of active layers 12. Here, the first direction and the second direction are perpendicular or oblique.

[0105] In one embodiment, the patterned spacer layer 13 and cap layer 14 are located on the top layer of the stacked structure ST and cover at least the first active portion 121 and the first sacrificial portion 111. In some embodiments, the patterned spacer layer 13 and cap layer 14 also cover the second active portion 122 and the second sacrificial portion 112, and the orthographic projections of the spacer layer 13 and cap layer 14 on the plane of the substrate 10 overlap with the orthographic projections of the sacrificial layer 11 and the active layer 12 on the plane of the substrate 10.

[0106] Next, execute step S103, as shown in FIG. Figures 10a to 10b As shown, a filling layer 17 is formed in the isolation trench T4.

[0107] Filling layer 17 covers substrate 10 in core region R1 and peripheral region R2 and fills isolation trench T4. In practice, filling layer 17 can be deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or any combination thereof. Materials for filling layer 17 include, but are not limited to, insulating materials such as tetraethyl orthosilicate (TEOS) and silicon dioxide.

[0108] Next, execute step S104, as shown in FIG. Figures 11a to 13b As shown, part of the filling layer 17 and part of the substrate 10 are removed to form a first trench T1 extending in a vertical direction and exposing the sidewall of the stacked structure ST, and a first recess S1 located below the first trench T1 and formed in the substrate 10 .

[0109] Specifically, removing a portion of the filling layer 17 and a portion of the substrate 10 to form the first trench T1 and the first recess S1 includes:

[0110] forming a patterned mask layer 19 on the stacked structure ST and the filling layer 17 , wherein the patterned mask layer 19 includes a first opening pattern H1 extending along the second direction;

[0111] The filling layer 17 located below the first opening pattern H1 is removed to form a first trench T1 , wherein the bottom of the first trench T1 exposes the substrate 10 ;

[0112] The substrate 10 exposed by the first trench T1 is etched to form a first recess S1.

[0113] In one embodiment, the first opening pattern H1 is located in the core region R1 , and the first trench T1 and the first recess S1 are formed in the core region R1 .

[0114] See again Figures 11a to 11b In one embodiment, before forming the patterned mask layer 19 on the stacked structure ST and the filling layer 17, the process further includes: forming a second mask layer 18 on the stacked structure ST, wherein the patterned mask layer 19 covers the second mask layer 18. Here, the second mask layer 18 can be a single-layer or multi-layer structure including a spin-on hard mask layer, wherein the spin-on hard mask layer includes an amorphous carbon layer or an amorphous silicon layer, etc. The second mask layer 18 can also be an anti-reflective layer. The patterned mask layer 19 can be a photoresist layer.

[0115] In actual operation, the first trench T1 and the first recess S1 can be formed by an anisotropic etching process. For example, the first trench T1 and the first recess S1 can be formed respectively by a dry etching process, or the first trench T1 can be formed by a dry etching process, and then the first recess S1 can be formed by a wet etching process or a gaseous etching process.

[0116] See again Figures 13a to 13b In one embodiment, before etching the substrate 10 exposed by the first trench T1 to form the first recess S1, the process further includes: forming a protective layer 24 that covers the bottom surface of the first trench T1 and the surface of the first active portion 121 exposed by the first trench T1; removing the protective layer 24 at the bottom of the first trench T1 to expose the substrate 10, and then forming the first recess S1. The protective layer 24 is used to protect the active layer 12 from damage and contamination when etching the substrate 10 to form the first recess S1. In some embodiments, the protective layer 24 also covers the sidewalls of the second active portion 122, sacrificial layer 11, spacer layer 13, and cap layer 14 exposed by the first trench T1. The material of the protective layer 24 includes, but is not limited to, an oxide, such as silicon oxide.

[0117] In one embodiment, a plurality of first trenches T1 arranged along the second direction are formed below a first opening pattern H1. The plurality of first trenches T1 and the plurality of first active portions 121 are alternately arranged along the second direction. The sidewalls of the first trenches T1 expose the sidewalls of the first active portion 121, the first sacrificial portion 111, the spacer layer 13, and the capping layer 14. In some embodiments, there are a plurality of first recesses S1, each arranged along the second direction and correspondingly disposed below the plurality of first trenches T1 arranged along the second direction.

[0118] A plurality of first trenches T1 formed correspondingly below a first opening pattern H1 constitute a trench group (not labeled). In one embodiment, the patterned mask layer 19 has a plurality of first opening patterns H1, and a plurality of trench groups (not labeled) are formed correspondingly below the plurality of first opening patterns H1. The plurality of trench groups (not labeled) include a first trench group T11, a second trench group T12, and a third trench group T13 arranged along a first direction. The plurality of first trenches T1 in the first trench group T11 expose the sidewalls of the end of the first active portion 121 adjacent to the second active portion 122. The first trenches T1 in the third trench group T13 expose the sidewalls of the end of the first active portion 121 away from the second active portion 122. The second trench group T12 is located between the first trench group T11 and the third trench group T13.

[0119] like Figure 12aAs shown, in one embodiment, the method further includes etching the filling layer 17 to form a third trench T3 extending along the second direction and exposing the substrate 10. The third trench T3 is located adjacent to the end of the first active portion 121 away from the second active portion 122 and is connected to the multiple first trenches T1 in the third trench group T13. In actual operation, the third trench T3 and the multiple first trenches T1 in the third trench group T13 are formed by etching the filling layer 17 below the same first opening pattern H1. In some embodiments, a first recess S1 is also formed below the third trench T3. The first recess S1 below the third trench T3 extends along the second direction and is connected to the multiple first recesses S1 below the third trench group T13. In some embodiments, the protective layer 24 also covers the sidewalls of the third trench T3.

[0120] See again Figures 11a to 13b In one embodiment, the patterned mask layer 19 further includes a second opening pattern H2 located in the peripheral region R2. Simultaneously with forming the first trench T1, the patterned mask layer 19 also includes etching the fill layer 17 located below the second opening pattern H2 to form at least one second trench T2, wherein the second trench T2 exposes the substrate 10. Simultaneously with forming the first recess S1, the patterned mask layer 19 further includes etching the substrate 10 exposed by the second trench T2 to form a second recess S2 below the second trench T2. In one embodiment, the second trench T2 and the second recess S2 are disposed around the core region R1. In some embodiments, the protective layer 24 also covers the sidewalls of the second trench T2.

[0121] Then, execute step S105, as shown in FIG. Figures 1a to 1c As shown, the first trench T1 and the first recess S1 are filled with insulating material to form a first through portion 211 and a first protruding portion 212 , respectively. The first through portion 211 and the first protruding portion 212 constitute the support structure 21 .

[0122] In actual operation, the first through portion 211 and the first protruding portion 212 can be integrally formed and made of the same material, including but not limited to insulating materials such as nitride (e.g., silicon nitride oxide (e.g., silicon oxynitride), oxynitride carbide (e.g., silicon oxynitride carbide), etc. The first through portion 211 and the first protruding portion 212 can be deposited by one or more thin film deposition processes, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or any combination thereof.

[0123] The support structure 21 provided in the present disclosure is used to support the stacked structure ST located on the substrate 10, wherein the support structure 21 includes a first through portion 211 and a first protruding portion 212, the first through portion 211 extends in the vertical direction in the isolation trench T4 and covers the side walls of the first active portion 121 and the first sacrificial portion 111, the first protruding portion 212 is located below the first through portion 211 and embedded in the substrate 10, and the first protruding portion 212 can enhance the firmness of the combination of the support structure 21 and the substrate 10, avoid or alleviate the support structure 21 from falling off the substrate 10, thereby improving the mechanical stability of the support structure 21, and further improving the support effect on the stacked structure ST; in addition, in subsequent processes, the filling layer 17 and the sacrificial layer 11 can be removed to perform subsequent processing on the active layer 12, and each active layer 12 will be suspended and spaced apart on the substrate 10. The support structure 21 with the first protruding portion 212 provided in the embodiment of the present disclosure plays a good supporting role for multiple active layers 12, and can avoid the collapse of the active layer 12.

[0124] In one embodiment, the support structure 21 includes a plurality of first through-portions 211 and a plurality of first protruding portions 212, each of which is arranged in an interval along the second direction. In a specific embodiment, the plurality of first through-portions 211 and the plurality of first active portions 121 are arranged alternately along the second direction. In some embodiments, the first through-portions 211 also cover the sidewalls of the cap layer 14. The plurality of first through-portions 211 arranged in the second direction are interconnected with the cap layer 14 to jointly support other structures located on the substrate 10. This further increases the mechanical stability of the support structure 21 and the supporting effect of the support structure 21.

[0125] In one embodiment, insulating material is filled within the first trench T1, the first recess S1 below the first trench T1, and the third trench T3 in the first trench group T11, the second trench group T12, and the third trench group T13, respectively, to form a first support structure SS1, a second support structure SS2, and a third support structure SS3 arranged along a first direction. The first support structure SS1 covers the end of the first active portion 121 near the second active portion 122 and is disposed adjacent to the second active portion 122. The third support structure SS3 covers the end of the first active portion 121 away from the second active portion 122. The second support structure SS2 is located between the first support structure SS1 and the third support structure SS3. The provision of multiple support structures 21 can further enhance the support for the stacked structure ST or the active layer 12 after the filling layer 17 and the sacrificial layer 11 are removed. In some embodiments, the cap layer 14 is simultaneously connected to the first support structure SS1, the second support structure SS2, and the third support structure SS3, further enhancing the mechanical stability and support effectiveness of the support structures 21.

[0126] In one embodiment, the third support structure SS3 further includes a connecting portion 214, which is located within the third trench T3 and extends along the second direction. The connecting portion 214 is disposed adjacent to the end of the first active portion 121 away from the second active portion 122 and is connected to a plurality of first through-portions 211 spaced apart along the second direction. A first protrusion 212 extending along the second direction is also formed below the connecting portion 214. The first protrusion 212 located below the connecting portion 214 is connected to a plurality of first protrusions 212 located below the first through-portions 211. This provides the third support structure SS3 with greater mechanical stability, further enhancing the supporting effect of the third support structure SS3. In actual operation, the first through-portions 211 and the connecting portion 214 of the third support structure SS3 are integrally formed and made of the same material.

[0127] Continue to see Figures 1a to 1c In one embodiment, before filling the first recess S1 with the insulating material, the method further includes forming an adhesion layer 23 on the inner wall of the first recess S1 to enhance the adhesion between the first protrusion 212 and the substrate 10, further improving the firmness of the bond between the first protrusion 212 and the substrate 10, and thereby enhancing the support effect of the support structure 21. The material of the adhesion layer 23 includes, but is not limited to, oxides (e.g., silicon oxide), oxynitrides (e.g., silicon oxynitride), oxynitride carbides (e.g., silicon oxynitride carbide), etc., and the material of the adhesion layer 23 can be different from the material of the first protrusion 212. In one specific embodiment, the material of the adhesion layer 23 is an oxide (e.g., silicon oxide), which can be formed by a deposition process or by performing a thermal oxidation process on the substrate 10.

[0128] See again Figures 1a to 1c , while filling the first trench T1 and the first recess S1 with insulating material to form the first through portion 211 and the first protrusion 212, respectively, it also includes: filling the second trench T2 and the second recess S2 with insulating material to form the second through portion 221 and the second protrusion 222, respectively, and the second through portion 221 and the second protrusion 222 constitute the isolation structure 22. In some embodiments, the isolation structure 22 is arranged around the core region R1, and the isolation structure 22 plays an isolating and supporting role for the structure located in the core region R1. In the embodiment of the present disclosure, the second protrusion 222 embedded in the substrate 10 is provided below the second through portion 221, which can improve the firmness of the bonding between the isolation structure 22 and the substrate 10, thereby improving the support effect of the isolation structure 22 on the core region R1. In actual operation, the isolation structure 22 can be formed in the same step as the support structure 21 to save process steps.

[0129] In one embodiment, an adhesive layer 23 is further disposed between the second protrusion 222 and the substrate 10 to improve adhesion between the second protrusion 222 and the substrate 10 .

[0130] Figures 13a to 13b as well as Figures 1a to 1c In the semiconductor structure shown, in the second direction, the width of the first recess S1 is the same as or similar to the width of the first trench T1. Figures 14a to 14b As shown, in another embodiment of the present disclosure, after forming the first recess S1 , the substrate 10 may be further laterally etched to form the first recess S1 with a larger width, thereby forming a first protrusion 212 with a larger width.

[0131] Specifically, after forming the first recess S1, the method further includes: side etching the substrate 10 exposed by the first recess S1 so that the maximum width of the first recess S1 is greater than the width of the first trench T1 in the second direction. In some embodiments, the maximum width of the first recess S1 is also greater than the width of the first trench T1 in the first direction.

[0132] In practice, an isotropic wet etching or gaseous etching process can be used to further laterally etch the substrate 10 to expand the width of the first recess S1. In the disclosed embodiment, a first recess S1 having the same or similar width as the first trench T1 is first formed, and then the substrate 10 is laterally etched to expand the width of the first recess S1. This two-step process of forming the first recess S1 reduces the difficulty of forming a first recess S1 having a larger width. However, the present invention is not limited to this. Alternatively, after forming the first trench T1, an isotropic wet etching process can be used to etch the substrate 10, thereby forming a first recess S1 having a larger width than the first trench T1 in a single step.

[0133] Then, step S105 is performed to form a first through portion 211 and a first protruding portion 212 in the first trench T1 and the first recess S1, respectively, to form a Figure 2a to Figure 2b In the semiconductor structure shown, the maximum width of the first protrusion 212 in the second direction is greater than the width of the first through portion 211 in the second direction. At the same time, in the first direction, the first protrusion 212 is at least partially located in the substrate 10 below the first active portion 121. In this way, the firmness of the combination between the support structure 21 and the substrate 10 is further increased, and the mechanical stability of the support structure 21 is enhanced.

[0134] In one embodiment, in the second direction, the width of the top of the second recess S2 is smaller than the maximum width of the first recess S1. Thus, the width of the top of the formed second protrusion 222 is smaller than the maximum width of the first protrusion 212, and the first protrusion 212 can be better embedded in the substrate 10. Figures 14a to 14b as well as Figure 2a to Figure 2b The first recess S1 and the first protrusion 212 shown in FIG. 2 have an arc-shaped profile. However, the present invention is not limited thereto. In some embodiments, the cross-sections of the first recess S1 and the first protrusion 212 in the vertical direction may also be trapezoidal, stepped, or the like.

[0135] See again Figures 14a to 14b While the substrate 10 exposed by the first recess S1 is laterally etched, the substrate 10 exposed by the second recess S2 is laterally etched so that the maximum width of the second recess S2 in the second direction is also greater than the width of the second trench T2. Figure 2a to Figure 2b As shown, a second protrusion 222 and a second through-portion 221 are formed in the second recess S2 and the second groove T2, respectively, and in the extension direction of the second through-portion 221 parallel to the plane of the substrate 10, the width of the second protrusion 222 is greater than the width of the second through-portion 221, further improving the firmness of the combination between the isolation structure 22 and the substrate 10.

[0136] It should be noted that in order to better illustrate the positional relationship of each structural layer in the semiconductor structure, Figure 13a 、 Figure 14a 、 Figure 1a 、 Figure 1c as well as Figure 2b The protective layer 24 is omitted.

[0137] In the embodiment of the present disclosure, the substrate 10 may also be a SOI (Silicon On Insulator) substrate. Figures 15a to 15b As shown, the substrate 10 includes a first semiconductor layer 101, an insulating layer 102 covering the first semiconductor layer 101, and a second semiconductor layer 103 covering the insulating layer 102. The first trench T1 at least penetrates the second semiconductor layer 103 and exposes the insulating layer 102. Materials of the first semiconductor layer 101 and the second semiconductor layer 103 include, but are not limited to, silicon, and materials of the insulating layer 102 include, but are not limited to, oxide (e.g., silicon oxide).

[0138] Next, if Figures 16a to 16b As shown, the insulating layer 102 exposed by the first trench T1 is etched to form a first recess S1 . The first recess S1 may or may not penetrate the insulating layer 102 . The bottom of the first recess S1 is a flat surface or a curved surface.

[0139] Then, step S105 is performed to form a first through portion 211 and a first protruding portion 212 in the first trench T1 and the first recess S1, respectively, to form a Figure 3a to Figure 3b wherein the first through portion 211 penetrates the second semiconductor layer 103 and connects to the first protruding portion 212 located within the insulating layer 102 . The first protruding portion 212 may penetrate or not penetrate the insulating layer 102 .

[0140] Figures 16a to 16b In the semiconductor structure shown, in the second direction, the width of the first recess S1 is the same as or similar to the width of the first trench T1. Figures 17a to 17bAs shown, in yet another embodiment of the present disclosure, etching the substrate 10 exposed by the first trench T1 to form a first recess S1 includes:

[0141] The insulating layer 102 exposed by the first trench T1 is etched to form a first recess S1. The etching rate of the insulating layer 102 is greater than the etching rate of the first semiconductor layer 101 and the second semiconductor layer 103, so that the width of the first recess S1 formed in the insulating layer 102 in the second direction is greater than the width of the first trench T1 in the second direction.

[0142] Next, step S105 is performed to form a first through portion 211 and a first protruding portion 212 in the first trench T1 and the first recess S1, respectively, to form a Figures 4a to 4b The semiconductor structure shown; wherein, in the second direction, the width of the first protrusion 212 located in the insulating layer 102 is greater than the width of the first through portion 211, and in the first direction, the first protrusion 212 is at least partially located in the substrate 10 below the first active portion 121, and the bottom of the first protrusion 212 is a plane or a curved surface.

[0143] The substrate 10 provided in the embodiment of the present disclosure includes an insulating layer 102. Thus, when forming the first recess S1, the etching rate of the insulating layer 102 can be controlled to be greater than the etching rates of the first semiconductor layer 101 and the second semiconductor layer 103, so that the width of the first recess S1 formed in the insulating layer 102 in the second direction is greater than the width of the first trench T1 in the second direction, thereby making the width of the formed first protrusion 212 in the second direction greater than the width of the first through portion 211 in the second direction, thereby reducing the process difficulty of forming the first protrusion 212 with a larger width.

[0144] See again Figures 15a to 16b as well as Figure 3a to Figure 3b In one embodiment, when the substrate 10 includes the insulating layer 102, the second trench T2 and the second penetrating portion 221 located in the second trench T2 penetrate the second semiconductor layer 103, the second recess S2 and the second protruding portion 222 located in the second recess S2 are located in the insulating layer 102, and the second recess S2 and the second protruding portion 222 may or may not penetrate the insulating layer 102. Figures 17a to 17b as well as Figures 4a to 4b In some embodiments, in the extension direction of the second trench T2 parallel to the plane of the substrate 10, the width of the second recess S2 formed in the insulating layer 102 is greater than the width of the second trench T2, and the width of the second protrusion 222 located in the insulating layer 102 is greater than the width of the second through portion 221.

[0145] It should be noted that although Figures 15a to 17b as well as Figures 3a to 4bThe protection layer 24 is not shown, but may be further formed on the sidewalls of the first trench T1 before forming the first recess S1 .

[0146] like Figures 18a to 18b As shown, in another embodiment of the present disclosure, after forming the first trench T1, the method further includes: laterally etching the first sacrificial portion 111 located below the first opening pattern H1 with the first trench T1 as an opening to form a gap S3 exposing the upper and lower surfaces of the first active portion 121.

[0147] In actual operation, the first sacrificial portion 111 located below the first opening pattern H1 may be removed before or after forming the first recess S1. Although not shown in the figures, when the first sacrificial portion 111 located below the first opening pattern H1 is removed before forming the first recess S1, a protective layer 24 may be formed to cover the surface of the active layer 12 exposed by the gap S3 and the first trench T1 before forming the first recess S1.

[0148] Then, if Figures 5a to 5c As shown, while filling the first trench T1 and the first recess S1 with insulating material to form the first through portion 211 and the first protruding portion 212 respectively, it also includes: filling the gap S3 with insulating material to form a horizontal portion 213 covering the upper and lower surfaces of the first active portion 121, the horizontal portion 213 extends along the second direction and intersects with the first through portion 211, and the first through portion 211, the first protruding portion 212 and the horizontal portion 213 together constitute a support structure 21.

[0149] In one embodiment, there are multiple horizontal portions 213, and the multiple horizontal portions 213 are arranged in a direction perpendicular to the plane of the substrate 10, and the multiple first through portions 211 and the multiple horizontal portions 213 cross and connect with each other to form a structure extending along the second direction and surrounding the multiple first active portions 121, further improving the supporting effect of the support structure 21.

[0150] It should be noted that although Figures 2a to 5c The adhesive layer 23 is not shown in the figure, but in actual operation, before forming the first protrusion 212 and the second protrusion 222, an adhesive layer 23 may be formed. Figures 2a to 5c FIG. 4 shows that an adhesion layer 23 is formed on the sidewalls of the first recess S1 and the second recess S2 .

[0151] It should be noted that the above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, and forming an initial stacking structure on the substrate, wherein the initial stacking structure includes sacrificial layers and active layers alternately stacked in sequence along a vertical direction; Patterning the initial stacked structure to form an isolation trench and a stacked structure, wherein the stacked structure includes first sacrificial portions and first active portions alternately stacked in a vertical direction, wherein a plurality of the first sacrificial portions and a plurality of the first active portions extend along a first direction and are spaced apart along a second direction; wherein the second direction intersects the first direction and is parallel to the substrate plane; forming a filling layer in the isolation trench; removing a portion of the filling layer and a portion of the substrate to form a first trench extending in a vertical direction and exposing a sidewall of the stacked structure, and a first recess located below the first trench and formed in the substrate; Filling the first groove and the first recess with insulating material to form a first through portion and a first protrusion, respectively, wherein the first through portion and the first protrusion constitute a support structure; After forming the first trench, the method further includes: Laterally etching the first sacrificial portion below the first opening pattern using the first trench as an opening to form a gap exposing the upper surface and the lower surface of the first active portion; While filling the first groove and the first recess with insulating material to form a first through portion and a first protruding portion respectively, it also includes: filling the insulating material in the gap to form a horizontal portion covering the upper surface and the lower surface of the first active portion, the horizontal portion extending along the second direction and intersecting with the first through portion, the first through portion, the first protruding portion and the horizontal portion together constitute the support structure.

2. The manufacturing method according to claim 1, characterized in that Removing a portion of the filling layer and a portion of the substrate to form the first trench and the first recess comprises: forming a patterned mask layer on the stacked structure and the filling layer, wherein the patterned mask layer includes a first opening pattern extending along the second direction; removing the filling layer below the first opening pattern to form the first trench, wherein the bottom of the first trench exposes the substrate; The substrate exposed by the first trench is etched to form the first recess.

3. The manufacturing method according to claim 2, characterized in that Before etching the substrate exposed by the first trench to form the first recess, the method further includes: forming a protection layer, the protection layer covering a bottom surface of the first trench and a surface of the first active portion exposed by the first trench; The protection layer at the bottom of the first trench is removed to expose the substrate.

4. The manufacturing method according to claim 1, characterized in that After forming the first recess, the method further includes: The substrate exposed by the first recess is laterally etched so that a maximum width of the first recess in the second direction is greater than a width of the first trench.

5. The manufacturing method according to claim 2, characterized in that The substrate includes a first semiconductor layer, an insulating layer covering the first semiconductor layer, and a second semiconductor layer covering the insulating layer; The first trench at least penetrates the second semiconductor layer and exposes the insulating layer; Etching the substrate exposed by the first trench to form the first recess, comprising: The insulating layer exposed by the first trench is etched to form the first recess, and the etching rate of the insulating layer is greater than the etching rate of the first semiconductor layer and the second semiconductor layer, so that the width of the first recess formed in the insulating layer in the second direction is greater than the width of the first trench in the second direction.

6. The manufacturing method according to claim 1, characterized in that Before filling the first recess with the insulating material, the method further includes: forming an adhesion layer on an inner wall of the first recess.

7. A semiconductor structure prepared according to any one of claims 1 to 6, characterized in that: include: substrate; a stacked structure located on the substrate, the stacked structure comprising a plurality of active layers spaced apart along a vertical direction, the active layer comprising a plurality of first active portions extending along a first direction and spaced apart along a second direction, wherein the second direction intersects the first direction and is parallel to the substrate plane; The support structure includes a first through portion and a first protruding portion, wherein the first through portion extends in a vertical direction and covers the sidewalls of the plurality of first active portions, and the first protruding portion is located below the first through portion and embedded in the substrate.

8. The semiconductor structure according to claim 7, wherein: In the second direction, the maximum width of the first protruding portion is greater than the width of the first through portion.

9. The semiconductor structure according to claim 7, wherein: The substrate includes a first semiconductor layer, an insulating layer covering the first semiconductor layer, and a second semiconductor layer covering the insulating layer. The first through-portion penetrates the second semiconductor layer and connects to a first protrusion located in the insulating layer. In the second direction, the width of the first protrusion located in the insulating layer is greater than the width of the first through-portion.

10. The semiconductor structure according to claim 7, wherein: The supporting structure has a plurality of first through-portions and a plurality of first protruding portions, and the plurality of first through-portions and the plurality of first protruding portions are arranged at intervals along the second direction, and in the first direction, the first protruding portions are at least partially located in the substrate below the first active portion.

11. The semiconductor structure according to claim 10, wherein: The support structure further includes a horizontal portion extending along the second direction and intersecting the first penetration portion, wherein the horizontal portion covers an upper surface and a lower surface of the first active portion.

12. The semiconductor structure according to claim 7, wherein: The semiconductor structure further includes an adhesion layer located between the first protrusion and the substrate.

13. The semiconductor structure according to claim 7, wherein: The active layer further includes a second active portion extending along the second direction and connected to ends of the plurality of first active portions; There are multiple support structures, and the multiple support structures include a first support structure, a second support structure and a third support structure arranged at intervals along a first direction, the first support structure covers the end of the first active part close to the second active part and is arranged adjacent to the second active part, the third support structure covers the end of the first active part away from the second active part, and the second support structure is located between the first support structure and the third support structure.

14. The semiconductor structure according to claim 7, wherein: The substrate includes a core area and a peripheral area surrounding the core area, and the stacked structure is located in the core area; the semiconductor structure also includes an isolation structure located in the peripheral area, and the isolation structure includes a second through-portion extending in a vertical direction and a second protrusion located below the second through-portion and embedded in the substrate.

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