Method for manufacturing a semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device, belonging to the field of semiconductor technology, the manufacturing method comprising: providing a substrate, forming a stack of at least two layers of oxide layer and nitride layer on the substrate; etching the stack and part of the substrate to form a shallow trench and an active area; etching back the stack to expand the opening of the shallow trench; depositing an isolation medium in the shallow trench, the surface of the isolation medium being flush with the surface of the stack; etching and removing the nitride layer and the oxide layer in sequence, and when removing the oxide layer, removing part of the isolation medium at the interface of the shallow trench and the active area simultaneously; performing ion implantation on the substrate to form a well area and a channel doping area, the channel doping area being located on the well area, and the ion implantation amount at the edge and the center of the active area being equal; forming a gate structure on the channel doping area. The manufacturing method of the semiconductor device provided by the present invention can avoid the abnormal reduction of the threshold voltage of the narrow channel device due to the inability to perform normal channel doping, thereby improving the electrical performance of the semiconductor device.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a method for manufacturing a semiconductor device. Background Art

[0002] With the development of microelectronics technology, the size of semiconductor devices has been miniaturized to achieve high-density and high-performance large-scale integrated circuits. The isolation process between semiconductor devices has become increasingly important. The isolation of active devices is achieved by using a shallow trench isolation structure (STI). At the top corners of the active area and the shallow trench isolation structure, the top corners of the active area are rounded to improve the electrical performance of the semiconductor device and facilitate the deposition of the isolation medium. However, during the formation process, the edge of the active area is easily covered by the isolation medium of the shallow trench isolation structure, resulting in the problem that the doping ions cannot be injected into the edge of the active area during channel doping, thereby causing the threshold voltage of the narrow channel device to drop. Summary of the invention

[0003] The object of the present invention is to provide a method for manufacturing a semiconductor device, which can avoid abnormal reduction of threshold voltage of a narrow channel device due to inability to perform normal channel doping, improve the electrical performance of the semiconductor device, and has a simple manufacturing process.

[0004] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0005] Providing a substrate, forming a stack of at least two layers of an oxide layer and a nitride layer on the substrate;

[0006] Etching the stack and a portion of the substrate to form shallow trenches and active areas;

[0007] Back-etching the stack to enlarge the opening of the shallow trench;

[0008] Depositing an isolation dielectric in the shallow trench, wherein a surface of the isolation dielectric is flush with a surface of the stack;

[0009] Sequentially etching and removing the nitride layer and the oxide layer, and when removing the oxide layer, simultaneously removing a portion of the isolation dielectric at the interface between the shallow trench and the active area;

[0010] Performing ion implantation on the substrate to form a well region and a channel doping region, wherein the channel doping region is located on the well region, and the ion implantation amount at the edge and the center of the active region is equal; and

[0011] A gate structure is formed on the channel doping region.

[0012] In one embodiment of the present invention, the manufacturing method further includes:

[0013] forming a pad oxide layer, a sacrificial nitride layer, and a stack of sacrificial oxide layers and pad nitride layers on the substrate;

[0014] After etching, etching back and deposition, the surface of the isolation medium is flush with the surface of the pad nitride layer;

[0015] removing the pad nitride layer;

[0016] The sacrificial oxide layer and part of the isolation medium are removed to form a groove at the interface between the isolation medium and the sacrificial nitride layer, wherein the bottom surface of the groove is flush with the surface of the pad oxide layer, or the bottom surface of the groove is lower than the surface of the pad oxide layer and higher than the surface of the substrate;

[0017] removing the sacrificial nitride layer; and

[0018] The pad oxide layer is used as an ion implantation buffer layer to perform ion implantation to form the well region and the channel doping region.

[0019] In one embodiment of the present invention, the sacrificial oxide layer and the isolation medium are made of the same material.

[0020] In one embodiment of the present invention, the sacrificial oxide layer and a portion of the isolation medium are removed by wet etching, and the wet etching solution is dilute hydrofluoric acid or a buffered oxide etching solution.

[0021] In one embodiment of the present invention, after the well region and the channel doping region are formed, the pad oxide layer is removed, and then the gate structure is formed.

[0022] In one embodiment of the present invention, the etching amount of the stack on one side of the shallow trench is 8nm-15nm.

[0023] In one embodiment of the present invention, the etching amount of the stacked layer on one side of the shallow trench is less than the thickness of the sacrificial nitride layer.

[0024] In one embodiment of the present invention, when removing a portion of the isolation dielectric, the etching thickness of the isolation dielectric is greater than the thickness of the sacrificial nitride layer.

[0025] In one embodiment of the present invention, before depositing the isolation dielectric, a liner oxide layer is formed on the sidewalls and the bottom of the shallow trench and on the substrate exposed at the top of the shallow trench.

[0026] In one embodiment of the present invention, the doping concentration of the channel doping region is greater than the doping concentration of the well region.

[0027] In summary, the present invention provides a method for manufacturing a semiconductor device. The unexpected technical effect of the present application is that it can prevent the accumulation of charges at the top corners and cause the gate dielectric layer to be broken down, increase the effective width of the device, and thus increase the turn-on current of the device. When forming the well region and the channel doping region, there is no thick isolation dielectric on the edge of the active area, which can avoid the problem of abnormal reduction of the threshold voltage of the narrow channel device due to the inability to perform normal channel doping, thereby improving the electrical performance of the semiconductor device. It can solve the problem that the doped ions cannot be injected into the edge of the active area, and during the etching process, no mask process is required, and a simple process can be used to solve the problem that ions cannot be injected into the edge of the active area, without increasing the process difficulty, which is beneficial to enterprise production. The method for forming a semiconductor device can be applied to any narrow channel semiconductor device and has a wide range of applications.

[0028] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0030] Figure 1 FIG. 4 is a top view of a semiconductor device in one embodiment.

[0031] Figure 2 for Figure 1 Cross-sectional view of substrate and pad oxide along AA direction.

[0032] Figure 3 for Figure 1 A cross-sectional view of a stack of oxide and nitride layers formed on a substrate along the AA direction.

[0033] Figure 4 for Figure 1 Cross-sectional view of the shallow trench located along the AA direction.

[0034] Figure 5 for Figure 1 Cross-sectional view of shallow trenches formed along the AA direction.

[0035] Figure 6 for Figure 1 Cross-sectional view of the oxide layer and nitride layer stack on both sides of the shallow trench being etched back along the AA direction.

[0036] Figure 7 for Figure 1 A cross-sectional view of a liner oxide layer formed along the AA direction.

[0037] Figure 8 for Figure 1 Cross-sectional view of the isolation dielectric after planarization along the AA direction.

[0038] Fig. 9 for Figure 1 Cross-sectional view after removing the pad nitride layer along the AA direction.

[0039] Fig.10 for Figure 1 Cross-sectional view of a recess formed by removing the sacrificial oxide layer along the AA direction.

[0040] Fig.11 for Figure 1 Cross-sectional view of removing the sacrificial nitride layer along the AA direction.

[0041] Fig.12 for Figure 1 A cross-sectional view of a well region and a channel doping region formed along the AA direction.

[0042] Fig.13 for Figure 1 Cross-sectional view of removing the pad oxide layer along the BB direction.

[0043] Fig.14 for Figure 1 A cross-sectional view of a gate structure formed along direction BB.

[0044] Fig.15 for Figure 1 A cross-sectional view of the semiconductor device after a heavily doped region is formed along direction BB.

[0045] Description of labels:

[0046] 10. substrate; 101. first well region; 102. second well region; 11. pad oxide layer; 12. sacrificial nitride layer; 13. sacrificial oxide layer; 14. pad nitride layer; 15. patterned photoresist layer; 151. first opening; 16. shallow trench; 161. liner oxide layer; 17. isolation dielectric; 171. groove; 18. shallow trench isolation structure; 19. first channel doping region; 20. second channel doping region; 21. gate dielectric layer; 221. first gate structure; 222. second gate structure; 231. first lightly doped region; 232. second lightly doped region; 24. sidewall structure; 251. first heavily doped region; 252. second heavily doped region. DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0049] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0050] See also Figure 1 As shown, in one embodiment of the present invention, a plurality of semiconductor devices are arranged on a substrate 10, and the semiconductor devices are, for example, narrow channel devices. In the present application, for example, a metal-oxide-semiconductor field-effect transistor (MOS) is taken as an example for description, wherein a plurality of semiconductor devices are isolated by a shallow trench isolation structure 18. In the present embodiment, for example, the structure and manufacturing method of the semiconductor device are described by taking NMOS transistors and PMOS transistors as examples. Among them, the NMOS transistors and the PMOS transistors are staggered. In other embodiments of the present invention, the plurality of semiconductor devices are, for example, a single type of MOS transistors. Through the present application, the performance of the semiconductor device can be improved and the integration of the semiconductor device can be increased.

[0051] See also Figure 1 to Figure 2 As shown, in one embodiment of the present invention, Figure 2 for Figure 1A cross-sectional view along the AA direction, i.e., a cross-sectional view along the channel width. A substrate 10 is provided, and the substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer or other semiconductor materials formed by III / V compounds, etc., including a stacked structure composed of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, and germanium on insulator. In this embodiment, the substrate 10 is, for example, a silicon wafer, and the substrate 10 is, for example, a P-type substrate.

[0052] See also Figure 2 As shown, in one embodiment of the present invention, a stack of at least two oxide layers and a nitride layer is formed on a substrate 10. In this embodiment, a pad oxide layer 11 is first formed, and the pad oxide layer 11 is, for example, a dense silicon oxide material. The pad oxide layer 11 is prepared, for example, by thermal oxidation, in-situ steam growth (ISSG) or chemical vapor deposition (CVD). In this embodiment, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced into the furnace tube. The substrate 10 reacts with the oxygen at a high temperature to generate a dense pad oxide layer 11. The thickness of the pad oxide layer 11 is, for example, 5nm to 15nm.

[0053] See also Figures 2 to 3 As shown, in one embodiment of the present invention, Figure 3 for Figure 1In the cross-sectional view along the AA direction, after the pad oxide layer 11 is formed, a sacrificial nitride layer 12 is formed on the pad oxide layer 11, and the sacrificial nitride layer 12 is, for example, a material such as silicon nitride, and can be formed on the pad oxide layer 11 by, for example, a low pressure chemical vapor deposition method (LPCVD) or a plasma enhanced chemical vapor deposition method (PECVD). The thickness of the sacrificial nitride layer 12 is, for example, 9nm~16nm. A sacrificial oxide layer 13 is formed on the sacrificial nitride layer 12, and the sacrificial oxide layer 13 is, for example, a material such as silicon oxide, and the sacrificial oxide layer 13 is prepared by, for example, chemical vapor deposition. In this embodiment, the thickness of the sacrificial oxide layer 13 is, for example, 2nm~10nm. A pad nitride layer 14 is formed on the sacrificial oxide layer 13, and the pad nitride layer 14 is, for example, a material such as silicon nitride, and the pad nitride layer 14 is formed, for example, by chemical vapor deposition, physical vapor deposition (PVD) or high-temperature nitridation. The thickness of the pad nitride layer 14 is, for example, 40nm to 80nm. The pad nitride layer 14 acts as a hard mask during shallow trench etching, and the sacrificial nitride layer 12 and the sacrificial oxide layer 13 can control the removal of the isolation medium on the active area during the subsequent removal process, so as to achieve the purpose of ion implantation at the edge of the active area.

[0054] See also Figure 3 to Figure 4 As shown, in one embodiment of the present invention, Figure 4 for Figure 1 In the cross-sectional view along the AA direction, a photoresist layer is formed on the pad nitride layer 14, for example, by spin coating, and a patterned photoresist layer 15 is formed through an exposure and development process. A plurality of first openings 151 are provided on the patterned photoresist layer 15, and the first openings 151 are used to define the position of the shallow trench isolation structure, and the first openings 151 expose a portion of the pad nitride layer 14.

[0055] See also Figures 4 to 5 As shown, in one embodiment of the present invention, Figure 5 for Figure 1In the cross-sectional view along the AA direction, after forming the patterned photoresist layer 15, the patterned photoresist layer 15 is used as a mask, for example, by dry etching to etch in the direction of the substrate 10. During the etching process, the patterned photoresist layer 15 and the pad nitride layer 14 are used as masks to etch toward the substrate 10, and the pad nitride layer 14, the sacrificial oxide layer 13, the sacrificial nitride layer 12, the pad oxide layer 11 and part of the substrate 10 exposed by the first opening 151 are removed to form a shallow trench 16, and the substrate area between the shallow trenches is defined as an active area. During the etching process, part of the pad nitride layer 14 will be etched away, and the thickness of the remaining pad nitride layer 14 on the substrate is, for example, 30nm~60nm. In this embodiment, dry etching is, for example, selective reactive ion etching, ion beam etching or plasma etching, and the etching gas includes, for example, one or a mixture of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), or a combination of these and oxygen (O2).

[0056] See also Figures 5 and 6 As shown, in one embodiment of the present invention, Figure 6 for Figure 1 In the cross-sectional view along the AA direction, after the shallow trench 16 is formed, the stack on the substrate 10 is back-etched, that is, the pad nitride layer 14, the sacrificial oxide layer 13, the sacrificial nitride layer 12 and the pad oxide layer 11 on both sides of the shallow trench 16 are back-etched to expand the opening size of the shallow trench 16. The pad nitride layer 14, the sacrificial oxide layer 13, the sacrificial nitride layer 12 and the pad oxide layer 11 are removed, for example, by wet etching, and the pad nitride layer 14 and the sacrificial nitride layer 12 are etched, for example, by phosphoric acid at 55° C. to 70° C., and the sacrificial oxide layer 13 and the pad oxide layer 11 are etched, for example, by dilute hydrofluoric acid, and the mass fraction of the dilute hydrofluoric acid is, for example, 5% to 15%, so as to control the etching speed and prevent the oxide layer and the nitride layer on both sides of the shallow trench 16 from being etched too much. In this embodiment, the stack etching amount on one side of the shallow trench 16 is, for example, slightly smaller than the thickness of the sacrificial nitride layer 12, and the stack etching amount on one side of the shallow trench 16 along the AA direction is, for example, 8nm~15nm, that is, the top angle of the substrate 10 is exposed, and the opening area of ​​the shallow trench 16 is expanded, which is beneficial to the subsequent deposition of the isolation medium.

[0057] See also Figure 6 to Figure 7 As shown, in one embodiment of the present invention, Figure 7 for Figure 1In the cross-sectional view along the AA direction, after the stack is etched back, a liner oxide layer 161 is formed, for example, by a thermal oxidation method or an in-situ water vapor growth method. In this embodiment, for example, the substrate 10 is placed in a furnace tube at a temperature of 1000° C. to 1100° C., and oxygen mixed with a small amount of hydrogen is introduced into the furnace tube. The substrate 10 reacts with the oxygen at a high temperature to form a dense liner oxide layer 161. At high temperatures, oxygen reacts with the sidewalls and bottom of the shallow trench 16, and the substrate 10 exposed at the top of the shallow trench 16 to form a silicon oxide layer, i.e., the liner oxide layer 161, and the thickness of the liner oxide layer 161 is, for example, 5 nm to 15 nm. In the process of forming the liner oxide layer 161, the liner oxide layer 161 rounds the top and bottom angles of the shallow trench to form rounded corners to prevent charge accumulation at the top angles and cause leakage, and repairs defects formed in the substrate 10 during the shallow trench etching process. Before forming the liner oxide layer 161, a portion of the stack of the pad nitride layer 14, the sacrificial oxide layer 13, the sacrificial nitride layer 12 and the pad oxide layer 11 is removed by etching to increase the exposed top corner area of ​​the substrate 10, which is beneficial to forming a larger fillet in the process of forming the liner oxide layer 161, preventing charge accumulation at the top corner that causes the gate dielectric layer to be punctured, and extending the width of the channel, thereby increasing the effective width of the device and increasing the turn-on current of the device.

[0058] See also Figures 7 and 8 As shown, in one embodiment of the present invention, Figure 8 for Figure 1 In the cross-sectional view along the AA direction, after the liner oxide layer 161 is formed, an isolation dielectric 17 is deposited in the shallow trench 16, for example, by high density plasma chemical vapor deposition (HDP-CVD) or high aspect ratio chemical vapor deposition (HARP-CVD), and the material of the isolation dielectric 17 is the same as the material of the sacrificial oxide layer 13. In this embodiment, the isolation dielectric 17 is, for example, an insulating material such as silicon oxide. After the isolation dielectric 17 is deposited, the isolation dielectric 17 and the pad nitride layer 14 are planarized, for example, by a chemical mechanical polishing (CMP) process, and the isolation dielectric 17 is flush with the height of the pad nitride layer 14 on both sides. In one embodiment of the present invention, after planarization, the remaining thickness of the pad nitride layer 14 is, for example, 30nm to 50nm. By enlarging the opening of the shallow trench 16, the filling quality of the isolation dielectric is improved and defects such as voids are reduced.

[0059] See also Figures 8 to 9 As shown, in one embodiment of the present invention, Fig. 9 for Figure 1In the cross-sectional view along the AA direction, after the isolation dielectric 17 is planarized, the pad nitride layer 14 is removed with the sacrificial oxide layer 13 as an etching stop layer, wherein the pad nitride layer 14 is removed by, for example, dry etching, wet etching, or a combination of dry etching and wet etching. In this embodiment, the pad nitride layer 14 is etched, for example, by phosphoric acid at 150° C. to 165° C. During the etching process, the etching solution has a relatively large etching selectivity for the pad nitride layer 14, the sacrificial oxide layer 13, and the isolation dielectric 17, thereby reducing damage to the sacrificial oxide layer 13 and the isolation dielectric 17.

[0060] See also Figures 9 and 10 As shown, in one embodiment of the present invention, Fig.10 for Figure 1 In the cross-sectional view along the AA direction, after removing the pad nitride layer 14, the sacrificial nitride layer 12 is used as an etching stop layer to remove the sacrificial oxide layer 13 and part of the isolation dielectric 17 to form a groove 171. For example, wet etching is used to remove the sacrificial oxide layer 13 and part of the isolation dielectric 17, and the wet etching solution is, for example, dilute hydrofluoric acid or buffered oxide etching solution (Buffered Oxide Etch, BOE), and the mass fraction of dilute hydrofluoric acid is, for example, 5% to 10%. During the etching process, since the sacrificial oxide layer 13 and the isolation dielectric 17 are made of the same material and the wet etching is isotropic, the isolation dielectric at the interface between the isolation dielectric 17 and the sacrificial nitride layer 12 will be removed synchronously to form a groove 171. In the present application, the etching amount of the isolation dielectric 17 is greater than the back etching amount of the stack, and greater than the thickness of the sacrificial nitride layer 12. In the present embodiment, the etching thickness of the isolation dielectric 17 is, for example, equal to the thickness of the sacrificial nitride layer 12 plus 2nm, that is, the etching thickness of the isolation dielectric 17 is, for example, 11nm to 18nm. Ensure that the bottom of the groove 171 is, for example, flush with the surface of the pad oxide layer 11, or slightly lower than the surface of the pad oxide layer 11, and higher than the surface of the substrate 10, so that the edge of the active area is no longer covered by the thicker isolation dielectric 17, thereby solving the problem that doped ions cannot be injected into the edge of the active area.

[0061] See also Figure 10 to Figure 11 As shown, in one embodiment of the present invention, Fig.11 for Figure 1In the cross-sectional view along the AA direction, after the groove 171 is formed, the sacrificial nitride layer 12 is removed with the pad oxide layer 11 as an etching stop layer, and the sacrificial nitride layer 12 is removed by wet etching, for example. In the present embodiment, the sacrificial nitride layer 12 is etched by phosphoric acid at 150°C to 165°C, for example. After etching, the surface of the pad oxide layer 11 is, for example, flush with the adjacent portion of the isolation medium 17. In another embodiment of the present invention, the surface of the pad oxide layer 11 is, for example, slightly higher than the adjacent portion of the isolation medium 17, and the isolation medium 17 in the shallow trench is defined as a shallow trench isolation structure 18. By providing the sacrificial nitride layer 12 and the sacrificial oxide layer 13, after the isolation medium is deposited, by adding two wet etchings, the problem that the doped ions cannot be injected into the edge of the active area can be solved, and in the two etching processes, no mask process is required, and a simple process can be used to solve the problem that ions cannot be injected into the edge of the active area, without additionally increasing the process difficulty, which is beneficial to enterprise production.

[0062] See also Figure 11 to Figure 12 As shown, in one embodiment of the present invention, Fig.12 for Figure 1 In the cross-sectional view along the AA direction, after removing the sacrificial nitride layer 12, the pad oxide layer 11 on the substrate 10 and the isolation medium are used as ion implantation buffer layers, and ion implantation is performed to form a well region and a channel doping region. The channel doping region is formed on the well region, and the doping concentration of the channel doping region is, for example, greater than the doping concentration of the well region. In this embodiment, the well region, for example, includes a first well region 101 and a second well region 102, and the channel doping region includes a first channel doping region 19 and a second channel doping region 20, and the ions implanted in the first well region 101 and the first channel doping region 19 are, for example, boron (B) or boron fluoride ions (BF2 + ) and other P-type ions to form an NMOS transistor, and the doped ions in the second well region 102 and the second channel doping region 20 are, for example, N-type ions such as phosphorus (P), arsenic (As) or tin (Sn) to form a PMOS transistor. When forming the well region and the channel doping region, the first well region 101 and the first channel doping region 19 are, for example, formed by the same patterned photoresist layer, and the second well region 102 and the second channel doping region 20 are, for example, formed by another patterned photoresist layer. Before forming the well region and the channel doping region, there is no thick isolation medium on the edge of the active region, so that when ion implantation is performed, the doped ions can be implanted into the edge of the active region, and the amount of ions implanted at the edge and the center of the active region is the same, so that the threshold voltage of the narrow channel device can be prevented from being abnormally reduced due to the inability to perform normal channel doping. And the method for forming the channel doping region provided by the present invention can be applied to any semiconductor device including a channel region to suppress the channel effect.

[0063] See also Fig.12In one embodiment of the present invention, after forming the well region and the channel doping region, the substrate 10 is subjected to a rapid thermal annealing process (RTA). The annealing temperature is, for example, 1000°C to 1200°C, the annealing time is, for example, 0.5h to 2h, and the annealing process is performed in a stable gas atmosphere, such as an atmosphere of nitrogen or argon. Through the annealing process, the doped ions in the well region and the channel doping region are activated at the same time, the lattice damage is repaired, the ion implantation is diffused to a suitable depth, and the anti-breakdown capability of the semiconductor device is improved. During the ion implantation and annealing process, the pad oxide layer 11 and the isolation dielectric on the substrate 10 can protect the substrate 10 and reduce the damage to the substrate 10.

[0064] See also Figure 12 to Figure 13 As shown, in one embodiment of the present invention, Fig.13 for Figure 1 A cross-sectional view along the BB direction, i.e., the length direction of the channel. After the substrate 10 is annealed, the pad oxide layer 11 on the substrate 10 is removed, for example, by wet etching, and the wet etching solution is, for example, hydrofluoric acid or buffered oxide etchant (BOE). When removing the pad oxide layer 11, part of the isolation dielectric and the liner oxide layer 161 at the interface between the shallow trench isolation structure 18 and the active area are removed.

[0065] See also Figure 13 to Figure 14 As shown, in one embodiment of the present invention, Fig.14 for Figure 1 In the cross-sectional view along the BB direction, after removing the pad oxide layer 11, a gate structure is formed on the channel doping region, and the gate structure includes, for example, a first gate structure 221 and a second gate structure 222, the first gate structure 221 is arranged on the first channel doping region 19, the second gate structure 222 is arranged on the second channel doping region 20, and a gate dielectric layer 21 is arranged between the gate structure and the channel doping region. Specifically, a gate dielectric layer 21 is formed on the substrate 10, the gate dielectric layer 21 is, for example, silicon oxide or silicon oxynitride, and the thickness is, for example, 5nm to 10nm, and the gate dielectric layer 21 is formed, for example, by thermal oxidation, in-situ water vapor growth method or plasma nitridation. A gate material layer (not shown in the figure) is formed on the gate dielectric layer 21, and the material of the gate material layer is, for example, polysilicon or metal material. In this embodiment, the gate material layer is polysilicon. The gate material layer and the gate dielectric layer 21 are then etched, for example, by dry etching the gate material layer to form a gate structure. After etching the gate material layer, the etching gas is replaced to etch the gate dielectric layer outside the gate structure. In this embodiment, the gate structure can be made of doped or undoped polysilicon, which is selected according to the manufacturing requirements.

[0066] See also Figure 14 to Figure 15 As shown, in one embodiment of the present invention, Fig.15 for Figure 1 In the cross-sectional view along the BB direction, after the gate structure is formed, a lightly doped region is formed in the substrate 10 on both sides of the gate structure, and the doping ion type in the lightly doped region is opposite to the doping ion type in the channel doping region. In the present embodiment, the lightly doped region includes a first lightly doped region 231 and a second lightly doped region 232, the first lightly doped region 231 is formed on both sides of the first gate structure 221, and the doping ions in the first lightly doped region 231 are, for example, N-type ions such as phosphorus, arsenic or tin, and the second lightly doped region 232 is formed on both sides of the second gate structure 222, and the doping ions in the second lightly doped region 232 are, for example, P-type ions such as boron or boron fluoride ions. After the lightly doped region is formed, a sidewall structure 24 is formed on both sides of the gate structure, wherein the sidewall structure 24 is, for example, a single-layer structure or a stacked structure. In the present embodiment, the sidewall structure 24 includes, for example, a stack of silicon oxide and silicon nitride to ensure the stability of the sidewall structure. Specifically, a sidewall dielectric layer (not shown in the figure) is formed on the substrate 10, and the sidewall dielectric layer covers the gate structure, the substrate 10 and the shallow trench isolation structure 18, and the material of the sidewall dielectric layer is, for example, a stack of silicon oxide and silicon nitride. After the sidewall dielectric layer is formed, for example, an etching process such as dry etching can be used to remove the sidewall dielectric layer located on the gate structure and part of the substrate 10, and part of the sidewall dielectric layer on both sides of the gate structure is retained to form a sidewall structure 24, and the height of the sidewall structure 24 is the same as the height of the gate structure. In this embodiment, the shape of the sidewall structure 24 is, for example, an arc shape, and in other embodiments, the sidewall structure 24 can be selected in any shape.

[0067] See also Fig.15 As shown, in one embodiment of the present invention, after the sidewall structure 24 is formed, a heavily doped region is formed in the substrate 10 on both sides of the gate structure, and the doping type of the heavily doped region is the same as the doping type of the lightly doped region, and the doping concentration and depth of the heavily doped region are greater than the doping concentration and depth of the lightly doped region. The heavily doped region includes a first heavily doped region 251 and a second heavily doped region 252, wherein the first heavily doped region 251 is formed in the substrate 10 on both sides of the first gate structure 221, and the second heavily doped region 252 is formed in the substrate 10 on both sides of the second gate structure 222. In the present application, the doping depth of the heavily doped region is greater than the depth of the channel doping region, ensuring that the heavily doped region is in contact with the well region with a low doping concentration, which is beneficial to the expansion of the depletion layer when the drain is applied with a voltage, avoiding an increase in the junction current, increasing the breakdown voltage, and improving the performance of the semiconductor device. By controlling the edges of the active region and the shallow trench isolation structure to form rounded corners, increasing the channel width and length, and increasing the turn-on current of the device, the double peak effect and the reverse narrow channel effect of the MOS transistor can be improved. In addition, the presence of a channel doping region at the edge of the active region can prevent the threshold voltage of the semiconductor device from being abnormally reduced, thereby improving the electrical performance of the semiconductor device.

[0068] In summary, the present invention provides a method for manufacturing a semiconductor device. By optimizing the method for manufacturing a semiconductor device, the unexpected technical effect of the present application is that a larger fillet can be formed at the top corner of the substrate to prevent the accumulation of charge at the top corner and cause the gate dielectric layer to be broken down, and the effective width of the device is increased, thereby increasing the turn-on current of the device, and expanding the opening area of ​​the shallow trench, which is conducive to the deposition of the isolation medium. When forming the well region and the channel doping region, there is no thick isolation medium on the edge of the active region, so that when ion implantation is performed, the doped ions can be implanted into the edge of the active region, and the amount of ions implanted at the edge and the center of the active region is the same, so that the threshold voltage of the narrow channel device can be prevented from being abnormally reduced due to the inability to perform normal channel doping, thereby improving the electrical performance of the semiconductor device. By adding two wet etchings, the problem that the doped ions cannot be implanted into the edge of the active region can be solved, and in the two etching processes, no mask process is required, and a simple process can be used to solve the problem that the ion implantation cannot be performed at the edge of the active region, without additionally increasing the process difficulty, which is conducive to enterprise production. Furthermore, the method for forming a semiconductor device can be applied to any narrow channel semiconductor device and has a wide application range.

[0069] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, forming a stack of at least two layers of an oxide layer and a nitride layer on the substrate; Etching the stack and a portion of the substrate to form shallow trenches and active areas; Back-etching the stack to enlarge the opening of the shallow trench; Depositing an isolation dielectric in the shallow trench, wherein a surface of the isolation dielectric is flush with a surface of the stack; Sequentially etching and removing the nitride layer and the oxide layer, and when removing the oxide layer, simultaneously removing a portion of the isolation dielectric at the interface between the shallow trench and the active area; Performing ion implantation on the substrate to form a well region and a channel doping region, wherein the channel doping region is located on the well region, and the ion implantation amount at the edge and the center of the active region is equal; as well as forming a gate structure on the channel doping region; Wherein, the manufacturing method further comprises: forming a pad oxide layer, a sacrificial nitride layer, and a stack of sacrificial oxide layers and pad nitride layers on the substrate; After etching, etching back and deposition, the surface of the isolation medium is flush with the surface of the pad nitride layer; removing the pad nitride layer; The sacrificial oxide layer and part of the isolation medium are removed to form a groove at the interface between the isolation medium and the sacrificial nitride layer, wherein the bottom surface of the groove is flush with the surface of the pad oxide layer, or the bottom surface of the groove is lower than the surface of the pad oxide layer and higher than the surface of the substrate; removing the sacrificial nitride layer; and The pad oxide layer is used as an ion implantation buffer layer to perform ion implantation to form the well region and the channel doping region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The sacrificial oxide layer and the isolation medium are made of the same material.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The sacrificial oxide layer and part of the isolation medium are removed by wet etching, and the wet etching solution is dilute hydrofluoric acid or buffered oxide etching solution.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the well region and the channel doping region, the pad oxide layer is removed, and then the gate structure is formed.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching amount of the stack on one side of the shallow trench is 8nm~15nm.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The etching amount of the stacked layer on one side of the shallow trench is less than the thickness of the sacrificial nitride layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: When removing part of the isolation medium, the etching thickness of the isolation medium is greater than the thickness of the sacrificial nitride layer.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: Before depositing the isolation dielectric, a liner oxide layer is formed on the sidewall and bottom of the shallow trench and on the substrate exposed at the top of the shallow trench.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The doping concentration of the channel doping region is greater than the doping concentration of the well region.

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