A semiconductor device testing method and system based on narrow current pulse acquisition

Abstract

The invention relates to the field of semiconductor testing technology, and specifically discloses a semiconductor device testing method and system based on narrow current pulse acquisition, comprising: a generating module: inputting a digital card channel connected to a testing device, and converting a voltage pulse into a current pulse and providing it to a chip to be tested; an acquiring module: receiving a current pulse input by a chip and converting it into a voltage pulse, and performing voltage amplification processing through a voltage amplification module; an integrating / following module: inputting the amplified voltage pulse signal into a following module, recapturing the voltage pulse signal at an output end after passing through a following circuit, and calculating the current value of the chip to be tested by a preset calibration coefficient; inputting the amplified voltage pulse signal into an integrating module, measuring the pulse energy through an integrating circuit, and calculating the current pulse energy by the calibration coefficient; and an undersampling module: used for monitoring the pulse amplitude corresponding to a certain time point.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing technology, and in particular to a semiconductor device testing method and system based on narrow current pulse acquisition. Background Art

[0002] As the integration of chips becomes higher and higher, manual testing can no longer meet the needs, so automated test equipment (ATE, Automated Test Equipment) is needed. Because today's chips are becoming more and more complex, ordinary bench tests cannot meet the needs. ATE can detect the integrity of integrated circuit functions and is the final process of integrated circuit manufacturing to ensure product quality. Chip testing is considered to be the last component in the upstream of the semiconductor industry chain. The devices under test are mainly divided into several categories: memory, digital circuits, analog circuits and mixed signal circuits.

[0003] Semiconductor testing is a very important part of the integrated circuit industry. Test equipment provides test conditions for different types of chips. However, existing semiconductor test equipment on the market usually only provides high-speed voltage pulses, and generally does not provide high-speed current pulses. For chips that need to provide narrow current pulse signals for testing (such as ILED, etc.) or need to collect and measure the high-speed current signals output by the chip to be tested, users need to design and develop narrow current pulse generation and collection functions by themselves. The general design is to put the voltage-to-current and current-to-voltage modules directly on the final circuit board. However, this design method is not flexible enough and occupies a large area of ​​the circuit board. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device testing method and system based on narrow current pulse acquisition to solve the above technical problems.

[0005] The purpose of the present invention can be achieved by the following technical solutions:

[0006] A semiconductor device testing system based on narrow current pulse acquisition, comprising:

[0007] Generation module: The input is connected to the digital card channel of the test equipment, and the voltage pulse is converted into a current pulse and provided to the chip under test;

[0008] Acquisition module: receives the current pulses input by the chip and converts them into voltage pulses, and performs voltage amplification processing through the voltage amplification module;

[0009] Integration / following module: the amplified voltage pulse signal is input to the following module, the voltage pulse signal is recaptured at the output end after passing through the following circuit, and the current value of the chip to be tested is calculated by the preset calibration coefficient; the amplified voltage pulse signal is input to the integration module, the pulse energy is measured through the integration circuit, and the current pulse energy is calculated by the calibration coefficient;

[0010] Undersampling module: used to monitor the pulse amplitude corresponding to a certain time point.

[0011] As a further solution of the present invention: the generation module uses the classic Howland current source, and adds a primary voltage follower and a secondary voltage amplifier module at the front end; and a relay is set at the output end, one end of the relay is used for output, and the other end is used for calibration.

[0012] As a further solution of the present invention: the calibration adopts a multi-point segmented calibration method, and its specific steps are as follows:

[0013] Get the minimum input voltage value V min and the maximum input voltage V max ;

[0014] V min To V max The 11 input voltage values ​​are evenly divided into 10 parts, and after sorting, the voltage values ​​V1, V2, V3, ..., V 11 ;

[0015] The output currents I1, I2, I3, ..., I corresponding to the 11 input voltages are measured respectively. 11 ;

[0016] Calculate the gain and deviation corresponding to each section respectively.

[0017] As a further solution of the present invention: In the multi-point segmented calibration process, the specific method for calculating the gain and deviation is as follows:

[0018] Calculate the gain and bias of the first segment:

[0019] Assume that the gain of voltage to current is G1 and the deviation is O1, then:

[0020] I1=V1*G1+O1

[0021] I2=V2*G1+O1

[0022] It follows that:

[0023] Gain G1 = (I2-I1) / (V2-V1)

[0024] Deviation O1=I1-V1*G1

[0025] Similarly, we get the gains of the other 9 segments G2-G 10 and Deviation O2-O 10 ;

[0026] And after obtaining the expected current value I out When I out Successively with I1 to I 11 Compare, when Iout ≥ I x And I out ≤I x+1 When the corresponding G x and O x , and calculate the voltage V required at the input x =(I out -O x ) / G x , x∈[1,11) and is a positive integer.

[0027] As a further solution of the present invention: the acquisition module is divided into a current-to-voltage module, a voltage amplification module, and an integration / following module;

[0028] The current-to-voltage module is used to convert current pulses into voltage pulses;

[0029] The voltage amplifier module is divided into primary amplifier and secondary amplifier. The primary amplifier has two gears, 8 times amplification and 0.5 times amplification respectively.

[0030] The output of the voltage amplifier module is connected to the integration / following module through a relay, and the pulse energy is obtained through the integration circuit or the voltage pulse is output by the following circuit.

[0031] As a further solution of the present invention: the acquisition module presets a calibration input pin, and the module can be calibrated through the voltage output pin. The specific method is as follows:

[0032] Get the minimum input voltage value I min and the maximum input current value I max ;

[0033] Will I min To I max The 11 input current values ​​are evenly divided into 10 parts, and after sorting, the current values ​​I1, I2, I3, ..., I 11 ;

[0034] The output voltage values ​​V1, V2, V3, ..., V corresponding to the 11 input currents are measured respectively. 11 ;

[0035] Calculate the gain and deviation corresponding to each section respectively;

[0036] Among them, the gain and deviation of the first segment are calculated:

[0037] Assume the gain of current to voltage is G1 and the deviation is O1, then:

[0038] V1=I1*G1+O1

[0039] V2=I2*G1+O1

[0040] It follows that:

[0041] Gain G1 = (V2-V1) / (I2-I1)

[0042] Deviation O1=V1-I1*G1

[0043] Similarly, we get the gains of the other 9 segments G2-G 10 and Deviation O2-O 10 ;

[0044] And measured output V out When V out Successively with V1 to V 11 Comparison, when Vout ≥ V x And V out ≤V x+1 When the corresponding G x and O x , and calculate the current I required at the input x =(V out -O x ) / G x , x∈[1,11) and is a positive integer.

[0045] As a further solution of the present invention: the acquisition module further includes an undersampling module, and the undersampling module includes:

[0046] Pulse input: The input signal is the voltage pulse signal after amplification;

[0047] Input synchronization signal: output the synchronization pulse signal of the pulse time point to be detected, the synchronization pulse signal is a jump signal from low to high;

[0048] DC output: After a periodic pulse signal has been continuously followed for several cycles, the output will gradually approach the pulse voltage value corresponding to the synchronization signal time point input by the user;

[0049] The specific steps of the undersampling method are as follows:

[0050] Set the digital board starting comparison voltage V OH =0V, and the comparison starts from time 0, and a comparison is performed every preset time interval until the preset comparison cycle is reached. When the sampling voltage at the comparison time is greater than V OHIf the sampling voltage is greater than V OH If it is smaller, output L;

[0051] Gradually increase the comparison voltage V OH , and repeat the above comparison process to obtain the output matrix;

[0052] The dividing line between L and H in the output matrix is ​​used as the shape of the pulse waveform.

[0053] A semiconductor device testing method based on narrow current pulse acquisition, comprising:

[0054] The input is connected to the digital card channel of the test equipment and converts the voltage pulse into current pulse to provide to the chip under test;

[0055] Receive the current pulse input by the chip and convert it into a voltage pulse, and perform voltage amplification processing through the voltage amplification module;

[0056] The amplified voltage pulse signal is input to the follower module, and the voltage pulse signal is recaptured at the output end after passing through the follower circuit, and the current value of the chip to be tested is calculated by the preset calibration coefficient; the amplified voltage pulse signal is input to the integration module, and the pulse energy is measured through the integration circuit, and the current pulse energy is calculated by the calibration coefficient;

[0057] Monitor the pulse amplitude corresponding to a certain time point.

[0058] Beneficial effects of the present invention: The first innovation of the present invention is to modularize the functions, which are functional modules designed based on the test equipment. It has a small size, is easy to use and flexible, improves the performance of the test equipment, and reduces the project development cycle and cost. In addition, the present invention designs a method for implementing undersampling that combines software and hardware. Furthermore, in order to reduce power consumption, a power switching circuit is designed to minimize power consumption and reduce module heating. At the same time, in order to reduce the occupied PCB board area, this module is installed vertically to save the test board area. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The present invention will be further described below in conjunction with the accompanying drawings.

[0060] Figure 1 It is a structural schematic diagram of a semiconductor device testing system based on narrow current pulse acquisition of the present invention;

[0061] Figure 2 It is a schematic diagram of the structure of the generation module in the present invention;

[0062] Figure 3 It is a structural schematic diagram of the acquisition module of the present invention;

[0063] Figure 4 It is a structural schematic diagram of the undersampling module of the present invention;

[0064] Figure 5 It is a diagram of the positive and negative terminal supply voltages of the power supply module of the present invention;

[0065] Figure 6 It is a schematic diagram of the principle of voltage switching of the power supply module of the present invention;

[0066] Figure 7 is a schematic diagram of 20-row comparison results in the undersampling method of the present invention;

[0067] Figure 8 is a schematic diagram of 30-line comparison results in the undersampling method of the present invention;

[0068] Fig. 9 is a schematic diagram of the irregular 30-row comparison results in the undersampling method of the present invention;

[0069] Fig.10 It is a schematic diagram of a circuit for converting current into voltage in an embodiment of the present invention;

[0070] Fig.11 It is a circuit schematic diagram of current-to-voltage conversion in one embodiment of the present invention. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0072] like Figure 1 As shown, the present invention is a semiconductor device testing system based on narrow current pulse acquisition, comprising:

[0073] The input of the generation module is connected to the digital board channel of the test equipment, and the voltage pulse is converted into a current pulse through the input module and provided to the chip under test.

[0074] The current pulse output by the chip is connected to the input of the acquisition module. After passing through the current-to-voltage module, the signal further passes through the voltage amplification module. Through the follower circuit, the user can capture the voltage pulse signal at the output end, and the current value of the chip to be tested can be calculated by the calibration coefficient calculated in advance; the pulse energy can be measured through the integration circuit, and the current pulse energy can be calculated by the calibration coefficient; through the undersampling module, the user can monitor the pulse amplitude corresponding to a certain point in time.

[0075] See also Figure 2It can be seen that the acquisition module uses the classic Howland current source and adds a first-level voltage follower and a second-level voltage amplifier module at the front end, thereby increasing the input impedance and the output current range. A relay is set at the output end, one end is used for output and the other end is used for calibration. The calibration path is shared by 8 channels. Since calibration only needs to be performed once before mass testing, the design of the present invention supports serial calibration and saves calibration resources. The typical calibration method is as follows:

[0076] It is known that when the input terminal supplies power V1, the current measured at the output terminal VI is I1;

[0077] It is known that when the input terminal supplies power V2, the current measured at the output terminal VI is I2;

[0078] Assuming the voltage-to-current gain is G and the deviation is O, then:

[0079] ① I1=V1*G+O;

[0080] ② I2=V2*G+O;

[0081] By deduction, we can conclude that:

[0082] ① Gain G = (I2-I1) / (V2-V1);

[0083] ② Deviation O=I1-V1*G;

[0084] When the user wants to output I3, the voltage V3=(I3-O) / G required at the input terminal.

[0085] The existing calibration method generally only performs single-point Gain calibration, or performs Gain and Offset calculations through the above two-point calibration method. The present invention uses a multi-point segmented calibration method to reduce the nonlinear effect, and the specific method is as follows:

[0086] It is known that the minimum input voltage range of the module is V min , the maximum is V max ;

[0087] V min To V max The input voltage values ​​are divided into 10 parts in total, and the output currents corresponding to the 11 input voltages are measured as follows:

[0088] V1→I1

[0089] V2→I2 ...

[0091] V 10 →I 10

[0092] V 11 →I11

[0093] Calculate the gain and deviation corresponding to each segment respectively; for example, the calculation of the first segment is as follows:

[0094] Assume that the gain of voltage to current is G1 and the deviation is O1, then:

[0095] ① I1=V1*G1+O1;

[0096] ② I2=V2*G1+O1;

[0097] By deduction, we can conclude that:

[0098] ① Gain G1=(I2-I1) / (V2-V1);

[0099] ② Deviation O1=I1-V1*G1;

[0100] Similarly, the corresponding gains G2-G of the other 9 segments can be deduced. 10 and Deviation O2-O 10 .

[0101] When the user wants to get a current I out When I out Successively with I1 to I 11 Compare, when I ou ≥I x And I out ≤I x+1 When the corresponding G x and O x , the voltage V required at the input x =(I out -O x ) / G x .

[0102] like Figure 3 As shown, the acquisition module is divided into a current-to-voltage module, a voltage amplification module, and an integration and following module. The current-to-voltage module can convert current pulses into voltage pulses; the voltage amplification module is divided into primary amplification and secondary amplification. The primary amplification has two gears, 8x amplification and 0.5x amplification, and the secondary amplification uses a dedicated amplification chip; the output of the amplification module is connected to the integration and following module through a relay, and the user can obtain pulse energy through integration or follow the output voltage pulse.

[0103] The acquisition module has preset calibration input pins. The module can be calibrated through the voltage output pin. The typical calibration method is similar to that of the generation module:

[0104] When the current I1 at the calibration input is known, the voltage measured at the voltage output is V1;

[0105] When the current I2 at the calibration input is known, the voltage measured at the voltage output is V2;

[0106] Assuming the total gain of current to voltage is G and the total deviation is O, then:

[0107] ① V1=I1*G+O;

[0108] ② V2=I2*G+O;

[0109] By deduction, we can conclude that:

[0110] ① Gain G = (V2-V1) / (I2-I1);

[0111] ② Deviation O=V1-I1*G;

[0112] When the user measures the output as V3, it can be deduced that the input current is I3=(V3-O) / G.

[0113] The existing calibration method generally only performs single-point Gain calibration, or performs Gain and Offset calculations through the above two-point calibration method. This design uses a multi-point segmented calibration method to reduce the impact of nonlinearity. The specific method is as follows:

[0114] It is known that the minimum input current range of a certain gear of the module is I min , the maximum is I max .

[0115] Will I min To I max The input current values ​​are divided into 10 parts in total, and the output voltages corresponding to the 11 input currents are measured as follows:

[0116] I1→V1

[0117] I2→V2 ...

[0119] I 10 →V 10

[0120] I 11 →V 11

[0121] Calculate the gain and deviation corresponding to each segment separately. For example, the calculation of the first segment is as follows:

[0122] Assume the current-to-voltage gain is G1 and the deviation is O1, then:

[0123] ① V1=I1*G+O;

[0124] ② V2=I2*G+O;

[0125] By deduction, we can conclude that:

[0126] ① Gain G1=(V2-V1) / (I2-I1);

[0127] ② Deviation O1=V1-I1*G1;

[0128] Similarly, the corresponding gains G2-G of the other 9 segments can be deduced. 10 and Deviation O2-O 10 ;

[0129] When the user measures the output as V out When V out Successively with V1 to V 11 Compare, when V out ≥V x And V out ≤V x+1 When the corresponding G x and O x , and inversely deduce the current value I x =(V out -O x ) / G x ;

[0130] Current-to-voltage module: Utilize the virtual short and virtual short of the operational amplifier to convert current into voltage through a 100-ohm resistor, and output it differentially through the output and positive end of the operational amplifier.

[0131] Voltage amplifier module: It is divided into primary differential amplifier and secondary amplifier. The primary differential amplifier has two gears controlled by CB (Control Bit) 2 and 3. The secondary amplifier uses a dedicated precision instrument amplifier AD853 for amplification, and the amplification gain and deviation can be adjusted.

[0132] Integral / Follower Module: The amplified voltage pulse can be integrated to output pulse energy or the integrating capacitor can be short-circuited to realize the voltage following function.

[0133] like Figure 4 As shown, the undersampling module includes:

[0134] Pulse input: The input signal is an amplified voltage pulse signal

[0135] Input synchronization signal: The user outputs the synchronization pulse signal at the pulse time point that he wants to detect. It is a jump signal from low to high.

[0136] DC output: After a periodic pulse signal has been continuously followed for several cycles, the output will gradually approach the pulse voltage value corresponding to the synchronization signal time point input by the user.

[0137] Since both the undersampling module and the integration module require the use of operational amplifiers, but will not be used at the same time, the operational amplifiers are merged to save resources and space.

[0138] How to implement software undersampling:

[0139] When the pulse width is narrow and the sampling speed of the analog board cannot meet the requirements, this solution uses a digital board to perform undersampling to restore and reconstruct the pulse. The specific implementation method is as follows.

[0140] The digital board can set a comparison voltage (V OH ), there are two types of captured data. When the sampling time voltage is higher than V OH If the voltage is larger than V OH If it is smaller, output L;

[0141] Assume that the output pulse period is 5us, the width is 3us, and the amplitude is 0.1V-0.5V. When there is no high-speed sampling ADC, we use the digital board voltage comparison to perform undersampling, and set a V OH The value and a comparison time point can get an H or L. The specific implementation steps are as follows:

[0142] Step 1: Program the digital board to start comparing the voltage V OH =0V, the programming digital board compares the edge from time 0, and performs a comparison every 100ns to 5us. Since the entire waveform is at V OH (0V), we will get a row of H as follows:

[0143] HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH

[0144] Step 2: Repeat step 1, each time V OH Increase 20mv, the first five times due to V OH Still less than or equal to 100mV, so we will get 5 rows of H as follows:

[0145] HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH

[0146] HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH

[0147] HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH

[0148] HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH

[0149] HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH

[0150] Step 3: Continue to increase V OH 20mV each time, when V OH >100mv, the voltage value before 1us and after 4us is less than V OH , we will get L, which is still greater than V between 1us and 4us OH , we will get H, and then we will get the following data:

[0151] LLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLL

[0152] In V OH >100mv and ≤500mv, we will get 20 lines of data as follows: Figure 7 As shown;

[0153] Step 4: Continue to increase V OH 20mV each time, when V OH When >500mv, all voltage values ​​are less than V OH , we will get full L, and we will get the following waveform:

[0154] LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL

[0155] V OH When the final voltage is increased to 0.6V, we get five rows of data as follows:

[0156] LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL

[0157] LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL

[0158] LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL

[0159] LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL

[0160] LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL

[0161] Step 5: Putting the data obtained in the above steps together, we get the following 30 rows of data. The dividing line between H and L in this figure is the shape of the pulse waveform. It is known that the step in the X direction is set to 100ns and the step in the Y direction is set to 20mv. If we want to know the voltage corresponding to the 1500ns, we can calculate that the number of H corresponding to the 15th (1500ns / 100ns) column is 25, and we get the voltage corresponding to 1500ns as 25*20mv=0.5V. If we want to know the voltage corresponding to the 500ns, we can calculate that the number of H corresponding to the 5th (500ns / 100ns) column is the 5th, and we get the voltage corresponding to 500ns as 5*20mv=0.1V.

[0162] In practical applications, we may capture irregular data, such as Fig. 9 However, we can still calculate the voltage value at the corresponding moment through the appearance, that is, Vt is the number of H corresponding to the t / 100ns column multiplied by 20mv.

[0163] In the existing current-to-voltage conversion methods, such as Fig.10 As shown, there are two main disadvantages:

[0164] 1. The current needs to flow into the reference voltage source. If more channels are turned on at the same time, the reference voltage requirement is higher.

[0165] 2. When different currents pass through a 100Ω resistor, the voltage seen by the chip under test will change. For example, when it is 10mA, the chip under test sees 1V, and if it is 5mA, the chip under test sees 0.5V. This will affect the chip under test and make the test inaccurate.

[0166] In the present invention, reference Fig.11 The sampling circuit in the circuit uses the characteristics of virtual short and virtual open of the op amp to design the circuit as shown in the figure, which can ensure that the voltage seen by the chip under test is always the reference voltage no matter how large the current is. When the chip under test outputs 10mA current, due to the virtual short characteristics of the op amp, the voltages of the op amp V+ and V- are the same, so the voltage seen by the chip is the reference voltage 0V.

[0167] In the present invention, the power supply module supports 12V / 0V and 5V / -5V power supply. When a higher output is required but there is no negative value, it can be switched to 12V / 0V power supply. When a small output value and negative output are required, 5V / -5V power supply is switched, which can reduce power consumption and heat generation. The switching is performed through a control signal, and the switching process is cleverly designed to ensure that the positive end power supply and the negative end power supply never exceed 12V.

[0168] refer to Figure 5 When switching from 12V / 0V to 5V / -5V power supply, the switching process is as follows:

[0169] 12V / 0V→5V / 0V→5V / -5V;

[0170] When switching from 5V / -5V to 12V / 0V power supply, the switching process is as follows:

[0171] 5V / -5V→5V / 0V→12V / 0V;

[0172] Implementation ideas:

[0173] The power switching sequence is controlled by controlling the conduction sequence of the field effect tubes through the resistor and capacitor charging and discharging circuit.

[0174] Specific implementation principle reference Figure 6 shown.

[0175] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A semiconductor device testing system based on narrow current pulse acquisition, characterized in that: include: Generation module: The input is connected to the digital card channel of the test equipment, and the voltage pulse is converted into a current pulse and provided to the chip under test; Acquisition module: receives the current pulses input by the chip and converts them into voltage pulses, and performs voltage amplification processing through the voltage amplification module; Integrator / follower module: The amplified voltage pulse signal is input to the follower module, and the voltage pulse signal is recaptured at the output end after passing through the follower circuit, and the current value of the chip to be tested is calculated based on the circuit gain and deviation; The amplified voltage pulse signal is input to the integration module, the pulse energy is measured by the integration circuit, and the current pulse energy is calculated based on the circuit gain and deviation; Undersampling module: used to monitor the pulse amplitude corresponding to a certain time point; The generation module uses the classic Howland current source, and adds a primary voltage follower and a secondary voltage amplifier module at the front end; and a relay is set at the output end, one end of the relay is used for output, and the other end is used for calibration; The calibration adopts a multi-point segmented calibration method, and the specific steps are as follows: Get the minimum input voltage value V min and the maximum input voltage V max ; V min To V max The 11 input voltage values ​​are evenly divided into 10 parts, and after sorting, the voltage values ​​V1, V2, V3, ..., V 11 ; The output currents I1, I2, I3, ..., I corresponding to the 11 input voltages are measured respectively. 11 ; Calculate the gain and deviation corresponding to each section respectively; During the multi-point segmented calibration process, the specific method for calculating the gain and deviation is as follows: Calculate the gain and bias of the first segment: Assume that the gain of voltage to current is G1 and the deviation is O1, then: I1=V1*G1+O1 I2=V2*G1+O1 It follows that: Gain G1 = (I2-I1) / (V2-V1) Deviation O1=I1-V1*G1 Similarly, we get the gains of the other 9 segments G2-G 10 and Deviation O2-O 10 ; And after obtaining the expected current value I out When I out Successively with I1 to I 11 Compare, when I out ≥I x And I out ≤I x+1 When the corresponding G x and O x , and calculate the voltage V required at the input x =(I out -O x ) / G x , x∈[1,11) and is a positive integer.

2. A semiconductor device testing system based on narrow current pulse acquisition according to claim 1, characterized in that: The acquisition module is divided into a current-to-voltage module, a voltage amplification module, and an integration / following module; The current-to-voltage module is used to convert current pulses into voltage pulses; The voltage amplifier module is divided into primary amplifier and secondary amplifier. The primary amplifier has two gears, 8 times amplification and 0.5 times amplification respectively. The output of the voltage amplifier module is connected to the integration / following module through a relay, and the pulse energy is obtained through the integration circuit or the voltage pulse is output by the following circuit.

3. A semiconductor device testing system based on narrow current pulse acquisition according to claim 2, characterized in that: The acquisition module has preset calibration input pins, and the module can be calibrated through the voltage output pins. The specific method is as follows: Get the minimum input current value I min and the maximum input current value I max ; Will I min To I max The 11 input current values ​​are evenly divided into 10 parts, and after sorting, the current values ​​I1', I2', I3', ..., I 11 '; The output voltage values ​​V1', V2', V3', ..., V corresponding to the 11 input currents are measured respectively. 11 '; Calculate the gain and deviation corresponding to each section respectively; Among them, the gain and deviation of the first segment are calculated: Assume the gain of current-to-voltage conversion is G1' and the deviation is O1', then: V1'=I1'*G1'+O1' V2'=I2'*G1'+O1' It follows that: Gain G1'=(V2'-V1') / (I2'-I1') Deviation O1'=V1'-I1'*G1' Similarly, we get the gains of the other 9 segments G2'-G 10 ' and deviation O2'-O 10 '; And measured output V out When V out Successively with V1' to V 11 'Compare, when V out ≥V x 'And V out ≤V x+1 ', get the corresponding G x ' and O x ', and calculate the current I required at the input x '=(V out -O x ') / G x ', x∈[1,11) and is a positive integer.

4. A semiconductor device testing system based on narrow current pulse acquisition according to claim 1, characterized in that: The acquisition module further includes an undersampling module, and the undersampling module includes: Pulse input: The input signal is the voltage pulse signal after amplification; Input synchronization signal: output the synchronization pulse signal of the pulse time point to be detected, the synchronization pulse signal is a jump signal from low to high; DC output: After a periodic pulse signal has been continuously followed for several cycles, the output will gradually approach the pulse voltage value corresponding to the synchronization signal time point input by the user; The specific steps of the undersampling method are as follows: Set the digital card starting comparison voltage V OH =0V, and the comparison starts from time 0, and a comparison is performed every preset time interval until the preset comparison cycle is reached. When the sampling voltage at the comparison time is greater than V OH If the sampling voltage is greater than V OH If it is smaller, output L; Gradually increase the comparison voltage V OH , and repeat the comparison process to obtain the output matrix; The dividing line between L and H in the output matrix is ​​used as the shape of the pulse waveform.

5. A test method using a semiconductor device test system based on narrow current pulse acquisition as described in any one of claims 1 to 4, characterized in that: include: The input is connected to the digital card channel of the test equipment and converts the voltage pulse into current pulse to provide to the chip under test; Receive the current pulse input by the chip and convert it into a voltage pulse, and perform voltage amplification processing through the voltage amplification module; The amplified voltage pulse signal is input to the follower module, and the voltage pulse signal is recaptured at the output end after passing through the follower circuit, and the current value of the chip to be tested is calculated by the preset calibration coefficient; The amplified voltage pulse signal is input to the integration module, the pulse energy is measured by the integration circuit, and the current pulse energy is calculated by the calibration coefficient; Monitor the pulse amplitude corresponding to a certain time point.

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