Code parallelization method, device, computer equipment, readable storage medium and program product

Abstract

The present application relates to a code parallelization method, apparatus, computer device, computer-readable storage medium, and computer program product. The method comprises: obtaining serial code and identifying parallelized computing tasks from the serial code; determining data dependencies between the computing tasks; dividing the computing task into at least two subtasks based on the data dependencies, executing the at least two subtasks in parallel, and obtaining parallelized task codes corresponding to the subtasks; and generating target parallel code based on the parallelized task codes. This method can improve the efficiency of code parallelization.

Description

Technical Field

[0001] The present application relates to the technical fields of parallel computing and GPU (Graphics Processing Unit) programming, and in particular to a code parallelization method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] With the rapid growth of data volumes and increasing computing demands, developers can develop applications using various development platforms. For example, CUDA (Compute Unified Device Architecture), a parallel computing platform and programming model launched by NVIDIA, enables developers to leverage the powerful computing capabilities of GPUs to accelerate computing tasks. However, traditional serial computing can no longer meet the needs of many application scenarios. Developers often resort to manually writing parallel code, which is inefficient. Summary of the Invention

[0003] Based on this, it is necessary to provide a code parallelization method, apparatus, computer equipment, computer-readable storage medium and computer program product that can improve efficiency in order to address the above technical problems.

[0004] In a first aspect, the present application provides a code parallelization method, comprising:

[0005] Obtaining serial code and identifying parallelized computing tasks from the serial code;

[0006] Determine the data dependencies between various computing tasks;

[0007] Dividing the computing task into at least two subtasks according to the data dependency, executing the at least two subtasks in parallel, and obtaining parallelized task codes corresponding to the subtasks;

[0008] Based on the parallelized task code, a target parallel code is generated.

[0009] In one embodiment, identifying parallelized computing tasks from serial code includes:

[0010] Parsing the grammatical structure of the serial code and constructing an abstract syntax tree of the serial code;

[0011] Parallelized computing tasks are identified according to the abstract syntax tree.

[0012] In one embodiment, identifying the parallelized computing tasks according to the abstract syntax tree includes:

[0013] Traversing the nodes in the abstract syntax tree to identify target structure codes and computing task nodes respectively;

[0014] If the target structure code is of a parallelizable type and the computing tasks corresponding to the computing task nodes in the target structure code do not have data dependencies, the computing tasks corresponding to the computing task nodes in the target structure code are determined as parallelizable computing tasks.

[0015] In one embodiment, determining the data dependency between the computing tasks includes:

[0016] Acquire data flows between the various computing tasks, and identify read and write dependencies between the various computing tasks based on the data flows between the various computing tasks;

[0017] Generate a dependency graph according to the read-write dependency relationship;

[0018] The data dependency relationships between the various computing tasks are determined from the dependency graph.

[0019] In one embodiment, generating a target parallel code based on the parallelized task code includes:

[0020] Each of the parallelized task codes is inserted into a kernel function, and a target parallel code is generated through the kernel function; the kernel function is used for parallel processing on a graphics processor.

[0021] In one embodiment, the method further comprises:

[0022] Loop unrolling, register allocation, and memory alignment are performed on the target parallel code to obtain an optimized target parallel code.

[0023] In a second aspect, the present application further provides a code parallelization device, comprising:

[0024] A code analysis module is used to obtain serial codes and identify parallelized computing tasks from the serial codes;

[0025] Dependency detection module, used to determine the data dependencies between various computing tasks;

[0026] A task division module, configured to divide the computing task into at least two subtasks according to the data dependency, execute the at least two subtasks in parallel, and obtain parallelized task codes corresponding to the subtasks;

[0027] The code generation module is used to generate a target parallel code based on the parallelized task code.

[0028] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0029] Obtaining serial code and identifying parallelized computing tasks from the serial code;

[0030] Determine the data dependencies between various computing tasks;

[0031] Dividing the computing task into at least two subtasks according to the data dependency, executing the at least two subtasks in parallel, and obtaining parallelized task codes corresponding to the subtasks;

[0032] Based on the parallelized task code, a target parallel code is generated.

[0033] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0034] Obtaining serial code and identifying parallelized computing tasks from the serial code;

[0035] Determine the data dependencies between various computing tasks;

[0036] Dividing the computing task into at least two subtasks according to the data dependency, executing the at least two subtasks in parallel, and obtaining parallelized task codes corresponding to the subtasks;

[0037] Based on the parallelized task code, a target parallel code is generated.

[0038] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the following steps:

[0039] Obtaining serial code and identifying parallelized computing tasks from the serial code;

[0040] Determine the data dependencies between various computing tasks;

[0041] Dividing the computing task into at least two subtasks according to the data dependency, executing the at least two subtasks in parallel, and obtaining parallelized task codes corresponding to the subtasks;

[0042] Based on the parallelized task code, a target parallel code is generated.

[0043] The above-mentioned code parallelization method, apparatus, computer device, computer-readable storage medium and computer program product obtain serial code and identify parallelized computing tasks from the serial code; determine the data dependency between each computing task, divide the computing task into at least two subtasks based on the data dependency, execute at least two subtasks in parallel, and obtain the parallelized task code corresponding to the subtask; then, based on the parallelized task code, the target parallel code can be automatically generated to improve the efficiency of code parallelization. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 1 is a flow chart of a code parallelization method according to an embodiment;

[0046] Figure 2 is a flowchart of a code parallelization method in another embodiment;

[0047] Figure 3 is a structural block diagram of a code parallelization device in one embodiment;

[0048] Figure 4 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0050] In one embodiment, Figure 1As shown, a code parallelization method is provided. This embodiment uses the method applied to a computer device as an example to illustrate. The computer device can be a terminal or a server. It can be understood that the method can also be applied to a system including a terminal and a server, and implemented through the interaction between the terminal and the server. Among them, the terminal can be, but is not limited to, various personal computers, laptops, smart phones, tablets, Internet of Things devices and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car devices, projection devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The head-mounted devices can be virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services. In this embodiment, the code parallelization method includes the following steps:

[0051] Step S102: Acquire serial code and identify parallelized computing tasks from the serial code.

[0052] The serial code is a code executed serially, and may be a CUDA serial code.

[0053] Optionally, the computer device obtains the serial code and performs syntax parsing on the serial code to identify the parallelized computing tasks.

[0054] Step S104: determining the data dependency relationship between the various computing tasks.

[0055] Data dependencies are the data read and write relationships between computing tasks, which determine the execution order and parallelism of tasks. For example, the result of computing task A is the input of computing task B, meaning that the input of computing task B depends on the result of computing task A. Another example is that the result of computing task C triggers computing task D to start or end its computation, meaning that the triggering condition of computing task D depends on the result of computing task C.

[0056] Optionally, the computer device performs data flow analysis on each computing task and uses a data dependency analysis algorithm to determine the data dependency relationship between the computing tasks, which can ensure data consistency during the parallelization process.

[0057] Optionally, the computer device generates a dependency graph by analyzing the data flows between the various computing tasks, and determines the data dependency relationships between the various computing tasks from the dependency graph.

[0058] Optionally, the computer device may also use other data dependency analysis algorithms to generate a dependency graph, such as dependency detection based on static analysis, to improve the accuracy and efficiency of detection.

[0059] Optionally, determining the data dependencies between the various computing tasks includes: obtaining the data flow between the various computing tasks, and identifying the read-write dependencies between the various computing tasks based on the data flow between the various computing tasks; generating a dependency graph based on the read-write dependencies; and determining the data dependencies between the various computing tasks from the dependency graph.

[0060] The dependency graph is an image that includes the dependency relationships between various computing tasks.

[0061] The computer device identifies the read and write dependency relationships between various computing tasks in the dependency graph, and can more accurately determine the data dependency relationships between various computing tasks from the dependency graph.

[0062] Step S106 : dividing the computing task into at least two subtasks according to the data dependency relationship, executing the at least two subtasks in parallel, and obtaining parallelized task codes corresponding to the subtasks.

[0063] Among them, a subtask is a part of a computing task.

[0064] Optionally, the computing device decomposes the computing task into at least two subtasks based on data dependencies, assigns a different GPU thread to each subtask, and executes the corresponding subtasks in parallel through the GPU threads to obtain parallelized task code corresponding to the subtasks. A GPU (Graphics Processing Unit) is a graphics processing unit used to accelerate graphics and parallel computing tasks.

[0065] Taking matrix multiplication as an example, suppose two matrices A and B need to be multiplied to obtain matrix C. In this matrix multiplication calculation, each element C[i][j] is calculated by taking the dot product of the i-th row of A and the j-th column of B. To parallelize this computation, matrix C can be decomposed into multiple sub-blocks, each containing several C[i][j] elements. Each sub-block is assigned to a different GPU thread block, with threads within each GPU thread block responsible for calculating each element in the corresponding sub-block. In this way, the large computational task (matrix multiplication) is divided into multiple smaller sub-tasks (computational sub-blocks), each of which is completed by multiple parallel threads, thereby improving computational efficiency and resource utilization. In this way, the matrix multiplication computational task is effectively decomposed into multiple sub-tasks, enabling efficient parallel computing on the GPU.

[0066] It is understandable that the computer device allocates a GPU thread to each subtask to ensure load balancing.

[0067] As you can understand, each subtask generates a parallelized task code, and multiple subtasks are combined into a single kernel function. The process of generating parallelized task code for a subtask is based on the specific subtask type. For example, if the subtask is a multiplication, multiplication parallel code is generated, while if the subtask is a squaring, square code is generated.

[0068] Optionally, based on a task partitioning strategy of a graph partitioning algorithm, the computing task is divided into at least two subtasks to improve the balance and parallelism of the task partitioning.

[0069] Step S108: Generate target parallel code based on the parallelized task code.

[0070] The target parallel code is the code executed in parallel.

[0071] Optionally, generating a target parallel code based on the parallelized task code includes: inserting each parallelized task code into a kernel function, and generating the target parallel code through the kernel function; the kernel function is used for parallel processing on a graphics processor.

[0072] A kernel function is a function that runs on the GPU. Kernel functions can be executed in parallel by multiple threads, each with a unique thread ID. Kernel functions are used to perform large-scale parallel computations on the GPU, fully leveraging the GPU's parallel processing capabilities. Optionally, kernel functions can be CUDA kernel functions.

[0073] Optionally, the computer device uses a predefined kernel function code template to generate a kernel function; inserts each parallelized task code into the kernel function, and finally generates a complete target parallel code.

[0074] Optionally, the computer device dynamically generates target parallel code according to a specific computing task through dynamic code generation technology.

[0075] The above-mentioned code parallelization method obtains serial code and identifies parallelized computing tasks from the serial code; determines the data dependency between each computing task, divides the computing task into at least two subtasks based on the data dependency, executes at least two subtasks in parallel, and obtains the parallelized task code corresponding to the subtask; then, based on the parallelized task code, the target parallel code can be automatically generated to improve the efficiency of code parallelization.

[0076] In large-scale scientific computing, the parallel code automatically generated using this code parallelization method can improve computational efficiency and accuracy, achieving high-performance computing. In artificial intelligence and machine learning scenarios, using this code parallelization method during the training and inference phases can accelerate the computation of deep learning models and shorten training time. In big data processing and analysis scenarios, using this code parallelization method during data preprocessing and analysis can increase data processing speed.

[0077] This code parallelization approach overcomes the complexity and error-proneness of traditional manual CUDA code writing, enabling automated generation of complex CUDA expressions and code, improving programming efficiency and code maintainability. Furthermore, it supports processing of multiple CUDA vector types, enhancing the versatility and flexibility of code generation tools.

[0078] In one embodiment, identifying parallelized computing tasks from serial code includes: parsing the syntax structure of the serial code, constructing an abstract syntax tree of the serial code; and identifying the parallelized computing tasks according to the abstract syntax tree.

[0079] Among them, grammatical structures include variable declarations, expressions, loops, etc. An Abstract Syntax Tree (ABST) represents the grammatical structure of source code in a tree-like format and is used for code analysis and transformation. An ABST is a tree-like representation of sequential code (source code), where each node represents a grammatical structure within the code.

[0080] Optionally, the computer device performs lexical analysis and syntactic analysis on the input serial code to construct an abstract syntax tree of the serial code; traverses the abstract syntax tree, and identifies parallel computing tasks based on the abstract syntax tree.

[0081] Optionally, identifying parallel computing tasks based on the abstract syntax tree includes: traversing the nodes in the abstract syntax tree to identify the target structure code and computing task nodes respectively; if the target structure code is of a parallelizable type, and the computing task corresponding to the computing task node in the target structure code does not have data dependency, then determining the computing task corresponding to the computing task node in the target structure code as a parallel computing task.

[0082] Optionally, the computer device starts from the root node of the abstract syntax tree, traverses each node in the abstract syntax tree, obtains the node type of each node, and identifies a computing task node based on the node type of each node. The type of the computing task node is a computing task. The computing task node may include, but is not limited to, a variable declaration, an assignment statement, an arithmetic operation, a function call, and the like.

[0083] Optionally, for each computing task node, information such as the location of the computing task node, operands, and operators is recorded.

[0084] Optionally, the computer device traverses the nodes in the abstract syntax tree and identifies target structure code. The target structure code includes at least one of a loop structure and a conditional structure. Loop structures include, but are not limited to, for loops and while loops. Conditional structures include, but are not limited to, if statements and switch statements.

[0085] Optionally, the computer device performs data flow analysis on the target structure code to detect whether there is data dependency in the target structure code; if there is no data dependency in the target structure code, it indicates that the target structure code is of a parallelizable type; if there is data dependency in the target structure code, it indicates that the target structure code is not of a parallelizable type.

[0086] It is understandable that there is no data dependency in the target structure code, which means that the loop structure or loop iterations of the conditional structure of the target structure code are independent, so the target structure code is considered to be a parallelizable type.

[0087] Optionally, the computer device determines the computing tasks corresponding to the computing task nodes in the target structure code, and detects whether there is data dependency between the computing tasks corresponding to the task nodes in the target structure code. If there is no data dependency between the computing tasks corresponding to the task nodes in the target structure code, it indicates that the computing task can be used as a parallel computing unit for parallel computing; if there is data dependency between the computing tasks corresponding to the task nodes in the target structure code, it indicates that the computing task cannot be used as a parallel computing unit.

[0088] Optionally, the computer device marks the parallelized computing tasks in the abstract syntax tree to provide a more accurate basis for subsequent parallel code generation and optimization.

[0089] In this embodiment, the computer device parses the syntax structure of the serial code and constructs an abstract syntax tree of the serial code, and can accurately identify the parallelized computing tasks based on the abstract syntax tree.

[0090] Furthermore, the computer device traverses the nodes in the abstract syntax tree and identifies the target structure code and the computing task nodes respectively. If the target structure code is of a parallelizable type and the computing task corresponding to the computing task node in the target structure code does not have data dependency, then the computing task corresponding to the computing task node in the target structure code is determined as a parallelized computing task, which can more accurately determine the parallelized computing task.

[0091] In one embodiment, the method further includes: performing loop unrolling, register allocation, and memory alignment on the target parallel code to obtain an optimized target parallel code.

[0092] Among them, loop unrolling is a compilation optimization technology that reduces loop control overhead and improves execution efficiency by unrolling the loop body.

[0093] Optionally, the computing device can perform loop unrolling using the #pragma unroll directive to reduce loop overhead. #pragma unroll is a non-standard compiler directive primarily used in CUDA programming to instruct the compiler to unroll loops to improve the performance of code running on the GPU.

[0094] Optionally, the computing device can use loop unrolling to reduce the overhead of loop control instructions, increase instruction-level parallelism, and optimize register utilization. Memory is aligned by default, and this ensures that constructed data structures (if any) are aligned.

[0095] It is understandable that optimizing register allocation and usage in computer devices can reduce memory access latency, and ensuring memory access alignment can increase access speed.

[0096] In this embodiment, the computer device performs loop unrolling, register allocation, and memory alignment on the target parallel code, resulting in a faster, optimized target parallel code and improved execution efficiency. The computer device automatically converts serial code into the target parallel code and optimizes the generated target parallel code to improve computational efficiency and code maintainability, resolving complexity and efficiency issues in existing technologies.

[0097] In one embodiment, a computer device obtains a serial code input by a user, parses the serial code, and identifies a computing task; generates a dependency graph between each computing task, and identifies the data dependency relationship between each computing task; decomposes the computing task into multiple subtasks, and assigns a GPU thread to each subtask; generates a parallelized task code through parallel execution of the GPU threads, and inserts the parallelized task code into a kernel function to generate a target parallel code; optimizes the target parallel code to obtain an optimized target parallel code; and outputs the optimized target parallel code.

[0098] In one embodiment, Figure 2As shown, a computer device inputs code to obtain serial code; performs code analysis and task identification on the serial code to identify parallel computing tasks; performs dependency detection on each computing task to determine the data dependency relationship between each computing task; generates a dependency graph based on the data dependency relationship; divides the computing task into at least two subtasks, assigns a GPU thread to each subtask, executes at least two subtasks in parallel, and generates parallelized task code; generates CUDA parallel code based on the parallelized task code; performs performance optimization on the CUDA parallel code to obtain optimized CUDA parallel code, and outputs the optimized CUDA parallel code.

[0099] In one embodiment, a code parallelization method is provided, which is applied to a computer device and includes the following steps:

[0100] Step A1, obtaining the serial code.

[0101] Step A2: parse the grammatical structure of the serial code and construct an abstract syntax tree of the serial code; traverse the nodes in the abstract syntax tree to identify the target structure code and the computing task node respectively; if the target structure code is a parallelizable type and the computing task corresponding to the computing task node in the target structure code does not have data dependency, then determine the computing task corresponding to the computing task node in the target structure code as a parallelized computing task.

[0102] Step A3, obtain the data flow between each computing task, and identify the read and write dependencies between each computing task based on the data flow between each computing task; generate a dependency graph based on the read and write dependencies; and determine the data dependencies between each computing task from the dependency graph.

[0103] Step A4: divide the computing task into at least two subtasks according to the data dependency relationship, execute the at least two subtasks in parallel, and obtain parallelized task codes corresponding to the subtasks.

[0104] Step A5: insert each parallelized task code into a kernel function, and generate a target parallel code through the kernel function; the kernel function is used for parallel processing on the graphics processor.

[0105] Step A6: perform loop expansion, register allocation, and memory alignment on the target parallel code to obtain an optimized target parallel code.

[0106] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0107] Based on the same inventive concept, embodiments of the present application also provide a code parallelization device for implementing the aforementioned code parallelization method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations in one or more embodiments of the code parallelization device provided below can be found in the aforementioned limitations on the code parallelization method and will not be further elaborated here.

[0108] In an exemplary embodiment, Figure 3 As shown, a code parallelization device is provided, including: a code analysis module 302, a dependency detection module 304, a task division module 306 and a code generation module 308, wherein:

[0109] The code analysis module 302 is used to obtain serial code and identify parallelized computing tasks from the serial code.

[0110] The dependency detection module 304 is used to determine the data dependency between various computing tasks.

[0111] The task division module 306 is used to divide the computing task into at least two subtasks according to the data dependency relationship, execute the at least two subtasks in parallel, and obtain parallelized task codes corresponding to the subtasks.

[0112] The code generation module 308 is configured to generate a target parallel code based on the parallelized task code.

[0113] The above-mentioned code parallelization device obtains serial code and identifies parallelized computing tasks from the serial code; determines the data dependency between each computing task, divides the computing task into at least two subtasks based on the data dependency, executes at least two subtasks in parallel, and obtains the parallelized task code corresponding to the subtask; then, based on the parallelized task code, the target parallel code can be automatically generated to improve the efficiency of code parallelization.

[0114] In one embodiment, the code analysis module 302 is further configured to parse the syntax structure of the serial code, construct an abstract syntax tree of the serial code, and identify parallel computing tasks based on the abstract syntax tree.

[0115] In one embodiment, the above-mentioned code analysis module 302 is also used to traverse the nodes in the abstract syntax tree to identify the target structure code and the computing task node respectively; if the target structure code is of a parallelizable type and the computing task corresponding to the computing task node in the target structure code does not have data dependency, then the computing task corresponding to the computing task node in the target structure code is determined as a parallelized computing task.

[0116] In one embodiment, the dependency detection module 304 is also used to obtain the data flow between each computing task, and identify the read-write dependency between each computing task based on the data flow between each computing task; generate a dependency graph based on the read-write dependency; and determine the data dependency between each computing task from the dependency graph.

[0117] In one embodiment, the code generation module 308 is further configured to insert each parallelized task code into a kernel function, and generate a target parallel code through the kernel function; the kernel function is configured to perform parallel processing on a graphics processor.

[0118] In one embodiment, the apparatus further includes a performance optimization module; the performance optimization module is configured to perform loop expansion, register allocation, and memory alignment on the target parallel code to obtain an optimized target parallel code.

[0119] Each module in the above-mentioned code parallelization device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0120] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 4As shown. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals via wired or wireless means, and the wireless means can be implemented via Wi-Fi, a mobile cellular network, near-field communication (NFC), or other technologies. When the computer program is executed by the processor, a code parallelization method is implemented. The display unit of the computer device is used to form a visually visible image, and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse.

[0121] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0122] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented: obtaining serial code and identifying parallelized computing tasks from the serial code; determining data dependencies between the computing tasks; dividing the computing task into at least two subtasks based on the data dependencies, executing the at least two subtasks in parallel, and obtaining parallelized task codes corresponding to the subtasks; and generating target parallel code based on the parallelized task codes.

[0123] In one embodiment, when executing the computer program, the processor further implements the following steps: parsing the syntax structure of the serial code and constructing an abstract syntax tree of the serial code; and identifying parallelized computing tasks according to the abstract syntax tree.

[0124] In one embodiment, when executing a computer program, the processor further implements the following steps: traversing the nodes in the abstract syntax tree to identify the target structure code and the computing task node respectively; if the target structure code is of a parallelizable type and the computing task corresponding to the computing task node in the target structure code does not have data dependency, then determining the computing task corresponding to the computing task node in the target structure code as a parallelized computing task.

[0125] In one embodiment, when the processor executes the computer program, it also implements the following steps: obtaining the data flow between each computing task, and identifying the read-write dependency relationship between each computing task based on the data flow between each computing task; generating a dependency graph based on the read-write dependency relationship; and determining the data dependency relationship between each computing task from the dependency graph.

[0126] In one embodiment, when executing the computer program, the processor further implements the following steps: inserting each parallelized task code into a kernel function, generating a target parallel code through the kernel function; and using the kernel function for parallel processing on the graphics processor.

[0127] In one embodiment, when executing the computer program, the processor further implements the following steps: performing loop unrolling, register allocation, and memory alignment on the target parallel code to obtain an optimized target parallel code.

[0128] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: obtaining a serial code and identifying a parallelized computing task from the serial code; determining a data dependency relationship between each computing task; dividing the computing task into at least two subtasks based on the data dependency relationship, executing at least two subtasks in parallel, and obtaining a parallelized task code corresponding to the subtask; and generating a target parallel code based on the parallelized task code.

[0129] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: parsing the syntax structure of the serial code and constructing an abstract syntax tree of the serial code; and identifying parallelized computing tasks according to the abstract syntax tree.

[0130] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: traversing the nodes in the abstract syntax tree to identify the target structure code and the computing task node respectively; if the target structure code is of a parallelizable type and the computing task corresponding to the computing task node in the target structure code does not have data dependency, then determining the computing task corresponding to the computing task node in the target structure code as a parallelized computing task.

[0131] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining the data flow between each computing task, and identifying the read-write dependency relationship between each computing task based on the data flow between each computing task; generating a dependency graph based on the read-write dependency relationship; and determining the data dependency relationship between each computing task from the dependency graph.

[0132] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: inserting each parallelized task code into a kernel function, generating a target parallel code through the kernel function; and the kernel function is used for parallel processing on a graphics processor.

[0133] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: loop unrolling, register allocation, and memory alignment are performed on the target parallel code to obtain an optimized target parallel code.

[0134] In one embodiment, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the following steps: obtaining serial code and identifying parallelized computing tasks from the serial code; determining data dependencies between the computing tasks; dividing the computing task into at least two subtasks based on the data dependencies, executing the at least two subtasks in parallel, and obtaining parallelized task codes corresponding to the subtasks; and generating target parallel code based on the parallelized task codes.

[0135] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: parsing the syntax structure of the serial code and constructing an abstract syntax tree of the serial code; and identifying parallelized computing tasks according to the abstract syntax tree.

[0136] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: traversing the nodes in the abstract syntax tree to identify the target structure code and the computing task node respectively; if the target structure code is of a parallelizable type and the computing task corresponding to the computing task node in the target structure code does not have data dependency, then determining the computing task corresponding to the computing task node in the target structure code as a parallelized computing task.

[0137] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining the data flow between each computing task, and identifying the read-write dependency relationship between each computing task based on the data flow between each computing task; generating a dependency graph based on the read-write dependency relationship; and determining the data dependency relationship between each computing task from the dependency graph.

[0138] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: inserting each parallelized task code into a kernel function, generating a target parallel code through the kernel function; and the kernel function is used for parallel processing on a graphics processor.

[0139] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: loop unrolling, register allocation, and memory alignment are performed on the target parallel code to obtain an optimized target parallel code.

[0140] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0141] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0142] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0143] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A code parallelization method, characterized in that: The method comprises: Acquire serial code, parse the grammatical structure of the serial code, and construct an abstract syntax tree of the serial code; Traversing the nodes in the abstract syntax tree, and identifying target structure codes and computing task nodes respectively; the target structure codes include at least one of a loop structure and a conditional structure; If the target structure code is of a parallelizable type and the computing task corresponding to the computing task node in the target structure code does not have data dependency, determining the computing task corresponding to the computing task node in the target structure code as a parallelizable computing task; Determine the data dependencies between various computing tasks; Dividing the computing task into at least two subtasks according to the data dependency, executing the at least two subtasks in parallel, and obtaining parallelized task codes corresponding to the subtasks; Based on the parallelized task code, a target parallel code is generated.

2. The method according to claim 1, characterized in that The executing the at least two subtasks in parallel to obtain parallelized task codes corresponding to the subtasks includes: Allocating GPU threads to each of the subtasks; Each of the subtasks is executed in parallel by each of the GPU threads to obtain a parallelized task code corresponding to the subtask.

3. The method according to claim 1, characterized in that The step of parsing the grammatical structure of the serial code and constructing an abstract syntax tree of the serial code includes: Performing lexical analysis and grammatical analysis on the serial code to construct an abstract syntax tree of the serial code.

4. The method according to claim 1, wherein Determining the data dependency between the computing tasks includes: Acquire data flows between the various computing tasks, and identify read and write dependencies between the various computing tasks based on the data flows between the various computing tasks; Generate a dependency graph according to the read-write dependency relationship; The data dependency relationships between the various computing tasks are determined from the dependency graph.

5. The method according to claim 1, characterized in that Generating a target parallel code based on the parallelized task code includes: Each of the parallelized task codes is inserted into a kernel function, and a target parallel code is generated through the kernel function; the kernel function is used for parallel processing on a graphics processor.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: Loop unrolling, register allocation, and memory alignment are performed on the target parallel code to obtain an optimized target parallel code.

7. A code parallelization device, characterized in that: The device comprises: A code analysis module is configured to obtain serial code, parse the syntax structure of the serial code, and construct an abstract syntax tree of the serial code; traverse the nodes in the abstract syntax tree to identify target structure code and computing task nodes, respectively; the target structure code includes at least one of a loop structure and a conditional structure; if the target structure code is of a parallelizable type and the computing task corresponding to the computing task node in the target structure code does not have data dependency, then determine the computing task corresponding to the computing task node in the target structure code as a parallelizable computing task; Dependency detection module, used to determine the data dependencies between various computing tasks; A task division module, configured to divide the computing task into at least two subtasks according to the data dependency, execute the at least two subtasks in parallel, and obtain parallelized task codes corresponding to the subtasks; The code generation module is used to generate a target parallel code based on the parallelized task code.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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