Semiconductor devices packaged using extensible interconnects

Abstract

The present disclosure relates to systems and methods for packaging semiconductor devices using extensible interconnects. According to exemplary embodiments, one or more substrate extensions are coupled to a base substrate, where portions of the one or more substrate extensions extend beyond the base substrate. Electrical and / or optical connections are connected to the substrate extensions. Additional embodiments also exist.

Description

Technical Field

[0001] This invention relates to semiconductor devices and packaging. Background Technology

[0002] High-performance computing systems (specifically, high-performance computing systems designed for machine learning and artificial intelligence applications) require efficient and robust interconnect solutions to enable seamless communication between various computing modules. These systems are typically constructed from large arrays of interconnected semiconductor devices containing multiple computing modules.

[0003] In the past, various methods have been proposed for interconnecting semiconductor devices, but they are insufficient for the reasons explained below. Novel and improved systems and methods for packaging semiconductor devices using scalable interconnects are desired. Summary of the Invention

[0004] In one aspect, the present invention provides a semiconductor device comprising: a first substrate including a first top surface and a first bottom surface, the first top surface including a first region, a second region and a third region, the third region being positioned between the first region and the second region, the first region including a first plurality of electrical contacts, the second region including a second plurality of electrical contacts, and the third region including a third plurality of electrical contacts; an integrated circuit including a fourth plurality of electrical contacts electrically coupled to the third plurality of electrical contacts; a second substrate including a fourth region and a fifth region, the fourth region including a fifth plurality of electrical contacts electrically coupled to the first plurality of electrical contacts, the fourth region being positioned above the first region and the fifth region being positioned outside the first substrate; a third substrate including a sixth region and a seventh region, the sixth region including a sixth plurality of electrical contacts electrically coupled to the second plurality of electrical contacts, the sixth region being positioned above the first region and the seventh region being positioned outside the first substrate; an electrical connector electrically coupled to the second substrate; and an optical connector coupled to the third substrate.

[0005] In another aspect, the present invention provides a semiconductor device comprising: a first substrate including a first top surface and a first bottom surface, the first top surface including a first region, a second region and a third region, the third region being positioned between the first region and the second region, the first region including a first plurality of electrical contacts, the second region including a second plurality of electrical contacts, and the third region including a third plurality of electrical contacts; an integrated circuit including a fourth plurality of electrical contacts electrically coupled to the third plurality of electrical contacts; a second substrate including a fourth region and a fifth region, the fourth region including a fifth plurality of electrical contacts electrically coupled to the first plurality of electrical contacts, the fourth region being positioned above the first region, and the fifth region being positioned outside the first substrate; a third substrate including a sixth region and a seventh region, the sixth region including a sixth plurality of electrical contacts electrically coupled to the second plurality of electrical contacts, the sixth region being positioned above the first region, and the seventh region being positioned outside the first substrate; and a stiffening ring including a ring including an eighth region and a ninth region, the eighth region being thermally coupled to the fourth region, and the ninth region being coupled to the third region.

[0006] In another aspect, the present invention provides a semiconductor device comprising: a first substrate including a first top surface and a first bottom surface, the first top surface including a first region, a second region, and a third region, the third region being positioned between the first region and the second region, the first region including a first plurality of electrical contacts, the second region including a second plurality of electrical contacts, and the third region including a third plurality of electrical contacts; an integrated circuit including a fourth plurality of electrical contacts electrically coupled to the third plurality of electrical contacts; and a second substrate including a second top region and a second bottom region, the second substrate further including the fourth region. The fourth region is positioned on the second top region, the fifth region is positioned on the second bottom region, the fourth region includes a fifth plurality of electrical contacts electrically coupled to the first plurality of electrical contacts, and the fourth region is positioned above the first region; a third substrate includes a sixth region and a seventh region, the sixth region includes a sixth plurality of electrical contacts electrically coupled to the second plurality of electrical contacts, the sixth region is positioned above the first region, and the seventh region includes a seventh plurality of electrical contacts; and an optical circuit includes an electrical interface and an optical interface, the electrical interface being coupled to the seventh plurality of electrical contacts. Attached Figure Description

[0007] Figure 1A and 1B This is a diagram illustrating a semiconductor device with an extended substrate according to an embodiment of the present invention.

[0008] Figure 2 This is a simplified diagram illustrating the electrical connections of a semiconductor device having an extended substrate according to an embodiment of the present invention.

[0009] Figure 3A and 3B This is a diagram illustrating the line bending of a semiconductor device with an extended substrate according to an embodiment of the present invention.

[0010] Figure 4 This is a simplified diagram illustrating an electrical connector for extending a substrate according to an embodiment of the present invention.

[0011] Figure 5 This is a simplified diagram illustrating a glass substrate with an extended substrate according to an embodiment of the present invention. Detailed Implementation

[0012] This invention relates to semiconductor devices and packages. According to an exemplary embodiment, one or more substrate extensions are coupled to a base substrate, wherein portions of the one or more substrates extend beyond the base substrate. Electrical and / or optical connections are connected to these substrate extensions. Additional embodiments also exist.

[0013] As mentioned above, efficient and robust interconnect solutions are desired. For example, connectivity between nearby boards (such as those in the same or adjacent racks) is typically facilitated by passive copper cabling. In contrast, more distant boards are connected via fiber optics using schematically identical data path connectors.

[0014] One design challenge of these systems is enabling module and board designs to accommodate both electrical (e.g., copper) and optical (e.g., fiber optic) interconnects. Some existing approaches involve using differential signaling to route high-speed data paths from the compute die through the module substrate to the motherboard and laterally along the motherboard to the panel. At the panel, standardized sockets allow for board-to-board connections via pluggable cables through passive copper cabling (E-to-E connections) or active optical cabling (E-to-O transitions). While this approach is widely adopted, it introduces additional complexity and parasitic losses associated with routing signals through the module and motherboard. To address these issues, “co-packaged optics” or “co-packaged copper” solutions have emerged, where data path cabling is directly connected to the module. As an example, co-packaging optical and electrical components within a semiconductor device refers to the process of integrating optical and electrical components into a single package. The package protects the semiconductor die, connects the chip to the board or other chips, and allows for heat dissipation. Co-packaging optical and electrical components is a promising technology for high-speed data transmission and processing in data centers. It can reduce power consumption and data transmission latency while improving data processing performance. However, existing common packaging methods typically require unique module designs for optical and electrical connections.

[0015] Some methods for module-to-board edge connections involve fanning out a signal from the top side of the module (where the SerDes circuitry is located), transitioning downwards along the lower perimeter of the module through solder ball connectors on the printed circuit board (PCB), and then delivering the signal to the board edge along planar differential transmission lines. Customization of the board-to-board connection between optics and telecommunications is generally achieved by using standardized cage connectors at the board edge designed to handle pluggable electrical (e.g., passive or active) cables or pluggable (active) optical cables. Alternative solutions involve “fly-through” electrical jumpers (e.g., “single-scale” jumpers without scale transition features, as provided by embodiments of the invention hereinafter) to a “middleboard” connector, then routing upwards through the board and module to SerDes, or dedicated co-packaged optics on the module with optical jumpers to the board edge.

[0016] Furthermore, the co-packaged connectors used in various existing methods occupy a significant area and perimeter on the module substrate, posing further challenges in system design. With the increasing demand for higher computing performance and interconnect density, there remains a need for innovative solutions that enable common base module designs to be tailored for co-packaged electrical or co-packaged optical applications. Additionally, there is a need to increase the interconnect area without increasing the size of the base module and to develop methods for significantly enhancing the density of co-packaged electrical connectors.

[0017] The following description is presented to enable those skilled in the art to make and use the invention in a particular application context. Those skilled in the art will readily understand various modifications and uses in different applications, and the general principles defined herein apply to a wide range of embodiments. Therefore, the invention is not intended to be limited to the presented embodiments, but is to be given the broadest scope consistent with the principles and novel features disclosed herein.

[0018] In the following detailed description, numerous specific details are set forth to provide a more thorough understanding of the invention. However, those skilled in the art will understand that the invention may be practiced without being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail so as not to obscure the invention.

[0019] The reader's attention should be directed to all papers and documents filed concurrently with and made publicly available with this specification, the contents of which are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any appended claims, abstracts, and figures) may be replaced by alternative features used for the same, equivalent, or similar purposes. Therefore, unless otherwise expressly stated, each disclosed feature is merely one example of an equivalent or similar feature in a general series.

[0020] Furthermore, any element in the claims that does not expressly state a “component” for performing the specified function or a “step” for performing a specific function is not to be interpreted as a “component” or “step” as specified in paragraph 6 of section 112 of 35 USC. Specifically, the use of “step of…” or “action of…” in the claims herein is not intended to invoke the provisions of paragraph 6 of 35 USC 112.

[0021] When an element is referred to herein as “connected” or “coupled” to another element, it should be understood that the element may be directly connected to the other element or have an intermediary element present between the elements. In contrast, when an element is referred to as “directly connected” or “directly coupled” to another element, it should be understood that there is no intermediary element in the “direct” connection between the elements. However, the presence of a direct connection does not preclude the presence of other connections in which an intermediary element may be present. When the term “electrically coupled” is used with reference to two elements, it implies that these elements have a direct electrical connection, allowing current or signals to flow between them. Alternatively, this connection may also be established by the presence of an intermediate conductive component that facilitates the transfer of electrical energy or information between the two elements. In either case, the primary purpose of “electrically coupled” is to enable electrical interaction between connected elements.

[0022] When an element is referred to herein as being "positioned" relative to another element in a certain manner (e.g., positioned on, between, below, adjacent to, or otherwise positioned in a relative manner), it should be understood that the element may be directly positioned relative to the other element (e.g., directly positioned on the other element) or may have an intermediary element present between the elements. In contrast, when an element is referred to as being "directly positioned" relative to another element, it should be understood that in a "direct" instance, there is no intermediary element. However, the presence of direct positioning does not preclude other instances in which an intermediary element may be present.

[0023] Similarly, when an element is referred to herein as being “joined” to another element, it should be understood that the element may be joined directly to the other element (without any intermediary element) or with an intermediary element present between the joined elements. In contrast, when an element is referred to as being “joined directly” to another element, it should be understood that there is no intermediary element in the “direct” joint between the elements. However, the presence of a direct joint does not preclude other forms of joint in which an intermediary element may be present.

[0024] Similarly, when an element is referred to herein as a “layer,” it should be understood that a layer may be a single layer or may contain multiple layers. For example, a conductive layer may include multiple different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include multiple dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it should be understood that the coupled or connected layer may contain intermediary elements present between the coupled or connected layers. In contrast, when a layer is referred to as being “directly” connected or coupled to another element, it should be understood that there are no intermediary elements between the layers. However, the presence of directly coupled or connected layers does not preclude the presence of other connections where intermediary elements may exist.

[0025] Furthermore, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for interpretive purposes only and are not limited to any fixed direction or orientation. Specifically, they are used only to indicate the relative position and / or orientation between various parts of an object and / or assembly.

[0026] Furthermore, the methods and processes described herein may be described in a specific order for ease of description. However, it should be understood that, unless the context otherwise specifies, intermediate processes may occur before and / or after any part of the described processes, and various other procedures may be reordered, added, and / or omitted according to various embodiments.

[0027] Unless otherwise indicated, all numbers used herein to express quantity, size, etc., shall be understood to be modified by the term “about” in all instances. In this application, unless otherwise specifically stated, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms “and” and “or” means “and / or”. Furthermore, the use of the terms “comprising” and “having”, as well as other forms (such as “includes,” “included,” “has,” “have,” and “had”), shall be considered non-exclusive. Additionally, unless otherwise specifically stated, terms such as “element” or “component” cover both elements and components comprising one unit and elements and components comprising more than one unit.

[0028] As used herein, the phrase “at least one of…” preceding a series of items, and the terms “and” or “or” used to separate any item, modify the entire list, not each member of the list (i.e., each item). The phrase “at least one of…” does not require selection of at least one of each of the listed items; rather, the phrase allows for the meaning of at least one of any of the items and / or at least one of any combination of items. For example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer to only A, only B, or only C; and / or any combination of A, B, and C. In examples where it is desired to select “at least one of each of A, B, and C” or alternatively “at least one of A, at least one of B, and at least one of C”, this is explicitly stated.

[0029] Figure 1A and 1B These figures illustrate a semiconductor device with an extended substrate according to embodiments of the present invention. These figures are merely illustrative and should not unduly limit the scope of the claims. For example, the terms "substrate" and "extended substrate" may refer to a circuit board, such as a printed circuit board (PCB), on which integrated circuits and other electrical components are mounted. These substrates provide a stable platform for the components, along with the necessary electrical connections for their interaction and to function as a complete system.

[0030] As an example, semiconductor device 100 illustrates a packaging platform that can be customized by selecting electrically or optically bonded substrate extensions for top-side compatible connections of high-speed serial data paths. For example, in the case of co-packaged copper (e.g., substrate extension 110) and / or co-packaged optics (e.g., substrate extension 120), the substrate extension will move the jumper to the edge of the base substrate (e.g., base substrate 101), where passive E-to-E or O-to-O connectors (respectively) will connect to board-to-board cables at the panel. In various embodiments, the internal module electronics (e.g., electronics 141, 142, 143, and 144) and the base substrate will resemble existing methods for configuring electrical or optical data paths (e.g., compared to existing methods). In various embodiments, the semiconductor with the substrate extension can be used to implement a serializer-deserializer (SerDes) circuit system, where the SerDes can be designed with sufficient drive force to drive the entire module-to-module channel between boards or will provide direct drive to the co-packaged optics. For example, the base substrate can differ from existing methods in three ways: first, it includes a set of electrical connection points on the top surface of both the electrical and optical extension substrates (e.g., connected to internal electronics via differential traces through the upper routing layer of the substrate); second, it may lack electrical paths for these signals to the circuit board; and third, it can reduce size and complexity by replacing vertical wiring and signal fan-out with simpler surface wiring of signal traces and eliminating the need for common packaged elements on the substrate surface.

[0031] Figure 1B A top view of a semiconductor device 100 is provided. For example, the semiconductor device 100 may also be referred to as a semiconductor package or a packaging platform. The semiconductor device includes a first substrate 101, commonly referred to as a base substrate. The base substrate 101 has a top surface and a bottom surface, both of which may include electrical contacts. For example, the top surface includes the depicted electrical contacts 103, 104, and 105, while the bottom surface has various electrical contacts including electrical contact 102.

[0032] The top surface of the base substrate 101 includes a first region 101A on the left, a second region 101B on the right, and a third region 101C positioned between the first region 101A and the second region 101B. Each of these regions contains multiple electrical contacts. For example, the first region 101A includes electrical contacts (e.g., electrical contact 103) for coupling to a second substrate 110, while the second region 101B includes electrical contacts (e.g., electrical contact 104) for coupling to a third substrate 120. The second substrate 110 and the third substrate 120 may be referred to as substrate extensions because corresponding portions of these substrates extend beyond the area of ​​the base substrate 101. It should be understood that substrate extensions increase the top surface area of ​​the base substrate, creating additional space for co-packaging components. Substrate extensions allow for greater flexibility and customization in the design of semiconductor devices, accommodating both electrical and optical I / O components. In various embodiments, the base substrate may be customized for electrical and / or optical connections, with or without substrate extensions extending beyond the base substrate.

[0033] For example, substrate extension 110 includes components for electrical connection. Substrate extension 110 includes two regions: one region is located between region 101A of the base substrate 101 and the stiffening ring region 130A, and another region extends beyond region 101A of the base substrate 101 and is coupled to electrical connector 111 (e.g., a copper connector). Electrical connector 111 is connected to an electrical connector or wire. Substrate extension 110 is thermally coupled to stiffening ring region 130A via thermal interface material (TIM) 131A. “Thermal interface material” can refer to a substrate that facilitates heat transfer between multiple surfaces or components. As an example, electrical connector 111 may include a miniature differential cable connector that can be used with 78 and 95 ohm conductor cables and operates from 0 to 200 MHz. For example, substrate extension 110 may include connection points (e.g., 1.6 mm miniature differential cable connection points) for accommodating miniature differential cable connectors.

[0034] As an example, stiffening ring region 130A is part of a stiffening ring that fixes the substrate extension and provides mechanical support to the base substrate 101. (See the top view of the semiconductor device 100 provided.) Figure 1BAs depicted, a stiffening ring is disposed at an outer region of a base substrate 101. Within the stiffening ring, region 130A is coupled to (and fixed to) substrate extension 110, region 130B is coupled to (and fixed to) substrate extension 120, and regions 130C and 130D are coupled to (and provide support to) the base substrate 101. The term "stiffening ring" refers to a component in a semiconductor package that supports electronic components, thereby reducing warpage. In various embodiments, the stiffening ring is mounted on the top surface of the package substrate and has reinforcing ribs coplanar with the stiffening ring on the top surface of the package substrate. For example, the stiffening ring can be configured in various shapes, and depending on the context, the stiffening ring may also be referred to as a "stiffening component." Depending on the embodiment, the stiffening ring or stiffening component may be located within the extension substrate (between the extension substrate and the internal electronics), or it may not be present at all, as in the case of a capped package.

[0035] A second region 101B of the base substrate 101 is coupled to a substrate extension 120. The substrate extension 120 includes components for optical connection and comprises two regions: one region is located between region 101B of the base substrate 101 and the stiffening ring region 130B, while the other region extends beyond region 101B of the base substrate 101 and is coupled to optical circuitry 121. Optical circuitry 121 is designed to convert electrical signals into optical signals and vice versa, and it is connected to optical connector 123 via interface 122. In various embodiments, optical connector 123 includes optical jumpers and / or other components. The substrate extension 120 is thermally coupled to the stiffening ring region 130B via thermal interface material (TIM) 131B.

[0036] A third region 101C of the base substrate 101 is coupled to the circuit 140 via an electrical connector (e.g., including electrical connector 105) and is located between regions 101A and 101B. Additional electronic components 141, 142, 143, and 144 are connected to the circuit 140.

[0037] The integration of substrate expansion and scale-shifting electronic connectors (e.g., jumpers) allows for the reduction or elimination of high-speed signal transmission through the base module and across the motherboard. Therefore, this innovation enables the re-optimization of the base substrate and motherboard design to reduce costs. Substrate expansion establishes electrical signal connections to the base module via solder bumps (similar to solder bumps used to connect electronic microchips to modules in a flip-chip configuration). The solder bump array for expansion board connections has the same pattern as array connectors used to connect to the expansion board to route signals to differential pair cables or to connect to the expansion board to route signal and power to an optical engine driving a fiber optic array. Depending on the implementation, materials other than solder (e.g., nanoparticle copper paste) can be used to establish the electrical connection between the expansion board and the base substrate.

[0038] In various embodiments, the substrate extension (e.g., substrate extensions 110 and 120) includes materials and routing layers designed for planar routing of high-frequency signals across differential signal pair conductor traces. These materials are selected to ensure near thermal expansion matching between the substrate extension and the base module substrate. The conductor and insulator layer thicknesses on the substrate extension can be designed independently of the conductor and insulator layer thicknesses of the base substrate to optimize efficient, longer-distance transmission of high-speed signals across the substrate extension compared to transmission across the base substrate. The substrate extension may overlap beyond the edge of the base module substrate, optionally increasing the area available for use in cable array connectors or optical engines without enlarging the base module. If the extension beyond the edge of the base substrate is significant, support elements can be added for mechanical support between the motherboard and the extension plate.

[0039] Figure 2 This is a simplified diagram illustrating the electrical connections of a semiconductor device with an extended substrate according to an embodiment of the present invention. This diagram is merely illustrative and should not unduly limit the scope of the claims. As an example, electronic component 241 is connected to electrical connector 211 via data path 260. Data path 260 traverses circuit 240, base substrate 201, and substrate extension 210, establishing a connection between electronic component 241 and electrical connector 211. As an example, circuit 240 may be optional and act as an interposer, which may be implemented using a silicon interposer, an organic interposer, an organic interposer with embedded components, or others. As an example, Figure 2 The embodiment shown in Figure 1 is modified as follows: the optical circuitry is positioned below the stiffening ring, enabling the stiffening ring to provide thermal management for the optical circuitry. Similarly, electronic component 242 is connected to optical circuitry 221 via data path 261. Data path 261 provides the connection between electronic component 242 and optical circuitry 221 via circuitry 240, base substrate 201, and substrate extension 220. Optical circuitry 221 converts electrical signals into optical signals for transmission at optical connector 223 and also converts received optical signals at optical connector 223 back into electrical signals.

[0040] It should be noted that the data paths to the optical and electrical connectors meet various operating parameters. For example, in embodiments of the invention, the data paths include a top-side path for high-speed signals, while other signals may remain within the base substrate. By confining high-speed signals to the top side, the base substrate can be simplified, potentially reducing the number of layers or area. The data path signaling on the top side of the base substrate enables internal electronics (e.g., interposers) to be extended to the soldered substrate. The layer composition of the substrate extension board can be optimized based on different operating parameters, such as electrical boards with dual-height top and bottom SerDes wiring without power supply wiring and optical boards with larger insertion loss tolerances in signal routing and additional supply wiring. In various embodiments, the power delivery problem of the optical engine on the optical extension board may be addressed by reducing the power of the optical engine through direct drive and external lasers, and a vertical connection from the optical engine to the motherboard may not be present. To accommodate cooling requirements, heat sinks or other components may be incorporated for the optical engine on the extension board outside the stiffener. In various embodiments, there are some differences between the electrical and optical connectors. Although the electrical connectors are passive and do not require power delivery, the optical components may require vertical power supply through the base substrate and the extension board. For example, an optical extension substrate routes power, while an electrical extension substrate does not. A common interface may include power connectors for the optical extension substrate, but not for the electrical extension substrate. For instance, whether power delivery to the optical element is vertical or has lateral routing in the optical extension substrate may depend on the positioning of the optical element relative to the base substrate. As an example, if it is in… Figure 1A The extension outside the base substrate region shown on the right (e.g.) Figures 1A to 2 In area 602), horizontal power cabling is required. Figure 2 In this configuration, the optical components are positioned below the stiffening ring, allowing for vertical power wiring. It should be noted that substrate extensions can be used in modules without stiffening rings or in modules where the stiffening ring is positioned on the bottom side of the base substrate rather than on top.

[0041] Figure 3A and 3B These are diagrams illustrating the wire bending of a semiconductor device with an extended substrate according to embodiments of the present invention. These diagrams are merely illustrative and should not unduly limit the scope of the claims. As previously mentioned, electrical connectors (e.g., TwinAx) on the substrate extension may require specific configuration. The required height of curvature for the micro-differential cable stack may be extremely high for some embodiments. However, it is important to note that the substrate extension can reduce the height of micro-differential cable curvature by splitting the cables into two bundles, thereby reducing cable stress and improving reliability. Figure 3A A side view of two bundles of electrical connectors is shown, wherein bundle 312 is coupled to connection region 311A ​​and bundle 313 is coupled to connection region 311B. Both connectors 311A ​​and 311B are attached to substrate extension 310. Figure 3B Provides a top view of two bundles of electrical connectors coupled to two different connection regions, thus avoiding excessive bending caused by a single thick bundle. Additionally, Figure 3A Showing bundles 312 and 313 bent around a stiffening ring 330 connected to a base substrate 301 via a TIM 331.

[0042] Figure 4 This is a simplified diagram illustrating an electrical connection for extending a substrate according to an embodiment of the invention. This diagram is merely illustrative and should not unduly limit the scope of the claims. In various embodiments, miniature differential cable jumper connectors may be used. For example, the miniature differential cable jumper may have a narrower gauge than board-to-board cables (e.g., 36 gauge in jumpers and 34 or higher in board-to-board cables), with a gauge conversion in the E-to-E connector at the panel. To maximize efficiency, an additional miniature differential cable scale conversion may be used from the existing jumper scale (e.g., 36 gauge lines with approximately 600 μm conductor spacing) to a spacing closer to the spacing of 224 Gbps (56 GHz Nyquist PAM4) differential pairs used for multi-mm wiring (e.g., approximately 200 μm conductor spacing with appropriately scaled lines).

[0043] like Figure 4 As illustrated, an electrical connector 411, which may include a micro differential cable connector, is connected to a substrate extension 410. A microcable 412 may be coupled to the electrical connector 411 via a dense pluggable connector. The microcable 412 transitions to a mini-cable 472 (e.g., a larger cable scale of approximately 600 μm at specification 36) only after a short distance (the length required to fan out to a larger cable). For example, the scale transition from microcable 412 to mini-cable 472 (e.g., for a jumper body to a panel) may be provided “in-line,” meaning that for each cable, the smaller scale will transition independently to the larger scale, potentially with permanent connections rather than requiring a group of connectors. At panel 475, the mini-cable 472 is transitioned to a board-to-board cable 474 using a pluggable E-to-E scale transition (e.g., an electrical-to-electrical pluggable connector where the conductor thickness specification changes). In various embodiments, the wired connection section 470 includes a set of custom-designed bundled cables with an embedded transition from mini to micro and a predetermined three-dimensional shape to conform to the physical layout required for the transition from a micro cable connector to a panel E-to-E connector.

[0044] In various implementations, the differential pair cables used for module-to-module connections within the board may use only microscale cables or their applicable scale-shifting cables. Electrical substrate extensions may be used with single-scale differential pair cables (at the expense of lower area connection density), or scale-shifting cables may be used with array connectors without extension boards, regardless of whether the connectors are direct-to-module (commonly packaged I / O) or to-board connections.

[0045] For example, to reduce or eliminate high-speed signal routing from a base module to the motherboard in a system with multiple modules on an onboard, a common-package I / O solution is needed for module-to-module routing within the board. This short-range routing may be electrical rather than optical and can be achieved by directly connecting a common-package cable from the substrate expansion array connector of one device to the substrate expansion array connector of another device. A variation could be to use a single double-ended electrical expansion board as a flying bridge between devices.

[0046] Figure 5 This is a simplified diagram illustrating a glass substrate with an extended substrate according to an embodiment of the invention. This diagram is merely illustrative and should not unduly limit the scope of the claims. In the case of using a substrate extension with a glass base substrate, the glass substrate extension can be used to ensure accurate matching of the coefficients of thermal expansion. The use of an extension plate will still provide the benefit of reducing the length of high-speed signal routing on the glass substrate base module, enabling easier design optimization. On the glass substrate, stiffening rings may be unnecessary, meaning the substrate extension does not need to significantly protrude beyond the base substrate. For example, substrate extension 510 mounted on base substrate 501 extends only slightly beyond the base substrate, providing sufficient contact area for mounting electrical connector 511 without the space occupied by stiffening rings. Similarly, substrate extension 520 mounted on base substrate 501 extends only slightly beyond the base substrate, providing sufficient contact area for mounting optical circuit connector 521 without the need for stiffening rings. In various embodiments, it remains advantageous to customize semiconductor packages for electrical or optical I / O after assembling the base substrate. For example, if matching the coefficient of thermal expansion (CTE) is required, then the substrate extension may be glass-based. In addition, by placing most of the differential signal routing length on the substrate extension, the complexity of supporting low-loss routing on the base glass substrate can be reduced.

[0047] Embodiments of the present invention offer various advantages. They are implemented based on a selected substrate extension custom base substrate for electrical or optical co-packaged input / output (I / O). This differs from conventional methods, which require designing a module base substrate and potentially SerDes circuitry systems specifically for co-packaged I / O (electrical or optical) types.

[0048] Existing co-packaged optical solutions are typically expensive and power-intensive for in-board connections, effectively limiting such solutions to a single module per board if cross-board connections are to be avoided. In contrast, embodiments of the present invention are more cost-effective and power-efficient.

[0049] Furthermore, these embodiments offer high area (extended by substrate) and connectivity density (through scale-shifting cables) to achieve the total bandwidth required for module-to-board edge or module-to-module-board communication. Existing common packaging methods (whether optical or electrical) typically utilize a one-dimensional array of cables or fiber optic connectors along the module perimeter, the density of which is insufficient to meet bandwidth requirements.

[0050] Embodiments of the present invention can be used in distributed high-performance computing or artificial intelligence systems consisting of numerous replicated interconnected processing modules spanning several device racks. These systems require module-to-module connectors of varying lengths, with short links favoring electrical signaling to reduce cost and power consumption, while longer links require optical signaling. However, systems with high-bandwidth signaling requirements can benefit from embodiments of the present invention, even without the need to customize a common underlying module for electrical-to-optical I / O.

[0051] A general aspect of the present invention includes a semiconductor device comprising a first substrate that may include a first top surface and a first bottom surface. The first top surface may include a first region, a second region, and a third region, the third region being positioned between the first region and the second region. The first region may include a first plurality of electrical contacts. The second region may include a second plurality of electrical contacts. The third region may include a third plurality of electrical contacts. The device further includes circuitry including a fourth plurality of electrical contacts electrically coupled to the third plurality of electrical contacts. The device further includes a second substrate that may include a fourth region and a fifth region, the fourth region including a fifth plurality of electrical contacts electrically coupled to the first plurality of electrical contacts, the fourth region being positioned above the first region, and the fifth region being positioned outside the first substrate. The device further includes a third substrate that may include a sixth region and a seventh region, the sixth region including a sixth plurality of electrical contacts electrically coupled to the second plurality of electrical contacts, the sixth region being positioned above the first region, and the fifth region being positioned outside the first substrate. The device further includes an electrical connector electrically coupled to the second substrate. The device also includes an optical connector electrically coupled to the third substrate.

[0052] The implementation may include one or more of the following features: The circuit may be directly coupled to the first substrate using the third plurality of electrical contacts and the fourth plurality of electrical contacts. The circuit is positioned above the third region. The optical connector may include optical circuitry. The electrical connector may include a copper connector. The semiconductor device may include a plurality of electronic devices coupled to the circuit. The semiconductor device may include a stiffening ring comprising an eighth region and a ninth region, the eighth region being coupled to the fourth region and the ninth region being coupled to the third region. The stiffening ring may further include a tenth region coupled to the sixth region. The circuit is electrically coupled to the second substrate via the first substrate. The semiconductor device may include a photonic integrated circuit coupled to the seventh region. For example, the term "photonic integrated circuit" may refer to an integrated circuit incorporating elements capable of interacting with light in various ways (such as processing or manipulating optical signals). The first bottom surface may include a seventh plurality of electrical contacts. The semiconductor device may include a cable jumper coupled to the second substrate. For example, "cable jumper" may refer to a short conductor used to establish a connection between different electronic components or points. The semiconductor device may include an optical fiber jumper coupled to the third substrate. The semiconductor device may include a thermal interface material coupled to the second substrate. For example, "optical fiber jumper" may refer to a short optical fiber segment used to create optical connections between various optical components.

[0053] Another general aspect of the present invention provides a semiconductor device comprising a first substrate, the first substrate comprising a first top surface and a first bottom surface. The first top surface may comprise a first region, a second region, and a third region, the third region being positioned between the first region and the second region. The first region may comprise a first plurality of electrical contacts. The second region may comprise a second plurality of electrical contacts. The third region may comprise a third plurality of electrical contacts. The device further comprises a circuit comprising a fourth plurality of electrical contacts electrically coupled to the third plurality of electrical contacts. The device further comprises a second substrate comprising a fourth region and a fifth region. The fourth region may comprise a fifth plurality of electrical contacts electrically coupled to the first plurality of electrical contacts, the fourth region being positioned above the first region, and the fifth region being positioned outside the first substrate. The device further comprises a third substrate comprising a sixth region and a seventh region. The sixth region may comprise a sixth plurality of electrical contacts electrically coupled to the second plurality of electrical contacts, the sixth region being positioned above the first region, and the fifth region being positioned outside the first substrate. The device further includes a stiffening ring comprising an eighth region and a ninth region, the eighth region being thermally coupled to the fourth region and the ninth region being coupled to the third region.

[0054] Another general aspect of the present invention provides a semiconductor device comprising a first substrate, the first substrate comprising a first top surface and a first bottom surface, the first top surface comprising a first region, a second region, and a third region, the third region being positioned between the first region and the second region. The first region may comprise a first plurality of electrical contacts, the second region may comprise a second plurality of electrical contacts, and the third region may comprise a third plurality of electrical contacts. The device further comprises a circuit comprising a fourth plurality of electrical contacts electrically coupled to the third plurality of electrical contacts. The device further comprises a second substrate comprising a second top region and a second bottom region. The second substrate may comprise a fourth region and a fifth region, the fourth region being positioned on the second top region and the fifth region being positioned on the second bottom region. The fourth region may comprise a fifth plurality of electrical contacts electrically coupled to the first plurality of electrical contacts, the fourth region being positioned above the first region and the fifth region being positioned outside the first substrate. The device further includes a third substrate that may include a sixth region and a seventh region. The sixth region may include a sixth plurality of electrical contacts electrically coupled to the second plurality of electrical contacts. The sixth region is positioned above the first region. The fifth region is positioned outside the first substrate. The seventh region may include a seventh plurality of electrical contacts. The device further includes optical circuitry that may include an electrical interface and an optical interface. The electrical interface is coupled to the seventh plurality of electrical contacts.

[0055] Although the foregoing is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. Therefore, the above description and illustrations should not be construed as limiting the scope of the invention as defined by the appended claims.

Claims

1. A semiconductor device comprising: A first substrate includes a first top surface and a first bottom surface. The first top surface includes a first region, a second region, and a third region. The third region is positioned between the first region and the second region. The first region includes a first plurality of electrical contacts, the second region includes a second plurality of electrical contacts, and the third region includes a third plurality of electrical contacts. An integrated circuit includes a fourth plurality of electrical contacts electrically coupled to the third plurality of electrical contacts; The second substrate includes a fourth region and a fifth region, the fourth region including a fifth plurality of electrical contacts electrically coupled to the first plurality of electrical contacts, the fourth region being positioned above the first region, and the fifth region being positioned outside the first substrate; A third substrate includes a sixth region and a seventh region, the sixth region including a sixth plurality of electrical contacts electrically coupled to the second plurality of electrical contacts, the sixth region being positioned above the second region, and the seventh region being positioned outside the first substrate; A stiffening ring coupled to the fourth region and the sixth region, the stiffening ring including an opening exposing a portion of the third region; An electrical connector, which is electrically coupled to the second substrate; and An optical connector, which is coupled to the third substrate.

2. The semiconductor device of claim 1, wherein the integrated circuit is directly mounted to the first substrate using the third plurality of electrical contacts and the fourth plurality of electrical contacts.

3. The semiconductor device of claim 1, wherein the integrated circuit is positioned above the third region.

4. The semiconductor device of claim 1, wherein the optical connector is coupled to an optical circuit.

5. The semiconductor device of claim 1, wherein the electrical connector comprises a copper connector.

6. The semiconductor device of claim 1, further comprising a plurality of electronic devices coupled to the integrated circuit.

7. The semiconductor device of claim 1, wherein the integrated circuit is electrically coupled to the second substrate via the first substrate.

8. The semiconductor device of claim 1, further comprising a photonic integrated circuit coupled to the seventh region.

9. The semiconductor device of claim 1, wherein the first bottom surface includes a seventh plurality of electrical contacts.

10. The semiconductor device of claim 1, further comprising a cable jumper coupled to the second substrate.

11. The semiconductor device of claim 1, further comprising an optical fiber jumper coupled to the third substrate.

12. The semiconductor device of claim 1, further comprising a thermal interface material coupled to the second substrate.

13. A semiconductor device comprising: A first substrate includes a first top surface and a first bottom surface. The first top surface includes a first region, a second region, and a third region. The third region is positioned between the first region and the second region. The first region includes a first plurality of electrical contacts, the second region includes a second plurality of electrical contacts, and the third region includes a third plurality of electrical contacts. The integrated circuit includes a fourth plurality of electrical contacts, which are electrically coupled to the third plurality of electrical contacts; The second substrate includes a fourth region and a fifth region, the fourth region including a fifth plurality of electrical contacts electrically coupled to the first plurality of electrical contacts, the fourth region being positioned above the first region, and the fifth region being positioned outside the first substrate; A third substrate includes a sixth region and a seventh region, the sixth region including a sixth plurality of electrical contacts electrically coupled to the second plurality of electrical contacts, the sixth region being positioned above the second region, and the seventh region being positioned outside the first substrate; and A stiffening ring includes a ring comprising an eighth region and a ninth region, the eighth region being thermally coupled to the fourth region and the ninth region being coupled to the sixth region, the stiffening ring including an opening exposing a portion of the third region.

14. The semiconductor device according to claim 13, wherein: The fifth region includes a seventh plurality of electrical contacts coupled to an electrical connector; and The seventh region includes an eighth plurality of electrical contacts coupled to the optical circuitry.

15. The semiconductor device of claim 14, further comprising: A cable jumper, which is coupled to the electrical connector; and The optical circuit includes an electrical interface and an optical interface coupled to the eighth plurality of electrical contacts.

16. A semiconductor device comprising: A first substrate includes a first top surface and a first bottom surface. The first top surface includes a first region, a second region, and a third region. The third region is positioned between the first region and the second region. The first region includes a first plurality of electrical contacts, the second region includes a second plurality of electrical contacts, and the third region includes a third plurality of electrical contacts. The integrated circuit includes a fourth plurality of electrical contacts, which are electrically coupled to the third plurality of electrical contacts; The second substrate includes a second top region and a second bottom region, and the second substrate further includes a fourth region and a fifth region, the fourth region being positioned on the second top region, the fifth region being positioned on the second bottom region, the fourth region including a fifth plurality of electrical contacts electrically coupled to the first plurality of electrical contacts, and the fourth region being positioned above the first region; A third substrate includes a sixth region and a seventh region, the sixth region including a sixth plurality of electrical contacts electrically coupled to the second plurality of electrical contacts, the sixth region being positioned above the second region, and the seventh region including a seventh plurality of electrical contacts; A stiffening ring coupled to the fourth region and the sixth region, the stiffening ring including an opening exposing a portion of the third region; and An optical circuit, comprising an electrical interface and an optical interface, wherein the electrical interface is coupled to the seventh plurality of electrical contacts.

17. The semiconductor device of claim 16, wherein the optical circuitry is configured to convert an electrical signal into an optical signal.

18. The semiconductor device of claim 16, wherein the integrated circuit is electrically coupled to the optical circuit via the first substrate and the third substrate.

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