Quadrature frequency divider error correction

Abstract

This disclosure relates to quadrature frequency divider error correction. A circuit includes: a frequency divider configured to receive a plurality of first frequency input clock signals and provide a plurality of second frequency output clock signals, wherein the frequencies of the plurality of second frequency output clock signals are lower than the plurality of first frequency input clock signals; a phase detector configured to determine a difference between the plurality of second frequency output clock signals; a low-pass filter configured to measure a clock signal interval error associated with the plurality of second frequency output clock signals based on the difference between the plurality of second frequency output clock signals and to generate one or more control signals in response to the clock signal interval error; and a control unit configured to generate one or more corrected first frequency input clock signals based on the one or more control signals.

Description

Technical Field

[0001] This disclosure generally relates to systems and methods for frequency division, including (but not limited to) systems and methods for providing clock signals of different frequencies and synchronizing multiple clock dividers. Background Technology

[0002] Over the past few decades, the market for electronic devices has grown exponentially, driven by the use of portable devices and the increasing connectivity, data transmission, and data storage in various devices. Many modern electronic devices rely on clock signals. In some embodiments, a clock signal can be defined as a signal that oscillates at a constant frequency between high and low states and is used to synchronize the operation of one or more circuits and devices. For example, a system-on-a-chip (SoC) typically uses several clock domains with different programmable frequencies to implement various functions and cover different operating modes. Summary of the Invention

[0003] In one aspect, this disclosure relates to a circuit comprising: a frequency divider configured to receive a plurality of first frequency input clock signals and provide a plurality of second frequency output clock signals, wherein the frequencies of the plurality of second frequency output clock signals are lower than the plurality of first frequency input clock signals; a phase detector configured to determine a difference between the plurality of second frequency output clock signals; a low-pass filter configured to measure a clock signal interval error associated with the plurality of second frequency output clock signals based on the difference between the plurality of second frequency output clock signals and to generate one or more control signals in response to the clock signal interval error; and a control unit configured to generate one or more corrected first frequency input clock signals based on the one or more control signals.

[0004] In another aspect, this disclosure relates to a method comprising: receiving a plurality of first frequency input clock signals; providing a plurality of second frequency output clock signals, wherein the frequencies of the plurality of second frequency output clock signals are lower than the plurality of first frequency input clock signals; determining a difference between the plurality of second frequency output clock signals to determine whether a clock signal interval error exists; measuring the clock signal interval error; determining one or more control signals based on the clock signal interval error; and generating a corrected first frequency input clock signal based on the one or more control signals.

[0005] In another aspect, this disclosure relates to a non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to: receive a plurality of first frequency input clock signals; provide a plurality of second frequency output clock signals, wherein the frequencies of the plurality of second frequency output clock signals are lower than the plurality of first frequency input clock signals; determine a difference between the plurality of second frequency output clock signals to determine whether a clock signal interval error exists; measure the clock signal interval error; determine one or more control signals based on the clock signal interval error; and generate one or more corrected first frequency input clock signals based on the one or more control signals. Attached Figure Description

[0006] The various objects, aspects, features, and advantages of this disclosure will be more clearly and better understood through a detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals identify corresponding elements throughout. In the drawings, like reference numerals generally indicate like, functionally similar, and / or structurally similar elements.

[0007] Figure 1A It is a block diagram depicting an embodiment of a computing environment comprising one or more access points communicating with one or more wireless devices or stations;

[0008] Figure 1B and 1C This is a block diagram depicting an embodiment of a computing device that can be used in conjunction with the methods and systems described herein.

[0009] Figure 2 It is a block diagram depicting an exemplary system comprising a pair of fractional frequency dividers according to one or more embodiments.

[0010] Figure 3 Includes two timing diagrams illustrating the alignment clock signal for an orthogonal frequency divider according to one or more embodiments.

[0011] Figure 4 This is a timing diagram illustrating the first skew clock signal for an orthogonal frequency divider according to one or more embodiments.

[0012] Figure 5 This is a timing diagram illustrating the second skew clock signal for an orthogonal frequency divider according to one or more embodiments.

[0013] Figure 6 This is a schematic circuit diagram illustrating an orthogonal frequency divider according to one or more embodiments.

[0014] Figure 7 It is according to one or more embodiments for Figure 6 Block diagram of the error correction system for the quadrature frequency divider.

[0015] Figure 8 This demonstrates the relationship between [the two] according to one or more embodiments. Figure 7 The first timing diagram of the clock signal associated with the phase detector of the error correction system.

[0016] Figure 9 This demonstrates the relationship between [the two] according to one or more embodiments. Figure 7 The second timing diagram of the clock signal associated with the phase detector of the error correction system.

[0017] Figures 10A to 10B The diagram illustrates a control signal for controlling a clock signal according to one or more embodiments, and a corresponding clock signal generated by the control signal.

[0018] Figure 11 This is a schematic diagram illustrating multiple high-speed clocks that undergo frequency division to generate multiple sub-rate clocks according to one or more embodiments.

[0019] Figure 12 This illustrates a method for using one or more embodiments. Figure 11 The first timing diagram of multiple high-speed clocks and sub-rate clocks.

[0020] Figure 13A This is a schematic diagram of a sliding divider circuit for synchronizing multiple sub-rate clocks according to one or more embodiments.

[0021] Figures 13B to 13C It is a waveform diagram showing a waveform signal for a clock divider synchronization technique according to one or more embodiments.

[0022] Figure 14 This is a first circuit diagram illustrating a frequency divider synchronizer according to one or more embodiments.

[0023] Figure 15 This is a second circuit diagram illustrating a frequency divider synchronizer according to one or more embodiments.

[0024] Figure 16 This is a third circuit diagram illustrating a frequency divider synchronizer according to one or more embodiments.

[0025] Figure 17 This is a fourth circuit diagram illustrating a frequency divider synchronizer according to one or more embodiments.

[0026] Details of various embodiments of the method and system are set forth in the accompanying drawings and the following description. Detailed Implementation

[0027] The entire contents of the following IEEE standards (including any draft versions of such standards) are hereby incorporated herein by reference for all purposes and are thus incorporated as part of this disclosure: IEEE 802.3, IEEE 802.11x, IEEE 802.11ad, IEEE 802.11ah, IEEE 802.11aj, IEEE 802.16 and 802.16a, and IEEE 802.11ac. Furthermore, although this disclosure may refer to aspects of these standards, it is in no way limited by these standards.

[0028] The following description of the various embodiments herein may be helpful in reading the descriptions of the sections and their corresponding contents. Section A describes network and computing environments in which frequency division can be used according to some embodiments described herein, and Sections B through D describe embodiments of frequency division systems and methods. Although this disclosure may refer to various aspects of standards and specifications, this disclosure is in no way limited to those aspects.

[0029] In some embodiments, the systems and methods provide a clock domain for integrated circuits (e.g., SoCs). The systems and methods can reduce the area and power consumption associated with phase-locked loop (PLL) cores used to generate clock signals. In some embodiments, the systems and methods meet frequency resolution, range, and low jitter requirements that are difficult to achieve using conventional PLL cores. In some embodiments, fractional dividers are provided in silicon products, application-specific integrated circuits (ASICs), digital signal processors, programmable logic circuits, SoCs, or standard products requiring highly programmable, low-jitter clock generators. In some embodiments, fractional dividers provide frequency resolution based on very fine ratios, use small silicon areas, provide low jitter performance, provide unlimited frequency modulation capabilities, and are scalable and portable to newer integrated circuit processes. In some embodiments, fractional divider systems and methods are used in modern high-speed and energy-efficient data communication and processing systems that include (but are not limited to) any backplane, serializer / deserializer (SERDES), Ethernet physical layer (PHY), optical transceivers, digital signal processor (DSP) modules in coherent transceivers, input / output (I / O) interfaces, multi-core processors, memory, power managers, and wireless transceivers.

[0030] Some embodiments relate to frequency dividers for providing a lower frequency clock output based on a higher frequency clock input. In some embodiments, the frequency divider may produce an output clock signal with clock signal interval errors. The systems and methods described herein provide techniques for correcting clock signal interval errors.

[0031] Furthermore, some embodiments involve enabling sub-rate clock synchronization in communication systems. In many analog-to-digital converters (ADCs), deserializer circuits (SERDES) in link communications, or even radio receivers (RF radios), information is processed synchronously using clocks. Because data rates have increased to well above 20 Gb / s, it is generally preferable to use multiple sub-rate clocks to process data. For example, in one embodiment, a data rate of 20 Gb / s can be captured using two 10 GHz clocks or four 5 GHz clocks, etc. When using such sub-rate clocks in a communication system with a specific data rate (e.g., 20 Gb / s), it is desirable that the multiple sub-rate clocks be spaced as evenly as possible in time, such that the timing reference is equal to the full data rate itself. For example, in the case of a 20 Gb / s system, the timing reference would be 20 GHz or a period of 50 ps. In this case, the data rate could be implemented by a sub-rate system with four 5 GHz clocks, where the rising edges (timing references) of the four clocks are ideally spaced exactly 50 ps apart. In some embodiments, a rising edge may refer to the time when the clock signal moves from a low state (e.g., 0) to a high state (e.g., 1). To ensure this, the sub-rate clocks can be synchronized when the frequency is divided to generate a sub-rate clock. In some embodiments, the sub-rate clock signal may refer to the output signal of a frequency divider that is at a lower frequency than the input of the frequency divider. The systems and methods described herein provide techniques for providing this synchronization.

[0032] A. Computing and Network Environment

[0033] Before discussing specific embodiments of this solution, it may be helpful to describe the operating environment and associated system components (e.g., hardware elements) in conjunction with the methods and systems described herein. References Figure 1A This describes an embodiment of a network environment. The network may include or communicate with one or more Storage Area Networks (SANs), security adapters, or Ethernet Aggregator Network Adapters (CNAs). In a brief overview, the network environment includes a wireless communication system comprising one or more access points 106, one or more wireless communication devices 102, and network hardware components 192. For example, wireless communication devices 102 may include laptop computers 102, tablet computers 102, personal computers 102, wearable devices 102, vehicles 102 (e.g., cars, drones, intelligent vehicles, robotic units, etc.), smart TVs 102, game consoles 102, Internet of Things (IoT) devices 102, cellular phone devices 102, and / or any other electronic devices capable of wireless communication. Reference will be made to... Figure 1B and 1CMore detailed descriptions are provided for embodiments of the wireless communication device 102 and / or access point 106. In one embodiment, the network environment may be an ad hoc network environment, an infrastructure wireless network environment, a wired network coupled to a wireless network, a subnet environment, and a combination thereof.

[0034] Access points (APs) 106 are operatively coupled to network hardware 192 via a local area network (LAN) connection. Network hardware 192 (which may include one or more routers, gateways, switches, bridges, modems, system controllers, devices, etc.) provides LAN connectivity for the communication system. Each of the access points 106 may have an associated antenna or antenna array for communicating with wireless communication devices 102 in its area. Wireless communication devices 102 may register with a specific access point 106 to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configuration). For direct connections (i.e., point-to-point communication), some wireless communication devices 102 may communicate directly via allocated channels and communication protocols. Some wireless communication devices 102 may be mobile or stationary relative to access points 106.

[0035] In some embodiments, access point 106 includes means or modules (combining hardware and software) that allow wireless communication device 102 to connect to a wired network using Wi-Fi or other standards. Access point 106 may sometimes be referred to as a wireless access point (WAP). Access point 106 may be configured, designed, and / or constructed to operate in a wireless local area network (WLAN). In some embodiments, access point 106 may be connected as a standalone device to a router (e.g., via a wired network). In other embodiments, access point 106 may be a component of a router. Access point 106 may provide network access to multiple devices. For example, access point 106 may connect to a wired Ethernet connection and provide wireless connectivity using the radio frequency link of another wireless communication device 102 to utilize the wired connection. Access point 106 may be constructed and / or configured to support standards for transmitting and receiving data using one or more radio frequencies. The standards and frequencies used may be defined by IEEE (e.g., the IEEE 802.11 standard). Access point 106 can be configured and / or used to support public Internet hotspots and / or extend the Wi-Fi signal range of the network on an internal network.

[0036] In some embodiments, access point 106 may be used in a home or building wireless network (e.g., IEEE 802.11, Bluetooth, ZigBee, or any other type of radio frequency-based network protocol and / or its variants). Each of the wireless communication devices 102 may include a built-in radio and / or be coupled to a radio. Such wireless communication devices 102 and / or access point 106 may operate in accordance with various aspects of the present disclosure to enhance performance, reduce cost and / or size, and / or enhance broadband applications. Each wireless communication device 102 may have the capability to act as a client node seeking access to resources (e.g., data and connections to network nodes such as servers) via one or more access points.

[0037] The network connection may include any type and / or form of network and may include any of the following: point-to-point network, broadcast network, telecommunications network, data communication network, or computer network. The network topology may be a bus, star, or ring network topology. The network may have any such network topology known to a person of ordinary skill in the art capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0038] The communication device 102 and the access point 106 can be deployed as any type and form of computing device and / or perform on any type and form of computing device, such as a computer, network device or device capable of communicating on any type and form of network and performing the operations described herein. Figure 1B and 1C A block diagram depicting a computing device 100 that can be used to implement embodiments of wireless communication device 102 or access point 106. (See diagram for reference.) Figure 1B and 1C As shown, each computing device 100 includes a central processing unit 121 and a main memory unit 122. Figure 1B As shown, computing device 100 may include storage device 128, mounting device 116, network interface 118, I / O controller 123, display devices 124a to n, keyboard 126, and pointing device 127 such as a mouse. Storage device 128 may include (but is not limited to) operating system and / or software. Figure 1C As shown, each computing device 100 may also include additional optional components such as memory port 103, bridge 170, one or more input / output devices 130a to 130n (generally referred to by component symbol 130), and cache memory 140 communicating with central processing unit 121.

[0039] Central processing unit 121 is any logic circuit system that responds to and processes instructions fetched from main memory unit 122. In many embodiments, central processing unit 121 is provided by, for example, a microprocessor unit manufactured by Intel Corporation of Mountain View, California; a microprocessor unit manufactured by International Business Machines of White Plains, New York; or a microprocessor unit manufactured by Advanced Micro Devices of Sunnyvale, California. Computing device 100 may be based on any of these processors or any other processor capable of operating as described herein.

[0040] Main memory unit 122 may be one or more memory chips capable of storing data and allowing access from any storage location by central processing unit 121, such as any type or variant of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND (“NAND”) flash or NOR (“NOR”) flash, and solid-state drive (SSD). Main memory 122 may be based on any of the aforementioned memory chips or any other available memory chips capable of operating as described herein. Figure 1B In the illustrated embodiment, the central processing unit 121 communicates with the main memory 122 via the system bus 150 (which will be described in more detail below). Figure 1C An embodiment of a computing device 100 in which the central processing unit 121 communicates directly with the main memory 122 via memory port 103 is depicted. For example, in Figure 1C In this context, the main memory 122 can be DRAM.

[0041] Figure 1C An embodiment is depicted in which the central processing unit 121 communicates directly with the cache memory 140 via a secondary bus (wired, referred to as the back bus). In other embodiments, the central processing unit 121 communicates with the cache memory 140 using a system bus 150. The cache memory 140 typically has a faster response time than the main memory 122 and is provided by, for example, SRAM, BSRAM, or EDRAM. Figure 1CIn the illustrated embodiment, the central processing unit 121 communicates with various I / O devices 130 via a local system bus 150. Various buses can be used to connect the central processing unit 121 to any of the I / O devices 130, such as the VESA VL bus, ISA bus, EISA bus, Micro Channel Architecture (MCA) bus, PCI bus, PCI-X bus, PCI Fast Bus, or NuBus. For an embodiment where the I / O device is a video display 124, the central processing unit 121 may communicate with the video display 124 using an Advanced Graphics Port (AGP). Figure 1C An embodiment of a computer or computing device 100 in which the central processing unit 121 can communicate directly with the I / O device 130b, for example, via HyperTransport, Fast Input / Output, or Infinite Bandwidth communication technologies is described. Figure 1C An embodiment in which local bus and direct communication are mixed is also depicted: the central processing unit 121 communicates with I / O device 130a using a local interconnect bus, while simultaneously communicating directly with I / O device 130b.

[0042] Various I / O devices 130a to 130n may exist in the computing device 100. Input devices include a keyboard, mouse, trackpad, trackball, microphone, dial, touchpad, touch screen, and drawing tablet. Output devices include a video display, speakers, inkjet printer, laser printer, projector, and dye-to-sublimation printer. I / O devices 130a to 130n can be controlled by I / O controller 123, such as... Figure 1B As shown in the figure. The I / O controller 123 can control one or more I / O devices 130a to 130n, such as a keyboard 126 and pointing devices 127, such as a mouse or optical pen. In addition, the I / O devices 130a to 130n can also provide storage and / or mounting media 116 to the computing device 100. In other embodiments, the computing device 100 can provide USB connectivity (not shown) to receive handheld USB storage devices, such as the USB flash drive series devices manufactured by Twintech Industry, Inc. of Los Alamitos, California.

[0043] Refer again Figure 1BThe computing device 100 may support any suitable installation device 116, such as a disk drive, CD-ROM drive, CD-R / RW drive, DVD-ROM drive, flash memory drive, tape drive of various formats, USB device, hard disk, network interface, or any other device suitable for installing software and programs. The computing device 100 may further include storage devices for storing the operating system and other related software, and for storing application software programs (e.g., any program or software 120 used to implement (e.g., software 120, which is configured and / or designed for) the systems and methods described herein), such as one or more hard disk drives or a redundant array of independent disks. Optionally, any of the installation devices 116 may also be used as storage devices. Additionally, the operating system and software 120 may run from a bootable medium.

[0044] Furthermore, the computing device 100 may include a network interface 118 to interface with the network 104 via various connections, including (but not limited to) standard telephone lines, LAN or WAN links (e.g., 802.11, T1, T3, 56kb, X.25, SNA, DECNET), broadband connections (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet over SONET), wireless connections, or combinations of any or all of the above. Connections may be established using various communication protocols (e.g., TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax, and Direct Asynchronous Connection). In one embodiment, computing device 100 communicates with other computing devices 100 via any type and / or form of gateway or tunneling protocol, such as Secure Sockets Layer (SSL) or Transport Layer Security (TLS). Network interface 118 may include a built-in network adapter, network interface card, PCMCIA network card, card bus network adapter, wireless network adapter, USB network adapter, modem, or any other means suitable for interfacing computing device 100 to any type of network capable of communicating and performing the operations described herein.

[0045] In some embodiments, computing device 100 may include or be connected to one or more display devices 124a to 124n. Consequently, any of the I / O devices 130a to 130n and / or the I / O controller 123 may include any type and / or form of suitable hardware, software, or a combination of hardware and software to support, implement, or provide connectivity to and use of display devices 124a to 124n by computing device 100. For example, computing device 100 may include any type and / or form of video adapter, video card, driver, and / or library to interface with, communicate with, connect to, or otherwise use display devices 124a to 124n. In one embodiment, a video adapter may include multiple connectors for interface with display devices 124a to 124n. In other embodiments, computing device 100 may include multiple video adapters, each connected to display devices 124a to 124n. In some embodiments, any portion of the operating system of computing device 100 may be configured to use multiple displays 124a to 124n. Those skilled in the art should recognize and understand that the computing device 100 can be configured to have one or more display devices 124a to 124n in various ways and embodiments.

[0046] In a further embodiment, I / O device 130 may be a bridge between system bus 150 and external communication buses such as: USB bus, Apple desktop bus, RS-232 serial connection, SCSI bus, FireWire bus, FireWire 800 bus, Ethernet bus, AppleTalk bus, Gigabit Ethernet bus, Asynchronous Transfer Mode bus, Fibre Channel bus, Serial Attached Small Computer System Interface bus, USB connection, or HDMI bus.

[0047] Figure 1B and 1CThe computing device or system 100 of the types described herein can operate under the control of an operating system that controls the scheduling of system tasks and access to system resources. The computing device 100 can run any operating system, such as any version of Microsoft Windows, different versions of Unix and Linux, any version of macOS for Apple computers, any embedded operating system, any real-time operating system, any open-source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include (but are not limited to): Android, manufactured by Google; Windows 7 and 8, manufactured by Microsoft Corporation of Redmond, Washington; macOS, manufactured by Apple Computer of Cupertino, California; WebOS, manufactured by RIM; OS / 2, manufactured by International Business Machines Corporation of Armonk, New York; and free operating systems distributed by Caldera Corporation of Salt Lake City, Utah, or any type and / or form of Unix operating system, etc.

[0048] The computing device 100 may be any workstation, telephone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunications device, media playback device, gaming system, mobile computing device, or any other type and / or form of computing, telecommunications, or media device capable of communication. The computing device 100 has sufficient processor performance and memory capacity to perform the operations described herein.

[0049] In some embodiments, computing device 100 may have a different processor, operating system, and input device consistent with the device. For example, in one embodiment, computing device 100 is a smartphone, mobile device, tablet computer, or personal digital assistant. In other embodiments, computing device 100 is an Android-based mobile device, an iPhone smartphone manufactured by Apple Computer, Cupertino, California, or a Blackberry, or a WebOS-based handheld device or smartphone, such as a device manufactured by Research In Motion Limited. Furthermore, computing device 100 may be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer, or other form of computing or telecommunications device capable of communication and having sufficient processor performance and memory capacity to perform the operations described herein. The above-described aspects of the operating environment and components will be understood in the context of the systems and methods disclosed herein.

[0050] B. Frequency divider

[0051] refer to Figure 2 System 200 is a DSP SERDES interface for complex SoCs. Although Figure 2 This description is for a specific application, but the frequency division system and method can be used in any electronic application. System 200 can be used for reference. Figure 1A In the system described in C and / or with reference Figure 1A Use it with the system described in C.

[0052] In some embodiments, system 200 includes signal source 202, analog-to-digital converter / digital-to-analog converter (ADC / DAC) unit 204, DSP / PHY unit 206, high-speed SERDES unit 208, signal source 210, fractional divider 212, and fractional divider 214. In some embodiments, units 204, 206, and 208 can operate at different clock frequencies (e.g., driven by different clock signals). In some embodiments, fractional dividers 212 and 214 provide programmable levels of synchronous fractional division for the DSP / PHY unit 206 or any other type of electronic device.

[0053] In some embodiments, signal source 202 is a crystal integrated circuit that provides a first reference frequency signal at a first frequency. The first reference frequency signal is provided to ADC / DAC unit 204. In some embodiments, signal source 210 is a crystal integrated circuit that provides a second reference frequency signal at a second frequency. The second reference frequency signal is provided to SERDES unit 208.

[0054] The ADC / DAC unit 204 is a high-speed macro, cell, circuit, logic, or other implementation that provides data to and receives data from the DSP / PHY unit 206. In some embodiments, the ADC / DAC unit 204 includes an integer or fractional N PLL 220. The PLL 220 receives a reference frequency signal from the signal source 202 and provides a clock signal at a first clock frequency. In some embodiments, the first clock signal may be at a frequency F. I / O1 The provided clock signal is a square wave or other signal used to drive gates, processors, or other logic. The first clock signal may be a segment (e.g., an integer or fractional) of a reference frequency signal and may be used by the ADC / DAC unit 204 to convert or otherwise process the data.

[0055] DSP / PHY unit 206 processes data provided between units 204 and 208. DSP / PHY unit 206 includes first-in-first-out (FIFO) memory 222 and FIFO memory 224. FIFO memory 222 and FIFO memory 224 rely on communication synchronization between processing units 204 and 208 based on clock signals provided from fractional dividers 212 and 214.

[0056] SERDES unit 208 is a high-speed macro, cell, circuit, logic, or other implementation that provides data to and receives data from DSP / PHY unit 206. In some embodiments, SERDES unit 208 includes an integer or fractional N PLL 226. PLL 226 receives a reference frequency signal from signal source 210 and provides a clock signal at a second clock frequency. In some embodiments, the second clock signal may be at a frequency F I / O2 The provided clock signal is a square wave or other signal used to drive gates, processors, or other logic. The second clock signal may be a segmented (e.g., integer or fractional) signal from the second reference frequency signal from signal source 210 and may be used by SERDES unit 208 to convert signals and data. The second clock signal may also be provided to fractional divider 214.

[0057] The fractional divider 212 is a macro, cell, circuit, logic, or other implementation that can provide a first divided clock signal with a selectable frequency using fractional frequency division. In some embodiments, the fractional divider 212 divides the first clock signal (e.g., the sum of the quotients of integer P1 and integer Q1 divided by R1) by a divisor to provide a frequency F. DSP1 The first segmented signal. The fractional divider 214 is a macro, cell, circuit, logic, or other implementation that can provide a second segmented clock signal with a selectable frequency using fractional division. In some embodiments, the fractional divider 214 divides the second clock signal by a divisor (e.g., the sum of the quotients of integer P2 and integer Q2 divided by R2) to provide frequency F.DSP2 The second segmented signal. In some embodiments, fractional dividers 212 and 214 are independent fractional divider (FDIV) macros. In some embodiments, fractional dividers 212 and 214 may be quadrature dividers configured to divide the reference signal by 2.

[0058] In some embodiments, units 204 and 208 operate independently at different clock rates, and FIFO memories 222 and 224 depend on clock frequency (F). I / O1 F I / O2 ...etc.) and DSP clock frequency (F DSP1 F DSP2 Precise ratio processing synchronization between (e.g., ...). In some embodiments, the fractional dividers 212 and 214 advantageously do not employ multiple dividers and PLL cores to achieve the desired ratio (F... DSP1 / F I / O1 =N1 / M1,F DSP2 / F I / O2 = N2 / M2, etc.), where N1, M1, N2, and M2 are integers. In some embodiments, the fractional dividers 212 and 214 advantageously do not occupy a large silicon area and do not consume high power, but meet more stringent jitter specifications associated with increased data rates.

[0059] In some embodiments, fractional dividers 212 and 214 are reconfigurable and greatly simplify frequency planning in complex SoCs. In some embodiments, fractional dividers 212 and 214 reuse available high-frequency clock signals from cells 204 and 208 or share a single PLL core to generate multiple independent output clock signals. In some embodiments, fractional dividers 212 and 214 can achieve accurate frequency ratios with very fine delta-sigma (ΔΣ) frequency resolution (up to 44 bits) for both the numerator and denominator. In some embodiments, fractional dividers 212 and 214 are implemented in compact (e.g., one or two orders of magnitude smaller than a PLL core), scalable, and easily portable to newer process-based all-digital circuitry (e.g., fully complementary metal-oxide-semiconductor (CMOS)). In some embodiments, fractional dividers 212 and 214 also achieve excellent low jitter performance (<0.5 ps) across process-voltage-temperature (PVT) variations using adaptive background calibration techniques. rms In some embodiments, the fractional dividers 212 and 214 employ an open-loop architecture that overcomes the bandwidth limitations of the PLL and achieves ideal spread spectrum modulation and instantaneous frequency switching without any frequency overshoot.

[0060] C. Systems and methods for frequency division error correction

[0061] refer to Figure 3Timing diagrams 300 and 302 illustrate aligned clock signals for an orthogonal frequency divider according to an exemplary embodiment. In some embodiments, a frequency divider may refer to circuitry that utilizes latches and / or flip-flops and is configured to receive a higher frequency input clock signal and divide the frequency of the higher frequency input clock signal to generate a lower frequency output clock signal. In some embodiments, a higher frequency input clock signal may refer to an input clock having a frequency higher than that of the lower frequency output clock signal. Conversely, in some embodiments, a lower frequency input clock signal may refer to a clock signal generated as the output of the frequency divider. In some embodiments, an orthogonal frequency divider may refer to a frequency divider of the type that receives two inputs and generates four outputs. In some embodiments, a flip-flop may refer to a circuit element having two stable states that can be used to store binary data. In some embodiments, a latch may refer to a circuit element having two inputs and one output. Timing diagram 300 includes a first clock signal 304 and a second clock signal 306. The first clock signal 304 is a high-frequency clock signal “CK_P”. The second clock signal 306 is a complementary clock signal “CK_N” with an operating period opposite to that of the first clock signal 304. The first clock signal 304 and the second clock signal 306 can be used as input clocks for a clock divider used to generate quadrature clock signals contained in the second timing diagram 302. For example, in some embodiments, the first clock signal 304 can be used as a signal source 202, and the second clock signal 306 can be used as a signal source 210.

[0062] Timing diagram 302 shows the output clock signals 308, 310, 312, and 314 from the quadrature divider. As can be seen, the frequencies of output clock signals 308, 310, 312, and 314 are divided by 2. Furthermore, as can be seen in timing diagram 302, the time intervals 316a to 316d between each of the clock signals are equal and ideally spaced. This type of spacing represents an ideal quadrature divider with no clock signal spacing error.

[0063] refer to Figure 4 Timing diagrams 400 and 402 are shown, illustrating clock signals for an orthogonal divider with clock signal interval error according to an exemplary embodiment. In some embodiments, the clock signal interval error may refer to the output of the clock divider, wherein the timing of the rising edges is unequal between each of the output clock signals. Except... Figure 4 Aside from the clock signal skew shown, timing diagrams 400 and 402 are similar to timing diagrams 300 and 302, respectively. Timing diagram 400 includes a first clock signal 404 and a second clock signal 406. The first clock signal 404 is a high-frequency clock signal "CK_P". The second clock signal 406 is a complementary clock signal "CK_N", which has a working cycle opposite to that of the first clock signal 404. Figure 4As can be seen, the timing skew of the second signal 406 reaches timing 405. The first clock signal 404 and the second clock signal 406 can be used as input clocks for a clock divider used to generate quadrature clock signals included in the second timing diagram 402. For example, in some embodiments, the first clock signal 404 can be used as signal source 202, and the second clock signal 406 can be used as signal source 210.

[0064] Timing diagram 402 shows the output clock signals 408, 410, 412, and 414 from the quadrature divider. As can be seen, the frequencies of the output clock signals 408, 410, 412, and 414 are divided by 2. Furthermore, as can be seen in timing diagram 402, the time intervals 416a to 416d between each of the clock signals are unequal and poorly spaced. This type of spacing demonstrates a quadrature divider with clock signal spacing errors.

[0065] refer to Figure 5 Timing diagrams 500 and 502 are shown, illustrating the clock signals for an orthogonal frequency divider with clock signal interval errors according to an exemplary embodiment. Except... Figure 5 The clock signals shown are skewed due to the input signal having a duty cycle exceeding 50%, and timing diagrams 500 and 502 are similar to 400 and 402, respectively. Timing diagram 500 includes a first clock signal 504 and a second clock signal 506. The first clock signal 504 is a high-frequency clock signal "CK_P". The second clock signal 506 is a complementary clock signal "CK_N", which has a duty cycle opposite to that of the first clock signal 504. Figure 5 As can be seen, the duty cycle of each of the first clock signal 504 and the second clock signal 506 is greater than 50%. The first clock signal 504 and the second clock signal 506 can be used as input clocks for a clock divider used to generate the quadrature clock signals included in the second timing diagram 502. For example, in some embodiments, the first clock signal 504 can be used as signal source 202, and the second clock signal 506 can be used as signal source 210.

[0066] Timing diagram 502 shows the output clock signals 508, 510, 512, and 514 from the quadrature divider. As can be seen, the frequencies of output clock signals 508, 510, 512, and 514 are divided by 2. Furthermore, as can be seen in timing diagram 502, the time intervals 516a to 516d between each of the clock signals are unequal and imperfectly spaced due to the duty cycles of clock signals 504 and 506. This type of spacing demonstrates a quadrature divider with clock signal spacing errors.

[0067] refer to Figure 6The diagram 600 illustrates a quadrature frequency divider 606 according to an exemplary embodiment. Circuit diagram 600 includes a flip-flop 606 configured to divide the frequencies of input clock signals 602 and 604. Specifically, the flip-flop 606 may be a divide-by-2 flip-flop, which may be a circuit component configured to receive the input signal and generate an output signal having half the frequency of the input signal. Specifically, the input clock signal 602 is fed into the frequency divider 606. The divided frequency signal from the frequency divider 606 is then fed into each of latches 608, 610, 612, and 614. Each of the input clock signals 602 and 604 is used to alternate the timing latches 608, 610, 612, and 614 to generate output frequency divided signals 616, 618, 620, and 622. In some embodiments, each of the latches 608, 610, 612, and 614 may be identical. In one embodiment, input clock signals 602 and 604 each have a 50% duty cycle and are skew-free. In this case, output frequency signals 616, 618, 620, and 622 will not have any clock signal interval error. However, in different embodiments, input clock signals 602 and 604 may have a duty cycle higher or lower than 50% and / or may have some timing skew. In this case, quadrature divider 606 can be used in conjunction with an error correction system that generates controllable input clock signals 602 and 604 to eliminate clock signal interval errors. The following will refer to... Figure 7 A more detailed explanation of the error correction system.

[0068] refer to Figure 7This illustration shows an error correction system 700 according to an exemplary embodiment. The error correction system 700 includes a quadrature divider 606, a phase detector 702, a low-pass filter 704, and a clock signal control unit 706. In some embodiments, the phase detector may refer to one or more logic gates that can be used to measure the difference between clock signals. In some embodiments, the difference may refer to the timing difference between different lower frequency output clock signals. In some embodiments, the low-pass filter 704 may refer to a filter that allows signals with frequencies below a certain threshold to pass through. In some embodiments, the control unit 706 may refer to computational circuitry configured to correct any clock signal interval errors observed within the error correction system. Clock signals “CK_P” and “CK_N” are used as inputs to the quadrature divider 606. As described above, the quadrature divider 606 produces divided output signals 616, 618, 620, and 622. As described above, in some embodiments, clock signal interval error may be observed in output clock signals 616, 618, 620, and 622 depending on whether there is a timing skew between the input clock signals "CK_P" and "CK_N". In some embodiments, clock signal interval error may refer to the timing of the output clock signals 616, 618, 620, and 622 being higher or lower than a certain time. In other embodiments, if the duty cycles of the input clock signals "CK_P" and "CK_N" are less than or greater than 50%, then clock signal interval error may be observed in output clock signals 616, 618, 620, and 622. The clock signal error may be corrected by error correction system 700.

[0069] Output clock signals 616, 618, 620, and 622 can be used as inputs to phase detector 702. Phase detector 702 may include two XOR (“Exclusive OR”) gates configured to receive output clock signals 616, 618, 620, and 622 and determine the difference between the rising edges of output clock signals 616, 618, 620, and 622. XOR gates may be defined as digital logic gates that provide a true output (e.g., high or 1) when the number of true inputs is odd. In some embodiments, XOR gates may act as inverters, which can be activated or deactivated by a switch. In some embodiments, phase detector 702 may include X-nor (“Exclusive OR”) gates instead of XOR gates. One of the XOR gates may be configured to measure the difference between output signal 616 and output signal 618, while the second XOR gate measures the difference between output signal 618 and 620. Furthermore, in some embodiments, the XOR gate of the phase detector 702 may be configured to also measure the difference between output signal 620 and output signal 622, and the difference between output signal 616 and output signal 622. For example, refer to Figure 8The following is a timing diagram 800 illustrating the clock signals associated with the phase detector 702 according to an exemplary embodiment. Specifically, timing diagram 800 shows the outputs of the two XOR gates of the phase detector 702. The outputs of the two XOR gates in the phase detector 702 are signals representing the difference between the rising edge of one clock and the rising edge of another clock. For example, signal 802 represents the difference between the rising edge of the first clock signal 616 and the rising edge of the second clock signal 618. As another example, signal 804 represents the difference between the rising edges of the second clock signal 618 and the third clock signal 620. Signals 802 and 804 indicate that the phase detector 702 did not detect a clock signal interval error because signals 802 and 804 each have 50% of their duty cycle. In contrast, Figure 9 The output signals of the XOR gates shown in the diagram are timing diagrams illustrating the detected clock signal interval error. Specifically, timing diagram 900 shows the outputs of the two XOR gates of phase detector 702. The outputs of the two XOR gates in phase detector 702 are signals representing the difference between the rising edge of one clock and the rising edge of another clock. For example, signal 902 represents the difference between the rising edge of the first clock signal 616 and the rising edge of the second clock signal 618. As another example, signal 904 represents the difference between the rising edges of the second clock signal 618 and the third clock signal 620. Signals 902 and 904 indicate that phase detector 702 has detected a clock signal interval error because signals 902 and 904 each have a duty cycle of less than or greater than 50%.

[0070] Return to reference Figure 7The output signal from the XOR gate is fed into a low-pass filter 704, which is configured to measure and amplify the clock signal interval error determined by the phase detector 702. Based on the measured and amplified clock signal interval error, the low-pass filter determines control signals “vctrl_p” and “vctrl_n”. The control signals may refer to electrical or communication signals that can be configured to control the operation of electronic circuit components or devices. In some embodiments, measuring the clock signal may refer to determining the amount of clock signal interval error present in the output signal. In some embodiments, amplifying the clock signal interval error may refer to a proportionally increased measurement of the clock signal interval error. The control signals can then be fed into a clock signal control unit 706. The clock signal control unit 706 is configured to receive the control signals and generate corrected higher-frequency input clock signals “CK_N” and “CK_P” to correct for any clock signal interval error. In some embodiments, the corrected higher-frequency input clock signals “CK_N” and “CK_P” may refer to higher-frequency input clock signals that have been modified to account for any clock signal interval error. Specifically, the clock signal control unit 706 may include one or more current-deficient inverters 708 and 710 for driving the calibrated input clock signals "CK_N" and "CK_P". The control voltage used to generate CK_N is opposite to the control voltage used to generate CK_P (another differential signal). Therefore, the control signal goes to the separate current-deficient inverter path, resulting in a controllable and clock signal interval-free duty cycle. Additional skew correction is possible by including a CMOS inverter (not shown) between CK_P and CK_N.

[0071] For reference Figures 10A to 10B This demonstrates control signals for controlling input clock signals "CK_N" and "CK_P" according to an exemplary embodiment, and the corresponding input clock signals generated by the control signals. Figure 10A In this configuration, the first control signal 1002 and the third control signal 1006 are control signals generated when the phase detector 702 does not detect a clock signal interval error. In this case, the rising and / or falling edges of control signals 1002 and 1006 do not need to be adjusted to account for and correct any clock signal interval error. Figure 10B As shown, when combined, voltage control signals 1002 and 1006 generate an input clock signal 1104 (e.g., "CK_N" or "CK_P") with a standard 50% duty cycle. Return to Reference Figure 10A The second clock signal 1004 and the fourth clock signal 1008 are control signals generated when the phase detector 702 detects a clock signal interval error. In this case, the rising edge and / or falling edge can be lengthened or shortened to adjust for any clock signal interval error. Figure 10BAs shown, when combined, voltage control signals 1004 and 1008 generate an input clock signal 1108 (e.g., “CK_N” or “CK_P”) with an adjusted duty cycle (e.g., above or below 50%).

[0072] D. Systems and methods for synchronizing multiple frequency dividers

[0073] In many analog-to-digital converters (ADCs), deserializer circuits (SERDES) in link communications, or even radio receivers (RF radios), information is processed using clock synchronization. When data rates increase to well above 20 Gb / s, it is generally preferable to process data using multiple sub-rate clocks. For example, in one embodiment, a data rate of 20 Gb / s can be captured using two 10 GHz clocks or four 5 GHz clocks, etc. When using such sub-rate clocks in a communication system with a specific data rate (e.g., 20 Gb / s), it is desirable that the multiple sub-rate clocks be spaced as evenly as possible in time, such that the timing reference is equal to the full data rate itself. For example, in the case of a 20 Gb / s system, the timing reference would be 20 GHz or a period of 50 ps. In this case, the data rate can be implemented by a sub-rate system with four 5 GHz clocks, where the rising edges (timing references) of the four clocks are ideally spaced exactly 50 ps apart. To ensure this, the sub-rate clocks can be synchronized when the frequency is divided to generate the sub-rate clocks. The systems and methods described herein provide techniques for providing this synchronization. In some embodiments, synchronization may refer to the process of ensuring that the timing of a sub-rate clock signal matches the timing of a higher frequency clock signal.

[0074] For reference Figure 11 The diagram illustrates multiple high-speed clocks 1201, 1203, and 1205 that undergo frequency division by one or more frequency dividers 1208a to 1208c to generate multiple sub-rate clocks 1202, 1204, and 1206. For example, high-speed clock CK1 can undergo frequency dividers (e.g., frequency divider 600, fractional divider 212, and fractional divider 214, etc.) to generate sub-rate clock 1202. "Sub-rate" means that the frequency of the sub-rate clock is less than the data rate itself and is generally an integer division. Figure 12 The diagram shows the timing diagrams associated with high-speed clocks 1201, 1203, and 1205 and sub-rate clocks 1202, 1204, and 1206. It is expected that each of the sub-rate clocks 1202, 1204, and 1206 can be synchronized by ensuring that the frequency dividers are synchronized. The frequency dividers can become asynchronous because they do not have a known initial state. For example, as... Figure 12As shown, both of the sub-rate clocks 1302b may have a low initial state that matches the initial state of the high-frequency clock 1302a. Therefore, sub-rate clocks 1302b are synchronized. In contrast, one of the sub-rate clocks 1304c does not have an initial state that matches the initial state of the other sub-rate clock 1304b or the high-frequency clock 1304a. Therefore, sub-rate clocks 1304 are not synchronized. The systems and methods described herein provide a way to synchronize clocks using only information provided by the sub-rate clocks without using an additional high-frequency clock. Specifically, a sub-rate clock is assigned as a “master” and each sub-rate clock is compared with the master sub-rate clock and individually synchronized with the master sub-rate clock that generates the master sub-rate clock signal. In some embodiments, the master sub-rate clock signal may refer to a clock signal associated with the master sub-rate clock. A follower sub-rate clock may be a sub-rate clock synchronized with the master sub-rate clock. In some embodiments, the follower sub-rate clock signal may refer to a clock signal associated with the follower sub-rate clock. Based on a comparison with the master-slave rate clock, a sliding divider can be applied to the clock divider of the follower-slave rate clock. The following will discuss... Figures 13A to 13C A more detailed explanation of the sliding divider is provided. For example, in one embodiment, the first sub-rate clock 1202 may be designated as the "master sub-rate clock." In this case, the relationship between the second sub-rate clock 1204 and the third sub-rate clock 1206 determines whether the clocks are synchronized. In some embodiments, the process of comparing other sub-rate clocks with the master sub-rate clock can be performed independently and simultaneously to save time. In some embodiments, making sub-rate clocks independently and simultaneously synchronized can refer to synchronizing multiple sub-rate clocks simultaneously without affecting each other. The following will discuss... Figures 14 to 17 A more detailed explanation of the process used to compare the sub-rate clock with the master sub-rate clock.

[0075] For reference Figure 13AThis diagram illustrates a circuit of a sliding divider 1300 according to an exemplary embodiment. In a typical divider, the rising edge of a high-frequency clock (e.g., “CK1”, “CK2”, and / or “CK3”) causes a sub-rate clock to switch from a high position to a low position or vice versa, making the position of the sub-rate clock directly related to the high-frequency clock. In contrast, the sliding divider 1300 includes an additional sliding signal, and the sub-rate clock switches based on both the sliding signal and the rising edge of the high-frequency clock. In some embodiments, the sliding signal may refer to a control signal that causes one or more of the sub-rate clocks to remain low for one or more time periods. Specifically, the sliding divider 1300 includes an XNOR gate 1310 that includes a sliding signal 1306. The output of the XNOR gate 1310 serves as the input to a flip-flop 1312 that generates a sub-rate clock 1202. When the slider signal 1306 is low, the XNOR gate 1301 behaves like an inverter and the sub-rate clock 1202 switches normally and is directly correlated with the rising edge of the high-frequency clock 1308 (e.g., as in a typical frequency divider). When the slider signal 1306 is high, the input of the flip-flop 1312 will be the same as the sub-rate clock 1202, and the sub-rate clock 1202 will not switch on the rising edge of the high-frequency clock 1308. In some embodiments, it may be desirable for the slider signal 1306 to be synchronized with the high-frequency clock 1308 such that the slider signal 1306 masks the desired number of rising edges of the high-frequency clock 1308. If it is determined that the sub-rate clock 1202 is out of sync based on a comparison with the master clock, then the slider signal 1306 can be activated to go high, which synchronizes the sub-rate clock 1202 with the master clock.

[0076] For reference Figures 13B to 13CWaveforms 1316 and 1318, according to an exemplary embodiment, show signals associated with a sliding divider 1300. Waveform 1316 shows the signals associated with the sliding divider 1300 when the sliding signal 1306 is low. Waveform 1318 shows the signals associated with the sliding divider 1300 when the sliding signal 1306 is high. As can be seen in waveform 1316, sub-rate clocks 1202 and 1204 are synchronized with high-frequency clocks 1201 and 1203. Because all clocks are synchronized, the div_good signal 1320 is set high in waveform 1316. The div_good signal 1320 can be described as a control signal that determines when the sliding should be activated based on a comparison between different sub-rate clocks and the master sub-rate clock. If the comparison shows that other sub-rate clocks are synchronized with the master sub-rate clock, then the div_good signal 1320 will be high and the sliding signal 1306 will be low. In contrast, if the comparison shows that other sub-rate clocks are not synchronized with the master sub-rate clock, then the div_good signal 1320 will be low and the slide signal 1306 will be activated low. Waveform diagram 1318 shows an exemplary embodiment where the sub-rate clocks are not synchronized and the slide signal 1306 is activated high. Figure 13C As shown, the div_good signal 1320 is low, indicating that the sub-rate clock 1204 is not synchronized with the sub-rate clock 1202. Once it is determined that the sub-rate clocks are not synchronized, the slide signal 1322 can be applied to the sub-rate clock 1204, causing the sub-rate clock 1204 not to switch with respect to a rising edge of the master clock.

[0077] For reference Figure 14 This illustrates a first circuit diagram 1400 of a frequency divider synchronizer according to an exemplary embodiment. The first circuit diagram 1400 is configured to determine whether one or more follower sub-rate clocks are synchronized with a master sub-rate clock. If the first circuit diagram 1400 determines that the sub-rate clocks are not synchronized, then the first circuit diagram 1400 may be configured to generate a sliding signal, which is configured to synchronize the follower sub-rate clocks with the master sub-rate clock. The first circuit diagram 1400 determines whether one or more follower sub-rate clocks are synchronized based on a div_good signal 1405. Specifically, in some embodiments, the first circuit diagram 1400 includes a buffer delay gate 1402 and may refer to circuit elements configured to provide a delay between the timing of the master sub-rate clock (e.g., sub-rate clock 1202) and one or more follower sub-rate clocks (e.g., sub-rate clock 1204) as needed. For example, as... Figure 13BAs shown, high-frequency clock 1203 lags behind high-frequency clock 1201 for a certain period of time. Therefore, for the sub-rate clocks to be properly synchronized, sub-rate clock 1204 should lag behind sub-rate clock 1202 by the same period of time. In this case, buffer delay gate 1402 will ensure the proper lag between the sub-rate clocks. In some embodiments, if the high-frequency clocks lag behind each other, then the first circuit diagram 1400 may not include buffer delay gate 1402.

[0078] The delayed clock signal used for the follower sub-rate clock (e.g., clock "ckp2" 1204) is used as an input to the timing flip-flop 1404. Flip-flop 1404 also contains an input to the master sub-rate clock, which in this case is ckp1 (e.g., sub-rate clock 1202). Flip-flop 1404 samples the master sub-rate clock ckp1 using the follower sub-rate clock ckp2 (e.g., sub-rate clock 1204). If the second sub-rate clock 1204 is correctly behind the first sub-rate clock 1202, then the sampling by flip-flop 1404 causes the output of the div_good signal 1405 to go high, indicating that the sub-rate clocks are synchronized. If the sub-rate clocks are not synchronized, then the rising edge of the follower sub-rate clock will align with the master sub-rate clock going low, and flip-flop 1404 will cause the div_good signal 1405 to go low, indicating that the clocks are not synchronized. In this way, flip-flop 1404 outputs a logical indication of whether the sub-rate clocks are synchronized.

[0079] The div_good signal 1405 is then used as an input to a NOR gate 1406, which is configured to invert the div_good signal 1405. For example, if the div_good signal 1405 is low, then it is inverted to high by the NOR gate 1406. Conversely, if the div_good signal 1405 is high, then it is inverted to low by the NOR gate. The output of the NOR gate 1406 is fed into a flip-flop 1408. In some embodiments, the flip-flop 1408 is timed by a high-frequency clock 1203. This is done to ensure that the slip signal is enabled only for the desired number of time periods of the high-frequency clock 1203. If the div_good signal 1405 is low to indicate that the sub-rate clock is not synchronized, then the signal is inverted to produce a high signal. This high signal is fed into the flip-flop 1408 to synchronize it with the high-frequency clock 1203 and produce a high to_slip signal 1409. The to_slip signal 1409 can then be used as an input to an AND gate 1414. Furthermore, the high signal generated by flip-flop 1408 is fed into flip-flop 1410, which is also timed by a high-frequency clock to generate a low signal. The low signal serves as the input to inverter 1412, which generates a high signal that serves as the second input to AND gate 1414. Given the high signal as an input to AND gate 1414, AND gate 1414 generates a pos_det signal 1415 that is fed into flip-flop 1416. Flip-flop 1416 is configured to time the pos_det signal 1415 to generate a high-level sliding signal 1417. The sliding signal 1417 can then be transmitted to a control unit associated with the frequency divider, which is configured to use the sliding signal 1417 to make the above relative to... Figures 13A to 13C The described follower sub-rate clock synchronization. If the div_good signal 1405 is high, then the sliding signal 1417 will be generated low according to the logic described above.

[0080] For reference Figure 15The diagram illustrates a second circuit diagram 1500, which demonstrates an exemplary embodiment of a frequency divider synchronizer according to an exemplary embodiment. Similar to the first circuit diagram 1400, the second circuit diagram 1500 is configured to determine whether one or more follower sub-rate clocks are synchronized with a master sub-rate clock. If the second circuit diagram 1500 determines that the sub-rate clocks are not synchronized, then the second circuit diagram 1500 may be configured to generate a sliding signal configured to synchronize the follower sub-rate clocks with the master sub-rate clock. The second circuit diagram 1500 determines whether one or more follower sub-rate clocks are synchronized based on a div_good signal 1505. The second circuit diagram 1500 includes many of the same elements described above with respect to the first circuit diagram 1400. For example, the second circuit diagram 1500 includes a buffer delay gate 1502 similar to a buffer delay gate 1402. The second circuit diagram 1500 also includes a flip-flop 1504, which is configured, similar to flip-flop 1404, to generate the div_good signal 1505. Furthermore, the second circuit diagram 1500 includes a NOR gate 1506 having an input div_good signal 1505 and a refresh signal 1507, which is similar to a NOR gate 1406 having an input div_good signal 1405 and a refresh signal 1407. The second circuit diagram 1500 also includes flip-flops 1508 and 1510 similar to the flip-flops 1408 and 1410 described above. Flip-flop 1508 generates a to_slip signal 1509, similar to how flip-flop 1408 generates the to_slip signal 1409 as described above. The second circuit diagram 1500 includes an inverter 1512 and an AND gate 1514 generating a pos_det signal 1515, the inverter 1512, AND gate 1514, and pos_det signal 1515 being similar to inverter 1412, AND gate 1414, and pos_det signal 1415, respectively. Similar to the pos_det signal 1415, the pos_det signal 1515 is fed into one or more flip-flops to generate a sliding signal. The second circuit diagram 1500 differs from the first circuit diagram 1400 in that it contains more flip-flops than the first circuit diagram 1400. The number of flip-flops used to generate the sliding signal directly corresponds to the amount of time the sliding signal is active during its duration. For example, the first circuit diagram 1400 contains only one flip-flop 1416 to generate the sliding signal 1417, meaning the sliding signal is active only during one period of clock 1203. In contrast, the second circuit diagram 1500 contains two flip-flops 1516 and 1518, which are fed into an OR gate 1520 to generate the sliding signal 1517, which is active during two periods of clock signal 1203.

[0081] In another exemplary embodiment, the circuit diagram may further include a multiplexer configured to provide an alternative method for determining the number of periods of operation of the sliding signal. For example, now referenced Figure 16 The diagram illustrates a third circuit diagram 1600, which is very similar to circuit diagram 1500 but includes a multiplexer 1620. Multiplexer 1620 serves as the input to OR gate 1622 to generate a slip signal 1617. Specifically, if the slip_2 signal 1624 is high, circuit diagram 1600 will generate a high slip signal for two time periods of clock signal 1203. However, if the slip_2 signal 1624 is low, circuit diagram 1600 will generate a high slip signal for only one time period of clock signal 1203.

[0082] In another exemplary embodiment, Figure 15 The circuit diagram shown can be extended to include more than two flip-flops to generate a sliding signal that lasts for more than two time periods of clock signal 1203. For example, now refer to Figure 17 The fourth circuit diagram 1700, according to an exemplary embodiment, is shown. The fourth circuit diagram 1700 includes most of the same components as the circuit 1500 described in more detail above. Furthermore, circuit diagram 1700 includes flip-flops 1716, 1718, 1720, and 1722, configured to generate a sliding signal that persists for more than two time periods of the clock signal 1203. Specifically, it includes... Figure 17 The four trigger signals in the code correspond to the sliding signals that are in operation for four clock periods within the clock signal 1203. Increasing the value of the triggers will result in a similar increase in the value of the sliding signals during the clock periods in operation.

[0083] It should be noted that certain paragraphs of this disclosure may be combined with device signals, data, inputs, channels, etc., and reference terms such as "first" and "second" to identify or distinguish them from each other. These terms are not intended to relate entities only temporarily or sequentially (e.g., first input and second input), but in some cases, these entities may contain this relationship. These terms also do not limit the number of possible entities (e.g., devices) that can operate in the system or environment.

[0084] It should be understood that the above-described system may provide any or multiple of these components. Furthermore, the above-described system and method may provide one or more computer-readable programs or executable instructions, programmable circuits, or digital logic embodied on or in one or more articles of manufacture. The articles of manufacture may be floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, ASICs, or magnetic tapes. Generally, the computer-readable program may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#, PROLOG) or any bytecode language (e.g., JAVA). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0085] While the foregoing description of the methods and systems enables those skilled in the art to make and use various embodiments of the methods and systems, those skilled in the art should understand and appreciate variations, combinations, and equivalents of the specific embodiments, methods, and examples present herein. Therefore, the methods and systems should not be limited to the foregoing embodiments, methods, and examples, but rather to all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. A circuit comprising: A frequency divider is configured to receive a plurality of first frequency input clock signals and provide a plurality of second frequency output clock signals, wherein the frequencies of the plurality of second frequency output clock signals are lower than the plurality of first frequency input clock signals. A phase detector configured to determine the difference between the plurality of second frequency output clock signals; A low-pass filter configured to measure a clock signal interval error associated with the plurality of second frequency output clock signals based on the difference between the plurality of second frequency output clock signals and to generate one or more control signals in response to the clock signal interval error; and A control unit configured to generate one or more calibrated first frequency input clock signals based on the one or more control signals, wherein the frequency divider is an orthogonal frequency divider.

2. The circuit according to claim 1, wherein the quadrature frequency divider comprises: A trigger configured to generate a single second frequency output clock signal among the plurality of second frequency output clock signals, the single second frequency output clock signal having half the frequency of a first frequency input clock signal among the plurality of first frequency input clock signals; and one or more latches configured to generate four second frequency output clock signals among the plurality of second frequency output clock signals.

3. The circuit of claim 1, wherein the phase detector comprises one or more logic gates configured to receive the plurality of second frequency output clock signals, wherein the plurality of second frequency output clock signals include at least a first signal and a second signal among the plurality of second frequency output clock signals, and wherein the phase detector compares the first signal and the second signal to detect a clock signal interval error.

4. The circuit according to claim 3, wherein the one or more logic gates are XOR gates.

5. The circuit of claim 1, wherein the low-pass filter is configured to amplify the clock signal interval error and to determine the one or more control signals based on the amplified clock signal interval error.

6. The circuit according to claim 1, wherein the clock signal interval error is a condition in which the rising edge timing of the plurality of second frequency output clock signals is not equal among each of the plurality of second frequency output clock signals.

7. A method comprising: Receives multiple first-frequency input clock signals; A plurality of second frequency output clock signals are provided, wherein the frequencies of the plurality of second frequency output clock signals are lower than the plurality of first frequency input clock signals, and wherein the generation of the plurality of second frequency output clock signals is performed by an orthogonal frequency divider; Determine the difference between the plurality of second frequency output clock signals to determine whether there is a clock signal interval error; Measure the clock signal interval error; One or more control signals are determined based on the clock signal interval error; and A corrected first frequency input clock signal is generated based on one or more control signals.

8. The method of claim 7, further comprising: Receive the plurality of second frequency output clock signals, wherein the plurality of second frequency output clock signals include at least a first signal and a second signal among the plurality of second frequency output clock signals; and The first signal is compared with the second signal to detect the clock signal interval error.

9. The method of claim 7, further comprising: Amplify the clock signal interval error; and The one or more control signals are determined based on the interval error of the amplified clock signal.

10. The method of claim 7, wherein the clock signal interval error is a condition in which the rising time of one of the plurality of second frequency output clock signals is not equal to the rising time of another of the plurality of second frequency output clock signals.

11. The method of claim 7, wherein the quadrature frequency divider comprises: A trigger configured to generate a second frequency output clock signal among the plurality of second frequency output clock signals, the second frequency output clock signal having half the frequency of the plurality of first frequency input clock signals; and one or more latches configured to generate four second frequency output clock signals among the plurality of second frequency output clock signals.

12. The method of claim 10, wherein the clock signal interval error is a condition in which the timing of the rising edges of the plurality of second frequency output clock signals is not equal among each of the plurality of second frequency output clock signals.

13. A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to: Receives multiple first-frequency input clock signals; A plurality of second frequency output clock signals are provided, wherein the frequencies of the plurality of second frequency output clock signals are lower than the plurality of first frequency input clock signals, and wherein the generation of the plurality of second frequency output clock signals is performed by an orthogonal frequency divider; Determine the difference between the plurality of second frequency output clock signals to determine whether there is a clock signal interval error; Measure the clock signal interval error; One or more control signals are determined based on the clock signal interval error; and One or more calibrated first frequency input clock signals are generated based on the one or more control signals.

14. The non-transitory computer-readable medium of claim 13, further causing the one or more processors to: Receive the plurality of second frequency output clock signals, wherein the plurality of second frequency output clock signals include at least a first signal and a second signal among the plurality of second frequency output clock signals; and The first signal is compared with the second signal to detect the clock signal interval error.

15. The non-transitory computer-readable medium of claim 13, further causing the one or more processors to: Amplify the clock signal interval error; and The one or more control signals are determined based on the interval error of the amplified clock signal.

16. The non-transitory computer-readable medium of claim 13, wherein the clock signal interval error is a condition in which the timing of the rising edge of one of the plurality of second frequency output clock signals is not equal to the timing of the rising edge of another of the plurality of second frequency output clock signals.

17. The non-transitory computer-readable medium of claim 13, wherein the quadrature frequency divider comprises: A trigger configured to generate a second frequency output clock signal among the plurality of second frequency output clock signals, the second frequency output clock signal having half the frequency of a first frequency input clock signal among the plurality of first frequency input clock signals; and one or more latches configured to generate four second frequency output clock signals among the plurality of second frequency output clock signals.

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