A segmented convergent crystal oscillator calibration method, device and system

Abstract

The present invention relates to the field of digital communications and discloses a segmented convergent crystal oscillator calibration system and method. The system includes a field programmable logic gate array (FPGA), a digital-to-analog converter (DAC), and a crystal oscillator. The FPGA uses the number of pulses per second or a reference frequency of 10 MHz as a reference benchmark and converts the sampling frequency from the commonly used megahertz to hertz. Hertz represents the number of periodic transformations completed per unit time and is converted into the number of cycles. An error cycle number is obtained by subtracting the actual number of cycles from the standard number of cycles. The digital grading of the error cycle number can determine the error cycle number step length table to be called. The step length corresponding to the error cycle number is determined by the error cycle number step length table. A control word is obtained and added to the corresponding step length to obtain a new control word, which is then transmitted to the DAC. The DAC generates a corresponding voltage based on the new control word and sends it to the crystal oscillator. The crystal oscillator generates a new feedback crystal oscillator clock based on the new voltage and feeds it back to the FPGA.

Description

Technical Field

[0001] The present invention relates to the field of digital communications, and in particular to a segmented convergent crystal oscillator calibration method, device and system. Background Art

[0002] In modern electronic systems, crystal oscillators are key components for providing stable clock signals. Their frequency accuracy and stability are crucial to system performance. With the continuous advancement of electronic technology, the demand for clock signal accuracy is becoming increasingly stringent, and traditional crystal oscillator calibration methods are increasingly unable to meet these demands.

[0003] Traditional crystal oscillator calibration methods generally use a fixed voltage difference for calibration. This method may cause continuous oscillation during the calibration process, and it takes a long time for the time system to stabilize.

[0004] Therefore, under this background, it is particularly urgent to develop an innovative segmented convergent crystal oscillator calibration system and method. Summary of the Invention

[0005] The object of the present invention is to provide a segmented convergent crystal oscillator calibration system and method, which can avoid continuous oscillation during the correction process and shorten the time it takes for the system to reach stability.

[0006] A segmented convergent crystal oscillator calibration method comprises the following steps:

[0007] S1. Outputs a control word for a digital-to-analog converter to generate a voltage to control a crystal oscillator to generate a feedback crystal clock;

[0008] S2 obtains the reference reference of the number of pulses per second or the frequency of 10MHz, determines whether the reference reference is valid, and if valid, samples the feedback crystal oscillator clock generated by the crystal oscillator when the first rising edge of the reference reference every N seconds arrives;

[0009] S3. Calculate the number of cycles corresponding to 1 second based on the frequency of the feedback crystal oscillator clock, multiply the number of cycles for 1 second by N to obtain the actual number of cycles for N seconds; calculate the number of cycles corresponding to 1 second based on the frequency of 100 MHz, multiply the number of cycles for 1 second by N to obtain the standard number of cycles for N seconds, and then calculate the error number of cycles, error number of cycles = actual number of cycles - standard number of cycles;

[0010] S4. When the error cycle number is less than or equal to the threshold, the lock control word turns to S1 and ends; when the error cycle number is greater than the threshold, it turns to S5;

[0011] S5. Based on the digital level of the error cycle number, a mapping table for error cycle step sizes corresponding to different digital levels is called. The error cycle step size mapping table contains information about error cycle value intervals and correction step sizes. The structure of the error cycle step size mapping table is a series of consecutive and non-overlapping error cycle value intervals. The error cycle value intervals are represented by starting and ending points, with the interval with the largest starting point and the largest ending point being ranked first, and the error cycle value intervals with gradually decreasing starting and ending points being ranked downwards. Each error cycle value interval corresponds to a correction step size, and the correction step sizes are arranged downwards in descending order following the corresponding interval;

[0012] S6. If an error cycle number is greater than the starting point of an error cycle value interval and less than or equal to the end point of the error cycle value interval, then the error cycle value interval is a matching interval;

[0013] S7. Retrieve the corrected step length corresponding to the matching interval as the target step length, sum the control word and the target step length to obtain a new control word, update the control word to the new control word, and then go to S1.

[0014] Furthermore, the error cycle step length mapping table includes ten thousand levels and individual levels according to the digit classification of the error cycle number.

[0015] Furthermore, the individual-level error cycle step mapping table includes at least a first error cycle value interval, a second error cycle value interval, and a third error cycle value interval. The first error cycle value interval is a thousands-digit interval and its corresponding correction step is a hundreds-digit interval. The second error cycle value interval is a hundreds-digit interval and its corresponding correction step is a tens-digit interval. The third error value interval is a tens-digit interval and its corresponding correction step is a units-digit interval. The above intervals can be further refined according to specific circumstances.

[0016] Furthermore, the ten thousand level error cycle step mapping table includes at least a first error cycle value interval, a second error cycle value interval, a third error cycle value interval, and a fourth error cycle value interval. The first error cycle value interval is a tens of millions digit interval and its corresponding correction step is a million digit. The second error cycle value interval is a millions digit interval and its corresponding correction step is a hundred thousand digit. The third error value interval is a hundred thousand digit interval and its corresponding correction step is a ten thousand digit. The fourth error value interval is a tens of thousands digit interval and its corresponding correction step is a thousand digit. The above intervals can be further refined according to specific circumstances.

[0017] Furthermore, the step size is modified to satisfy the rapid descent fitting curve.

[0018] Furthermore, the threshold represents the minimum starting point of the interval in which the number of error cycles is less than or equal to the error cycle step length mapping table.

[0019] A segmented convergent crystal oscillator calibration device is characterized in that the device is a field programmable logic gate array: the field programmable logic gate array can execute a segmented convergent crystal oscillator calibration method.

[0020] A segmented convergent crystal oscillator calibration system includes a field programmable logic gate array, a digital-to-analog converter, and a crystal oscillator.

[0021] The field programmable logic gate array is capable of executing a piecewise convergent crystal oscillator calibration method;

[0022] The digital-to-analog converter can generate a voltage in response to a control word;

[0023] The crystal oscillator can generate a feedback crystal clock in response to voltage.

[0024] The present invention has the beneficial effects:

[0025] 1. Selecting different control word step sizes for the error period segment can avoid overcorrection and continuous oscillation during the correction process, thereby improving the modification accuracy; compared with the fixed pressure difference correction method used in the existing technology, this method reduces the time it takes for the system to stabilize.

[0026] 2. By sampling every N seconds to meet the minimum response time slice of the crystal oscillator after accepting the new voltage control, the response is fastest, and stable fast sampling is possible, thereby improving the responsiveness of the correction system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the system structure of the present invention.

[0028] Figure 2 Schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below with reference to the embodiments and drawings, but the implementation manner of the present invention is not limited to these embodiments.

[0030] Example 1

[0031] See also Figures 1 to 2 As shown,

[0032] A segmented convergent crystal oscillator calibration method comprises the following steps:

[0033] S1. Outputs a control word for a digital-to-analog converter to generate a voltage to control a crystal oscillator to generate a feedback crystal clock;

[0034] S2 obtains the reference reference of the number of pulses per second or the frequency of 10MHz, determines whether the reference reference is valid, and if valid, samples the feedback crystal oscillator clock generated by the crystal oscillator when the first rising edge of the reference reference every N seconds arrives;

[0035] S3. Calculate the number of cycles corresponding to 1 second based on the frequency of the feedback crystal oscillator clock, multiply the number of cycles for 1 second by N to obtain the actual number of cycles for N seconds; calculate the number of cycles corresponding to 1 second based on the frequency of 100 MHz, multiply the number of cycles for 1 second by N to obtain the standard number of cycles for N seconds, and then calculate the error number of cycles, error number of cycles = actual number of cycles - standard number of cycles;

[0036] S4. When the error cycle number is less than or equal to the threshold, the lock control word turns to S1 and ends; when the error cycle number is greater than the threshold, it turns to S5;

[0037] S5. Based on the digital level of the error cycle number, a mapping table for error cycle step sizes corresponding to different digital levels is called. The error cycle step size mapping table contains information about error cycle value intervals and correction step sizes. The structure of the error cycle step size mapping table is a series of consecutive and non-overlapping error cycle value intervals. The error cycle value intervals are represented by starting and ending points, with the interval with the largest starting point and the largest ending point being ranked first, and the error cycle value intervals with gradually decreasing starting and ending points being ranked downwards. Each error cycle value interval corresponds to a correction step size, and the correction step sizes are arranged downwards in descending order following the corresponding interval;

[0038] S6. If an error cycle number is greater than the starting point of an error cycle value interval and less than or equal to the end point of the error cycle value interval, then the error cycle value interval is a matching interval;

[0039] S7. Retrieve the corrected step length corresponding to the matching interval as the target step length, sum the control word and the target step length to obtain a new control word, update the control word to the new control word, and then go to S1.

[0040] Traditional crystal oscillator calibration is generally performed using a fixed voltage difference technique, which can be understood as setting a fixed step size.

[0041] The present invention generates a control word by generating a voltage through a digital-to-analog converter to act on a crystal oscillator to generate a new feedback crystal oscillator clock, a field programmable logic gate array receives the feedback crystal oscillator clock and performs sampling, calculates the actual number of sampled cycles and the standard number of cycles, and subtracts the standard number of cycles from the actual number of sampled cycles to obtain the error number of cycles, compares the error number of cycles with a threshold, locks the control word and ends the correction if the error number of cycles is less than the threshold, matches an error period step length mapping table if the error number of cycles is greater than the threshold, finds a corresponding step length through the matched error period step length mapping table, sums the corresponding step length with the generated control word to obtain a new control word, and updates the control word to the new control word.

[0042] Compared with traditional crystal oscillator correction, the present invention converts the frequency into the number of cycles, amplifies the processed data, and has different error cycle value intervals in the error cycle step length mapping table, corresponding to different correction step lengths. The correction step length values ​​are arranged from large to small to meet the fast-drop fitting curve, allowing the system to operate stably in a short time and reducing system debugging time. The number of cycles and the correction step length are matched through the error cycle step length mapping table, and the correction step length is summed with the control word to obtain a new control word.

[0043] Furthermore, the error cycle step length mapping table includes ten thousand levels and individual levels according to the digit classification of the error cycle number.

[0044] Digital grading refers to every four counting units as a level: units, tens, hundreds, and thousands are called units level; ten thousand, one hundred thousand, one million, and ten million are called ten thousand level; one hundred million, one billion, ten billion, and one hundred billion are called one hundred million level, etc.

[0045] Furthermore, the individual-level error cycle step mapping table includes at least a first error cycle value interval, a second error cycle value interval, and a third error cycle value interval. The first error cycle value interval is a thousands-digit interval and its corresponding correction step is a hundreds-digit interval. The second error cycle value interval is a hundreds-digit interval and its corresponding correction step is a tens-digit interval. The third error value interval is a tens-digit interval and its corresponding correction step is a units-digit interval. The above intervals can be further refined according to specific circumstances.

[0046] Furthermore, the ten thousand level error cycle step mapping table includes at least a first error cycle value interval, a second error cycle value interval, a third error cycle value interval, and a fourth error cycle value interval. The first error cycle value interval is a tens of millions digit interval and its corresponding correction step is a million digit. The second error cycle value interval is a millions digit interval and its corresponding correction step is a hundred thousand digit. The third error value interval is a hundred thousand digit interval and its corresponding correction step is a ten thousand digit. The fourth error value interval is a tens of thousands digit interval and its corresponding correction step is a thousand digit. The above intervals can be further refined according to specific circumstances.

[0047] Furthermore, the step size is modified to satisfy the rapid descent fitting curve.

[0048] Furthermore, the threshold represents the minimum starting point of the interval in which the number of error cycles is less than or equal to the error cycle step length mapping table.

[0049] A segmented convergent crystal oscillator calibration device is characterized in that the device is a field programmable logic gate array: the field programmable logic gate array can execute a segmented convergent crystal oscillator calibration method.

[0050] A segmented convergent crystal oscillator calibration system includes a field programmable logic gate array, a digital-to-analog converter, and a crystal oscillator.

[0051] The field programmable logic gate array is capable of executing a piecewise convergent crystal oscillator calibration method;

[0052] The digital-to-analog converter can generate a voltage in response to a control word;

[0053] The crystal oscillator can generate a feedback crystal clock in response to voltage.

[0054] Example 2,

[0055] The control word generated in the field programmable logic gate array is 32767, the digital-to-analog converter generates a voltage according to the generated control word 32767, and the crystal oscillator generates a new feedback crystal oscillator clock according to the voltage.

[0056] The field programmable logic gate array receives the feedback crystal oscillator clock and the reference reference. If the reference reference is valid, the feedback crystal oscillator clock generated by the crystal oscillator is sampled every 5 seconds at the first rising edge of the reference reference. The sampling frequency is 100.001 MHz, where 100 MHz is the target frequency and 0.001 MHz is the frequency deviation to be corrected. The sampling frequency is converted to 100001000 Hz in Hertz, which means that there are 100001000 cycles in 1 second. Therefore, the number of cycles of the 5-second sampling of the feedback crystal oscillator clock is 500005000. Based on the same principle, the number of cycles of the standard 100 MHz in 5 seconds is 500000000. Therefore, the number of error cycles = 500005000 - 5000000000 = 5000.

[0057] Then, according to the obtained digital level of the error cycle number, find the error cycle step length mapping table of the corresponding digital level to see which error cycle value interval the error cycle number falls into. For example, in this embodiment, the error cycle number is individual level, so the individual level error cycle step length mapping table called is as follows:

[0058] 2000<error cycles<=9999, correction step size 800;

[0059] 1000<error cycles<=2000, correction step size 600;

[0060] 600<error cycles<=1000, correction step size 300;

[0061] 200<error cycles<=600, correction step size 50;

[0062] 10<error cycles<=200, correction step size 3;

[0063] The error cycle number is 5000. By determining whether the error cycle number falls within the error cycle value range of 2000 < error cycle number <= 9999, the correction step size used for this error cycle value range is 800, and the generated control word is 32767. Therefore, the new control word is 32767 + 800 = 33567. The control word is updated to the new control word 33567. The digital-to-analog converter generates a voltage based on the new control word, and the crystal oscillator generates a new feedback crystal oscillator clock based on the voltage and feeds it back to the field programmable logic gate array. Calibration is completed until the error cycle number is less than or equal to 10, the control word value is locked, and the crystal oscillator continues to output the feedback crystal oscillator clock.

[0064] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Persons skilled in the art will readily appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are considered within the scope of protection of the present invention.

Claims

1. A segmented convergent crystal oscillator calibration method, characterized in that: The following steps are involved: S1. Outputs a control word for a digital-to-analog converter to generate a voltage to control a crystal oscillator to generate a feedback crystal clock; S2 obtains the reference reference of the number of pulses per second or the frequency of 10MHz, determines whether the reference reference is valid, and if valid, samples the feedback crystal oscillator clock generated by the crystal oscillator when the first rising edge of the reference reference every N seconds arrives; S3. Calculate the number of cycles corresponding to 1 second based on the frequency of the feedback crystal oscillator clock, multiply the number of cycles for 1 second by N to obtain the actual number of cycles for N seconds; calculate the number of cycles corresponding to 1 second based on the frequency of 100 MHz, multiply the number of cycles for 1 second by N to obtain the standard number of cycles for N seconds, and then calculate the error number of cycles, error number of cycles = actual number of cycles - standard number of cycles; S4. When the error cycle number is less than or equal to the threshold, the lock control word switches to S1 and ends; When the error cycle number is greater than the threshold, go to S5; S5. Based on the digital level of the error cycle number, call the error cycle step length mapping table of different digital levels. The error cycle step length mapping table contains error cycle value interval information and correction step length information. The structure of the error cycle step length mapping table is a plurality of continuous and non-overlapping error cycle value intervals. The error cycle value intervals are represented in the form of starting points and ending points. The interval with the largest starting point and the largest ending point is ranked first, and the error cycle value intervals with gradually decreasing starting points and ending points are arranged downwards. Each error cycle value interval corresponds to a correction step length, and the correction step lengths are arranged downwards in descending order following the corresponding interval; S6. If an error cycle number is greater than the starting point of an error cycle value interval and less than or equal to the end point of the error cycle value interval, then the error cycle value interval is a matching interval; S7. Retrieve the corrected step length corresponding to the matching interval as the target step length, sum the control word and the target step length to obtain a new control word, update the control word to the new control word, and then go to S1.

2. The segmented convergent crystal oscillator calibration method according to claim 1, wherein: The error cycle step length mapping table includes ten thousand levels and individual levels according to the digit classification of the error cycle number.

3. The segmented convergent crystal oscillator calibration method according to claim 2, wherein: The individual-level error cycle step mapping table includes at least a first error cycle value interval, a second error cycle value interval, and a third error cycle value interval. The first error cycle value interval is a thousands-digit interval and its corresponding correction step is a hundreds-digit interval. The second error cycle value interval is a hundreds-digit interval and its corresponding correction step is a tens-digit interval. The third error value interval is a tens-digit interval and its corresponding correction step is a units-digit interval.

4. The segmented convergent crystal oscillator calibration method according to claim 2, wherein: The ten thousand level error cycle step mapping table includes at least a first error cycle value interval, a second error cycle value interval, a third error cycle value interval, and a fourth error cycle value interval. The first error cycle value interval is a ten-million digit interval and its corresponding correction step is a million-digit interval. The second error cycle value interval is a million-digit interval and its corresponding correction step is a hundred-thousand-digit interval. The third error value interval is a hundred-thousand-digit interval and its corresponding correction step is a ten-thousand-digit interval. The fourth error value interval is a ten-thousand-digit interval and its corresponding correction step is a thousand-digit interval.

5. The segmented convergent crystal oscillator calibration method according to claim 3, wherein: The modified step size satisfies the rapid descent fitting curve.

6. The segmented convergent crystal oscillator calibration method according to claim 1, wherein: The threshold represents the minimum starting point of the interval where the number of error cycles is less than or equal to the error cycle step length mapping table.

7. A segmented convergent crystal oscillator calibration device, characterized in that: The device is a field programmable logic gate array: the field programmable logic gate array can execute a segmented convergent crystal oscillator calibration method according to any one of claims 1 to 6.

8. A segmented convergent crystal oscillator calibration system comprising a field programmable logic gate array, a digital-to-analog converter, and a crystal oscillator, characterized in that: The field programmable logic gate array is capable of executing a segmented convergent crystal oscillator calibration method according to any one of claims 1 to 6; The digital-to-analog converter can generate a voltage in response to a control word; The crystal oscillator can generate a feedback crystal clock in response to voltage.

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