Semiconductor structure and its preparation method

Abstract

A semiconductor structure fabrication method includes: forming an initial structure comprising multiple main semiconductor pillars, each main semiconductor pillar including a first sub-semiconductor pillar and a second sub-semiconductor pillar; a first isolation layer is disposed between two adjacent main semiconductor pillars; a second isolation layer is disposed between the first and second sub-semiconductor pillars; a first sacrificial pattern is disposed on the first and second sub-semiconductor pillars, and the first sacrificial pattern is located between the first and second isolation layers; etching the first sacrificial pattern to expose the first and second sub-semiconductor pillars, wherein the etching rate of the etching material on the first sacrificial pattern is greater than the etching rate on the first and second isolation layers; forming a conductive contact layer; patterning the conductive contact layer to form multiple conductive contact structures, wherein the conductive contact structures are in contact with the first or second sub-semiconductor pillars; and filling the gaps between the conductive contact structures with an isolation material to form a third isolation layer.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit manufacturing, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of volatile memory. It consists of multiple memory cells. Each memory cell mainly includes a transistor and a capacitor. The source of the transistor is connected to the capacitor through a node contact (NC) structure and a landing pad (LP). The memory cells are electrically connected to each other through word lines (WL) and bit lines (BL).

[0003] To improve DRAM integration density, a 4F2 architecture (where "F" represents the minimum feature size) has been proposed, utilizing a vertical gate-all-around (GAA) transistor structure as the DRAM access transistor. This DRAM involves forming vertically extending active pillars on a substrate, with a gate-all-around structure formed outside the active pillars, along with buried bit lines and buried word lines. In principle, this can achieve higher density efficiency. However, in existing 4F2 memory architectures, the contact area of ​​the memory node is relatively small, leading to problems such as difficult alignment and low alignment accuracy when forming capacitors.

[0004] Therefore, there is an urgent need for a new semiconductor structure and its fabrication method to overcome the above problems. Summary of the Invention

[0005] The technical problem to be solved by the embodiments of this disclosure is to provide a semiconductor structure and a method for preparing the same, which can reduce the difficulty of the process.

[0006] To address the aforementioned problems, this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0007] An initial structure is formed on a substrate, the initial structure including a plurality of main semiconductor pillars arranged in an array along a first direction and a second direction, and the main semiconductor pillars extending along a third direction. Each main semiconductor pillar includes a first sub-semiconductor pillar and a second sub-semiconductor pillar spaced apart along the first direction. A first isolation layer is disposed between two adjacent main semiconductor pillars in the first direction, and a second isolation layer is disposed between the first sub-semiconductor pillar and the second sub-semiconductor pillar. Both the first isolation layer and the second isolation layer extend along the second direction. In the third direction, both the first isolation layer and the second isolation layer protrude beyond the first sub-semiconductor pillar and the second sub-semiconductor pillar. A first sacrificial pattern is disposed on the first sub-semiconductor pillar and the second sub-semiconductor pillar in the third direction, and the first sacrificial pattern is located between the first isolation layer and the second isolation layer in the first direction.

[0008] The first sacrificial pattern is etched to expose the first sub-semiconductor pillar and the second sub-semiconductor pillar, wherein the etching rate of the etching material on the first sacrificial pattern is greater than the etching rate on the first isolation layer and the second isolation layer.

[0009] A conductive contact layer is formed, which fills the space between the first isolation layer and the second isolation layer and covers the first sub-semiconductor pillar and the second sub-semiconductor pillar, and the conductive contact layer extends along the second direction;

[0010] The conductive contact layer is patterned to form a plurality of independent conductive contact structures, which are in contact with the first sub-semiconductor pillar or the second sub-semiconductor pillar.

[0011] An insulating material is filled into the gaps between the conductive contact structures to form a third insulating layer.

[0012] This disclosure also provides a semiconductor structure, including:

[0013] Substrate;

[0014] A plurality of main semiconductor pillars are arranged in an array along a first direction and a second direction on the substrate, and the main semiconductor pillars extend along a third direction. Each main semiconductor pillar includes a first sub-semiconductor pillar and a second sub-semiconductor pillar that are spaced apart along the first direction.

[0015] A first isolation layer is disposed between two adjacent main semiconductor pillars in the first direction, and the first isolation layer extends along the second direction, and in the third direction, the first isolation layer protrudes beyond the first sub-semiconductor pillar and the second sub-semiconductor pillar;

[0016] A second isolation layer is disposed between the first sub-semiconductor pillar and the second sub-semiconductor pillar, and the second isolation layer extends along the second direction, and in the third direction, the second isolation layer protrudes beyond the first sub-semiconductor pillar and the second sub-semiconductor pillar;

[0017] Multiple independent conductive contact structures are disposed on the first sub-semiconductor pillar or the second sub-semiconductor pillar, and the conductive contact structures are in contact with the top surface and part of the side surface of the first sub-semiconductor pillar or the second sub-semiconductor pillar. In the first direction, the conductive contact structures are located between the first isolation layer and the second isolation layer.

[0018] A third insulating layer is disposed between the conductive contact structures in the second direction.

[0019] The semiconductor structure fabrication method provided in this embodiment utilizes a first isolation layer and a second isolation layer as limiting layers. It also utilizes the characteristic that the etching rate of the first sacrificial pattern is greater than the etching rate of the first and second isolation layers to self-align and remove the first sacrificial pattern, forming a gap between the first and second isolation layers. A conductive contact layer is then formed within this gap, and the conductive contact layer is patterned to form a conductive contact structure. This eliminates the need to separately form conductive contact holes and then form a conductive contact structure within them, avoiding the problems of high alignment difficulty and low alignment accuracy when forming conductive contact holes, thus significantly reducing the process complexity.

[0020] In the semiconductor structure provided in this embodiment, the conductive contact structure contacts the top surface and part of the side surface of the first sub-semiconductor pillar or the second sub-semiconductor pillar, thereby increasing the contact area between the conductive contact structure and the first and second sub-semiconductor pillars and reducing the contact resistance between the conductive contact structure and the first and second sub-semiconductor pillars. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0022] Figures 2A to 2N This is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0023] The specific embodiments of the semiconductor structure and its preparation method provided in this disclosure are described in detail below with reference to the accompanying drawings.

[0024] Figure 1 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Please refer to [link / reference]. Figure 1The fabrication method includes: step S10, forming an initial structure 21 on a substrate 20. The initial structure 21 includes a plurality of main semiconductor pillars 210 arranged in an array along a first direction D1 and a second direction D2, and the main semiconductor pillars 210 extend along a third direction D3. Each main semiconductor pillar 210 includes a first sub-semiconductor pillar 211 and a second sub-semiconductor pillar 212 spaced apart along the first direction D1. A first isolation layer 213 is disposed between two adjacent main semiconductor pillars 210 in the first direction D1, and a second isolation layer 214 is disposed between the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212. Both the first isolation layer 213 and the second isolation layer 214 extend along the second direction D2. In the third direction D3, both the first isolation layer 213 and the second isolation layer 214 protrude beyond the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212. A first sacrificial pattern 313 is disposed on the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 in the third direction D3. A first sacrificial pattern 313 is located between the first isolation layer 213 and the second isolation layer 214 on D1; in step S11, the first sacrificial pattern 313 is etched to expose the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, wherein the etching rate of the etching material on the first sacrificial pattern 313 is greater than the etching rate on the first isolation layer 213 and the second isolation layer 214; in step S12, a conductive contact layer 700 is formed, which fills the space between the first isolation layer 213 and the second isolation layer 214 and covers the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, and extends along the second direction D2; in step S13, the conductive contact layer 700 is patterned to form a plurality of independent conductive contact structures 720, which contact the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212; in step S14, an insulating material is filled in the gaps between the conductive contact structures 720 to form a third isolation layer 730.

[0025] The semiconductor structure fabrication method provided in this embodiment utilizes a first isolation layer 213 and a second isolation layer 214 as limiting layers. It utilizes the characteristic that the etching rate of the first sacrificial pattern 313 is greater than the etching rate of the first isolation layer 213 and the second isolation layer 214 to self-align and remove the first sacrificial pattern 313, forming a gap between the first isolation layer 213 and the second isolation layer 214. A conductive contact layer 700 is then formed in the gap, and the conductive contact layer 700 is patterned to form a conductive contact structure 720. This eliminates the need to separately form conductive contact holes and then form the conductive contact structure 720 within those holes, avoiding the problems of high alignment difficulty and low alignment accuracy when forming conductive contact holes. This significantly reduces the process difficulty and increases the contact area between the conductive contact structure 720 and the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, thereby reducing the contact resistance between the conductive contact structure 720 and the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212.

[0026] Figures 2A to 2N This is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. In this embodiment, the first direction D1 is the X direction in the Cartesian coordinate system, the second direction D2 is the Y direction in the Cartesian coordinate system, and the third direction D3 is the Z direction in the Cartesian coordinate system, as an example for illustration.

[0027] Please see Figure 1 and Figure 2H In the diagram, (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a). In step S10, an initial structure 21 is formed on the substrate 20. The initial structure 21 includes a plurality of main semiconductor pillars 210 arranged in an array along a first direction D1 and a second direction D2, and the main semiconductor pillars 210 extend along a third direction D3. Each main semiconductor pillar 210 includes a first sub-semiconductor pillar 211 and a second sub-semiconductor pillar 212 spaced apart along the first direction D1. A first isolation layer 2 is disposed between two adjacent main semiconductor pillars 210 in the first direction D1. 13. A second isolation layer 214 is provided between the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, and both the first isolation layer 213 and the second isolation layer 214 extend along the second direction D2. In the third direction D3, both the first isolation layer 213 and the second isolation layer 214 protrude beyond the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212. In the third direction D3, a first sacrificial pattern 313 is provided on the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, and in the first direction D1, the first sacrificial pattern 313 is located between the first isolation layer 213 and the second isolation layer 214.

[0028] For example, in the first direction D1, main semiconductor pillars 210A and 210B are spaced apart, and a first isolation layer 213 is disposed between the main semiconductor pillars 210A and 210B; the main semiconductor pillar 210A includes a first sub-semiconductor pillar 211A and a second sub-semiconductor pillar 212A spaced apart along the first direction D1, and a second isolation layer 214A is disposed between the first sub-semiconductor pillar 211A and the second sub-semiconductor pillar 212A; the main semiconductor pillar 210B includes a first sub-semiconductor pillar 211B and a second sub-semiconductor pillar 212B spaced apart along the first direction D1, and a second isolation layer 214B is disposed between the first sub-semiconductor pillar 211B and the second sub-semiconductor pillar 212B. On the third direction D3, a first sacrificial pattern 313 is provided on the first sub-semiconductor pillar 211A, the second sub-semiconductor pillar 212A, the first sub-semiconductor pillar 211B, and the second sub-semiconductor pillar 212B, and the first sacrificial pattern 313 is located between the first isolation layer 213 and the second isolation layer 214A, and between the first isolation layer 213 and the second isolation layer 214B in the first direction D1.

[0029] In some embodiments, a fourth isolation material layer 401 is further disposed between the first isolation layer 213 and the main semiconductor pillar 210 in the first direction D1, for forming a fourth isolation layer 215 in a subsequent process. The fourth isolation material layer 401 extends along the second direction D2, and in the third direction D3, the surfaces of the first isolation layer 213 and the second isolation layer 214 are flush with the surface of the fourth isolation material layer 401. The etching rate of the etching material on the fourth isolation material layer is greater than the etching rate on the first isolation layer and the second isolation layer.

[0030] In some embodiments, a fifth isolation material layer 400 is further disposed between adjacent main semiconductor pillars 210 in the second direction D2. In the third direction D3, the surface of the fifth isolation material layer 400 is flush with the surfaces of the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, and the first sacrificial pattern 313 also covers the surface of the fifth isolation material layer 400.

[0031] In some embodiments, the initial structure 21 further includes a sixth isolation layer 217, which is disposed between the first sub-semiconductor pillar 211 and the second isolation layer 214, and between the second sub-semiconductor pillar 212 and the second isolation layer 214, to further prevent particles in the main semiconductor pillar 210 from diffusing into the second isolation layer 214 and to improve the adhesion between the second isolation layer 214 and the main semiconductor pillar 210. For example, the sixth isolation layer 217 is disposed between the first sub-semiconductor pillar 211A and the second isolation layer 214A of the main semiconductor pillar 210A, and between the second sub-semiconductor pillar 212A and the second isolation layer 214A of the main semiconductor pillar 210A.

[0032] In some embodiments, an air gap 2140 is formed in the second isolation layer 214. The air gap 2140 may be a naturally formed air gap 2140 during the formation of the second isolation layer 214, in order to reduce the parasitic capacitance between the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212. In other embodiments, the second isolation layer 214 may not have an air gap 2140 formed, but may instead be directly filled with isolation material.

[0033] In some embodiments, a first gate structure 218 (denoted as ) is further provided on both sides of each main semiconductor pillar along the first direction D1. Figure 2F ) and the second gate structure 219 (marked in Figure 2F The first gate structure 218 and the second gate structure 219 extend along the second direction D2, and the first gate structure 218 contacts the first sub-semiconductor pillar 211, and the second gate structure 219 contacts the second sub-semiconductor pillar 212.

[0034] In some embodiments, a bit line structure (not shown in the figures) is further provided within the substrate 20. The bit line structure extends along a first direction D1, and multiple bit line structures are arranged at intervals along a second direction D2. In a third direction D3, the bit line structure is connected to the bottom of the main semiconductor pillar. In some embodiments, in order to isolate the bit line structure from the first gate structure 218 and the second gate structure 219, the initial structure 21 further includes a seventh isolation layer 220. The seventh isolation layer 220 is disposed between the main semiconductor pillars 210 in the first direction D1, and in the third direction D3, the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 protrude from the seventh isolation layer 220. The first gate structure 218 and the second gate structure 219 are disposed on the seventh isolation layer 220.

[0035] In some embodiments, on the third-party D3, the top surface of the first sacrificial pattern 313 is flush with the first isolation layer 213 and the second isolation layer 214.

[0036] As an example, this disclosure also provides a method for forming an initial structure 21. The method includes:

[0037] Please see Figures 2A-2EA first structure 300 is provided, the first structure 300 includes a plurality of main semiconductor pillars, and in a first direction D1, a third trench 316 is provided between adjacent main semiconductor pillars 210, the third trench 316 extends along a second direction D2, each main semiconductor pillar 210 includes a first sub-semiconductor pillar 211 and a second sub-semiconductor pillar 212 spaced apart along the first direction D1, a second isolation layer 214 is provided between the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, and in a third direction D3, a first sacrificial pattern 313 is provided on the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, the surface of the first sacrificial pattern 313 is flush with the surface of the second isolation layer 214.

[0038] In some embodiments, in the first structure 300, a fifth isolation material layer 400 is further disposed between adjacent main semiconductor pillars 210 in the second direction D2. In the third direction D3, the surface of the fifth isolation material layer 400 is flush with the surfaces of the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, and the first sacrificial pattern 313 also covers the surface of the fifth isolation material layer 400.

[0039] As an example, methods for forming the first structure 300 include:

[0040] Please see Figure 2A (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a). A substrate 20 is provided, on which semiconductor layers 301 are arranged at intervals along the second direction D2 and extending along the first direction D1, and an initial isolation material layer 302 is provided between adjacent semiconductor layers 301.

[0041] The substrate 20 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The substrate 20 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 20 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the substrate 20 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or diodes, may also be formed within the substrate 20. In this embodiment, the substrate 20 is a silicon substrate, and it may also include other device structures, such as transistor structures, metal wiring structures, etc., but these are not shown because they are irrelevant to the embodiments of this disclosure.

[0042] The initial isolation material layer 302 is used to insulate and isolate the semiconductor layer 301, and its material may be an oxide, such as silicon oxide. On the third direction D3, the surface of the initial isolation material layer 302 is flush with the surface of the semiconductor layer 301.

[0043] In this step, the method of forming the semiconductor layer 301 and the initial isolation material layer 302 includes: etching the substrate 20 to form a plurality of trenches, the trenches extending along a first direction D1 and the plurality of trenches arranged along a second direction D2; filling the trenches with an insulating material to form the initial isolation material layer 302, wherein the substrate 20 between the initial isolation material layers 302 serves as the semiconductor layer 301.

[0044] Please see Figure 2B In the diagram, (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a), forming a cover layer 310. The cover layer 310 includes a plurality of first patterns 311 extending along a second direction D2, and the plurality of first patterns 311 are spaced apart along a first direction D1. A first trench 312 is formed between adjacent first patterns 311 in the first direction D1, and the first trench 312 exposes a portion of the semiconductor layer 301 and the initial isolation material layer 302. In the first direction D1, the first pattern 311 includes two first sacrificial patterns 313 and a second sacrificial pattern 314 disposed between the two first sacrificial patterns 313. The sidewalls of the first trench 312 expose the first sacrificial patterns 313 of the first pattern 311.

[0045] In some embodiments, the method of forming the cover layer 310 includes: forming a second sacrificial material layer on the surfaces of the semiconductor layer 301 and the initial isolation material layer 302; patterning the second sacrificial material layer to form a second sacrificial pattern 314, the second sacrificial patterns 314 having gaps extending along a second direction D2 and exposing a portion of the semiconductor layer 301 and the initial isolation material layer 302; covering the sidewalls and top surface of the second sacrificial pattern 314 and the exposed surfaces of the semiconductor layer 301 and the initial isolation material layer 302 with a first sacrificial material layer; removing the first sacrificial material layer from the top surface of the second sacrificial pattern 314 and the surfaces of the semiconductor layer 301 and the initial isolation material layer 302, and retaining the first sacrificial material layer as the first sacrificial pattern 313.

[0046] In some embodiments, the material of the first sacrificial pattern 313 includes, but is not limited to, polysilicon and silicon oxynitride, and the material of the second sacrificial pattern 314 has a higher etching selectivity than that of the first sacrificial pattern 313, so as to ensure that the second sacrificial pattern 314 is not damaged when the first sacrificial material layer is removed.

[0047] Please see Figure 2CIn the diagram, (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a). Using the capping layer 310 as a mask layer 710, a portion of the semiconductor layer 301 and the initial isolation material layer 302 are removed along the first trench 312 to form a second trench 315. The second trench 315 extends along the second direction D2, and a plurality of second trenches 315 are arranged at intervals along the first direction D1. The sidewalls of the second trenches 315 expose the semiconductor layer 301 and the initial isolation material layer 302.

[0048] Please see Figure 2D In the diagram, (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a). An insulating material is filled in the first trench 312 and the second trench 315 to form a second insulating layer 214. The second insulating layer 214 includes, but is not limited to, a silicon nitride layer. In some embodiments, on the third-direction D3, the surface of the second insulating layer 214 is flush with the surfaces of the first sacrificial pattern 313 and the second sacrificial pattern 314.

[0049] In some embodiments, if the insulating material also covers the surface of the cover layer 310, the step further includes removing the insulating material located on the surface of the cover layer 310 and retaining the insulating material located in the first trench 312 and the second trench 315, wherein the retained insulating material serves as the second insulating layer 214.

[0050] In some embodiments, prior to the step of forming the second isolation layer 214, a sixth isolation layer 217 is formed on the sidewall of the second trench 315. The sixth isolation layer 217 has voids, and when the isolation material is filled in the first trench 312 and the second trench 315, the isolation material also fills the voids in the sixth isolation layer 217.

[0051] The sixth isolation layer 217 may be formed only on the surface of the semiconductor layer 301 exposed on the sidewall of the second trench 315, or it may be formed on the surface of the semiconductor layer 301 and the initial isolation material layer 302 exposed on the sidewall of the second trench 315, or it may be formed on the surface of the semiconductor layer 301 and the initial isolation material layer 302 exposed on the sidewall of the second trench 315, as well as on the sidewall of the first trench 312. In this embodiment, an oxide is formed on the surface of the semiconductor layer 301 on the sidewall of the second trench 315 using a thermal oxidation process. This oxide serves as the sixth isolation layer 217. The sixth isolation layer 217 is not formed on the surface of the initial isolation material layer 302 exposed on the sidewall of the second trench 315, nor on the sidewall of the first trench 312.

[0052] In some embodiments, when filling the isolation material to form the second isolation layer 214, since the second trench 315 and the first trench 312 have a large depth and width ratio, the isolation material is not easy to fill the second trench 315, and an air gap 2140 will naturally form in the second isolation layer 214.

[0053] Please see Figure 2E In the diagram, (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a). The second sacrificial pattern 314, a portion of the semiconductor layer 301 below the second sacrificial pattern 314, and the initial isolation material layer 302 are removed to form the third trench 316, the main semiconductor pillar, and the fifth isolation material layer 400. On the third direction D3, the extension depth of the third trench 316 in the substrate 20 is greater than or equal to the extension depth of the second trench 315 in the substrate 20.

[0054] In this step, the second sacrificial pattern 314 is removed, the first sacrificial pattern 313 is retained, and part of the surface of the semiconductor layer 301 and the initial isolation material layer 302 is exposed; using the first sacrificial pattern 313 as a mask, the semiconductor layer 301 and the initial isolation material layer 302 are removed to form the third trench 316.

[0055] The third trench 316 divides the semiconductor layer 301 into a plurality of main semiconductor pillars 210, and each main semiconductor pillar 210 is further divided into a first sub-semiconductor pillar 211 and a second sub-semiconductor pillar 212 by the second isolation layer 214 and the sixth isolation layer 217. The third trench 316 also cuts the initial isolation material layer 302 to form a fifth isolation material layer 400, which is disposed between adjacent main semiconductor pillars 210 along the second direction D2.

[0056] In this embodiment, in the third direction D3, the extension depth of the third trench 316 in the substrate 20 is greater than the extension depth of the second trench 315 in the substrate 20. That is, in the third direction D3, the bottom of the main semiconductor pillar 210 is not separated by the second trench 315, but is a single main semiconductor pillar 210. The upper part of the main semiconductor pillar 210 is separated into a first sub-semiconductor pillar 211 and a second sub-semiconductor pillar 212 by the second trench 315. In other embodiments, in the third direction D3, the extension depth of the third trench 316 in the substrate 20 may also be equal to the extension depth of the second trench 315 in the substrate 20. That is, the main semiconductor pillar 210 is completely separated into the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212.

[0057] At this point, the above steps form the first structure 300.

[0058] Please see Figure 2FWhere (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a), the step of depositing isolation material in the third trench 316 to form the fourth isolation material layer 401 includes:

[0059] A seventh isolation layer 220 is formed at the bottom of the third trench 316, and the surface of the seventh isolation layer 220 protrudes from the bottom surface of the second trench 315 on the third direction D3. The seventh isolation layer 220 serves as an insulating layer between the subsequently formed first gate structure 218 and second gate structure 219 and the substrate 20 or the bit line structure located within the substrate 20. The seventh isolation layer 220 includes, but is not limited to, an oxide layer or a nitride layer.

[0060] After the seventh isolation layer 220 is formed, a first gate structure 218 and a second gate structure 219 are formed in the third trench 316. In the first direction D1, a gap E exists between the first gate structure 218 and the second gate structure 219 located in the same third trench 316, so that the first gate structure 218 and the second gate structure 219 located in the same third trench 316 are insulated from each other. The first gate structure 218 includes a gate dielectric layer 2180 and a conductive layer 2181, with the gate dielectric layer 2180 located between the first sub-semiconductor pillar 211 and the conductive layer 2181. The second gate structure 219 includes a gate dielectric layer 2190 and a conductive layer 2191, with the gate dielectric layer 2190 located between the first sub-semiconductor pillar 212 and the conductive layer 2191. The region corresponding to the first sub-semiconductor pillar 211 and the conductive layer 2181 serves as the channel region of a transistor, and the region corresponding to the second sub-semiconductor pillar 212 and the conductive layer 2191 serves as the channel region of another transistor.

[0061] In some embodiments, gate dielectric layer 2180 and gate dielectric layer 2190 are the same gate dielectric material layer 500, wherein the area of ​​the gate dielectric material layer 500 covered by the conductive layer 2181 is the gate dielectric layer 2180, and the area of ​​the gate dielectric material layer 500 covered by the conductive layer 2191 is the gate dielectric layer 2190. In this step, the gate dielectric material layer 500 not only covers the surface of the main semiconductor pillar exposed on the sidewall of the third trench 316, but also covers the surface of the fifth isolation material layer 400 exposed on the sidewall of the third trench 316, the side and top surfaces of the first sacrificial pattern 313, and the top surface of the second isolation layer 214.

[0062] In some embodiments, the method of forming the first gate structure 218 and the second gate structure 219 includes: forming a gate dielectric material layer 500 in at least a third trench 316; filling the third trench 316 with gate material; removing a portion of the gate material, with the remaining gate material serving as conductive layer 2181 and conductive layer 2191.

[0063] On the third-direction D3, the surfaces of the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 protrude from the first gate structure 218 and the second gate structure 219 to form a buried gate.

[0064] Please see Figure 2G In the diagram, (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a). An isolation material is deposited within the third trench 316 to form a fourth isolation material layer 401. The fourth isolation material layer 401 covers the sides of the main semiconductor pillar 210 and the sides of the first sacrificial pattern 313. In this step, the fourth isolation material layer 401 does not completely fill the third trench 316. The fourth isolation material layer 401 includes, but is not limited to, an oxide layer.

[0065] In some embodiments, the fourth isolation layer 401 further covers the sidewalls of the fifth isolation layer 400. The fourth isolation layer 401 also fills the gap between the first gate structure 218 and the second gate structure 219 located in the same third trench 316, so that the first gate structure 218 and the second gate structure 219 located in the same third trench 316 are insulated from each other. In some embodiments, if the sidewalls of the main semiconductor pillar 210 and the sidewalls of the first sacrificial pattern 313 have a gate dielectric layer, the fourth isolation layer 401 covers the surface of the gate dielectric layer.

[0066] Please see Figure 2H In the diagram, (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a). The third trench 316 is filled with insulating material to form the first insulating layer 213. On the third direction D3, the surface of the first insulating layer 213 is flush with the surface of the second insulating layer 214.

[0067] In some embodiments, the isolation material not only fills the third trench 316 but also covers the top surface of the semiconductor structure. In this step, the method further includes removing the isolation material from the top surface of the semiconductor structure, leaving only the isolation material located within the third trench 316. If the top surface of the semiconductor structure also has a fourth isolation material layer 401 and a gate dielectric material layer 500, in this step, these layers on the top surface of the semiconductor structure are simultaneously removed, such that the surfaces of the first isolation layer 213, the second isolation layer 214, the first sacrificial pattern 313, the fourth isolation material layer 401, and the gate dielectric material layer 500 are flush on the third direction D3. In some embodiments, the method for removing the surfaces of the first isolation layer 213, the fourth isolation material layer 401, and the gate dielectric material layer 500 on the top of the semiconductor structure may be chemical mechanical polishing.

[0068] At this point, the above steps form the initial structure 21.

[0069] Please see Figure 1 and Figure 2I In the diagram, (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a). In step S11, the first sacrificial pattern 313 is etched to expose the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212. The etching rate of the etching material on the first sacrificial pattern 313 is greater than the etching rate on the first isolation layer 213 and the second isolation layer 214. In this step, after removing the first sacrificial pattern 313, the surfaces of the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 are exposed, and on the third direction D3, both the first isolation layer 213 and the second isolation layer 214 protrude beyond the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212.

[0070] In this embodiment, the first sacrificial pattern 313 is used as a placeholder. After removing the first sacrificial pattern 313, the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 are exposed. This avoids the need to create small-sized contact holes corresponding to the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 in order to expose the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, thereby reducing the process difficulty and improving the alignment accuracy between the subsequent conductive contact structure 720 and the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, further improving the reliability of the semiconductor structure.

[0071] This step utilizes the fact that the etching rate of the first sacrificial pattern 313 is greater than the etching rate of the first isolation layer 213 and the second isolation layer 214 by the etching material to selectively remove the first sacrificial pattern 313 while retaining the first isolation layer 213 and the second isolation layer 214, so as to form a gap between the first isolation layer 213 and the second isolation layer 214. The gap extends along the second direction D2, and the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 are located in different gaps.

[0072] For example, the second isolation layer 214A, the first isolation layer 213 and the second isolation layer 214B are spaced apart, there is a gap C between the second isolation layer 214A and the first isolation layer 213, there is a gap D between the first isolation layer 213 and the second isolation layer 214B, the second sub-semiconductor pillar 212A is located in the gap C, and the first sub-semiconductor pillar 211B is located in the gap D.

[0073] In some embodiments, in this step, taking advantage of the characteristic that the etching rate of the etching material on the fourth isolation material layer 401 is greater than the etching rate on the first isolation layer 213 and the second isolation layer 214, a portion of the fourth isolation material layer 401 is selectively removed, and the remaining fourth isolation material layer 401 serves as the fourth isolation layer 215. The fourth isolation layer 215 extends along the second direction D2, and in the third direction D3, the surfaces of the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 are flush with or protrude from the surface of the fourth isolation layer 215.

[0074] For example, a fourth isolation layer 215A is further disposed between the first isolation layer 213 and the main semiconductor pillar 210A, and a fourth isolation layer 215B is further disposed between the first isolation layer 213 and the main semiconductor pillar 210B. In the third direction D3, the surface of the second sub-semiconductor pillar 212A protrudes beyond the surface of the fourth isolation layer 215A, and the surface of the first sub-semiconductor pillar 211B protrudes beyond the surface of the fourth isolation layer 215B, in order to increase the exposed surface area of ​​the second sub-semiconductor pillar 212A and the first sub-semiconductor pillar 211B, thereby increasing the contact area between the second sub-semiconductor pillar 212A and the first sub-semiconductor pillar 211B and the conductive contact structure 720. In other embodiments, the surface of the second sub-semiconductor pillar 212A may also be flush with the surface of the fourth isolation layer 215A, and the surface of the first sub-semiconductor pillar 211B may also be flush with the surface of the fourth isolation layer 215B.

[0075] In some embodiments, there is a gap between the gate structures of adjacent main semiconductor pillars 210, and a fourth isolation layer 215 covers the gate structure and fills the gap between the gate structures so that the gate structures of adjacent main semiconductor pillars 210 are insulated from each other.

[0076] For example, a second gate structure 219 is provided on the side of the main semiconductor pillar 210A facing the main semiconductor pillar 210B, and a first gate structure 218 is provided on the side of the main semiconductor pillar 210B facing the main semiconductor pillar 210A. The second gate structure 219 and the first gate structure 218 are arranged adjacent to each other and there is a gap E between them. The fourth isolation layer 215 covers the second gate structure 219 and the first gate structure 218 and fills the gap E between them, so that the second gate structure 219 provided on the side of the main semiconductor pillar 210A facing the main semiconductor pillar 210B and the first gate structure 218 provided on the side of the main semiconductor pillar 210B facing the main semiconductor pillar 210A are insulated from each other.

[0077] In some embodiments, in this step, taking advantage of the characteristic that the etching rate of the etching material on the fifth isolation material layer 400 is greater than the etching rate on the first isolation layer 213 and the second isolation layer 214, a portion of the fifth isolation material layer 400 is selectively removed, and the remaining fifth isolation material layer 400 serves as the fifth isolation layer 216. On the third direction D3, the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 protrude from the fifth isolation layer 216.

[0078] For example, in the second direction D2, the main semiconductor pillars 210A and 210C are spaced apart, and the fifth isolation layer 216 is disposed between the main semiconductor pillars 210A and 210C. That is, the fifth isolation layer 216 is disposed between the first sub-semiconductor pillar 211A of the main semiconductor pillar 210A and the first sub-semiconductor pillar 211C of the main semiconductor pillar 210C, and between the second sub-semiconductor pillar 212A of the main semiconductor pillar 210A and the second sub-semiconductor pillar 212C of the main semiconductor pillar 210C. The first sub-semiconductor pillar 211A, the second sub-semiconductor pillar 212A, the first sub-semiconductor pillar 211C, and the second sub-semiconductor pillar 212C all protrude beyond the fifth isolation layer 216.

[0079] In some embodiments, in this step, the etching rate of the gate dielectric layer is greater than the etching rate of the first isolation layer 213 and the second isolation layer 214 by using an etching substance to selectively remove the gate dielectric layer until the surface of the gate dielectric layer on the third direction D3 is flush with the surface of the fourth isolation layer 215.

[0080] In some embodiments, the material of the first isolation layer 213 is configured to give the first sacrificial pattern 313, the fourth isolation material layer 401, and the fifth isolation material layer 400 a high etching selectivity with respect to the first isolation layer 213, thereby enabling selective etching in semiconductor processes. For example, in some embodiments, the first sacrificial pattern 313 is a polysilicon layer, the fourth isolation material layer 401 and the fifth isolation material layer 400 are all silicon oxide layers, and the first isolation layer 213 is a nitride layer. In this case, in semiconductor processes, selective removal of the first sacrificial pattern 313, the fourth isolation material layer 401, and the fifth isolation layer 400 can be achieved by selecting an etching solution that has a higher etching rate for the silicon oxide layer and the polysilicon layer and a lower etching rate for the silicon nitride layer.

[0081] In some embodiments, the preparation method further includes: Please refer to Figure 2JIn the diagram, (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a), metallization is performed on the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 to form a first metal silicide layer 600 on the surface of the first sub-semiconductor pillar 211 and a second metal silicide layer 601 on the surface of the second sub-semiconductor pillar 212. The method for metallizing the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 includes: filling a space between a first isolation layer 213 and a second isolation layer 214 with a metal, such as cobalt, covering the exposed surfaces of the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212; and performing a heat treatment to bond the metal to the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 to form a metal silicide, such as a cobalt metal silicide.

[0082] Please see Figure 1 and Figure 2K In step S12, a conductive contact layer 700 is formed. The conductive contact layer 700 fills the space between the first isolation layer 213 and the second isolation layer 214 and covers the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212. The conductive contact layer 700 extends along the second direction D2. (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a). In step S12, a conductive contact layer 700 is formed. The conductive contact layer 700 fills the space between the first isolation layer 213 and the second isolation layer 214 and covers the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212. The conductive contact layer 700 extends along the second direction D2.

[0083] In some embodiments, the conductive contact layer 700 is a multilayer composite structure. For example, in this embodiment, the conductive contact layer 700 is a composite structure of a titanium layer, a titanium nitride layer, and a tungsten layer, wherein the thickness of the titanium layer and the titanium nitride layer is less than the thickness of the tungsten layer.

[0084] In some embodiments, in the first direction D1, the first isolation layer 213 and the second isolation layer 214 are not only provided with a first sub-semiconductor pillar 211 or a second sub-semiconductor pillar 212, but also with a fourth isolation layer 215. The conductive contact layer 700 also covers the fourth isolation layer 215, which further increases the width of the gap between the first isolation layer 213 and the second isolation layer 214 in the second direction D2, reduces the aspect ratio of the gap between the first isolation layer 213 and the second isolation layer 214, and improves the film quality of the conductive contact layer 700.

[0085] As an example, this disclosure also provides a method for forming a conductive contact layer 700, the method comprising: depositing a titanium material layer covering the exposed surfaces of a semiconductor structure, such as the surfaces of a first isolation layer 213, a second isolation layer 214, a first sub-semiconductor pillar 211, a second sub-semiconductor pillar 212, a fourth isolation layer 215, a fifth isolation layer 216, and a gate dielectric material layer 500; depositing a titanium nitride material layer on the titanium material layer, the titanium nitride material layer covering the titanium material layer but not filling the gap between the first isolation layer 213 and the second isolation layer 214; forming a tungsten layer on the titanium nitride material layer, the tungsten layer filling the gap between the first isolation layer 213 and the second isolation layer 214 and covering the top surface of the semiconductor structure; removing the tungsten layer, the titanium nitride layer, and the titanium layer on the top surface of the semiconductor structure, retaining the tungsten layer, the titanium nitride layer, and the titanium layer between the first isolation layer 213 and the second isolation layer 214, to form the conductive contact layer 700.

[0086] In some embodiments, the conductive contact layer 700 is in contact with the first metal silicide layer 600 and the second metal silicide layer 601.

[0087] Please see Figure 1 and Figure 2M In step S13, the conductive contact layer 700 is patterned to form a plurality of independent conductive contact structures 720, and the conductive contact structures 720 are in contact with the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212. (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a).

[0088] In this step, a portion of the conductive contact layer 700 is removed to form multiple conductive contact structures 720. The arrangement of the conductive contact structures 720 is the same as that of the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212. One first sub-semiconductor pillar 211 is connected to one conductive contact structure 720, and one second sub-semiconductor pillar 212 is connected to one conductive contact structure 720.

[0089] In some embodiments, the conductive contact structure 720 not only contacts the top surface of the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212, but also contacts a portion of the side surface of the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212, greatly increasing the contact area and thereby reducing the contact resistance between the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212 and the conductive contact structure 720.

[0090] As an example, this disclosure also provides a method for patterning a conductive contact layer 700. The method includes:

[0091] Please see Figure 2LIn the diagram, (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a), a patterned mask layer 710 is formed on the conductive contact layer 700. The mask layer 710 includes a plurality of second patterns 711 extending along a first direction D1 and spaced apart along a second direction D2. A fourth trench 712 is provided between adjacent second patterns 711, and the fourth trench 712 exposes a portion of the conductive contact layer 700. In some embodiments, the first direction D1 is the extension direction of the bit line structure.

[0092] Please see Figure 2M Using the mask layer 710 as a mask, a portion of the conductive contact layer 700 is removed along the fourth trench 712 to form the conductive contact structure 720. The mask layer 710 is removed after the conductive contact structure 720 is formed. In some embodiments, in the second direction D2, the side surface of the conductive contact structure 720 is flush with the side surface of the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212.

[0093] Please see Figure 1 and Figure 2N In step S14, an insulating material is filled into the gaps between the conductive contact structures 720 to form a third insulating layer 730. (a) is a top view, (b) is a cross-sectional view along line AA' in (a), and (c) is a cross-sectional view along line BB' in (a).

[0094] The third insulating layer 730 fills the gaps between adjacent conductive contact structures 720 to insulate the adjacent conductive contact structures 720 from each other. In some embodiments, the material of the third insulating layer 730 is the same as that of the first insulating layer 213 and the second insulating layer 214, for example, all three are silicon nitride.

[0095] In some embodiments, on the third-direction D3, the surface of the third isolation layer 730 is flush with the surface of the conductive contact structure 720.

[0096] The semiconductor structure fabrication method provided in this embodiment does not require forming a conductive contact hole separately, and then forming a conductive contact structure 720 in the conductive contact hole. This avoids the problems of high alignment difficulty and low alignment accuracy when forming conductive contact holes, greatly reduces the process difficulty, and increases the contact area between the conductive contact structure 720 and the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, thereby reducing the contact resistance between the conductive contact structure 720 and the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212.

[0097] After forming the third isolation layer 730, the fabrication method further includes the step of forming a charge storage structure, which is in contact with the conductive contact structure 720. Since the conductive contact structure 720 formed by the fabrication method provided in this disclosure has a flat surface, it can provide a flat substrate for the subsequently formed charge storage structure, further preventing leakage of the charge storage structure. Furthermore, in some embodiments, the exposed surface area of ​​the conductive contact structure 720 is larger than the area of ​​the top surface of the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212, which can reduce the difficulty of aligning the capacitor storage structure and increase the contact area between the capacitor storage structure and the conductive contact structure 720, thereby reducing the contact resistance.

[0098] This disclosure also provides a semiconductor structure prepared using the above-described method. Please refer to [link to relevant documentation]. Figures 2A to 2N The semiconductor structure includes: a substrate 20; a plurality of main semiconductor pillars 210 arranged in an array along a first direction D1 and a second direction D2 on the substrate 20, and the main semiconductor pillars 210 extending along a third direction D3, each main semiconductor pillar 210 including a first sub-semiconductor pillar 211 and a second sub-semiconductor pillar 212 spaced apart along the first direction D1; a first isolation layer 213 disposed between two adjacent main semiconductor pillars 210 in the first direction D1, and the first isolation layer 213 extending along the second direction D2, and protruding beyond the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212 in the third direction D3; and a second isolation layer 214 disposed on the first sub-semiconductor pillar 211. Between the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212, and the second isolation layer 214 extends along the second direction D2. In the third direction D3, the second isolation layer 214 protrudes from the first sub-semiconductor pillar 211 and the second sub-semiconductor pillar 212. A plurality of independent conductive contact structures 720 are disposed on the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212, and the conductive contact structures 720 are in contact with the top surface and part of the side surface of the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212. In the first direction D1, the conductive contact structures 720 are located between the first isolation layer 213 and the second isolation layer 214. A third isolation layer 730 is disposed between the conductive contact structures 720 in the second direction D2.

[0099] In this embodiment of the present disclosure, the conductive contact structure 720 can contact the top surface and part of the side surface of the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212, thereby increasing the contact area between the conductive contact structure 720 and the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212 and reducing the contact resistance.

[0100] In some embodiments, the semiconductor structure further includes a charge storage structure, which is in contact with the conductive contact structure 720. The conductive contact structure 720 has a large surface area for connecting with the charge storage structure, further increasing the contact area between the charge storage structure and the conductive contact structure 720 and reducing contact resistance. Furthermore, the flat surface of the conductive contact structure 720 provides a flat substrate for the charge storage structure, further preventing leakage.

[0101] In some embodiments, the semiconductor structure further includes a fourth isolation layer 215. The fourth isolation layer 215 is disposed between two main semiconductor pillars 210 in a first direction D1, and in a third direction D3, a first sub-semiconductor and a second sub-semiconductor pillar 212 protrude beyond the fourth isolation layer 215. The conductive contact structure 720 also covers the fourth isolation layer 215. In some embodiments, the material of the fourth isolation layer 215 is different from the material of the first isolation layer 213; for example, the material of the fourth isolation layer 215 is silicon oxide, and the material of the first isolation layer 213 is silicon nitride.

[0102] In some embodiments, the semiconductor structure further includes a fifth isolation layer 216 disposed between the main semiconductor pillars 210 in a second direction D2. In a third direction D3, a first sub-semiconductor pillar 211 and a second sub-semiconductor pillar 212 protrude beyond the fifth isolation layer 216, and a third isolation layer 730 is also disposed above and covers the fifth isolation layer 216. In a first direction D1, a fourth isolation layer 215 also covers the sidewalls of the fifth isolation layer 216, and in a third direction D3, the fourth isolation layer 215 is flush with the surface of the fifth isolation layer 216. In some embodiments, the material of the fifth isolation layer 216 is the same as the material of the fourth isolation layer 215, for example, both are silicon oxide.

[0103] In some embodiments, the semiconductor structure further includes a sixth isolation layer 217. The sixth isolation layer 217 is disposed in the first direction D1 between the first sub-semiconductor pillar 211 and the second isolation layer 214, and between the second sub-semiconductor pillar 212 and the second isolation layer 214, and serves to block particle diffusion and improve adhesion. In some embodiments, the material of the sixth isolation layer 217 is different from the material of the second isolation layer 214; for example, the material of the sixth isolation layer 217 is silicon oxide, and the material of the second isolation layer 214 is silicon nitride.

[0104] In some embodiments, on the third-direction D3, the extension depth of the first isolation layer 213 in the substrate 20 is greater than or equal to the extension depth of the second isolation layer 214 in the substrate 20. When the extension depth of the first isolation layer 213 in the substrate 20 is greater than the extension depth of the second isolation layer 214 in the substrate 20, the bottom of the main semiconductor pillar 210 is not separated by the second isolation layer 214, and only the top of the main semiconductor pillar 210 is separated into a first sub-semiconductor pillar 211 and a second sub-semiconductor pillar 212. In some embodiments, an air gap 2140 is formed in the second isolation layer 214.

[0105] In some embodiments, the semiconductor structure further includes a seventh isolation layer 220, a first gate structure 218, and a second gate structure 219. The seventh isolation layer 220 is disposed between the main semiconductor pillars 210 in a first direction D1, and in a third direction D3, a first sub-semiconductor pillar 211 and a second sub-semiconductor pillar 212 protrude from the seventh isolation layer 220. The first gate structure 218 and the second gate structure 219 extend along a second direction D2 and are disposed on the seventh isolation layer 220. The first gate structure 218 and the second gate structure 219 are respectively located on both sides of each main semiconductor pillar 210 along the first direction D1, with the first gate structure 218 contacting the first sub-semiconductor pillar 211 and the second gate structure 219 contacting the second sub-semiconductor pillar 212. The region corresponding to the first sub-semiconductor pillar 211 and the first gate structure 218 serves as the channel region of a transistor, and the region corresponding to the second sub-semiconductor pillar 212 and the second gate structure 219 serves as the channel region of another transistor.

[0106] In some embodiments, the semiconductor structure further includes a first metal silicide layer 600 and a second metal silicide layer 601. The first metal silicide layer 600 is located on the surface of the first sub-semiconductor pillar 211, and the second metal silicide layer 601 is located on the surface of the second sub-semiconductor pillar 212. The conductive contact structure 720 is in contact with the first metal silicide layer 600 or the second metal silicide layer 601. The first metal silicide layer 600 and the second metal silicide layer 601 are used to reduce the contact resistance between the conductive contact structure 720 and the first sub-semiconductor pillar 211 or the second sub-semiconductor pillar 212, and both can be tungsten cobalt layers.

[0107] The semiconductor structure and its fabrication method provided in this disclosure can be applied to dynamic random access memory, including but not limited to dynamic random access memory with a 4F2 memory architecture.

[0108] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: An initial structure is formed on a substrate, the initial structure including a plurality of main semiconductor pillars arranged in an array along a first direction and a second direction, and the main semiconductor pillars extending along a third direction. Each main semiconductor pillar includes a first sub-semiconductor pillar and a second sub-semiconductor pillar spaced apart along the first direction. A first isolation layer is disposed between two adjacent main semiconductor pillars in the first direction, and a second isolation layer is disposed between the first sub-semiconductor pillar and the second sub-semiconductor pillar. Both the first isolation layer and the second isolation layer extend along the second direction. In the third direction, both the first isolation layer and the second isolation layer protrude beyond the first sub-semiconductor pillar and the second sub-semiconductor pillar. A first sacrificial pattern is disposed on the first sub-semiconductor pillar and the second sub-semiconductor pillar in the third direction, and the first sacrificial pattern is located between the first isolation layer and the second isolation layer in the first direction. The first sacrificial pattern is etched to expose the first sub-semiconductor pillar and the second sub-semiconductor pillar, wherein the etching rate of the etching material on the first sacrificial pattern is greater than the etching rate on the first isolation layer and the second isolation layer. A conductive contact layer is formed, which fills the space between the first isolation layer and the second isolation layer and covers the first sub-semiconductor pillar and the second sub-semiconductor pillar, and the conductive contact layer extends along the second direction; the conductive contact layer is patterned to form a plurality of independent conductive contact structures, which are in contact with the first sub-semiconductor pillar or the second sub-semiconductor pillar; An insulating material is filled into the gaps between the conductive contact structures to form a third insulating layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, A fourth isolation layer is further provided between the first isolation layer and the main semiconductor pillar in the first direction. The fourth isolation layer extends along the second direction, and in the third direction, the surfaces of the first sub-semiconductor pillar and the second sub-semiconductor pillar are flush with or protrude from the surface of the fourth isolation layer. The conductive contact structure also covers the fourth isolation layer, and the conductive contact structure contacts the top surface or the top surface and part of the side surface of the first sub-semiconductor pillar or the second sub-semiconductor pillar. The step of forming the initial structure further includes: A first structure is provided, the first structure includes a plurality of main semiconductor pillars, and in the first direction, a third trench is provided between adjacent main semiconductor pillars, the third trench extends along the second direction, each main semiconductor pillar includes a first sub-semiconductor pillar and a second sub-semiconductor pillar spaced apart along the first direction, a second isolation layer is provided between the first sub-semiconductor pillar and the second sub-semiconductor pillar, and in the third direction, a first sacrificial pattern is provided on the first sub-semiconductor pillar and the second sub-semiconductor pillar; An isolation material is deposited in the third trench to form a fourth isolation material layer, which covers the side surface of the main semiconductor pillar and the side surface of the first sacrificial pattern. The third trench is filled with insulating material to form the first insulating layer; In the step of etching the first sacrificial pattern, a portion of the fourth isolation material layer is removed, and the remaining fourth isolation material layer serves as the fourth isolation layer. The etching rate of the etching substance on the fourth isolation material layer is greater than the etching rate on the first isolation layer and the second isolation layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, A fifth isolation layer is further disposed between adjacent main semiconductor pillars in the second direction, and in the third direction, the fifth isolation layer protrudes beyond the first sub-semiconductor pillar and the second sub-semiconductor pillar; the step of forming the initial structure further includes: In the first structure, a fifth isolation material layer is further disposed between the adjacent main semiconductor pillars in the second direction. In the third direction, the surface of the fifth isolation material layer is flush with the surfaces of the first sub-semiconductor pillar and the second sub-semiconductor pillar, and the first sacrificial pattern also covers the surface of the fifth isolation material layer. In the step of forming the fourth insulating material layer, the fourth insulating material layer also covers the side surface of the fifth insulating material layer; In the step of removing the first sacrificial pattern, a portion of the fifth isolation material layer is also removed, and the remaining fifth isolation material layer serves as the fifth isolation layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The steps for forming the first structure include: A substrate is provided, on which semiconductor layers are arranged at intervals along a second direction and extending along a first direction, and an initial isolation material layer is provided between adjacent semiconductor layers; A cover layer is formed, the cover layer including a plurality of first patterns extending along a second direction and the plurality of first patterns being spaced apart along the first direction, a first trench being provided between adjacent first patterns in the first direction, the first trench exposing a portion of the semiconductor layer and the initial isolation material layer, and in the first direction, the first pattern including two first sacrificial patterns and a second sacrificial pattern disposed between the two first sacrificial patterns. Using the capping layer as a mask layer, a portion of the semiconductor layer and the initial isolation material layer are removed along the first trench to form a second trench; The first trench and the second trench are filled with insulating material to form the second insulating layer; The second sacrificial pattern, a portion of the semiconductor layer below the second sacrificial pattern, and the initial isolation material layer are removed to form the third trench, the main semiconductor pillar, and the fifth isolation material layer. In the third direction, the extension depth of the third trench in the substrate is greater than or equal to the extension depth of the second trench in the substrate.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, Prior to the step of filling the first trench and the second trench with insulating material to form the second insulating layer, the following steps are included: A sixth isolation layer is formed on the sidewall of the second trench, the sixth isolation layer having gaps; In the step of filling the first and second trenches with insulating material to form the second insulating layer, the insulating material also fills the voids in the sixth insulating layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, In the step of filling the voids in the sixth isolation layer with the isolation material, an air gap is formed in the second isolation layer.

7. The method for preparing a semiconductor structure according to claim 4, characterized in that, A first gate structure and a second gate structure are further provided on both sides of each main semiconductor pillar along the first direction. The first gate structure and the second gate structure extend along the second direction, and the first gate structure contacts the first sub-semiconductor pillar, and the second gate structure contacts the second sub-semiconductor pillar. The step of forming the initial structure further includes: Before the fourth insulating material layer is formed, a seventh insulating layer is formed at the bottom of the third trench, and in the third direction, the surface of the seventh insulating layer protrudes from the bottom surface of the second trench; The first gate structure and the second gate structure are formed in the third trench, and in the first direction, there is a gap between the first gate structure and the second gate structure located in the same third trench. In the step of forming the fourth insulating material layer, the fourth insulating material layer also fills the gap.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that, The step of patterning the conductive contact layer further includes: A patterned mask layer is formed on the conductive contact layer. The mask layer includes a plurality of second patterns that extend along the first direction and are spaced apart along the second direction. A fourth trench is provided between adjacent second patterns, and the fourth trench exposes a portion of the conductive contact layer. Using the mask layer as a mask, a portion of the conductive contact layer is removed along the fourth trench to form the conductive contact structure.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that, Prior to the step of forming the conductive contact layer, the method further includes: The first sub-semiconductor pillar and the second sub-semiconductor pillar are metallized to form a first metal silicide layer on the surface of the first sub-semiconductor pillar and a second metal silicide layer on the surface of the second sub-semiconductor pillar; in the step of patterning the conductive contact layer to form a plurality of independent conductive contact structures, the conductive contact structures are in contact with the first metal silicide layer or the second metal silicide layer.

10. A semiconductor structure, characterized in that, include: Substrate; A plurality of main semiconductor pillars are arranged in an array along a first direction and a second direction on the substrate, and the main semiconductor pillars extend along a third direction. Each main semiconductor pillar includes a first sub-semiconductor pillar and a second sub-semiconductor pillar that are spaced apart along the first direction. A first isolation layer is disposed between two adjacent main semiconductor pillars in the first direction, and the first isolation layer extends along the second direction, and in the third direction, the first isolation layer protrudes beyond the first sub-semiconductor pillar and the second sub-semiconductor pillar; A second isolation layer is disposed between the first sub-semiconductor pillar and the second sub-semiconductor pillar, and the second isolation layer extends along the second direction, and in the third direction, the second isolation layer protrudes beyond the first sub-semiconductor pillar and the second sub-semiconductor pillar; Multiple independent conductive contact structures are disposed on the first sub-semiconductor pillar or the second sub-semiconductor pillar, and the conductive contact structures are in contact with the top surface and part of the side surface of the first sub-semiconductor pillar or the second sub-semiconductor pillar. In the first direction, the conductive contact structures are located between the first isolation layer and the second isolation layer. A third insulating layer is disposed between the conductive contact structures in the second direction.

11. The semiconductor structure according to claim 10, characterized in that, Also includes: A fourth isolation layer is disposed between the two main semiconductor pillars in the first direction, and in the third direction, the first sub-semiconductor and the second sub-semiconductor pillar protrude from the fourth isolation layer, and the conductive contact structure also covers the fourth isolation layer; A fifth isolation layer is disposed between the main semiconductor pillars in the second direction, and in the third direction, the first sub-semiconductor pillar and the second sub-semiconductor pillar protrude beyond the fifth isolation layer, and the third isolation layer also covers the fifth isolation layer; A sixth isolation layer is disposed in the first direction between the first sub-semiconductor pillar and the second isolation layer, and between the second sub-semiconductor pillar and the second isolation layer.

12. The semiconductor structure according to claim 10, characterized in that, In the third direction, the depth of the first isolation layer in the substrate is greater than or equal to the depth of the second isolation layer in the substrate.

13. The semiconductor structure according to claim 10, characterized in that, An air gap is formed in the second isolation layer.

14. The semiconductor structure according to claim 10, characterized in that, Also includes: A seventh isolation layer is disposed between the main semiconductor pillars in the first direction, and in the third direction, the first sub-semiconductor pillar and the second sub-semiconductor pillar protrude from the seventh isolation layer; A first gate structure and a second gate structure extend along the second direction and are disposed on the seventh isolation layer, and are respectively located on both sides of each of the main semiconductor pillars along the first direction. The first gate structure is in contact with the first sub-semiconductor pillar, and the second gate structure is in contact with the second sub-semiconductor pillar.

15. The semiconductor structure according to any one of claims 10 to 14, characterized in that, Also includes: A first metal silicide layer is located on the surface of the first sub-semiconductor pillar; A second metal silicide layer is located on the surface of the second sub-semiconductor pillar; The conductive contact structure is in contact with either the first metal silicide layer or the second metal silicide layer.

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