Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the semiconductor structure comprising: a semiconductor substrate; a stacked structure located on the semiconductor substrate, the stacked structure comprising a plurality of linear patterns extending along a first direction and discretely arranged along a second direction, the linear patterns comprising first separator layers and composite layers alternately stacked along a vertical direction, the composite layer in a capacitor region comprising a semiconductor layer located between adjacent first separator layers and at least one second separator layer located between the semiconductor layer and the first separator layer, a first cavity being sandwiched between any two of the semiconductor layer, the first separator layer, and the second separator layer; a first electrode layer located on vertical sidewall surfaces of the second separator layer and the semiconductor layer and an inner wall of the first cavity; a dielectric layer located on a surface of the first electrode layer and on a vertical sidewall surface of the first separator layer; and a second electrode layer located on a surface of the dielectric layer and filling the first cavity.

Description

Technical Field

[0001] The present disclosure relates to the field of memory, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor. The transistor's gate is connected to a word line, its drain is connected to a bit line, and its source is connected to a capacitor. The voltage signal on the word line controls the transistor's on and off state, allowing it to read data stored in the capacitor through the bit line or write data to the capacitor for storage.

[0003] To improve integration, existing 3D DRAM manufacturing processes typically use a multi-layer stacked lateral transistor structure. However, the capacitors in existing DRAMs occupy a large area, leaving DRAM storage density to be improved. Summary of the Invention

[0004] Some embodiments of the present disclosure provide a method for forming a semiconductor structure, comprising:

[0005] providing a semiconductor substrate;

[0006] forming a stacked structure on the semiconductor substrate, the stacked structure comprising a plurality of linear patterns extending along a first direction and discretely arranged along a second direction, the linear patterns comprising first separation layers and composite layers alternately stacked along a vertical direction, the composite layer comprising a first sacrificial layer, a semiconductor layer, and a second sacrificial layer sequentially stacked along the vertical direction, the composite layer further comprising at least one second separation layer located in the first sacrificial layer and / or the second sacrificial layer;

[0007] removing the first sacrificial layer and the second sacrificial layer in the capacitor region of the stacked structure to form a first cavity;

[0008] forming a first electrode layer on the vertical sidewall surfaces of the second separation layer and the semiconductor layer and the inner wall of the first cavity;

[0009] forming a dielectric layer on a surface of the first electrode layer and on vertical sidewall surfaces of the first separation layer;

[0010] A second electrode layer is formed on the surface of the dielectric layer, and the second electrode layer fills the remaining first cavity.

[0011] In some embodiments, the process of forming the stacked structure includes: forming an initial stacked structure on the semiconductor substrate, the initial stacked structure including an initial first spacer layer and an initial composite layer alternately stacked in a vertical direction, the initial composite layer including an initial first sacrificial layer, an initial semiconductor layer, and an initial second sacrificial layer sequentially stacked in the vertical direction, the initial composite layer also including at least one initial second spacer layer located in the initial first sacrificial layer and / or the initial second sacrificial layer;

[0012] forming a plurality of grooves extending along a first direction and penetrating the initial stacking structure in a vertical direction in the initial stacking structure, so as to form the linear pattern between adjacent grooves;

[0013] A first isolation layer is filled in the trench located in the capacitor region, and a second isolation layer is filled in the trench located in the transistor region.

[0014] In some embodiments, before removing the first sacrificial layer and the second sacrificial layer located in the capacitor area in the stacked structure, it also includes: removing a portion of the length of the semiconductor layer and the second separation layer located in the capacitor area along the first direction, so that the vertical side wall surface of the first separation layer protrudes beyond the vertical side wall surfaces of the remaining semiconductor layer and the second separation layer along the first direction.

[0015] In some embodiments, the lengths of the first sacrificial layer and the second sacrificial layer removed along the first direction are greater than the lengths of the semiconductor layer and the second separation layer removed along the first direction.

[0016] In some embodiments, the first cavity exposes the upper and lower surfaces of the first separator layer, the remaining semiconductor layer, and the second separator layer of the capacitor region, and the forming process of the first electrode layer includes: forming a first electrode material layer on the vertical sidewall surfaces of the first separator layer, the second separator layer, and the semiconductor layer and on the inner wall of the first cavity;

[0017] A portion of the first electrode material layer located on the vertical sidewall surface of the first separation layer is removed to form a plurality of first electrode layers.

[0018] In some embodiments, the process of removing a portion of the first electrode material layer located on the vertical sidewall surface of the first separator layer to form a plurality of first electrode layers includes: forming a first filling material layer on the surface of the first electrode material layer to fill the first cavity;

[0019] removing a portion of the first filling material layer to expose the first electrode material layer located on the vertical sidewall surface of the first separation layer;

[0020] The exposed first electrode material layer is removed.

[0021] In some embodiments, the material of the first filling material layer is different from the materials of the first electrode material layer and the first separator layer.

[0022] In some embodiments, the material of the semiconductor layer is polycrystalline silicon. After forming the stacked structure on the semiconductor substrate, it also includes: removing the semiconductor layer located in the transistor area to form a second cavity; and sequentially forming a word line dielectric layer and a metal oxide semiconductor layer located on the surface of the word line dielectric layer and filling the second cavity in the second cavity.

[0023] In some embodiments, before forming the word line dielectric layer, the method further includes: forming an adhesion layer on the inner wall of the second cavity, wherein the word line dielectric layer is formed on the inner wall of the adhesion layer;

[0024] After forming the metal oxide semiconductor layer, the method further includes removing a portion of the adhesion layer in the transistor region near the capacitor region.

[0025] In some embodiments, the transistor region includes a first active region, a channel region, and a second active region arranged in sequence along a first direction; the first sacrificial layer and the second sacrificial layer of the channel region are removed so that the metal oxide semiconductor layer of the channel region is suspended; a selective deposition process is used to form a metal word line extending along the second direction on the surface of each suspended adhesion layer; and a bit line is formed to connect the multiple metal oxide semiconductor layers in the vertical direction in the first active region.

[0026] Some embodiments of the present disclosure further provide a semiconductor structure, including:

[0027] semiconductor substrates;

[0028] a stacked structure located on the semiconductor substrate, the stacked structure comprising a plurality of linear patterns extending along a first direction and discretely arranged along a second direction, the linear patterns comprising first spacer layers and composite layers alternately stacked along a vertical direction, the composite layer in the capacitor region comprising a semiconductor layer located between adjacent first spacer layers and at least one second spacer layer located between the semiconductor layer and the first spacer layer, a first cavity being sandwiched between any two of the semiconductor layer, the first spacer layer, and the second spacer layer;

[0029] a first electrode layer located on the vertical sidewall surfaces of the second separation layer and the semiconductor layer and the inner wall of the first cavity;

[0030] a dielectric layer located on a surface of the first electrode layer and on vertical sidewall surfaces of the first separator layer;

[0031] A second electrode layer is located on the surface of the dielectric layer and fills the first cavity.

[0032] In some embodiments, the vertical sidewall surface of the first spacer layer protrudes from the vertical sidewall surfaces of the semiconductor layer and the second spacer layer along the first direction.

[0033] In some embodiments, there is at least one second spacer layer vertically arranged between the semiconductor layer and the first spacer layer above, or there is at least one second spacer layer vertically arranged between the semiconductor layer and the second spacer layer below.

[0034] In some embodiments, at least one second spacer layer is vertically arranged between the semiconductor layer and the upper and lower first spacer layers.

[0035] In some embodiments, the transistor region includes a first active region, a channel region, and a second active region arranged in sequence along a first direction; and further includes: a word line structure extending along a second direction on the surface of each semiconductor layer located in the channel region; and a bit line connecting the multiple semiconductor layers in the vertical direction in the first active region.

[0036] The semiconductor structure formed in some of the aforementioned embodiments of the present disclosure, the capacitor structure includes a first electrode layer, a dielectric layer and a second electrode layer. Due to the presence of the first separation layer and the second separation layer, the surface area of ​​the formed first electrode layer, the dielectric layer and the second electrode layer is increased, so that under the same storage capacitance, the area occupied by the vertical projection of the formed capacitor on the surface of the semiconductor substrate is reduced, thereby improving the storage density of the DRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1-Figure 24 Schematic diagram of the formation process of a semiconductor structure in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] The following detailed description of the specific embodiments of the present disclosure is provided in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure, the schematic diagrams may be partially enlarged to a different scale for ease of explanation. Furthermore, the schematic diagrams are merely illustrative and should not limit the scope of protection of the present disclosure. Furthermore, in actual production, the three-dimensional dimensions of length, width, and depth should be included.

[0039] Some embodiments of the present disclosure first provide a method for forming a semiconductor structure, which is described in detail below with reference to the accompanying drawings.

[0040] refer to Figure 5 and Figure 6 ,in Figure 6 The four figures in the upper left, upper right, lower left and lower right are Figure 5A semiconductor substrate 200 is provided, including a schematic diagram of the cross-sectional structure along the cutting line AA1, a schematic diagram of the cross-sectional structure along the cutting line BB1, a schematic diagram of the cross-sectional structure along the cutting line CC1, and a schematic diagram of the cross-sectional structure along the cutting line DD1; a stacking structure 211 is formed on the semiconductor substrate 200, the stacking structure 211 includes a plurality of linear patterns 212 extending along the first direction and separately arranged along the second direction, the linear patterns 212 include a first separation layer 201 and a composite layer 202 alternately stacked along the vertical direction, the composite layer 202 includes a first sacrificial layer 203, a semiconductor layer 204, and a second sacrificial layer 205 stacked in sequence along the vertical direction, the composite layer 202 also includes at least one second separation layer 207 located in the first sacrificial layer 203 and / or the second sacrificial layer 205, the first direction and the second direction are parallel to the upper surface of the semiconductor substrate 200, and the vertical direction is a direction perpendicular to the upper surface of the semiconductor substrate 200.

[0041] The material of the semiconductor substrate 200 can be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 200 is single crystal silicon (Si).

[0042] In some embodiments, the stacked structure 211 includes a transistor region 21 along a first direction and a capacitor region 22 located to one side of the transistor region 21. The transistor region 21 is used to form a lateral transistor having a horizontal channel, and the capacitor region 22 is used to form a capacitor. In some embodiments, the transistor region 21 may further include a first active region, a channel region, and a second active region sequentially arranged along the first direction. In some embodiments, the first active region is subsequently used to form one of the drain region or source region of the lateral transistor, the channel region is subsequently used to form the channel region of the lateral transistor, and the second active region is subsequently used to form the other of the drain region or source region of the lateral transistor.

[0043] The first separation layer 201 is subsequently used at least to define the position and area of ​​the first electrode layer, dielectric layer, and second electrode layer of different capacitors in the vertical direction; the second separation layer 207 is subsequently used at least to increase the surface area of ​​the first electrode layer, dielectric layer, and second electrode layer in the capacitor; the first sacrificial layer 203 and the second sacrificial layer 205 are subsequently used at least as sacrificial materials to form a cavity after removal; the semiconductor layer 204 is subsequently used at least for the formation of lateral transistors in the transistor region 21, and at least for controlling the formation of the first electrode layer of the capacitor in the capacitor region 22.

[0044] In some embodiments, the first spacer layer 201 , the second spacer layer 207 , the semiconductor layer 204 and the first sacrificial layer 203 (the second sacrificial layer 205 ) are all different, so as to improve the etching selectivity when etching a certain layer. In some embodiments, the material of the first spacer layer 201 is one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride; the material of the second spacer layer 207 is one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride; the material of the first sacrificial layer 203 and the second sacrificial layer 205 is a stack of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, polycrystalline silicon, and silicon germanium; the material of the semiconductor layer 204 is one of polycrystalline silicon, silicon germanium, or a metal oxide semiconductor; the material of the metal oxide semiconductor is zinc tin oxide (ZnxSnyO, commonly known as "ZTO"), indium zinc oxide (InxZnyO, commonly known as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly known as "IGZO"), indium gallium silicon oxide (InxGaySizO, commonly known as "IGSO"), or indium tungsten oxide (InxWyO, commonly known as "IWO"). In this embodiment, the material of the first separation layer 201 is silicon nitride, the material of the second separation layer 207 is silicon carbide nitride, the material of the semiconductor layer 204 is polysilicon, and the material of the first sacrificial layer 203 and the second sacrificial layer 205 is silicon oxide.

[0045] The second spacer layer 207 may be located only in the first sacrificial layer 203, only in the second sacrificial layer 205, or located in both the first sacrificial layer 203 and the second sacrificial layer 205. Specifically, in some embodiments, the first sacrificial layer 203 has at least one second spacer layer 207 arranged vertically, or the second sacrificial layer 205 has at least one second spacer layer 207 arranged vertically. In some embodiments, both the first sacrificial layer 203 and the second sacrificial layer 205 have at least one second spacer layer 207 arranged vertically. In this embodiment, the first sacrificial layer 203 and the second sacrificial layer 205 each have only one second spacer layer 207. The first sacrificial layer 203 is divided into two layers (a lower first sacrificial layer 206 and an upper first sacrificial layer 208) by the second spacer layer 207, and the second sacrificial layer 205 is divided into two layers (a lower second sacrificial layer 209 and an upper second sacrificial layer 210) by the second spacer layer 207.

[0046] In some embodiments, an isolation layer is placed between adjacent linear patterns 212 along the second direction. In some embodiments, the isolation layer includes a first isolation layer 242 and a second isolation layer 243. The first isolation layer 242 is placed between adjacent linear patterns 212 in the capacitor region 22, and the second isolation layer 243 is placed between adjacent linear patterns 212 in the transistor region 21. The first isolation layer 242 and the second isolation layer 243 are made of different materials, thereby protecting the transistor region 21 and the capacitor region 22 from subsequent processing. Furthermore, the positions of the first isolation layer 242 and the second isolation layer 243 correspond to the positions of the capacitor region 22 and the transistor region 21, further ensuring process accuracy.

[0047] In some embodiments, the material of the first isolation layer 242 is one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, and the material of the second isolation layer 243 is one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. In this embodiment, the material of the first isolation layer 242 is silicon nitride, and the material of the second isolation layer 243 is silicon oxide.

[0048] In some embodiments, the following Figures 1-6 The formation process of the stacked structure 211 is described in detail.

[0049] First reference Figure 1-Figure 2 ,in Figure 2 The four figures in the upper left, upper right, lower left and lower right are Figure 1 A schematic diagram of the cross-sectional structure along the cutting line AA1, a schematic diagram of the cross-sectional structure along the cutting line BB1, a schematic diagram of the cross-sectional structure along the cutting line CC1, and a schematic diagram of the cross-sectional structure along the cutting line DD1, form an initial stacking structure 230 on the semiconductor substrate 200, the initial stacking structure 230 includes an initial first separation layer 231 and an initial composite layer 232 alternately stacked in a vertical direction, the initial composite layer 232 includes an initial first sacrificial layer 233, an initial semiconductor layer 234, and an initial second sacrificial layer 235 stacked in sequence in the vertical direction, the initial composite layer 232 also includes at least one initial second separation layer 237 located in the initial first sacrificial layer 233 and / or the initial second sacrificial layer 235.

[0050] The initial stacking structure 230 is subsequently used to form a stacking structure, the initial first separation layer 231 is subsequently used to form a first separation layer, the initial composite layer 232 is subsequently used to form a composite layer, the initial first sacrificial layer 233 is subsequently used to form a first sacrificial layer, the initial semiconductor layer 234 is subsequently used to form a semiconductor layer, the initial second sacrificial layer 235 is subsequently used to form a second sacrificial layer, and the initial second separation layer 237 is subsequently used to form a second separation layer.

[0051] The initial stacked structure 230 includes an initial first spacer layer 231 and an initial composite layer 232 alternately stacked in a vertical direction. The alternating stacking of the initial first spacer layer 231 and the initial composite layer 232 means that after forming an initial first spacer layer 2312 on the semiconductor substrate 200, an initial composite layer 232 is formed on the surface of the initial first spacer layer 231. The steps of forming the initial first spacer layer 231 and the initial composite layer 232 located on the initial first spacer layer 231 are then repeated in a sequential manner. Each layer structure in the initial composite layer 232 is also formed sequentially. The number of initial first spacer layers 231 and initial composite layers 232 can be determined based on actual needs. In this embodiment, three initial first spacer layers 231 and two initial composite layers 232 are used as an example for illustration. Both the bottom and top layers of the stacked structure 211 are composed of one initial first spacer layer 231. In other embodiments, the number of initial first spacer layers 231 and initial composite layers 232 can be other numbers.

[0052] In some embodiments, the initial stacking structure 230 includes a transistor region 21 and a capacitor region 22 located on one side of the transistor region 21 along the first direction. In some embodiments, the transistor region 21 may also include a first active region, a channel region, and a second active region arranged in sequence along the first direction.

[0053] In some embodiments, the initial second spacer layer 237 may be located only in the initial first sacrificial layer 233, or only in the initial second sacrificial layer 235, or located in both the initial first sacrificial layer 233 and the initial second sacrificial layer 235. Specifically, in some embodiments, the initial first sacrificial layer 233 has at least one initial second spacer layer 237 discretely arranged along the vertical direction, or the initial second sacrificial layer 235 has at least one initial second spacer layer 237 discretely arranged along the vertical direction. In some embodiments, both the initial first sacrificial layer 233 and the initial second sacrificial layer 235 have at least one initial second spacer layer 237 discretely arranged along the vertical direction. In this embodiment, the initial first sacrificial layer 233 and the initial second sacrificial layer 235 both have only one initial second separation layer 237 as an example for explanation. The initial first sacrificial layer 233 is divided into two layers (the lower initial first sacrificial layer 236 and the upper initial first sacrificial layer 238) by an initial second separation layer 237, and the initial second sacrificial layer 235 is divided into two layers (the lower initial second sacrificial layer 239 and the upper initial second sacrificial layer 240) by an initial second separation layer 237.

[0054] In some embodiments, each layer structure in the initial stacked structure 230 is formed by a deposition process.

[0055] refer to Figure 3-Figure 4 ,in Figure 4The four figures in the upper left, upper right, lower left and lower right are Figure 3 A schematic diagram of the cross-sectional structure along the cutting line AA1 direction, a schematic diagram of the cross-sectional structure along the cutting line BB1 ​​direction, a schematic diagram of the cross-sectional structure along the cutting line CC1 direction, and a schematic diagram of the cross-sectional structure along the cutting line DD1 direction, wherein a plurality of grooves 241 extending along the first direction and penetrating the initial stacking structure 230 along the vertical direction are formed in the initial stacking structure 230 to form a linear pattern 212 between adjacent grooves 241, the linear pattern 212 includes a first separation layer 201 and a composite layer 202 alternately stacked along the vertical direction, the composite layer 202 includes a first sacrificial layer 203, a semiconductor layer 204, and a second sacrificial layer 205 stacked in sequence along the vertical direction, the composite layer 202 also includes at least one second separation layer 207 located in the first sacrificial layer 203 and / or the second sacrificial layer 205, the first direction and the second direction are parallel to the upper surface of the semiconductor substrate 200, and the vertical direction is a direction perpendicular to the upper surface of the semiconductor substrate 200.

[0056] The initial stack structure 230 is etched to form a plurality of grooves 241 extending along the first direction and penetrating the initial stack structure 230 along the vertical direction in the initial stack structure 230. The initial first separation layer 231 (refer to Figure 2 ) forms the first separation layer 201, the initial composite layer 232 (reference Figure 2 ) forms a composite layer 202, an initial first sacrificial layer 233 (reference Figure 2 ) forms a first sacrificial layer 203, an initial semiconductor layer 234 (reference Figure 2 ) forms a semiconductor layer 204, an initial second sacrificial layer 235 (reference Figure 2 ) forms a second sacrificial layer 205, an initial second separation layer 237 (reference Figure 2 ) forms the second separation layer 207. It should be noted that, during the etching, the bottommost initial first separation layer 231 may be etched through or not.

[0057] In some embodiments, reference Figure 5-Figure 6 , further comprising: filling a first isolation layer 242 in the trench located in the capacitor region 22, and filling a second isolation layer 243 in the trench located in the transistor region 21, to form a stacked structure 211 spaced apart along the second direction.

[0058] In some embodiments, when the material of the semiconductor layer 204 is polysilicon or silicon germanium, subsequent steps such as forming a metal oxide semiconductor layer 216 and selectively forming a metal word line are required to form a lateral transistor (see Figure 7-18, which will be described in detail later). It should be noted that, in other embodiments, when the material of the semiconductor layer 204 is directly the metal oxide semiconductor layer 216, there is no need to perform the subsequent step of forming the metal oxide semiconductor layer 216.

[0059] First, refer to Figure 7-10 ,in Figure 8 The four figures in the upper left, upper right, lower left and lower right are Figure 7 The schematic diagram of the cross-sectional structure along the cutting line AA1, the schematic diagram of the cross-sectional structure along the cutting line BB1, the schematic diagram of the cross-sectional structure along the cutting line CC1, and the schematic diagram of the cross-sectional structure along the cutting line DD1. Figure 10 The four figures in the upper left, upper right, lower left and lower right are Figure 9 A schematic diagram of the cross-sectional structure along the cutting line AA1, a schematic diagram of the cross-sectional structure along the cutting line BB1, a schematic diagram of the cross-sectional structure along the cutting line CC1, and a schematic diagram of the cross-sectional structure along the cutting line DD1. When the material of the semiconductor layer 204 is polysilicon or silicon germanium, after forming the stacked structure 211 on the semiconductor substrate 200, it also includes: removing the semiconductor layer 204 located in the transistor area 21 to form a second cavity 214.

[0060] Before removing the semiconductor layer 204, a first etched hole 213 is formed on the side of the transistor region 21 away from the capacitor region 22, passing through the linear pattern. The semiconductor layer 204 in the transistor region 21 is then removed along the first etched hole 213 to form a second cavity 214. In some embodiments, the semiconductor layer 204 can be removed using an isotropic wet or dry etching process.

[0061] The purpose of removing the semiconductor layer 204 to form the second cavity 214 is to form a metal oxide semiconductor layer as a trench of a lateral transistor and to form an adhesion layer for the subsequent selective formation of a metal word line.

[0062] refer to Figure 11-12 ,in Figure 12 The four figures in the upper left, upper right, lower left and lower right are Figure 11 A schematic diagram of the cross-sectional structure along the cutting line AA1, a schematic diagram of the cross-sectional structure along the cutting line BB1, a schematic diagram of the cross-sectional structure along the cutting line CC1, and a schematic diagram of the cross-sectional structure along the cutting line DD1 show that an adhesion layer 215, a word line dielectric layer (not shown in the figure), and a metal oxide semiconductor layer 216 are sequentially formed on the inner wall of the second cavity.

[0063] The word line dielectric layer is formed on the inner wall of the adhesion layer 215 , and the metal oxide semiconductor layer 216 is located on the surface of the word line dielectric layer and fills the second cavity.

[0064] The purpose of forming the adhesion layer 215 is: after removing the adhesion layers 215 in the first active area and the second active area and retaining the adhesion layer 215 in the channel area, and correspondingly removing the first sacrificial layer and the second sacrificial layer, a plurality of metal word lines extending along the first direction and discretely arranged along the vertical direction can be formed on the surface of the adhesion layer 215 in the channel area through a selective formation process, thereby improving the position accuracy of the formed metal word lines and simplifying the difficulty of the metal word line formation process.

[0065] The adhesion layer 215 , the word line dielectric layer (not shown) and the metal oxide semiconductor layer 216 are formed by a deposition process and a maskless etching process.

[0066] In some embodiments, the material of the adhesion layer 215 is TiN.

[0067] In some embodiments, the metal oxide semiconductor layer 216 is made of zinc tin oxide (ZnxSnyO, commonly known as "ZTO"), indium zinc oxide (InxZnyO, commonly known as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly known as "IGZO"), indium gallium silicon oxide (InxGaySiO, commonly known as "IGSO"), or indium tungsten oxide (InxWyO, commonly known as "IWO"). The word line dielectric layer is made of silicon oxide or a high-K (K greater than 2.5) dielectric material. The high-K (K greater than 2.5) dielectric material can include HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO.

[0068] refer to Figure 13-14 ,in Figure 14 The four figures in the upper left, upper right, lower left and lower right are Figure 13 The schematic diagram of the cross-sectional structure along the cutting line AA1, the schematic diagram of the cross-sectional structure along the cutting line BB1, the schematic diagram of the cross-sectional structure along the cutting line CC1, and the schematic diagram of the cross-sectional structure along the cutting line DD1 also include: removing the first sacrificial layer 203 and the second sacrificial layer 205 (including the lower first sacrificial layer 206, the upper first sacrificial layer 208, the lower second sacrificial layer 209 and the upper second sacrificial layer 210) located in the capacitor area 22 and the second active area of ​​the transistor area 21, exposing part of the surface of the adhesion layer 215.

[0069] Before removing the first sacrificial layer 203 and the second sacrificial layer 205, a second etching hole 217 is formed on the side of the capacitor region 22 away from the transistor region 21, and the first sacrificial layer 203 and the second sacrificial layer 205 located in the second active area of ​​the capacitor region 22 and the transistor region 21 are removed along the second etching hole 217, exposing a portion of the surface of the adhesion layer 215.

[0070] In some embodiments, the first sacrificial layer 203 and the second sacrificial layer 205 may be removed by an isotropic wet or dry etching process.

[0071] refer to Figure 15 ,in Figure 15 The four figures in the upper left, upper right, lower left and lower right are Figure 13 The cross-sectional structural diagram along the cutting line AA1, the cross-sectional structural diagram along the cutting line BB1, the cross-sectional structural diagram along the cutting line CC1 and the cross-sectional structural diagram along the cutting line DD1, wherein the exposed adhesive layer 215 is removed.

[0072] In some embodiments, the exposed adhesion layer 215 may be removed by an isotropic wet or dry etching process.

[0073] refer to Figure 16 ,in Figure 16 The four figures in the upper left, upper right, lower left and lower right are Figure 13 The schematic diagram of the cross-sectional structure along the cutting line AA1, the schematic diagram of the cross-sectional structure along the cutting line BB1, the schematic diagram of the cross-sectional structure along the cutting line CC1, and the schematic diagram of the cross-sectional structure along the cutting line DD1, show that the sacrificial layer material is refilled at the position where the first sacrificial layer 203 and the second sacrificial layer 205 (including the lower first sacrificial layer 206, the upper first sacrificial layer 208, the lower second sacrificial layer 209, and the upper second sacrificial layer 210) are removed, and the filled sacrificial layer material is the same as the material of the first sacrificial layer and the second sacrificial layer.

[0074] In one embodiment, reference Figure 17 ,in Figure 17 The four figures in the upper left, upper right, lower left and lower right are Figure 13 The schematic diagram of the cross-sectional structure along the cutting line AA1, the schematic diagram of the cross-sectional structure along the cutting line BB1, the schematic diagram of the cross-sectional structure along the cutting line CC1, and the schematic diagram of the cross-sectional structure along the cutting line DD1 also include: removing a portion of the length of the semiconductor layer 204 and the second separation layer 207 located in the capacitor area 22 along the first direction, so that the vertical side wall surface of the first separation layer 201 protrudes from the vertical side wall surface of the remaining semiconductor layer 204 and the second separation layer 207 along the first direction.

[0075] The purpose of removing a portion of the length of the semiconductor layer 204 and the second separation layer 207 located in the capacitor area 22 along the first direction is to make the vertical side wall surface of the first separation layer 201 protrude from the vertical side wall surface of the remaining semiconductor layer 204 and the second separation layer 207 along the first direction. After the first electrode material layer is formed, the protruding first separation layer 201 makes part of the first electrode material layer also protruding, so that the first electrode material layer can be conveniently disconnected from the protruding first separation layer 201, thereby forming a plurality of first electrode layers arranged separately in the vertical direction, and finally forming a plurality of individually controlled capacitors in the vertical direction.

[0076] In some embodiments, removing a portion of the semiconductor layer 204 and the second spacer layer 207 located in the capacitor region 22 along the first direction may be performed using an isotropic wet or dry etching process.

[0077] refer to Figure 18 ,in Figure 18 The four figures in the upper left, upper right, lower left and lower right are Figure 13 The cross-sectional structural schematic diagram along the cutting line AA1, the cross-sectional structural schematic diagram along the cutting line BB1, the cross-sectional structural schematic diagram along the cutting line CC1, and the cross-sectional structural schematic diagram along the cutting line DD1 are shown, wherein the first sacrificial layer 203 and the second sacrificial layer 205 (including the lower first sacrificial layer 206, the upper first sacrificial layer 208, the lower second sacrificial layer 209, and the upper second sacrificial layer 210) located in the capacitor area 22 in the stacked structure are removed to form a first cavity 218.

[0078] The first cavity 218 is used to form a capacitor later. The first cavity 218 exposes the upper and lower surfaces of the first spacer layer 201, the remaining semiconductor layer 204 and the second spacer layer 207 in the capacitor region.

[0079] In some embodiments, the first sacrificial layer 203 and the second sacrificial layer 205 located in the capacitor region 22 of the stacked structure may be removed by an isotropic wet or dry etching process.

[0080] In some embodiments, the length of the first sacrificial layer 203 and the second sacrificial layer 205 removed along the first direction is greater than the length of the semiconductor layer 204 and the second spacer layer 207 removed along the first direction. In a specific embodiment, the first sacrificial layer 203 and the second sacrificial layer 205 in the capacitor region 22 are completely removed, while the first sacrificial layer 203 and the second sacrificial layer 205 in the transistor region 21 are retained, thereby protecting the metal oxide semiconductor layer 216.

[0081] After the first cavity 218 is formed, a first electrode layer needs to be formed. The formation process of the first electrode layer will be described in detail below with reference to the accompanying drawings.

[0082] refer to Figure 19 ,in Figure 19 The four figures in the upper left, upper right, lower left and lower right are Figure 13 A schematic diagram of the cross-sectional structure along the cutting line AA1, a schematic diagram of the cross-sectional structure along the cutting line BB1, a schematic diagram of the cross-sectional structure along the cutting line CC1, and a schematic diagram of the cross-sectional structure along the cutting line DD1, wherein a first electrode material layer is formed on the vertical side wall surfaces of the first separation layer 201, the second separation layer 207, and the semiconductor layer 204, and on the inner wall of the first cavity 218; a portion of the first electrode material layer located on the vertical side wall surface of the first separation layer 201 is removed to form a plurality of first electrode layers 219.

[0083] In some embodiments, the process of removing a portion of the first electrode material layer located on the vertical side wall surface of the first separation layer 201 to form multiple first electrode layers 219 includes: forming a first filling material layer (not shown in the figure) that fills the first cavity on the surface of the first electrode material layer; removing a portion of the first filling material layer to expose the first electrode material layer located on the vertical side wall surface of the first separation layer 201; removing the exposed first electrode material layer and disconnecting the first electrode material layer to form multiple first electrode layers 219 arranged separately in the vertical direction; and removing the remaining first filling material layer. When forming the first electrode layer 219, since the first separation layer 201 protrudes from the remaining semiconductor layer 204 and the second separation layer 207 along the first direction, the first electrode material layer on the vertical side wall surface of the first separation layer 201 also protrudes from the first electrode material layer on the vertical side wall surface of the remaining semiconductor layer 204 and the second separation layer 207 along the first direction. After forming the first filling material layer, by removing part of the first filling material layer, the first electrode material layer located on the vertical side wall surface of the first separation layer 201 can be easily exposed, and then the exposed first electrode material layer is removed to disconnect the first electrode material layer, so that a plurality of first electrode layers 219 arranged separately along the vertical direction can be formed very simply and accurately.

[0084] In some embodiments, the material of the first filling material layer is different from the material of the first electrode material layer and the first separator layer 201. In some embodiments, the first filling material layer can be silicon dioxide or an organic material.

[0085] The first electrode material layer (or first electrode layer 219) can be a single-layer structure formed by one of the following materials: W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, or WSi, or a stacked-layer structure formed by two or more materials from the group consisting of the foregoing materials. In this embodiment, the first electrode material layer (or first electrode layer 219) is a TiN layer.

[0086] In some embodiments, the first electrode material layer (or the first electrode layer 219 ) may be formed by a chemical vapor deposition process, a physical vapor deposition process, electroplating, or chemical plating process.

[0087] refer to Figure 20 ,in Figure 20 The four figures in the upper left, upper right, lower left and lower right are Figure 13 The cross-sectional structure schematic diagram along the cutting line AA1, the cross-sectional structure schematic diagram along the cutting line BB1, the cross-sectional structure schematic diagram along the cutting line CC1, and the cross-sectional structure schematic diagram along the cutting line DD1 show that a dielectric layer 220 is formed on the surface of the first electrode layer 219 and on the vertical side wall surface of the first separation layer 201.

[0088] In some embodiments, dielectric layer 220 is made of a high-K (K greater than 2.8) dielectric material to increase the capacitance per unit area of ​​the capacitor. In specific embodiments, dielectric layer 220 can be a single layer structure formed from one of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO, or a stacked structure formed from two or more of the foregoing materials. In this embodiment, dielectric layer 220 is an HfO2 layer formed by a deposition process.

[0089] refer to Figure 21-22 ,in Figure 22 The four figures in the upper left, upper right, lower left and lower right are Figure 21 The cross-sectional structural diagrams along the cutting line AA1, the cutting line BB1, the cutting line CC1, and the cutting line DD1 show that a second electrode layer 221 is formed on the surface of the dielectric layer 220. The second electrode layer 221 fills the remaining first cavity 218. The formed second electrode layer 221 is integrally connected along the vertical direction and may be separate along the second direction.

[0090] In some embodiments, the second electrode layer 221 fills up the remaining second etched holes 217 , and the formed second electrode layer 221 is integrally connected along the vertical direction and the second direction.

[0091] The second electrode layer 221 can be a single-layer structure formed of one material selected from the group consisting of polysilicon, silicon germanium, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi, or a stacked-layer structure formed of two or more materials selected from the group consisting of the foregoing materials. In this embodiment, the second electrode layer 221 is a TiN layer.

[0092] In some embodiments, the second electrode layer 221 can be formed by chemical vapor deposition, physical vapor deposition, electroplating, or chemical plating.

[0093] The capacitor structure (including the first electrode layer 219, the dielectric layer 220 and the second electrode layer 221) formed by the aforementioned method of the present disclosure, the presence of the first separation layer 201 and the second separation layer 207 increases the surface area of ​​the formed first electrode layer 219, the dielectric layer 220 and the second electrode layer 221, so that under the same storage capacitance, the area occupied by the vertical projection of the formed capacitor on the surface of the semiconductor substrate will be reduced, thereby improving the storage density of the DRAM.

[0094] In some embodiments, reference Figure 23-24 ,in Figure 24 The four figures in the upper left, upper right, lower left and lower right are Figure 23 The cross-sectional structure diagram along the cutting line AA1, the cross-sectional structure diagram along the cutting line BB1, the cross-sectional structure diagram along the cutting line CC1 and the cross-sectional structure diagram along the cutting line DD1, removing the first sacrificial layer 203 in the channel area (reference Figure 12 ) and the second sacrificial layer 205 (reference Figure 12 ), so that the metal oxide semiconductor layer 216 in the channel area is suspended; a selective deposition process is used to form a metal word line 225 extending along the second direction on the surface of each suspended adhesion layer 215; and a bit line 222 is formed to connect the multiple metal oxide semiconductor layers 21 in the vertical direction in the first active area.

[0095] In some embodiments, only the first sacrificial layer 203 and the second sacrificial layer 205 in the channel region may be removed before forming the metal word line 225. In other embodiments, the first sacrificial layer 203 and the second sacrificial layer 205 in the first active region may be removed first to expose the adhesion layer 215 in the first active region; the exposed adhesion layer 215 may then be removed, leaving the adhesion layer 215 in the channel region; the first sacrificial layer 203 and the second sacrificial layer 205 in the channel region may then be removed, and a selective deposition process may be used to form the metal word line 225 extending along the second direction on the surface of the adhesion layer 215 in the channel region.

[0096] The plurality of metal word lines 225 formed extend along the second direction and are separated from each other in the vertical direction. In some embodiments, the adhesion layer 215 is made of TiN and the metal word lines 225 are made of Mo. Mo can be selectively deposited on TiN to form the metal word lines 225 extending in the second direction. The metal word lines 225 are spaced apart from each other in the vertical direction.

[0097] In some embodiments, after the metal word line 225 is formed, a dielectric material is filled in the position where the first sacrificial layer 203 and the second sacrificial layer 205 are removed to form an isolation dielectric layer 224 .

[0098] In some embodiments, the material of the bit line 222 is metal, and the metal can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and WSi.

[0099] Some embodiments of the present disclosure further provide a semiconductor structure, Figure 19 and Figure 24 ,include:

[0100] a semiconductor substrate 200;

[0101] A stacked structure 211 located on a semiconductor substrate 200 includes a plurality of linear patterns 212 extending along a first direction and arranged discretely along a second direction. The linear patterns 212 include first spacer layers 201 and composite layers 202 alternately stacked in a vertical direction. The composite layer 202 in the capacitor region 22 includes semiconductor layers 204 located between adjacent first spacer layers 201 and at least one second spacer layer 207 located between the semiconductor layers 204 and the first spacer layers 201. A first cavity 218 is sandwiched between any two of the semiconductor layers 204, the first spacer layers 201, and the second spacer layers 207.

[0102] a first electrode layer 219 located on the vertical sidewall surfaces of the second separation layer 207 and the semiconductor layer 204 and the inner wall of the first cavity 218;

[0103] a dielectric layer 220 located on the surface of the first electrode layer 219 and on the vertical sidewall surfaces of the first separation layer 201;

[0104] The second electrode layer 221 is located on the surface of the dielectric layer 220 and fills the first cavity.

[0105] In some embodiments, vertical sidewall surfaces of the first spacer layer 201 protrude beyond vertical sidewall surfaces of the semiconductor layer 204 and the second spacer layer 207 along the first direction.

[0106] In some embodiments, there is at least one second spacer layer 207 vertically arranged between the semiconductor layer 204 and the first spacer layer 201 above, or there is at least one second spacer layer 207 vertically arranged between the semiconductor layer 204 and the first spacer layer 201 below.

[0107] In some embodiments, at least one second spacer layer 207 is vertically arranged between the semiconductor layer 204 and the upper and lower first spacer layers 201 .

[0108] In some embodiments, the semiconductor structure includes a transistor region 21 adjacent to a capacitor region 22 along a first direction. The transistor region 21 includes a first active region, a channel region, and a second active region sequentially arranged along the first direction. The structure also includes: a wordline structure extending along a second direction on the surface of each semiconductor layer (metal oxide semiconductor layer 216) in the channel region; the wordline structure includes a wordline dielectric layer and a metal wordline 225 located on the wordline dielectric layer; and a bitline 222 connecting the multiple semiconductor layers (metal oxide semiconductor layer 216) in a vertical direction in the first active region. In the direction from the transistor region 21 toward the capacitor region 22, the vertical sidewall surfaces of the first spacer layer 201 protrude in the first direction beyond the vertical sidewall surfaces of the semiconductor layer 204 and the second spacer layer 207.

[0109] In some embodiments, the second spacer layer 207 extends along the first direction and intersects both the transistor region 21 and the capacitor region 22 .

[0110] It should be noted that the definitions or descriptions of the same or similar parts in some embodiments of the aforementioned semiconductor structure and some embodiments of the aforementioned semiconductor structure forming method will not be repeated here. Please refer to the definitions or descriptions of the corresponding parts in some embodiments of the aforementioned semiconductor structure forming method for details.

[0111] Although the present disclosure has been disclosed as above in terms of preferred embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present disclosure by using the methods and technical contents disclosed above without departing from the spirit and scope of the present disclosure. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solutions of the present disclosure shall fall within the scope of protection of the technical solutions of the present disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a semiconductor substrate; forming a stacked structure on the semiconductor substrate, the stacked structure comprising a plurality of linear patterns extending along a first direction and discretely arranged along a second direction, the linear patterns comprising first separation layers and composite layers alternately stacked along a vertical direction, the composite layer comprising a first sacrificial layer, a semiconductor layer, and a second sacrificial layer sequentially stacked along the vertical direction, the composite layer further comprising at least one second separation layer located in the first sacrificial layer and / or the second sacrificial layer; removing the first sacrificial layer and the second sacrificial layer in the capacitor region of the stacked structure to form a first cavity; forming a first electrode layer on the vertical sidewall surfaces of the second separation layer and the semiconductor layer and the inner wall of the first cavity; forming a dielectric layer on a surface of the first electrode layer and on vertical sidewall surfaces of the first separation layer; A second electrode layer is formed on the surface of the dielectric layer, and the second electrode layer fills the remaining first cavity.

2. The method for forming a semiconductor structure according to claim 1, wherein: The stacking structure forming process comprises: forming an initial stacking structure on the semiconductor substrate, the initial stacking structure comprising an initial first separation layer and an initial composite layer alternately stacked in a vertical direction, the initial composite layer comprising an initial first sacrificial layer, an initial semiconductor layer, and an initial second sacrificial layer sequentially stacked in a vertical direction, the initial composite layer further comprising at least one initial second separation layer located in the initial first sacrificial layer and / or the initial second sacrificial layer; forming a plurality of grooves extending along a first direction and penetrating the initial stacking structure in a vertical direction in the initial stacking structure, so as to form the linear pattern between adjacent grooves; A first isolation layer is filled in the trench located in the capacitor region, and a second isolation layer is filled in the trench located in the transistor region.

3. The method for forming a semiconductor structure according to claim 1, wherein: Before removing the first sacrificial layer and the second sacrificial layer located in the capacitor area in the stacked structure, it also includes: removing a partial length of the semiconductor layer and the second separation layer located in the capacitor area along the first direction, so that the vertical side wall surface of the first separation layer protrudes from the vertical side wall surfaces of the remaining semiconductor layer and the second separation layer along the first direction.

4. The method for forming a semiconductor structure according to claim 3, wherein: The lengths of the first sacrificial layer and the second sacrificial layer removed along the first direction are greater than the lengths of the semiconductor layer and the second separation layer removed along the first direction.

5. The method for forming a semiconductor structure according to claim 3, wherein: The first cavity exposes the upper and lower surfaces of the first separator layer, the remaining semiconductor layer, and the second separator layer in the capacitor region, and the forming process of the first electrode layer includes: forming a first electrode material layer on the vertical sidewall surfaces of the first separator layer, the second separator layer, and the semiconductor layer and on the inner wall of the first cavity; A portion of the first electrode material layer located on the vertical sidewall surface of the first separation layer is removed to form a plurality of first electrode layers.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process of removing a portion of the first electrode material layer located on the vertical sidewall surface of the first separator layer to form a plurality of first electrode layers includes: forming a first filling material layer on the surface of the first electrode material layer to fill the first cavity; removing a portion of the first filling material layer to expose the first electrode material layer located on the vertical sidewall surface of the first separation layer; The exposed first electrode material layer is removed.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the semiconductor layer is polycrystalline silicon. After forming a stacked structure on the semiconductor substrate, the method further includes: removing the semiconductor layer located in the transistor area to form a second cavity; and sequentially forming a word line dielectric layer and a metal oxide semiconductor layer located on the surface of the word line dielectric layer and filling the second cavity in the second cavity.

8. The method for forming a semiconductor structure according to claim 7, wherein: Before forming the word line dielectric layer, the method further includes: forming an adhesion layer on the inner wall of the second cavity, wherein the word line dielectric layer is formed on the inner wall of the adhesion layer; After forming the metal oxide semiconductor layer, the method further includes removing a portion of the adhesion layer in the transistor region near the capacitor region.

9. The method for forming a semiconductor structure according to claim 8, wherein: The transistor region includes a first active region, a channel region, and a second active region sequentially arranged along a first direction; the first sacrificial layer and the second sacrificial layer in the channel region are removed, so that the metal oxide semiconductor layer in the channel region is suspended; A selective deposition process is adopted to form a metal word line extending along the second direction on the surface of each suspended adhesion layer; and a bit line is formed to connect the vertical multi-layer metal oxide semiconductor layers in the first active area.

10. A semiconductor structure, characterized in that include: semiconductor substrates; a stacked structure located on the semiconductor substrate, the stacked structure comprising a plurality of linear patterns extending along a first direction and discretely arranged along a second direction, the linear patterns comprising first spacer layers and composite layers alternately stacked along a vertical direction, the composite layer in the capacitor region comprising a semiconductor layer located between adjacent first spacer layers and at least one second spacer layer located between the semiconductor layer and the first spacer layer, a first cavity being sandwiched between any two of the semiconductor layer, the first spacer layer, and the second spacer layer; a first electrode layer located on the vertical sidewall surfaces of the second separation layer and the semiconductor layer and the inner wall of the first cavity; a dielectric layer located on a surface of the first electrode layer and on vertical sidewall surfaces of the first separator layer; A second electrode layer is located on the surface of the dielectric layer and fills the first cavity.

11. The semiconductor structure according to claim 10, wherein: The vertical sidewall surfaces of the first spacer layer protrude from the vertical sidewall surfaces of the semiconductor layer and the second spacer layer along the first direction.

12. The semiconductor structure according to claim 10, wherein: There is at least one second separation layer arranged vertically between the semiconductor layer and the first separation layer above, or there is at least one second separation layer arranged vertically between the semiconductor layer and the second separation layer below.

13. The semiconductor structure according to claim 10, wherein: At least one second separation layer is arranged vertically between the semiconductor layer and the first separation layer above and below.

14. The semiconductor structure according to claim 10, wherein: The semiconductor structure includes a transistor region adjacent to the capacitor region along a first direction, the transistor region including a first active region, a channel region, and a second active region arranged in sequence along the first direction; and further includes: a word line structure extending along a second direction on the surface of each semiconductor layer located in the channel region; and a bit line connecting the multiple semiconductor layers in the vertical direction in the first active region.

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