Semiconductor structure and preparation method thereof

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof, wherein the semiconductor structure includes a substrate, a capacitor unit group, and a stress buffer layer. The capacitor unit group is located on the top surface of the substrate, and the capacitor unit group includes a plurality of capacitor columns arranged in an array along a first direction and a second direction, and the capacitor columns extend along a third direction; the stress buffer layer is located on the top surface of the substrate, extends along the third direction, and circumferentially surrounds the capacitor unit group, wherein the first direction, the second direction, and the third direction are perpendicular to each other. The above-mentioned semiconductor structure can reduce the stress impact on the capacitor unit group, thereby improving the bending deformation of the capacitor column caused by the stress impact, thereby avoiding the risk of circuit leakage, capacitor short circuit, capacitor internal insulation medium failure or electrode damage, improving the quality of the capacitor, and thus improving the overall performance of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that typically consists of capacitors and transistors. The capacitors store data, while the transistors control access to the data stored in the capacitors. Therefore, capacitance is a key factor affecting the overall performance of DRAM integrated circuits.

[0003] With the development of semiconductor technology, the aspect ratio of capacitors continues to increase. However, capacitors are easily damaged during the manufacturing process, which can cause DRAM integrated circuit failure. Therefore, there is an urgent need to provide a semiconductor structure to improve capacitor quality and optimize overall memory performance. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure and a method for preparing the same, which can improve the quality of capacitors, reduce damage, and thus improve the overall performance of the semiconductor.

[0005] According to various embodiments of the present disclosure, a semiconductor structure is provided, comprising: a substrate, a capacitor unit group, and a stress buffer layer. The capacitor unit group is located on a top surface of the substrate and includes a plurality of capacitor columns arranged in an array spaced apart along a first direction and a second direction, with the capacitor columns extending along a third direction. The stress buffer layer is located on a top surface of the substrate, extends along the third direction, and circumferentially surrounds the capacitor unit group, wherein the first direction, the second direction, and the third direction are mutually perpendicular.

[0006] In the semiconductor structure of the above embodiment, a stress buffer layer is arranged around the circumferential position of the capacitor unit group, and the part of the capacitor unit group exposed to the outside during the device manufacturing process is wrapped up, so that it uses the stress buffer layer as a protective layer, which can reduce the damage to the capacitor unit group caused by the surrounding stress or other impact forces. Therefore, the stress buffer layer is arranged around the capacitor unit group, which can reduce the stress impact on the capacitor unit group. The stress buffer layer serves as an intermediate buffer zone for the transmission of external stress to the capacitor unit group, which can reduce the force of the stress at the boundary of the capacitor unit group to the capacitor column inside the capacitor unit group, thereby improving the bending deformation of the capacitor column caused by stress impact, thereby avoiding the risk of circuit leakage, capacitor short circuit, failure of the internal insulation medium of the capacitor or electrode damage, improving the quality of the capacitor, and thus improving the overall performance of the memory.

[0007] In some embodiments, an orthographic projection of the stress buffer layer on the top surface of the substrate encloses a target region, and the capacitor unit group is located in the target region.

[0008] In some embodiments, an orthographic projection of the stress buffer layer on the top surface of the substrate is a continuous closed shape.

[0009] In some embodiments, the orthographic projection of the stress buffer layer on the top surface of the substrate is a plurality of spaced-apart sub-patterns, and the sub-patterns are rectangular or have corners.

[0010] In some embodiments, the length of a rectangle extending along a first direction in the first direction is equal to the spacing between adjacent rectangles extending along the first direction; the difference between the length of a rectangle extending along a second direction in the second direction and the spacing between adjacent rectangles extending along the second direction is equal to the graphic size of the positive projection of the capacitor column on the top surface of the substrate.

[0011] In some embodiments, the semiconductor structure further includes an air gap structure located within the stress buffer layer and located on a side away from the capacitor unit group along the first direction.

[0012] In some embodiments, the material of the stress buffer layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, and combinations thereof.

[0013] In some embodiments, the semiconductor structure further includes a first supporting layer, a second supporting layer, and a spacer layer. The first supporting layer is at least partially located between adjacent capacitor pillars along the first direction and near the middle of the capacitor pillars along the third direction. The second supporting layer is at least partially located between adjacent capacitor pillars along the first direction and located on a side of the first supporting layer away from the substrate along the third direction. Both the first supporting layer and the second supporting layer extend along the first direction. The spacer layer at least fills the gaps between adjacent capacitor pillars.

[0014] In some embodiments, the capacitor column includes a second electrode layer, a first electrode layer, and a dielectric layer. The second electrode layer is located on the top surface of the substrate and extends along the third direction. The first electrode layer covers the outer sidewalls and bottom surface of the second electrode layer. The dielectric layer is located between the first and second electrode layers.

[0015] In some embodiments, the material of the first electrode layer is selected from polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, and combinations thereof.

[0016] In some embodiments, the material of the second electrode layer is selected from polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, and combinations thereof.

[0017] In some embodiments, the material of the dielectric layer is selected from nitride, metal oxide, and combinations thereof.

[0018] In some embodiments, an active area defined by a trench isolation structure is formed in the substrate, and the multiple active areas are arranged in an array along the first direction and the second direction, and the multiple active areas are located on the side of the capacitor unit group close to the substrate along the third direction; the semiconductor structure also includes a metal conductive layer and a word line structure; wherein the metal conductive layer is located in the substrate, extends along the first direction, and is located between the capacitor unit group and the active area; the word line structure is located in the active area and on the side of the metal conductive layer away from the capacitor unit group along the third direction.

[0019] According to some embodiments of the present disclosure, another aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps: providing a substrate; forming an intermediate unit group on the top surface of the substrate, the intermediate unit group comprising a plurality of capacitor trenches arranged in an array along a first direction and a second direction, and a first electrode layer located on the bottom surface and sidewall of the capacitor trench; the capacitor trench extends along a third direction; forming a stress buffer layer on the top surface of the substrate, the stress buffer layer extends along the third direction and circumferentially surrounds the intermediate unit group, wherein the first direction, the second direction and the third direction are perpendicular to each other; forming a dielectric layer and a second electrode layer in sequence in the capacitor trench to form a capacitor unit group, the dielectric layer conformally covering the first electrode layer, the second electrode layer, the dielectric layer and the first electrode layer together fill the capacitor trench and constitute a capacitor column, and the capacitor unit group comprises a plurality of capacitor columns.

[0020] In the method for preparing the semiconductor structure in the above embodiment, after forming an intermediate unit group having a capacitor groove and a first electrode layer, a circle of stress buffer layer is formed around the circumferential position of the intermediate unit group, and then, a dielectric layer and a second electrode layer are sequentially formed in the capacitor groove to form a capacitor unit group, so that the portion of the capacitor unit group exposed to the periphery is protected by the stress buffer layer, reducing the stress shock or other shock it is subjected to, improving the phenomenon of bending and deformation of the capacitor column in the capacitor unit group, thereby improving the overall quality of the capacitor column. In addition, since the stress buffer layer in the present disclosure is formed before the capacitor column is formed, the stress buffer layer can also protect the capacitor column during the capacitor column manufacturing process, prevent external force impacts caused by various acid solutions on the capacitor unit group area, increase the stability of the capacitor unit group, further improve the deformation problem of the capacitor column, thereby improving the quality of the capacitor, and improving the stability and yield of the device.

[0021] In some embodiments, an orthographic projection of the stress buffer layer on the top surface of the substrate is a continuous closed shape.

[0022] In some embodiments, the orthographic projection of the stress buffer layer on the top surface of the substrate is a plurality of spaced-apart sub-patterns, and the sub-patterns are rectangular or have corners.

[0023] In some embodiments, the step of forming a stress buffer layer on the top surface of the substrate includes: forming the stress buffer layer including an air gap structure by physical vapor deposition and / or chemical vapor deposition.

[0024] In some embodiments, the material of the stress buffer layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, and combinations thereof.

[0025] In some embodiments, the step of forming a stress buffer layer on the top surface of the substrate includes: forming a hard mask layer and a patterned photoresist layer in the capacitor trench and on the top surface of the substrate; etching the substrate using the patterned photoresist layer as a mask to form the stress buffer layer; and removing the patterned photoresist layer.

[0026] In some embodiments, the hard mask layer includes a sacrificial layer and an anti-reflective layer, the sacrificial layer fills the capacitor trench and covers the top surface of the substrate, and the anti-reflective layer covers the top surface of the sacrificial layer; the patterned photoresist layer is located on the top surface of the anti-reflective layer and has an opening, and the opening defines the size of the stress buffer layer.

[0027] In some embodiments, the material of the sacrificial layer is selected from a carbon layer, an oxide layer, a nitride layer, and combinations thereof.

[0028] In some embodiments, the material of the anti-reflection layer includes silicon oxynitride or other nitrogen-containing compounds.

[0029] In some embodiments, a first dielectric layer, a first supporting layer, a second dielectric layer, and a second supporting layer are stacked in sequence along a third direction on the top surface of the substrate, and the first dielectric layer is adjacent to the substrate. After the step of forming a stress buffer layer on the top surface of the substrate and before the step of sequentially forming a dielectric layer and a second electrode layer in the capacitor trench, the process further includes: removing the first dielectric layer and the second dielectric layer, and removing the first supporting layer and the second supporting layer surrounding the stress buffer layer.

[0030] In some embodiments, the materials of the first supporting layer and the second supporting layer are selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, and combinations thereof.

[0031] In some embodiments, after sequentially forming the dielectric layer and the second electrode layer in the capacitor trench, the method further includes forming a continuous protective cap layer on the top surface of the capacitor unit group and the surface of the stress buffer layer away from the capacitor unit group. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1a Shown is a schematic top view of a semiconductor structure provided in one embodiment of the present disclosure;

[0034] Figure 1b 、 Figure 1c 、 Figure 2 、 Figure 6 、 Figure 24a 、 Figure 24b 、 Figure 25a Schematic diagrams of cross-sectional structures of semiconductor structures provided in different embodiments of the present disclosure are respectively shown;

[0035] Figure 3-Figure 5 Schematic diagrams of top views of semiconductor structures provided in different embodiments of the present disclosure are respectively shown;

[0036] Figure 7 、 Figure 13 Schematic diagrams showing the flow of semiconductor structure preparation methods provided in different embodiments of the present disclosure;

[0037] Figures 8-12 、 Figure 14-Figure 23 Schematic diagrams of cross-sectional structures of structures obtained in different steps of the method for preparing a semiconductor structure provided in different embodiments of the present disclosure are respectively shown;

[0038] Figure 25b A table schematically showing the relationship between a stress drop ratio and a capacitor column type provided in an embodiment of the present disclosure;

[0039] Figure 25c A curve diagram showing the relationship between a stress drop ratio and capacitor column type provided in an embodiment of the present disclosure is shown.

[0040] Description of reference numerals:

[0041] 10. Base; 11. Capacitor group; 12. Support structure; 20. Substrate; 201. Trench isolation structure; 202. Active area; 203. Metal conductive layer; 204. Word line structure; 205. Capacitor plug; 21. First dielectric layer; 22. First support layer; 23. Second dielectric layer; 24. Second support layer; 241. Sub-support layer; 25. First mask layer; 26. Second mask layer; 27. Third mask layer; 28. Capacitor trench Groove; 29, capacitor column; 291, first electrode layer; 292, second electrode layer; 30, capacitor unit group; 31, hard mask layer; 311, sacrificial layer; 312, anti-reflective layer; 32, patterned photoresist layer; 33, stress buffer groove; 34, stress buffer layer; 341, target area; 35, fourth mask layer; 36, fifth mask layer; 37, sixth mask layer; 38, protective cover layer; 39, air gap structure; 40, spacer layer. DETAILED DESCRIPTION

[0042] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0044] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0045] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0046] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0048] Memory is a storage component used to store programs and various data. It can be categorized by usage type into ROM (Read-Only Memory) and RAM (Random Access Memory). Based on the operating principles of the memory cells, random access memory is divided into SRAM (Static RAM) and DRAM. Compared to SRAM, DRAM offers advantages such as high integration, low power consumption, and low price, making it widely used in large-capacity memory. The basic storage cell in DRAM consists of two components: a transistor and a capacitor. The transistor is used to charge and discharge the capacitor, both of which are accomplished through word lines and bit lines. Since the capacitor stores data and the transistor controls access to the data stored in the capacitor, capacitance is a key factor affecting the overall performance of DRAM integrated circuits.

[0049] See also Figure 1a 、 Figure 1b and Figure 1c With the high integration of semiconductors and the evolution of Moore's Law to the 1xnm level (between 10nm and 20nm), the active area is required to be arranged more densely and the aspect ratio of capacitors is also increasing. However, due to the poor bending resistance of capacitors, the deformation caused by various impact forces during the production and assembly process may cause the capacitors to crack. After the capacitors crack, there is a high possibility of short circuit, which leads to device failure. Figure 1a It is a top view schematic diagram of the capacitor group 11. The capacitor group 11 is composed of a plurality of capacitor columns arranged along a first direction (for example, the ox direction) and a second direction (for example, the oz direction). In the present disclosure, based on the analysis of PFA (Predictive Failure Analysis) and a number of simulation data, it is found that there is a strong stress attack on the array boundary of the capacitor group 11. The capacitor group 11 includes a plurality of capacitor columns extending along a third direction (for example, the oy direction). The stress attack will be transmitted to the capacitor group 11 located on the top surface of the substrate 10, and from the capacitor located at the boundary of the capacitor group 11 to the internal capacitor until the stress release is completed. This causes the capacitor columns on the upper part of the support structure 12 in the capacitor group 11 and the capacitor columns on the lower part of the support structure 12 to bend. The closer to the boundary of the capacitor group 11, the greater the stress impact and the greater the degree of capacitor deformation. Specifically, the support structure 12 close to the boundary of the capacitor group 11 is subjected to the strongest stress impact, and the stress gradually diffuses and conducts with this point as the center of the circle. Figure 1c The maximum stress value is 5.600e+05. This stress impact will cause the overall quality of the capacitor bank 11 to deteriorate and even cause a short circuit risk.

[0050] Based on the above technical problems, the present disclosure provides a semiconductor structure and a preparation method thereof, which can improve the quality of capacitors and reduce capacitor damage, thereby improving the yield and overall performance of the semiconductor structure.

[0051] As an example, in the embodiment of the present disclosure, the first direction may be the ox direction, the second direction may be the oz direction, and the third direction may be the oy direction.

[0052] As an example, see Figure 2 The present disclosure provides a semiconductor structure, comprising: a substrate 20, a capacitor unit group 30 (see Figure 3-Figure 5) and a stress buffer layer 34. The capacitor unit group 30 is located on the top surface of the substrate 20 and includes a plurality of capacitor columns 29 arranged in an array along a first direction (e.g., the ox direction) and a second direction (e.g., the oz direction). The capacitor columns 29 extend along a third direction (e.g., the oy direction). The stress buffer layer 34 is located on the top surface of the substrate 20, extends along the third direction (e.g., the oy direction), and circumferentially surrounds the capacitor unit group 30. The first direction (e.g., the ox direction), the second direction (e.g., the oz direction), and the third direction (e.g., the oy direction) are perpendicular to each other.

[0053] In the semiconductor structure of the above embodiment, a stress buffer layer 34 is provided around the circumference of the capacitor unit group 30 to wrap the portion of the capacitor unit group 30 exposed to the outside during the device manufacturing process, so that the stress buffer layer 34 serves as a protective layer, which can reduce the damage to the capacitor unit group 30 caused by the surrounding stress or other impact forces. Therefore, by providing a stress buffer layer 34 around the capacitor unit group 30, the stress impact on the capacitor unit group 30 can be reduced. The stress buffer layer 34 acts as an intermediate buffer zone for the transmission of external stress to the capacitor unit group 30, which can reduce the stress at the boundary of the capacitor unit group 30 from being transmitted to the capacitor column 29 inside the capacitor unit group 30, thereby improving the bending deformation of the capacitor column 29 caused by the stress impact, thereby avoiding the risk of circuit leakage, capacitor short circuit, failure of the internal insulation medium of the capacitor or damage to the electrode, improving the quality of the capacitor, and thus improving the yield and overall performance of the memory.

[0054] As an example, the substrate 20 can be made of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 20 can be a single-layer structure or a multi-layer structure. For example, the substrate 20 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 20 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Those skilled in the art can select the type of substrate 20 according to the type of transistor formed on the substrate 20, so the type of substrate 20 should not limit the scope of protection of this application.

[0055] As an example, see Figure 2The semiconductor structure further includes a first support layer 22, a second support layer 24, and a spacer layer 40. The first support layer 22 is at least partially located between adjacent capacitor pillars 29 along a first direction (e.g., the ox direction) and is close to the middle of the capacitor pillars 29 along a third direction (e.g., the oy direction). The second support layer 24 is at least partially located between adjacent capacitor pillars 29 along the first direction (e.g., the ox direction) and is located on a side of the first support layer 22 away from the substrate 20 along the third direction (e.g., the oy direction). Both the first support layer 22 and the second support layer 24 extend along the first direction (e.g., the ox direction). The spacer layer 40 at least fills the gaps between adjacent capacitor pillars 29. A first dielectric layer 21 is formed between the substrate 20 and the first support layer 22, and a second dielectric layer 23 is formed between the first support layer 22 and the second dielectric layer 23.

[0056] As an example, see Figure 2 The capacitor column 29 includes a second electrode layer 292, a first electrode layer 291, and a dielectric layer (not shown). The second electrode layer 292 is located on the top surface of the substrate 20 and extends along a third direction (e.g., the oy direction). The first electrode layer 291 covers the outer sidewalls and bottom surface of the second electrode layer 292. The dielectric layer is located between the first electrode layer 291 and the second electrode layer 292. The first electrode layer 291 and the second electrode layer 292 serve as the two electrodes of the capacitor column 29, and the dielectric layer serves as an insulating isolation structure between the first electrode layer 291 and the second electrode layer 292.

[0057] As an example, see Figure 2 An active area 202 defined by a trench isolation structure 201 is formed within the substrate 20. Multiple active areas 202 are arranged in an array along a first direction (e.g., the ox direction) and a second direction (e.g., the oz direction), and are located on a side of the capacitor unit group 30 that is closer to the substrate 20 along a third direction (e.g., the oy direction). The semiconductor structure further includes a metal conductive layer 203 and a wordline structure 204. The metal conductive layer 203 is located within the substrate 20, extends along the first direction (e.g., the ox direction), and is located between the capacitor unit group 30 and the active area 202. The wordline structure 204 is located within the active area 202 and on a side of the metal conductive layer 203 that is farther away from the capacitor unit group 30 along the third direction (e.g., the oy direction). A capacitor plug 205 is also formed between the active area 202 and the metal conductive layer 203. Insulation structures are also formed between adjacent metal conductive layers 203 and on top of the wordline structures 204.

[0058] It should be noted that, in other embodiments, the word line structure 204 and the metal conductive layer 203 in the substrate 20 may also be arranged in other ways, and the specific arrangement does not limit the protection scope of the present disclosure.

[0059] As an example, see Figure 3-Figure 5 The orthographic projection of the stress buffer layer 34 on the top surface of the substrate 20 encloses a target area 341, and the capacitor unit group 30 is located in the target area 341, that is, the stress buffer layer 34 completely surrounds the sidewalls of the capacitor unit group 30 and protects it to resist the tilting of the capacitor unit group 30 due to stress concentration.

[0060] As an example, see Figure 3 The positive projection of the stress buffer layer 34 on the top surface of the substrate 20 is a continuous closed figure, that is, the stress buffer layer 34 completely wraps the exposed side wall of the capacitor column 29, and has a strong protective effect on the capacitor unit group 30, serving as a stress buffer zone for the entire capacitor unit group 30 to alleviate stress impact.

[0061] As an example, see Figure 4 and Figure 5 The stress buffer layer 34 has a positive projection on the top surface of the substrate 20 as a plurality of spaced sub-patterns, which are rectangular or have corners, so as to save material while buffering the stress impact on the capacitor unit group 30.

[0062] As an example, see Figure 4 and Figure 5 The length x1 of the rectangle extending along the first direction in the first direction is equal to the spacing x2 between the adjacent rectangles extending along the first direction; the length y1 of the rectangle extending along the second direction in the second direction, and the spacing y2 between the adjacent rectangles extending along the second direction, are equal to the graphic size d of the positive projection of the capacitor column 29 on the top surface of the substrate 20.

[0063] As an example, see Figure 4 and Figure 5 , the length x1 of the rectangle extending along the first direction (for example, the ox direction) in the first direction (for example, the ox direction) is (d+s1), and the length y1 of the rectangle extending along the second direction (for example, the oz direction) in the second direction (for example, the oz direction) is (d+s2); wherein, d is the graphic size of the positive projection of the capacitor column 29 on the top surface of the substrate 20, s1 is the spacing between adjacent capacitor columns 29 along the first direction (for example, the ox direction), and s2 is the spacing between adjacent capacitor columns 29 along the second direction (for example, the oz direction).

[0064] As an example, see Figure 4 and Figure 5 The spacing x2 between adjacent rectangles extending along the first direction (for example, the ox direction) is (d+s1), and the spacing y2 between adjacent rectangles extending along the second direction (for example, the oz direction) is s2.

[0065] The size and spacing of the above-mentioned rectangles can ensure stable relief of stress impact when the capacitor columns 29 are most densely packed, so as to improve the bending condition of the capacitor columns 29. Because in the relevant process, in the preparation process of the capacitor group, multiple capacitor holes generally share a grid support hole, for example, four capacitor columns 29 share a support hole, resulting in concentrated stress at the edge of the capacitor unit group 30 during the step of wet etching to remove the sacrificial layer, so that the entire capacitor column tilts or even tends to collapse. When different rectangular spacing sizes are set in the first direction (for example, the ox direction) and the second direction (for example, the oz direction), it can be ensured that when the sacrificial layer is removed by wet etching, stress concentration will not be generated at the edge, thereby avoiding the tilt of the capacitor column 29, thereby improving the preparation yield.

[0066] As an example, see Figure 5 For example, since four capacitor columns 29 share one support hole during the preparation process, that is, the first support layer 22 and the second support layer 24 include multiple sub-support layers, specifically, the second support layer 24 may include multiple sub-support layers 241, and each sub-support layer 241 supports four adjacent capacitor columns 29. Then, the longest diameter of the multiple capacitor hole openings exposed in one sub-support layer 241 is (d+s2), and the spacing x2 of the rectangles extending along the first direction (for example, ox direction) adjacent to each other and the spacing y2 of the rectangles extending along the second direction (for example, oz direction) adjacent to each other and the second direction (for example, oz direction) are both smaller than the longest diameter of the opening of one sub-support layer 241, thereby ensuring that during wet etching, the stress buffer layer 34 supports the capacitor column 29, and the capacitor column 295 will not bend or tilt under the influence of stress concentration.

[0067] As an example, the graphic size d of the orthographic projection of the capacitor column 29 on the top surface of the substrate 20 is in the range of [10nm, 30nm]; the spacing s1 of the capacitor columns 29 adjacent along the first direction (for example, the ox direction) is 1 / 2 of the graphic size d of the orthographic projection of the capacitor column 29 on the top surface of the substrate 20, and the size range is [5nm, 15nm]; the spacing s2 of the capacitor columns 29 adjacent along the second direction (for example, the oz direction) is 1.2 times the graphic size d of the orthographic projection of the capacitor column 29 on the top surface of the substrate 20, and the size range is [12nm, 36nm]. Specifically, the graphic size d of the positive projection of the capacitor column 29 on the top surface of the substrate 20 can be 10nm, 15nm, 20nm, 25nm or 30nm, etc.; the spacing s1 of the capacitor columns 29 adjacent along the first direction (for example, the ox direction) can be 5nm, 8nm, 10nm, 12nm or 15nm, etc.; the spacing s2 of the capacitor columns 29 adjacent along the second direction (for example, the oz direction) can be 12nm, 15nm, 20nm, 25nm, 30nm or 36nm, etc.

[0068] As an example, see Figure 6 The semiconductor structure further includes an air gap structure 39, which is located within the stress buffer layer 34 and on a side away from the capacitor unit group 30 along the first direction (e.g., the ox direction) to prevent leakage of the conductive material in the capacitor column 29. The gas filled in the air gap structure 39 can be any insulating gas. The air gap structure 39 can replace the material of the stress buffer layer 34 as a stress buffer structure, weakening the conduction of stress impact, further relieving stress, improving the bending problem of the capacitor column 29, improving the quality of the capacitor column 29, and avoiding the occurrence of short circuits.

[0069] As an example, the material of the stress buffer layer 34 is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and combinations thereof. In other embodiments, the material of the stress buffer layer 34 may also be other tensile stress materials to reduce the impact of stress on the capacitor unit group 30. In this embodiment, the material of the stress buffer layer 34 is silicon nitride.

[0070] As an example, the material of the first electrode layer 291 is selected from polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, and combinations thereof. In this embodiment, the material of the first electrode layer 291 is titanium nitride.

[0071] As an example, the material of the second electrode layer 292 is selected from polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, and combinations thereof. In this embodiment, the material of the second electrode layer 292 is tungsten.

[0072] As an example, the material of the dielectric layer is selected from nitride, metal oxide and a combination thereof. The dielectric layer may also be made of any other high dielectric constant (High-k) material to insulate and isolate the first electrode layer 291 and the second electrode layer 292 .

[0073] As an example, the material of the first supporting layer 22 and the second supporting layer 24 is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof. In this embodiment, the material of the first supporting layer 22 and the second supporting layer 24 is silicon oxide.

[0074] As an example, see Figure 7 In another aspect, the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps:

[0075] Step S2: providing a substrate;

[0076] Step S4: forming an intermediate unit group on the top surface of the substrate, the intermediate unit group comprising a plurality of capacitor trenches arranged in an array along a first direction (e.g., the ox direction) and a second direction (e.g., the oz direction), and a first electrode layer located on the bottom surface and sidewalls of the capacitor trenches; the capacitor trenches extend along a third direction (e.g., the oy direction);

[0077] Step S6: forming a stress buffer layer on the top surface of the substrate, wherein the stress buffer layer extends along a third direction (e.g., the oy direction) and circumferentially surrounds the intermediate unit group, wherein the first direction (e.g., the ox direction), the second direction (e.g., the oz direction), and the third direction (e.g., the oy direction) are perpendicular to each other;

[0078] Step S8: A dielectric layer and a second electrode layer are sequentially formed in the capacitor trench to form a capacitor unit group. The dielectric layer conformally covers the first electrode layer. The second electrode layer, the dielectric layer and the first electrode layer together fill the capacitor trench and constitute a capacitor column. The capacitor unit group includes a plurality of capacitor columns.

[0079] In step S2, see Figure 7 Step S2 and Figure 8 A substrate 20 is provided. The substrate 20 includes an active area 202 defined by a trench isolation structure 201. The active areas 202 are arranged in an array along a first direction (e.g., the ox direction) and a second direction (e.g., the oz direction). The active areas 202 are located on a side of the capacitor unit group 30 that is closer to the substrate 20 along a third direction (e.g., the oy direction). The semiconductor structure further includes a metal conductive layer 203 and a word line structure 204. The metal conductive layer 203 is located within the substrate 20, extends along the first direction (e.g., the ox direction), and is located between the capacitor unit group 30 and the active area 202. The word line structure 204 is located within the active area 202 and on a side of the metal conductive layer 203 that is farther from the capacitor unit group 30 along the third direction (e.g., the oy direction). The substrate 20 is formed with a first dielectric layer 21, a first supporting layer 22, a second dielectric layer 23, a second supporting layer 24, a first mask layer 25, a second mask layer 26, and a third mask layer 27 stacked in sequence from bottom to top.

[0080] As an example, the material of the first supporting layer 22 and the second supporting layer 24 is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof. In this embodiment, the material of the first supporting layer 22 and the second supporting layer 24 is silicon oxide.

[0081] As an example, the materials of the first dielectric layer 21 and the second dielectric layer 23 are selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, and combinations thereof.

[0082] In step S4, see Figure 7 Step S4 in Figures 8-12The step of forming an intermediate unit group on the top surface of the substrate includes:

[0083] Step S41: forming a capacitor trench on the top surface of the substrate;

[0084] Step S42 : forming a first electrode layer on the bottom surface and sidewalls of the capacitor trench, wherein the capacitor trench and the first electrode layer therein together constitute an intermediate unit group.

[0085] For details, please refer to Figures 8-12 , first of all, in Figure 8 In the process, the third mask layer 27 is used as a mask to etch the second mask layer 26 to form a plurality of trench structures penetrating from top to bottom in the second mask layer 26. Figure 9 In the process, the third mask layer 27 is removed, and the first mask layer 25 is etched using the etched second mask layer 26 as a mask to form a plurality of trench structures penetrating from top to bottom in the first mask layer 25. Figure 10 In the process, the second mask layer 26 is removed, and the second support layer 24, the second dielectric layer 23, the first support layer 22 and the first dielectric layer 21 are etched using the etched first mask layer 25 as a mask to form a plurality of capacitor trenches 28 that penetrate the second support layer 24, the second dielectric layer 23, the first support layer 22 and the first dielectric layer 21 from top to bottom. Figure 11 In the process, the first mask layer 25 is removed. Figure 12 In the embodiment, the bottom surface and sidewall of the capacitor trench 28 are covered with the first electrode layer 291 , and a plurality of capacitor trenches 28 and the first electrode layer 291 therein together constitute an intermediate unit group.

[0086] As an example, the material of the first mask layer 25 may include but is not limited to polysilicon, the material of the second mask layer 26 may include but is not limited to silicon dioxide, and the material of the third mask layer 27 may include but is not limited to a carbon layer, an oxide layer, a nitride layer, and combinations thereof.

[0087] As an example, see Figure 13 The step of forming a stress buffer layer on the top surface of the substrate in step S6 includes the following steps:

[0088] Step S61: forming a hard mask layer and a patterned photoresist layer in the capacitor trench and on the top surface of the substrate;

[0089] Step S62: using the patterned photoresist layer as a mask, etching the substrate to form a stress buffer layer;

[0090] Step S63: removing the patterned photoresist layer.

[0091] In step S61, refer to Figure 13 Step S61 in Figure 14A hard mask layer 31 and a patterned photoresist layer 32 are formed in the capacitor trench 28 and on the top surface of the substrate 20; the hard mask layer 31 includes a sacrificial layer 311 and an anti-reflective layer 312, the sacrificial layer 311 fills the capacitor trench 28 and covers the top surface of the substrate 20, and the anti-reflective layer 312 covers the top surface of the sacrificial layer 311; the patterned photoresist layer 32 is located on the top surface of the anti-reflective layer 312 and has an opening, which defines the size of the stress buffer layer 34.

[0092] In step S62, refer to Figure 13 Step S62 in Figure 15 Using the patterned photoresist layer 32 as a mask, the substrate 20 is etched to form a stress buffer trench 33 that penetrates the second supporting layer 24, the second dielectric layer 23, the first supporting layer 22, and the first dielectric layer 21 from top to bottom. The stress buffer trench 33 circumferentially surrounds the intermediate unit group.

[0093] As an example, the material of the sacrificial layer 311 is selected from a carbon layer, an oxide layer, a nitride layer, and a combination thereof. In this embodiment, the material of the sacrificial layer 311 is an amorphous carbon layer.

[0094] As an example, the material of the anti-reflection layer 312 includes silicon oxynitride or other nitrogen-containing compounds. In this embodiment, the material of the anti-reflection layer 312 is silicon oxynitride to make pattern positioning more accurate during photolithography.

[0095] In step S63, refer to Figure 13 Step S63, Figure 15 as well as Figure 16 Then, the patterned photoresist layer 32 and anti-reflective layer 312 are removed, and the sacrificial layer 311 located on the top surface of the middle cell group is removed. The sacrificial layer 311 inside the capacitor trench 28 is retained to facilitate subsequent etching processes. Then, a material is filled inside the stress buffer trench 33 to form a stress buffer layer 34. In other embodiments, the patterned photoresist and hard mask layer 31 may also be removed after forming the stress buffer layer 34.

[0096] As an example, the material of the stress buffer layer 34 is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and combinations thereof. In other embodiments, the material of the stress buffer layer 34 may also be other tensile stress materials to reduce the impact of stress on the capacitor unit group 30. In this embodiment, the material of the stress buffer layer 34 is silicon nitride.

[0097] As an example, after forming the stress buffer layer 34 on the top surface of the substrate 20 in step S6 and before sequentially forming the dielectric layer and the second electrode layer 292 in the capacitor trench 28 in step S8, the process further includes:

[0098] Step S7: removing the first dielectric layer and the second dielectric layer, and removing the first supporting layer and the second supporting layer surrounding the stress buffer layer.

[0099] In step S7, refer to Figures 17-21 ,exist Figure 17 In the process, first, a fourth mask layer 35, a fifth mask layer 36 and a sixth mask layer 37 are formed on the top surface of the middle unit group. Figure 18 In the process, the sixth mask layer 37 is used as a mask to etch away the second support layer 24 surrounding the stress buffer layer 34, and then the fourth mask layer 35, the fifth mask layer 36 and the sixth mask layer 37 are removed, and the sacrificial layer 311 located inside the capacitor trench 28 is removed. Figure 19 In the process, the entire second dielectric layer 23 is removed. Figure 20 In the embodiment, the first support layer 22 surrounding the stress buffer layer 34 is etched away. Figure 21 In the above etching process, the stress buffer layer 34 can also alleviate the external force impact caused by various acids on the middle unit group area, increase stability, and help reduce the deformation of the capacitor column 29 formed subsequently.

[0100] As an example, the material of fourth mask layer 35 is selected from carbon layer, oxide layer, nitride layer and combinations thereof, the material of fifth mask layer 36 includes silicon oxynitride or other nitrogen-containing compounds, and the material of sixth mask layer 37 may include photoresist.

[0101] In step S8, refer to Figure 7 Step S8 in Figure 22 A dielectric layer (not shown) and a second electrode layer 292 are sequentially formed within the capacitor trench 28 to form a capacitor unit group 30. The dielectric layer conformally covers the first electrode layer 291. The second electrode layer 292, the dielectric layer, and the first electrode layer 291 together fill the capacitor trench 28 and form capacitor columns 29. The capacitor unit group 30 includes a plurality of capacitor columns 29. A spacer layer 40 is formed in the gaps between adjacent capacitor columns 29 to isolate adjacent capacitor columns 29.

[0102] As an example, the material of the spacer layer 40 may include any insulating material.

[0103] In the method for preparing the semiconductor structure in the above embodiment, after forming the intermediate unit group having the capacitor trench 28 and the first electrode layer 291, a circle of stress buffer layer 34 is formed around the circumferential position of the intermediate unit group, and then a dielectric layer and a second electrode layer 292 are sequentially formed in the capacitor trench 28 to form the capacitor unit group 30, so that the portion of the capacitor unit group 30 exposed to the periphery is protected by the stress buffer layer 34, reducing the stress impact or other impact it is subjected to, improving the bending deformation of the capacitor column 29 in the capacitor unit group 30, and thus improving the overall quality of the capacitor column 29. In addition, since the stress buffer layer 34 is formed before the capacitor column 29 is formed in the embodiment of the present disclosure, the stress buffer layer 34 can also protect the capacitor column 29 during the manufacturing process of the capacitor column 29, prevent the external force impact caused by various acid solutions on the capacitor unit group 30 area, increase the stability of the capacitor unit group 30, further improve the deformation problem of the capacitor column 29, thereby improving the quality of the capacitor, and improving the stability and yield of the device.

[0104] As an example, the orthographic projection of the stress buffer layer 34 on the top surface of the substrate 20 is a continuous closed figure, that is, the stress buffer layer 34 completely wraps the exposed sidewalls of the capacitor column 29, and has a strong protective effect, so as to serve as a stress buffer zone for the entire capacitor unit group 30 to alleviate stress impact. In other embodiments, the orthographic projection of the stress buffer layer 34 on the top surface of the substrate 20 is a plurality of spaced sub-figures, and the sub-figures are rectangular or have corners, so as to save materials while buffering the stress impact on the capacitor unit group 30. The above two stress buffer layers 34 are formed in different positions, but the formation methods are similar. Please refer to the above embodiments for the formation steps.

[0105] As an example, see Figure 22 After the step of sequentially forming the dielectric layer and the second electrode layer 292 in the capacitor trench 28 in step S8, the method further includes:

[0106] Step S9 : forming a continuous protective capping layer 38 on the top surface of the capacitor unit group 30 and the surface of the stress buffer layer 34 away from the capacitor unit group 30 .

[0107] In step S9 , the protective capping layer 38 covers the top of the capacitor unit group 30 and the outer sidewall of the stress buffer layer 34 . The protective capping layer 38 may also cover other exposed portions of the substrate 20 to protect the exposed portions.

[0108] As an example, the material of the protective cap layer 38 may include at least one of silicon oxide, silicon nitride, single crystal silicon, and polycrystalline silicon. In this embodiment, the material of the protective cap layer 38 is polycrystalline silicon.

[0109] As an example, see Figure 23The step of forming a stress buffer layer 34 on the top surface of the substrate 20 may further include:

[0110] Step S61 ′: forming a stress buffer layer 34 including an air gap structure 39 by physical vapor deposition and / or chemical vapor deposition.

[0111] In step S61', physical vapor deposition and / or chemical vapor deposition are used, and appropriate process parameters are selected to form a stress buffer layer 34 including an air gap structure 39. The air gap structure 39 is located within the stress buffer layer 34 and is located on a side away from the capacitor unit group 30 along a first direction (e.g., the ox direction) to prevent leakage of the conductive material in the capacitor column 29. The gas filled in the air gap structure 39 can be any insulating gas. The air gap structure 39 can replace the material of the stress buffer layer 34 as a stress buffer structure, weakening the conduction of stress impacts, further releasing stress, improving the bending problem of the capacitor column 29, improving the quality of the capacitor column 29, and avoiding the occurrence of short circuits.

[0112] The above-mentioned chemical vapor deposition is a technology that causes gaseous substances to undergo chemical reactions on the surface of a solid and deposit on the surface to form a stable structure. Since the chemical reaction speed is relatively fast, the gaseous substances have already undergone chemical reactions to produce solid substances before reaching the solid surface. Therefore, according to the characteristics of the chemical vapor deposition process itself, when the chemical vapor deposition process is used to deposit on a surface with steps, the thickness from the bottom to the top of the step gradually increases until it is closed at the top opening. Therefore, an air gap structure 39 can be formed by using the chemical vapor deposition process, thereby further alleviating stress impact and improving the reliability, stability and yield of semiconductor devices.

[0113] It should be understood that, although the various steps in the flow chart of the present disclosure are shown in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in order, and these steps can be performed in other orders. Moreover, although at least a portion of the steps in the figure may include multiple steps or multiple stages, these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of the steps or stages in other steps.

[0114] As an example, see Figure 24a and Figure 24b , in the above semiconductor structure and preparation method thereof, Figure 24aFor a semiconductor structure without a stress buffer layer 34, it can be seen that there is a strong stress attack at the array boundary of the capacitor group 11. The stress attack is transmitted inward from the boundary of the capacitor group 11, causing the capacitor columns above and below the support structure 12 in the capacitor group 11 to bend and deform. The closer to the boundary, the greater the stress impact and the greater the degree of bending of the capacitor column. Among them, the stress impact on the support structure 12 near the boundary is the strongest. The stress gradually spreads and conducts with this point as the center of the circle, thereby reducing the quality of the capacitor and affecting the device yield. Figure 24b This is the semiconductor structure after the stress buffer layer 34 is provided in the embodiment of the present disclosure. It can be seen that the stress impact on the capacitor column 29 in the capacitor unit group 30 is significantly reduced compared to before the stress buffer layer 34 is provided. The degree of bending of the capacitor column 29 is also significantly reduced, and almost no bending occurs. Therefore, the semiconductor structure and preparation method provided by the present disclosure significantly improve the quality of capacitors and the yield rate of devices.

[0115] As an example, see Figure 25a 、 Figure 25b as well as Figure 25c , Figure 25a The diagram shows the distribution of the upper capacitor column 29 and the lower capacitor column 29 with the first support layer 22 as the dividing point. Figure 25b and Figure 25c The figure shows the reduction ratio of the stress value after the stress buffer layer 34 is set in the capacitor columns 29 of different sizes compared with the stress value before the stress buffer layer 34 is set. As can be seen from the curve diagram, after the stress buffer layer 34 is set, the stress of different types of capacitor columns 29 is significantly reduced, and the stress reduction ratio is distributed between 16% and 18%. Therefore, the setting of the stress buffer layer 34 can significantly reduce the stress impact on the capacitor column 29, thereby improving the capacitor bending problem, avoiding device short circuit phenomenon, and thus improving the yield rate and overall performance of the memory.

[0116] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0117] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0118] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The above embodiments merely illustrate several implementations of the present disclosure, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person of ordinary skill in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the disclosed patent shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a capacitor unit group located on the top surface of the substrate, the capacitor unit group comprising a plurality of capacitor columns arranged in an array along the first direction and the second direction, the capacitor columns extending along the third direction; a stress buffer layer, located on a top surface of the substrate, extending along the third direction and circumferentially surrounding the capacitor unit group, wherein the first direction, the second direction, and the third direction are perpendicular to each other; The orthographic projection of the stress buffer layer on the top surface of the substrate forms a target area, and the capacitor unit group is located in the target area; The orthographic projection of the stress buffer layer on the top surface of the substrate is a plurality of spaced sub-patterns, and the sub-patterns are rectangular; The length of the rectangle extending along the first direction is equal to the distance between adjacent rectangles extending along the first direction. The difference between the length of the rectangle extending along the second direction and the spacing between the adjacent rectangles extending along the second direction is equal to the graphic size of the positive projection of the capacitor column on the top surface of the substrate.

2. The semiconductor structure according to claim 1, wherein: Also includes: The air gap structure is located in the stress buffer layer and on a side away from the capacitor unit group along the first direction.

3. The semiconductor structure according to claim 1, wherein: The material of the stress buffer layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride and combinations thereof.

4. The semiconductor structure according to claim 1, wherein: Also includes: a first supporting layer, at least partially located between the capacitor columns adjacent to each other along the first direction and close to the middle of the capacitor columns along the third direction; a second supporting layer, at least partially located between the capacitor columns adjacent to each other along the first direction, and located on a side of the first supporting layer away from the substrate along the third direction, wherein both the first supporting layer and the second supporting layer extend along the first direction; The spacer layer at least fills the gaps between adjacent capacitor columns.

5. The semiconductor structure according to claim 1, wherein: The capacitor column comprises: a second electrode layer, located on the top surface of the substrate and extending along the third direction; a first electrode layer covering the outer sidewall and bottom surface of the second electrode layer; The dielectric layer is located between the first electrode layer and the second electrode layer.

6. The semiconductor structure according to claim 5, wherein: Include at least one of the following features: The material of the first electrode layer is selected from polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride and combinations thereof; The material of the second electrode layer is selected from polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride and combinations thereof; The material of the dielectric layer is selected from nitride, metal oxide and a combination thereof.

7. The semiconductor structure according to claim 1, wherein: An active area defined by a trench isolation structure is formed in the substrate, a plurality of the active areas are arranged in an array along the first direction and the second direction, and the plurality of the active areas are located on a side of the capacitor unit group close to the substrate along the third direction; The semiconductor structure further comprises: a metal conductive layer, located in the substrate, extending along the first direction, and located between the capacitor unit group and the active area; The word line structure is located in the active area and on a side of the metal conductive layer away from the capacitor unit group along the third direction.

8. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming an intermediate unit group on the top surface of the substrate, the intermediate unit group including a plurality of capacitor trenches arranged in an array along the first direction and the second direction, and a first electrode layer located on the bottom surface and sidewalls of the capacitor trenches; the capacitor trenches extending along the third direction; forming a stress buffer layer on a top surface of the substrate, the stress buffer layer extending along the third direction and circumferentially surrounding the intermediate unit group, wherein the first direction, the second direction, and the third direction are perpendicular to each other; A dielectric layer and a second electrode layer are sequentially formed in the capacitor trench to form a capacitor unit group, wherein the dielectric layer conformally covers the first electrode layer, and the second electrode layer, the dielectric layer, and the first electrode layer together fill the capacitor trench and constitute a capacitor column, wherein the capacitor unit group includes a plurality of capacitor columns; The orthographic projection of the stress buffer layer on the top surface of the substrate forms a target area, and the capacitor unit group is located in the target area; The orthographic projection of the stress buffer layer on the top surface of the substrate is a plurality of spaced sub-patterns, and the sub-patterns are rectangular; The length of the rectangle extending along the first direction is equal to the distance between adjacent rectangles extending along the first direction. The difference between the length of the rectangle extending along the second direction and the spacing between the adjacent rectangles extending along the second direction is equal to the graphic size of the positive projection of the capacitor column on the top surface of the substrate.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The step of forming a stress buffer layer on the top surface of the substrate comprises: The stress buffer layer including the air gap structure is formed by a physical vapor deposition process and / or a chemical vapor deposition process.

10. The method for preparing a semiconductor structure according to claim 8, wherein: The material of the stress buffer layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride and combinations thereof.

11. The method for preparing a semiconductor structure according to claim 8, wherein: The step of forming a stress buffer layer on the top surface of the substrate includes: forming a hard mask layer and a patterned photoresist layer in the capacitor trench and on the top surface of the substrate; Using the patterned photoresist layer as a mask, etching the substrate to form a stress buffer layer; The patterned photoresist layer is removed.

12. The method for preparing a semiconductor structure according to claim 11, wherein: The hard mask layer includes a sacrificial layer and an anti-reflective layer, the sacrificial layer fills the capacitor trench and covers the top surface of the substrate, and the anti-reflective layer covers the top surface of the sacrificial layer; The patterned photoresist layer is located on the top surface of the anti-reflection layer and has an opening, and the opening defines the size of the stress buffer layer.

13. The method for preparing a semiconductor structure according to claim 12, wherein: Include at least one of the following features: The material of the sacrificial layer is selected from a carbon layer, an oxide layer, a nitride layer and a combination thereof; The material of the anti-reflection layer includes silicon oxynitride or other nitrogen-containing compounds.

14. The method for preparing a semiconductor structure according to claim 8, wherein: The top surface of the substrate is further formed with a first dielectric layer, a first supporting layer, a second dielectric layer, and a second supporting layer stacked in sequence along the third direction, and the first dielectric layer is adjacent to the substrate; after the step of forming the stress buffer layer on the top surface of the substrate and before the step of sequentially forming the dielectric layer and the second electrode layer in the capacitor trench, the method further includes: The first dielectric layer and the second dielectric layer are removed, and the first supporting layer and the second supporting layer surrounding the stress buffer layer are removed.

15. The method for preparing a semiconductor structure according to claim 14, wherein: The materials of the first supporting layer and the second supporting layer are selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, and combinations thereof.

16. The method for preparing a semiconductor structure according to claim 8, wherein: After the step of sequentially forming a dielectric layer and a second electrode layer in the capacitor trench, the method further includes: A continuous protective cover layer is formed on the top surface of the capacitor unit group and the surface of the stress buffer layer away from the capacitor unit group.

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