Implementation Method of EPC-MIMO Radar Transmitted Signal Based on FPGA

Abstract

This invention relates to a method and apparatus for implementing EPC-MIMO radar transmission signals based on an FPGA, comprising: storing the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model into the FPGA; when the FPGA completes the storage of the baseband waveform and phase coding factor, sending the generated timing information to the FPGA; parsing the timing information to obtain a global timing signal; wherein, when the global timing signal is generated or after its generation, the timing information is updated, ending the generation of the global timing signal, and regenerating the global timing signal using the updated timing information; modulating the baseband waveform according to the global timing signal and the phase coding factor to obtain a modulated signal; performing up-conversion processing on the modulated signal to obtain an intermediate frequency (IF) signal, and using the IF signal as the transmission signal. This allows for changes to the radar's operating timing by sending new timing information, making the radar operation more flexible.

Description

Technical Field

[0001] This invention relates to the field of radar data processing, and more specifically, to a method and apparatus for implementing EPC-MIMO radar transmission signals based on FPGA. Background Technology

[0002] Radar determines the target's range or range gate by calculating the time delay between the electromagnetic wave transmission time and the target echo arrival time, a crucial function of radar. In traditional pulse radar systems, because the transmitted pulse corresponding to the received echo signal can be arbitrary, a single PRF (Pulse Repetition Frequency) cannot be used to estimate the number of range regions, leading to range ambiguity. Solving this ambiguity requires using multiple PRFs, which consumes significant time resources. EPC-MIMO (Element Pulse Coding Multiple Input Multiple Output) radar, however, uses orthogonal waveforms in its transmitting antenna elements. The initial phase of each transmitting element and the transmitted pulse is modulated by a phase coding factor. This phase coding allows for the differentiation of echo signals received from different pulses illuminating the target, enabling the estimation of the target's range region using a single PRF. However, existing radar technologies, regardless of their specific modes, generate radar signals with a single timing sequence, resulting in a lack of flexibility in the radar system. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this invention provides a method and apparatus for implementing EPC-MIMO radar transmission signals based on FPGA.

[0004] According to a first aspect of the present invention, a method for implementing EPC-MIMO radar transmission signals based on FPGA is provided, the method comprising:

[0005] Store the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model into the FPGA;

[0006] Generate timing information;

[0007] When the FPGA completes the storage of the baseband waveform and phase coding factor, the timing information is sent to the FPGA.

[0008] The timing information is parsed to obtain a global timing signal; wherein, when the global timing signal is generated or after the global timing signal is generated, the timing information is updated, the generation of the global timing signal ends, and the global timing signal is regenerated using the updated timing information;

[0009] The baseband waveform is modulated according to the global timing signal and the phase coding factor to obtain a modulated signal;

[0010] The modulation signal is up-converted to obtain an intermediate frequency signal;

[0011] The intermediate frequency signal is sent to the radio frequency terminal as a transmission signal for transmission.

[0012] Optionally, storing the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model to the FPGA includes:

[0013] The baseband waveform and phase coding factor of each channel are generated based on the EPC-MIMO radar signal model.

[0014] After processing the baseband waveform and phase coding factor of each channel respectively, the waveform data matrix and phase coding factor matrix of each channel are obtained.

[0015] The waveform data matrix of each channel is stored in the corresponding position of the first RAM of the FPGA, and the phase coding factor matrix of each channel is stored in the corresponding position of the second RAM of the FPGA, so as to represent the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model being stored in the FPGA; wherein, the first RAM and the second RAM are two different parts of RAM in the FPGA.

[0016] Optionally, before storing the waveform data matrix of each channel in the corresponding location of the first RAM of the FPGA and storing the phase encoding factor matrix of each channel in the corresponding location of the second RAM of the FPGA, the method further includes:

[0017] The first preamble is concatenated with the waveform data matrix of each channel to characterize the channel corresponding to each waveform data matrix; wherein, the first preamble is used to characterize the channel corresponding to the waveform data matrix as well as the data type and data length of the waveform data matrix;

[0018] The second preamble is concatenated with the phase coding factor matrix of each channel; wherein the second preamble is used to characterize the channel corresponding to the phase coding factor matrix, as well as the data type and data length of the phase coding factor matrix.

[0019] Optionally, the generation of timing information includes:

[0020] The required time parameters for this EPC-MIMO radar are determined based on the functions that the EPC-MIMO radar needs to achieve.

[0021] The time parameters are sorted in a preset order, and the time parameters are concatenated with a third preamble to obtain the timing information; wherein, the third preamble is used to characterize the data type and data length of the time parameters.

[0022] Optionally, parsing the timing information to obtain the global timing signal includes:

[0023] When the message is determined to be a timing message based on the third preamble, the timing message is assigned to the corresponding register to obtain the assigned register, so as to generate a timing signal after receiving all the timing information.

[0024] After parsing all the assigned registers, the global timing signals are obtained.

[0025] Optionally, modulating the baseband waveform according to the global timing signal and the phase coding factor to obtain a modulated signal includes:

[0026] When the baseband waveform, the phase coding factor, and the timing information are not updated, the rising edge of the PRT signal in the global timing signal is detected, and the detection of the rising edge of the external clock signal begins.

[0027] When the rising edge of the external clock signal arrives, the waveform data matrix of each channel is retrieved from the first RAM, and the phase encoding factor matrix of each channel is retrieved from the second RAM.

[0028] The modulation signal is obtained by performing a complex multiplication operation on the waveform data matrix of each channel and the phase coding factor matrix of each channel.

[0029] Optionally, after detecting the rising edge of the PRT signal in the global timing signal when the baseband waveform, the phase coding factor, and the timing information have not been updated, the method further includes:

[0030] When any one of the baseband waveform, the phase coding factor, or the timing information is updated, the modulation of the baseband waveform is stopped and the updated data is stored.

[0031] After the updated data is stored, the rising edge of the PRT signal in the global timing signal and the rising edge of the external clock signal are detected to restart the modulation of the baseband waveform.

[0032] Optionally, the up-conversion processing of the modulated signal to obtain the intermediate frequency signal includes:

[0033] The real part of the modulated signal is multiplied by the cosine signal generated by the DDS module to obtain the first signal;

[0034] The imaginary part of the modulated signal is multiplied by the sine signal obtained by phase shifting the cosine signal to obtain the second signal;

[0035] The intermediate frequency signal is obtained by summing the first signal and the second signal.

[0036] According to a second aspect of the present invention, an apparatus for implementing EPC-MIMO radar transmission signals based on an FPGA is provided, the apparatus comprising:

[0037] The storage module is used to store the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model into the FPGA;

[0038] The timing generation module is used to generate timing information;

[0039] The timing information delivery module is used to deliver the timing information to the FPGA when the FPGA completes the storage of the baseband waveform and phase coding factor;

[0040] The timing parsing module is used to parse the timing information to obtain a global timing signal; wherein, when the global timing signal is generated or when the timing information is updated after the global timing signal is generated, the generation of the global timing signal is stopped, and the global timing signal is regenerated using the updated timing information.

[0041] A modulation module is used to modulate the baseband waveform according to the global timing signal and the phase coding factor to obtain a modulated signal;

[0042] An upconversion module is used to perform upconversion processing on the modulated signal to obtain an intermediate frequency signal;

[0043] The signal transmission module is used to send the intermediate frequency signal to the radio frequency terminal as a transmission signal for transmission.

[0044] The technical solution provided by this invention may include the following beneficial effects:

[0045] With the above technical solution, since the timing information is updated when the global timing signal is generated or after the global timing signal is generated, the generation of the global timing signal is stopped, and the global timing signal is regenerated using the updated timing information. Therefore, the radar's operating timing can be changed by issuing new timing information, making the system more flexible.

[0046] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0047] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof. In the drawings:

[0048] Figure 1 This is a flowchart illustrating an implementation method of FPGA-based EPC-MIMO radar transmission signal according to an exemplary embodiment.

[0049] Figure 2 This is a flowchart illustrating an implementation method for an FPGA-based EPC-MIMO radar transmission signal according to an exemplary embodiment.

[0050] Figure 3 This is a schematic diagram illustrating a global timing signal according to an exemplary embodiment.

[0051] Figure 4 This is a schematic diagram illustrating a process for acquiring an intermediate frequency signal according to an exemplary embodiment.

[0052] Figure 5a This is a timing simulation diagram illustrated according to an exemplary embodiment.

[0053] Figure 5b This is yet another timing simulation diagram illustrated according to an exemplary embodiment.

[0054] Figure 6 This is a schematic diagram illustrating another oscilloscope timing measurement according to an exemplary embodiment.

[0055] Figure 7 This is a schematic diagram illustrating an intermediate frequency signal according to an exemplary embodiment.

[0056] Figure 8 This is a schematic diagram illustrating yet another intermediate frequency signal according to an exemplary embodiment.

[0057] Figure 9 This is a block diagram illustrating an FPGA-based EPC-MIMO radar transmission signal implementation device according to an exemplary embodiment. Detailed Implementation

[0058] Figure 1 This is a flowchart illustrating an implementation method for EPC-MIMO radar transmission signals based on an exemplary embodiment, as shown below. Figure 1 As shown, the method includes the following steps.

[0059] S101. Store the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model to the FPGA.

[0060] Understandably, EPC-MIMO radar is an advanced radar technology that combines electronically phased array (EPC) and multiple-input multiple-output (MIMO) technologies. This type of radar can electronically change the direction and shape of the beam, simultaneously using multiple antennas to receive and transmit signals, thereby achieving high-resolution radar imaging and target detection. FPGA (Field-Programmable Gate Array) is a field-programmable gate array.

[0061] In one implementation, an EPC-MIMO radar signal model can be constructed:

[0062] Suppose a MIMO radar with M transmit antenna elements arranged in a uniform linear array and isotropic. For the k-th pulse of the m-th transmit element, the transmitted signal is as follows:

[0063]

[0064] in, It is an impulse function, T p f0 is the pulse width, f0 is the carrier frequency, and j is the imaginary unit. 2 =-1, signal s m,k (t) is a function of time t, which represents a period of time rather than a point in time. For example, if the length of a PRT is 1ms, the value of t is (0, 1ms).

[0065] c m,k It is the phase coding factor. For the m-th transmit element and the k-th pulse, the phase coding factor is: c m,k =e j2 πγ(m-1)(k-1) , where γ∈(0,1) is a customizable and adjustable encoding parameter.

[0066] This is the baseband signal corresponding to the m-th transmitting element. Since it is a MIMO radar, the signals of each channel satisfy the condition of orthogonal waveforms: Where τ is the time delay.

[0067] S102, Generate timing information.

[0068] S103. When the FPGA completes the storage of the baseband waveform and phase encoding factor, the timing information is sent to the FPGA.

[0069] S104. Parse the timing information to obtain the global timing signal; wherein, when the global timing signal is generated or after the global timing signal is generated, the timing information is updated, the generation of the global timing signal ends, and the global timing signal is regenerated using the updated timing information.

[0070] It is understandable that timing information parsing is performed on the FPGA, and during the parsing of timing signals and the generation of global timing signals, there is a timing information update, the generation of global timing signals is stopped, the timing information in the FPGA is overwritten, and then the global timing signals are regenerated.

[0071] S105. Modulate the baseband waveform according to the global timing signal and the phase coding factor to obtain the modulated signal.

[0072] S106. Perform up-conversion processing on the modulation signal to obtain the intermediate frequency signal.

[0073] S107. The intermediate frequency signal is sent to the radio frequency terminal as a transmission signal for transmission.

[0074] Understandably, the modulation and up-conversion of the baseband waveform require a certain processing time. When the phase coding factor for modulating the baseband waveform and the bit width of the baseband waveform data are determined, the processing time for other data with the same bit width can be considered to be of the same order of magnitude, and the processing time can be pre-calculated through testing. After the intermediate frequency signal is generated, it is sent to the radio frequency (RF) end for transmission. With the pre-calculated processing time, the system's computation time can be excluded during data processing, resulting in accurate data.

[0075] Optionally, S101 may include:

[0076] The baseband waveforms and phase coding factors for each channel are generated based on the EPC-MIMO radar signal model.

[0077] After processing the baseband waveform and phase coding factor of each channel respectively, the waveform data matrix and phase coding factor matrix of each channel are obtained.

[0078] The first preamble is concatenated with the waveform data matrix of each channel to represent the channel corresponding to each waveform data matrix; wherein, the first preamble is used to represent the channel corresponding to the waveform data matrix as well as the data type and data length of the waveform data matrix;

[0079] The second preamble is concatenated with the phase coding factor matrix of each channel; wherein, the second preamble is used to characterize the channel corresponding to the phase coding factor matrix, as well as the data type and data length of the phase coding factor matrix;

[0080] The waveform data matrix of each channel is stored in the corresponding position of the first RAM of the FPGA, and the phase coding factor matrix of each channel is stored in the corresponding position of the second RAM of the FPGA, so as to represent the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model and stored in the FPGA; wherein, the first RAM and the second RAM are two different parts of RAM in the FPGA.

[0081] Understandably, in one implementation, Figure 2 This is a flowchart illustrating an implementation method for an FPGA-based EPC-MIMO radar transmission signal according to an exemplary embodiment, as shown below. Figure 2 As shown, firstly, for the baseband waveform, since the pulse is continuous, but digital processing can only handle discrete signals, the continuous signal needs to be divided into discrete signals according to the sampling rate. For example, to transmit a 1-second pulse, sampling at a 100MHz sampling rate would require 100MHz * 1s = 1 × 10⁸ sampling points. Then, based on the length of the signal to be transmitted, the required number of sampling points n is obtained. The baseband waveforms for each channel are generated according to the formula in S101, decomposing each channel's baseband waveform into real and imaginary data. Wherein, according to Euler's formula e jθ The waveform is decomposed using cos(θ) + jsin(θ), where cos(θ) is the real part and sin(θ) is the imaginary part. It is then quantized, and the quantized real and imaginary parts are concatenated to obtain an n×1 dimensional waveform data matrix. A first preamble for verification is added to the waveform data matrix to help the FPGA distinguish the received data type, data length, and channel number. The data is then sent to the FPGA sequentially according to the channel number. After receiving the data, the FPGA determines that the data is the baseband waveform of the m-th transmit channel by parsing the first preamble corresponding to the waveform data matrix. After offsetting the address and removing the first preamble, the baseband waveform is stored sequentially in the m-th first RAM. A storage completion enable signal is generated upon completion of storage. After storage, m first RAMs are obtained, each storing the waveform data matrix of n points corresponding to the channel.

[0082] For the phase coding factor, first select the number of pulses k, and generate the phase coding factor according to the formula in S101. Similar to the method used for processing baseband waveforms, the phase coding factor is quantized. Since FPGAs have difficulty processing floating-point numbers, they need to be converted to binary numbers; this process is called quantization. The quantization length is determined by the input requirements of the AD / DA chips on the FPGA or by factors such as the allocated bit width. For example, if the data to be transmitted is 0, it is agreed to quantize it into an 8-bit unsigned number, resulting in 8'b0000_0000. After concatenation, a k×1 dimensional phase coding factor matrix is ​​obtained for each channel. A second preamble is added to indicate that it is the phase coding factor matrix of the m-th transmit channel, and it is sent to the FPGA sequentially according to the channel number. The FPGA stores the data in the second RAM according to the parsed second preamble and generates a storage completion enable signal, resulting in m RAMs, each storing the phase coding factor matrix of the k-point corresponding channel.

[0083] Optionally, S102 may include:

[0084] Determine the required timing parameters for this EPC-MIMO radar based on the functions it needs to achieve.

[0085] The time parameters are sorted in a preset order, and the time parameters are concatenated with the third preamble to obtain the timing information; the third preamble is used to characterize the data type and data length of the time parameters.

[0086] Understandably, reference Figure 2 In EPC-MIMO pulse radar, the radar's timing parameters, such as pulse width, pulse repetition frequency, and coherent processing time, are crucial to the radar system's operation. By changing different parameters, the radar can achieve different functions.

[0087] Therefore, the types, order, data bit width, and conversion units of parameter information can be agreed upon with the FPGA. The desired timing parameters are sorted in the agreed order, and a third preamble is added before the data for the FPGA to recognize. The length of the generated timing information data is (a+b)×x bits, where a is the length of the third preamble, b is the number of timing information items, and x is the data bit width.

[0088] Optionally, S104 may include:

[0089] When the message is determined to be a timing message based on the third preamble, the timing message is assigned to the corresponding register to obtain the assigned register, so as to generate timing signals after all timing information has been received.

[0090] After parsing all the assigned registers, the global timing signals are obtained.

[0091] Understandably, reference Figure 2 After the FPGA parses the third preamble and determines that the received data is timing information, it does not store it in RAM. Since the number of timing information items is fixed and the data length is short, the values ​​of the timing information can be directly assigned to the corresponding registers. This also facilitates the generation of timing information after receiving the timing information. After receiving the data, b registers with a bit width of x bits after assignment are obtained.

[0092] Because the third preamble specifies the data length, the FPGA begins counting when it starts receiving valid timing information. Once the timing information reception is complete and there are no further timing information updates, the FPGA begins generating corresponding timing signals based on the values ​​of each register: determining the number of CPIs (Coherent Processing Intervals) based on the type of stagger, generating a CPI count; determining the number of PRTs within a CPI based on the number of pulse accumulations, generating a PRT count; determining the length of a PRT based on the pulse repetition frequency, generating a PRT length count; generating a count based on the pulse width; and finally generating a global timing signal for each module to operate. Note that since subsequent signal modulation and frequency conversion require processing time, the pulse width should be increased appropriately based on the waveform data length, but cannot exceed the PRT length. Furthermore, the length of PRTs within a CPI is the same; however, if there are staggers, the PRT lengths in different CPIs may differ. If there is a timing information update during or after the generation of the global timing signal, the generation of the global timing signal is stopped, the timing information in the registers is overwritten, and a new signal is generated.

[0093] In one implementation, Figure 3 This is a schematic diagram illustrating a global timing signal according to an exemplary embodiment. The radar's operating timing is as follows: Figure 3 As shown, each CPI contains multiple PRTs. Figure 3 One CPI contains 4 PRTs (often used in 8, 16, 32, etc.). The radar transmits a signal when each PRT is high and receives a signal when the PRT is low (some radar systems use a high-level reception and low-level transmission). After receiving the timing information, the FPGA needs to generate a timing diagram similar to the one shown above, so it needs to count and generate corresponding signals based on the timing information. For example: different CPIs may point at different angles, so there needs to be a count of the number of CPIs; different PRTs require different coding factors for modulation, so there needs to be a count of the number of PRTs; different pulses have different widths, so there needs to be a count of the PRT lengths.

[0094] Optionally, S105 may include:

[0095] When the baseband waveform, phase coding factor and timing information are not updated, the rising edge of the external clock signal is detected when the rising edge of the PRT signal in the global timing signal is detected.

[0096] When the rising edge of the external clock signal arrives, the waveform data matrix of each channel is retrieved from the first RAM, and the phase encoding factor matrix of each channel is retrieved from the second RAM.

[0097] The modulated signal is obtained by performing complex multiplication on the waveform data matrix of each channel and the phase coding factor matrix of each channel.

[0098] Optionally, after detecting the rising edge of the external clock signal when the baseband waveform, phase coding factor, and timing information are not updated, the method further includes:

[0099] When any data in the baseband waveform, phase coding factor, or timing information is updated, the modulation of the baseband waveform is stopped and the updated data is stored.

[0100] After the updated data has been stored, the rising edge of the PRT signal in the global timing signal and the rising edge of the external clock signal are detected to restart the modulation of the baseband waveform.

[0101] Understandably, reference Figure 2 After the global timing signal is generated, if there are no updates to the baseband waveform, phase coding factor, or timing information, the rising edge of the PRT signal in the global timing signal is detected. Simultaneously, data is retrieved from the first RAM storing multiple waveform data matrices and the second RAM storing phase coding factor matrices, according to the rising edge of the external clock signal. Complex multiplication is performed between the waveform data matrices of different channels and their corresponding phase coding factor matrices, thus completing the modulation of the baseband waveform. The modulated signal is then digitally up-converted. If there are updates to the baseband waveform, phase coding factor, or timing information, modulation of the baseband waveform stops and the new data is stored. Modulation of the baseband waveform resumes when the next rising edge of the PRT signal arrives.

[0102] Optionally, S106 may include:

[0103] The real part of the modulated signal is multiplied by the cosine signal generated by the DDS module to obtain the first signal;

[0104] The second signal is obtained by multiplying the imaginary part of the modulated signal with the sine signal obtained by phase shifting the cosine signal.

[0105] The intermediate frequency signal is obtained by summing the first and second signals.

[0106] Understandable, Figure 4 This is a schematic diagram illustrating a process for acquiring an intermediate frequency signal according to an exemplary embodiment, such as... Figure 4 As shown, the baseband waveform is multiplied by the coding factor to obtain the modulation signal. The carrier frequency signal required for up-conversion is generated by the DDS module, which generates a cosine signal and converts it to a sine signal after phase shifting. The real part of the modulation signal, I(t), is multiplied by the cosine signal generated by the DDS module to obtain the first signal. The imaginary part of the modulation signal, Q(t), is multiplied by the cosine signal cosω. c The sinusoidal signal -sinω obtained after phase shifting t c Multiplying by t yields the second signal, where ω c The up-conversion frequency is determined by summing the calculated results, thus completing the up-conversion process and obtaining the intermediate frequency signal used for this transmission.

[0107] In one embodiment, the present invention can change the radar's operating timing by re-issuing timing information, making the system more flexible. Figure 5a This is a timing simulation diagram illustrated according to an exemplary embodiment. Using the method proposed in this invention, parameters such as PRF and CPI are changed to send different timing information to the FPGA. Figure 5a This is the timing sequence in the simulation experiment of this invention, when there is no stagger during transmission, the PRT length is 5µs, the pulse width is 1µs, and the number of pulses is 16. Figure 5b This is yet another timing simulation diagram illustrated according to an exemplary embodiment. Figure 5b This is the timing sequence in the simulation experiment of this invention when the conditions are changed to no variation, PRT length 10µs, pulse width 1µs, and pulse count 32. As can be seen from the figure, the system correctly generated the required working timing sequence, and the timing sequence can be changed by re-issuing parameters.

[0108] Figure 6 This is a schematic diagram illustrating another oscilloscope timing measurement according to an exemplary embodiment. Figure 7 This is a schematic diagram illustrating an intermediate frequency signal according to an exemplary embodiment. Figure 8 This is a schematic diagram of another intermediate frequency signal according to an exemplary embodiment. The present invention can realize the generation of different pulse code radar signals. Instead of retransmitting the baseband waveform, the radar system can transmit multiple radar signals by transmitting coding factor information with a data volume much smaller than the waveform data volume, thereby improving the working efficiency of radar configuration. Figure 7 In the experiment of this invention, a 1MHz point frequency signal was sent to the FPGA, and the phase encoding factor was set to all 1s (for easy observation). The point frequency signal was then digitally up-converted and processed according to... Figure 6The timing of the transmission was observed, and the results from its four channels were recorded. As shown in the figure, the system's stored signal is correct, the digital up-conversion result is correct without distortion, and the waveform is transmitted synchronously according to the specified timing. Figure 8 Given a set of phase coding factors, the intermediate frequency signal is obtained by digital up-conversion of a 1MHz point frequency signal after modulation, and the results are obtained by observing four channels.

[0109] Figure 9 This is a block diagram illustrating an FPGA-based EPC-MIMO radar transmission signal implementation device according to an exemplary embodiment, such as... Figure 9 As shown, the device 900 may include:

[0110] Storage module 901 is used to store the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model to the FPGA;

[0111] Timing generation module 902 is used to generate timing information;

[0112] The timing information delivery module 903 is used to deliver timing information to the FPGA when the FPGA completes the storage of baseband waveform and phase encoding factor;

[0113] The timing parsing module 904 is used to parse timing information to obtain a global timing signal. When the global timing signal is generated or when the timing information is updated after the global timing signal is generated, the generation of the global timing signal is stopped, and the global timing signal is regenerated using the updated timing information.

[0114] The modulation module 905 is used to modulate the baseband waveform according to the global timing signal and the phase coding factor to obtain the modulated signal;

[0115] The upconversion module 906 is used to upconvert the modulated signal to obtain the intermediate frequency signal;

[0116] The signal transmission module 907 is used to send the intermediate frequency signal to the radio frequency terminal as a transmission signal for transmission.

[0117] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0118] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0119] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0120] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A method for implementing EPC-MIMO radar transmission signals based on FPGA, characterized in that, The method includes: The baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model are stored in the FPGA; Generate timing information; When the FPGA completes the storage of the baseband waveform and phase coding factor, the timing information is sent to the FPGA. The timing information is parsed to obtain a global timing signal; wherein, when the global timing signal is generated or after the global timing signal is generated, the timing information is updated, the generation of the global timing signal ends, and the global timing signal is regenerated using the updated timing information; The baseband waveform is modulated according to the global timing signal and the phase coding factor to obtain a modulated signal; The modulation signal is up-converted to obtain an intermediate frequency signal; The intermediate frequency signal is sent to the radio frequency terminal as a transmission signal for transmission.

2. The method for implementing EPC-MIMO radar transmission signals based on FPGA according to claim 1, characterized in that, The step of storing the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model to the FPGA includes: The baseband waveform and phase coding factor of each channel are generated based on the EPC-MIMO radar signal model. After processing the baseband waveform and phase coding factor of each channel respectively, the waveform data matrix and phase coding factor matrix of each channel are obtained. The waveform data matrix of each channel is stored in the corresponding position of the first RAM of the FPGA, and the phase coding factor matrix of each channel is stored in the corresponding position of the second RAM of the FPGA, so as to represent the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model being stored in the FPGA; wherein, the first RAM and the second RAM are two different parts of RAM in the FPGA.

3. The method for implementing EPC-MIMO radar transmission signals based on FPGA according to claim 2, characterized in that, Before storing the waveform data matrices of each channel into the corresponding locations in the first RAM of the FPGA, and storing the phase encoding factor matrices of each channel into the corresponding locations in the second RAM of the FPGA, the method further includes: The first preamble is concatenated with the waveform data matrix of each channel to characterize the channel corresponding to each waveform data matrix; wherein, the first preamble is used to characterize the channel corresponding to the waveform data matrix as well as the data type and data length of the waveform data matrix; The second preamble is concatenated with the phase coding factor matrix of each channel; wherein the second preamble is used to characterize the channel corresponding to the phase coding factor matrix, as well as the data type and data length of the phase coding factor matrix.

4. The method for implementing EPC-MIMO radar transmission signals based on FPGA according to claim 1, characterized in that, The generated timing information includes: The required time parameters for this EPC-MIMO radar are determined based on the functions that the EPC-MIMO radar needs to achieve. The time parameters are sorted in a preset order, and the time parameters are concatenated with a third preamble to obtain the timing information; wherein, the third preamble is used to characterize the data type and data length of the time parameters.

5. The method for implementing EPC-MIMO radar transmission signals based on FPGA according to claim 4, characterized in that, The process of parsing the timing information to obtain the global timing signal includes: When the message is determined to be a timing message based on the third preamble, the timing message is assigned to the corresponding register to obtain the assigned register, so as to generate a timing signal after receiving all the timing information. After parsing all the assigned registers, the global timing signals are obtained.

6. The method for implementing EPC-MIMO radar transmission signals based on FPGA according to claim 2, characterized in that, The step of modulating the baseband waveform according to the global timing signal and the phase coding factor to obtain the modulated signal includes: When the baseband waveform, the phase coding factor, and the timing information are not updated, the rising edge of the PRT signal in the global timing signal is detected, and the detection of the rising edge of the external clock signal begins. When the rising edge of the external clock signal arrives, the waveform data matrix of each channel is retrieved from the first RAM, and the phase encoding factor matrix of each channel is retrieved from the second RAM. The modulation signal is obtained by performing a complex multiplication operation on the waveform data matrix of each channel and the phase coding factor matrix of each channel.

7. The method for implementing EPC-MIMO radar transmission signals based on FPGA according to claim 6, characterized in that, When the baseband waveform, the phase coding factor, and the timing information are not updated, after detecting the rising edge of the PRT signal in the global timing signal and starting to detect the rising edge of the external clock signal, the method further includes: When any one of the baseband waveform, the phase coding factor, or the timing information is updated, the modulation of the baseband waveform is stopped and the updated data is stored. After the updated data is stored, the rising edge of the PRT signal in the global timing signal and the rising edge of the external clock signal are detected to restart the modulation of the baseband waveform.

8. The method for implementing EPC-MIMO radar transmission signals based on FPGA according to claim 1, characterized in that, The up-conversion process of the modulated signal to obtain the intermediate frequency signal includes: The real part of the modulated signal is multiplied by the cosine signal generated by the DDS module to obtain the first signal; The imaginary part of the modulated signal is multiplied by the sine signal obtained by phase shifting the cosine signal to obtain the second signal; The intermediate frequency signal is obtained by summing the first signal and the second signal.

9. A device for implementing EPC-MIMO radar transmission signals based on FPGA, characterized in that, The device includes: The storage module is used to store the baseband waveform and phase coding factor generated by the EPC-MIMO radar signal model into the FPGA; The timing generation module is used to generate timing information; The timing information delivery module is used to deliver the timing information to the FPGA when the FPGA completes the storage of the baseband waveform and phase coding factor; The timing parsing module is used to parse the timing information to obtain a global timing signal; wherein, when the global timing signal is generated or when the timing information is updated after the global timing signal is generated, the generation of the global timing signal is stopped, and the global timing signal is regenerated using the updated timing information. A modulation module is used to modulate the baseband waveform according to the global timing signal and the phase coding factor to obtain a modulated signal; An upconversion module is used to perform upconversion processing on the modulated signal to obtain an intermediate frequency signal; The signal transmission module is used to send the intermediate frequency signal to the radio frequency terminal as a transmission signal for transmission.

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