Software simulation method, computer device and medium for data processor

Abstract

The present application relates to the field of computer technology and provides a software simulation method, computer device and medium for a data processor. The method includes: using the system simulator software of the data processor to simulate and generate a first quick peripheral device interconnection topology corresponding to the first root port of the host machine; at least before completing the simulation and generation of the first quick peripheral device interconnection topology, the system simulator software negotiates with the message transceiver hardware to generate the corresponding first transaction layer data packet receiving queue and the first transaction layer data packet sending queue; through the interaction between the system simulator software and the message transceiver hardware, the first transaction layer data packet receiving queue is used to realize the associated message reception, and the first transaction layer data packet sending queue is used to realize the associated message sending. In this way, the quick peripheral device interconnection topology can be flexibly and dynamically modified, which helps to maintain the message transceiver efficiency and improve the data transmission performance.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a software simulation method, computer equipment and medium for a data processor. Background Art

[0002] In the application scenarios of data processing unit (DPU), such as data center, smart network card, high-performance server, DPU is used to simulate various types of standard peripheral component interconnect express (PCIE) devices, which follow the PCIE protocol. PCIE protocol is a layered protocol, which consists of transaction layer, data link layer and physical layer. Among them, the routing and response of transaction layer packet (TLP) message needs to determine which path to pass through the switch or PCIE bridge to reach the destination, so the routing and response of TLP message are affected by the specific structure of PCIE topology. In the prior art, the PCIE topology is implemented by hardware and the routing and response of TLP message is responsible for the hardware. The basic input and output operating system (BIOS) on the host side can enable different types of PCIE devices through various types of drivers by enumerating all PCIE devices of PCIE topology during system initialization and during system operation. Such hardware implementation can improve the efficiency of message sending and receiving by utilizing the hardware offload feature. However, when the specific structure of the PCIE topology needs to be modified or new PCIE functional features need to be added in the DPU scenario, the hardware logic needs to be updated as a whole, which is not conducive to rapid response and simplified operation.

[0003] To this end, the present application provides a software simulation method, computer device and medium for a data processor, which not only overcomes the shortcomings of pure hardware implementation, can flexibly and dynamically modify the PCIE topology according to needs, but also helps to maintain the efficiency of message sending and receiving and improve data transmission performance. Summary of the invention

[0004] In a first aspect, the present application provides a software simulation method for a data processor. The software simulation method includes: simulating and generating a first quick peripheral device interconnection topology corresponding to a first root port of a host machine through system simulator software of a data processor, wherein the first quick peripheral device interconnection topology includes at least one quick peripheral device interconnection bridge device and at least one quick peripheral device interconnection end device; at least before the system simulator software completes the simulation and generation of the first quick peripheral device interconnection topology, the system simulator software negotiates with the message transceiver hardware to generate a first transaction layer data packet receiving queue and a first transaction layer data packet sending queue corresponding to the first root port managed by the message transceiver hardware; through the interaction between the system simulator software and the message transceiver hardware, using the first transaction layer data packet receiving queue to realize the message reception associated with the first quick peripheral device interconnection topology, and using the first transaction layer data packet sending queue to realize the message sending associated with the first quick peripheral device interconnection topology.

[0005] Through the first aspect of the present application, through the overall optimization design, the division of labor between the software and hardware is realized, the system simulator software is responsible for simulating and generating the first quick peripheral device interconnection topology corresponding to the first root port of the host machine, and the message transceiver hardware is responsible for providing the message forwarding hardware engine function, and is also responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue. In this way, the first quick peripheral device interconnection topology can be flexibly and dynamically modified according to needs, and there is no need to update the hardware logic, so as to ensure that the routing and response of the transaction layer data packet message are timely adjusted in coordination with the modification of the first quick peripheral device interconnection topology, which helps to maintain the message transceiver efficiency and improve the data transmission performance.

[0006] In a possible implementation of the first aspect of the present application, through the interaction between the system simulator software and the message transceiver hardware, the first transaction layer data packet receiving queue is used to implement the message reception associated with the first quick peripheral device interconnection topology, including: through the message transceiver hardware, storing the transaction layer data packet message sent by the host machine to the first transaction layer data packet receiving queue; through the system simulator software, detecting whether there is a transaction layer data packet message to be received in the first transaction layer data packet receiving queue according to a preset detection strategy, and, when the transaction layer data packet message to be received is detected, parsing the message header of the transaction layer data packet message to be received to determine the message type of the transaction layer data packet message to be received, and then, selecting a routing method based on the message type of the transaction layer data packet message to be received, and forwarding the transaction layer data packet message to be received to the destination quick peripheral device interconnection device through the selected routing method.

[0007] In a possible implementation of the first aspect of the present application, a routing mode is selected based on the message type of the transaction layer data packet message to be received, including: when the message type of the transaction layer data packet message to be received indicates reading and writing of the configuration space, an identification routing mode is selected, and the identification routing mode uses the bus-device-function identification information in the message header of the transaction layer data packet message to be received to forward the transaction layer data packet message to be received to the destination quick peripheral device interconnect device.

[0008] In a possible implementation of the first aspect of the present application, a routing mode is selected based on the message type of the transaction layer data packet message to be received, including: when the message type of the transaction layer data packet message to be received indicates reading and writing of the base address register space, an address routing mode is selected, and the address routing mode uses the address information in the message header of the transaction layer data packet message to be received to forward the transaction layer data packet message to be received to the destination quick peripheral device interconnect device.

[0009] In a possible implementation of the first aspect of the present application, a routing mode is selected based on the message type of the transaction layer data packet to be received, including: when the message type of the transaction layer data packet to be received is a message type, an implicit routing mode is selected.

[0010] In a possible implementation manner of the first aspect of the present application, the destination peripheral device interconnect express device is a destination peripheral device interconnect express bridge device in the at least one peripheral device interconnect express bridge device, or a destination peripheral device interconnect express terminal device in the at least one peripheral device interconnect express terminal device.

[0011] In a possible implementation of the first aspect of the present application, the system simulator software is used to detect whether the first transaction layer data packet receiving queue contains the transaction layer data packet message to be received according to the preset detection strategy, including: when the preset detection strategy is an interrupt mode strategy, the message transceiver hardware sends an interrupt signal to the system simulator software each time it stores the transaction layer data packet message sent by the host machine to the first transaction layer data packet receiving queue, and the system simulator software, in response to receiving the interrupt signal, detects whether the first transaction layer data packet receiving queue contains the transaction layer data packet message to be received.

[0012] In a possible implementation method of the first aspect of the present application, the system simulator software is used to detect whether the first transaction layer data packet receiving queue contains the transaction layer data packet message to be received according to the preset detection strategy, including: when the preset detection strategy is a polling strategy, the system simulator software polls to detect whether the first transaction layer data packet receiving queue contains the transaction layer data packet message to be received.

[0013] In a possible implementation of the first aspect of the present application, when the data processor is used in an application scenario with high response speed requirements, the preset detection strategy is a polling mode strategy; when the data processor is used in an application scenario with low response speed requirements, the preset detection strategy is an interrupt mode strategy.

[0014] In a possible implementation of the first aspect of the present application, through the interaction between the system simulator software and the message transceiver hardware, the first transaction layer data packet sending queue is used to implement the message sending associated with the first quick peripheral device interconnection topology, including: through the system simulator software, storing the transaction layer data packet message to be sent to the first transaction layer data packet sending queue; through the message transceiver hardware, when it is detected that the transaction layer data packet message to be sent or the transaction layer data packet message to be responded to exists in the first transaction layer data packet sending queue, sending the transaction layer data packet message to be sent or the transaction layer data packet message to be responded to to the host machine.

[0015] In a possible implementation manner of the first aspect of the present application, the software simulation method further includes: changing the first quick peripheral device interconnection topology through the configuration interface of the system simulator software, wherein the changing of the first quick peripheral device interconnection topology includes one or more of the following: increasing the number of downstream ports, reducing the number of downstream ports, using a multi-stage switch structure, increasing quick peripheral device interconnection functional characteristics, reducing quick peripheral device interconnection functional characteristics, increasing quick peripheral device interconnection terminal devices, and reducing quick peripheral device interconnection terminal devices.

[0016] In a possible implementation of the first aspect of the present application, the system simulator software completes the simulation and generation of the first peripheral device interconnect express topology, including allocating memory space for storing associated bus-device-function identification information and configuration space information to all peripheral device interconnect express bridge devices and all peripheral device interconnect express end devices in the first peripheral device interconnect express topology.

[0017] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0018] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0019] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A flowchart of a software simulation method for a data processor provided in an embodiment of the present application;

[0022] Figure 2 A reference provided for the embodiments of this application Figure 1 The software simulation method shown is a schematic diagram of a first quick peripheral device interconnection topology generated by system simulator software simulation;

[0023] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0025] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0026] Figure 1A flowchart of a software simulation method for a data processor provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the software simulation method includes the following steps.

[0027] Step S110: using system simulator software of a data processor to simulate and generate a first peripheral device interconnect express topology corresponding to a first root port of a host machine, wherein the first peripheral device interconnect express topology includes at least one peripheral device interconnect express bridge device and at least one peripheral device interconnect express terminal device.

[0028] Step S120: At least before the system simulator software completes the simulation to generate the first quick peripheral device interconnect topology, the system simulator software negotiates with the message transceiver hardware to generate a first transaction layer data packet receive queue and a first transaction layer data packet send queue corresponding to the first root port and managed by the message transceiver hardware.

[0029] Step S130: Through the interaction between the system simulator software and the message receiving and sending hardware, the first transaction layer data packet receiving queue is used to implement the message reception associated with the first express peripheral device interconnect topology, and the first transaction layer data packet sending queue is used to implement the message sending associated with the first express peripheral device interconnect topology.

[0030] Figure 1The software simulation method for a data processor shown can be applied to relevant application scenarios of a data processor (data processing unit, DPU), such as a data center, a smart network card, and a high-performance server. In these DPU application scenarios, a variety of different types of standard peripheral component interconnect express (PCIE) devices are simulated by the DPU, and these PCIE devices follow the PCIE protocol. The PCIE protocol is a layered protocol consisting of a transaction layer, a data link layer, and a physical layer. Among them, the routing and response of the transaction layer packet (TLP) message needs to determine which path to pass through the switch or PCIE bridge to reach the destination, so the routing and response of the TLP message are affected by the specific structure of the PCIE topology. For example, the memory request message and the input and output request message use an address-based routing method, and the address-based routing method uses the address field in the TLP message for routing selection and finally reaches the destination. For another example, the configuration request message uses an identification (ID)-based routing method. The ID-based routing method generally uses the bus-device-function (BFD) identification information for routing selection and finally reaches the destination. In addition, after completing the initial installation of the system, during the operation of the system, the user may need to flexibly and dynamically modify the PCIE topology as needed, such as adding or reducing PCIE functional characteristics, or adding or reducing PCIE devices. This may affect the routing and response of existing TLP messages, and thus requires timely adjustments in conjunction with the modifications made to the PCIE topology to ensure that the TLP message can reach the correct destination. If a pure hardware implementation is used to implement the PCIE topology and the hardware is responsible for the routing and response of the TLP message, when the specific structure of the PCIE topology needs to be modified in the DPU scenario, or new PCIE functional characteristics need to be added, the hardware logic needs to be updated as a whole, which is not conducive to rapid response and simplified operation. For this reason, Figure 1 The software simulation method for the data processor shown is mainly implemented by software simulation. At the same time, through the overall optimization design, it not only overcomes the shortcomings of pure hardware implementation, but also can flexibly and dynamically modify the PCIE topology according to needs, and helps to maintain the efficiency of message reception and transmission and improve data transmission performance. The following is further described in detail.

[0031] See also Figure 1, in step S110, a first quick peripheral device interconnect topology corresponding to a first root port of a host machine is simulated and generated through the system simulator software of a data processor, wherein the first quick peripheral device interconnect topology includes at least one quick peripheral device interconnect bridge device and at least one quick peripheral device interconnect terminal device. Here, the system simulator software refers to software running on a data processor for simulating and generating various system platforms and operating systems, for example, it can run on an embedded central processing unit (Embedded CPU, ECPU) of a data processor, such as an ECPU simulator. In some embodiments, the ECPU simulator initializes the PCIE topology and allocates memory space for all PCIE devices in the PCIE topology to store BDF information and configuration space information. In step S120, at least before the system simulator software completes the simulation and generation of the first quick peripheral device interconnect topology, the system simulator software negotiates with the message transceiver hardware to generate a first transaction layer data packet receiving queue and a first transaction layer data packet sending queue corresponding to the first root port managed by the message transceiver hardware. In this way, before the system simulator software completes the simulation and generation of the first quick peripheral device interconnection topology, that is, before the system simulator software completes the simulation and generation of the quick peripheral device interconnection bridge device and the quick peripheral device interconnection terminal device included in the first quick peripheral device interconnection topology, it negotiates with the message transceiver hardware, thereby realizing the deployment of the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue corresponding to the first root port. In this way, the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue are used for the transceiver of the transaction layer data packet message through the first root port, that is, sending the transaction layer data packet message to the host machine through the first root port, and receiving the transaction layer data packet message sent by the host machine through the first root port. Here, the message transceiver hardware is responsible for executing the message transceiver externally, that is, providing the message forwarding hardware engine function, and is also responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue. In some embodiments, considering that the storage resources of the message transceiver hardware itself are limited, the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue corresponding to the first root port managed by the message transceiver hardware are actually located in the memory used to support the operation of the system simulator software. Through the negotiation between the system simulator software and the message transceiver hardware, the starting address and length of the memory allocated to the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue are notified to the message transceiver hardware, so that the message transceiver hardware manages them. In other embodiments, the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue corresponding to the first root port managed by the message transceiver hardware are actually allocated the storage resources of the message transceiver hardware, and therefore are actually located in the memory of the message transceiver hardware itself.

[0032] Continue reading Figure 1In step S130, through the interaction between the system simulator software and the message receiving and sending hardware, the first transaction layer data packet receiving queue is used to implement the message reception associated with the first express peripheral device interconnect topology, and the first transaction layer data packet sending queue is used to implement the message sending associated with the first express peripheral device interconnect topology. Thus, through the overall optimization design, on the one hand, the system simulator software is responsible for simulating and generating the first quick peripheral device interconnection topology corresponding to the first root port of the host machine, including being responsible for simulating and generating the quick peripheral device interconnection bridge device and the quick peripheral device interconnection terminal device included in the specific structure of the first quick peripheral device interconnection topology, and is also responsible for configuring various functional characteristics of the quick peripheral device interconnection terminal device and allocating memory space for all quick peripheral device interconnection terminal devices to store identification information (such as bus-device-function identification information) and configuration space information; on the other hand, the message transceiver hardware is responsible for providing the message forwarding hardware engine function, and is also responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue, specifically, being responsible for caching the transaction layer data packet message received from the host machine side to the first transaction layer data packet receiving queue, and being responsible for sending the transaction layer data packet message in the first transaction layer data packet sending queue to the host machine. Such an overall optimization design realizes the division of labor between the decoupled software and hardware. On the one hand, the system simulator software is not responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue, and therefore is not responsible for sending the transaction layer data packet message to the host machine through the first root port and receiving the transaction layer data packet message sent by the host machine through the first root port. In this way, the system simulator software performs message processing on the basis that the message transceiver hardware is responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue. For example, the system simulator software such as the ECPU simulator puts the transaction layer data packet message to be sent to the host machine into the corresponding first transaction layer data packet sending queue, and then the message transceiver hardware sends it to the host machine. On the other hand, the message transceiver hardware is unaware of the relevant modifications to the first quick peripheral device interconnection topology, that is, the system simulator software can modify the quick peripheral device interconnection topology, such as adding new quick peripheral device interconnection functional characteristics, and the message transceiver hardware may be unaware of this modification. By retaining the interaction between software and hardware, that is, the interaction between the system simulator software and the message transceiver hardware, a bridge can be established between the system simulator software and the message transceiver hardware through the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue, so that the hardware side can meet the uplink and downlink requirements of the transaction layer data packet messages through the transaction layer data packet transceiver queue without knowing the specific PCIE topology structure or the changes in TLP message routing caused by changes in the PCIE topology.When the routing and response of the TLP message need to be adjusted in time with the modification of the PCIE topology, the system simulator software is responsible for parsing the TLP message header and performing routing selection, so as to ensure that the TLP message reaches the destination, such as a PCIE bridge device or a PCIE terminal device, via the correct routing method. In addition, because the hardware side is unaware of the relevant modifications to the first fast peripheral device interconnection topology, and the message transceiver hardware does not need to know the specific PCIE topology structure or the changes in the TLP message routing caused by the change of the PCIE topology when managing the transaction layer data packet transceiver queue, this means that the first fast peripheral device interconnection topology can be flexibly and dynamically modified without updating the hardware logic.

[0033] In conclusion, Figure 1 The software simulation method for a data processor shown in the figure realizes the division of labor between the decoupled software and the hardware through the overall optimization design. The system simulator software is responsible for simulating and generating the first quick peripheral device interconnection topology corresponding to the first root port of the host machine, and the message transceiver hardware is responsible for providing the message forwarding hardware engine function and managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue. In this way, the first quick peripheral device interconnection topology can be flexibly and dynamically modified according to the needs, and there is no need to update the hardware logic to ensure that the routing and response of the transaction layer data packet message are timely adjusted in coordination with the modification of the first quick peripheral device interconnection topology, which helps to maintain the message transceiver efficiency and improve the data transmission performance.

[0034] Figure 2 A reference provided for the embodiments of this application Figure 1 The software simulation method shown is a schematic diagram of a first quick peripheral device interconnection topology generated by system simulator software simulation. Figure 2 As shown, the host machine 201 includes a first root port 203. The message transceiver hardware 211 is responsible for managing the first transaction layer data packet receiving queue 213 and the first transaction layer data packet sending queue 215. The system simulator software 221 simulates and generates a first fast peripheral device interconnect topology 223. The first fast peripheral device interconnect topology 223 includes an upstream port 231, a downstream port A241, a downstream port B243, a downstream port C245, a fast peripheral device interconnect device A251, a fast peripheral device interconnect device B253, and a fast peripheral device interconnect device C255. It should be understood that Figure 2 The specific structure of the first peripheral device interconnect express topology 223 shown is only exemplary. The first peripheral device interconnect express topology 223 includes at least one peripheral device interconnect express bridge device and at least one peripheral device interconnect express terminal device. Figure 2The illustrated quick peripheral device interconnect device A251, quick peripheral device interconnect device B253, and quick peripheral device interconnect device C255 include at least one quick peripheral device interconnect bridge device and at least one quick peripheral device interconnect terminal device. In some embodiments, Figure 2 The first peripheral device interconnect express topology 223 shown may have more hierarchical structures, such as more upstream ports and downstream ports, so as to connect more peripheral device interconnect express devices. Figure 2 The first quick peripheral device interconnect topology shown in Figure 1 is shown in Figure 2. Figure 1 The software simulation method shown achieves flexible and dynamic modification of the quick peripheral device interconnection topology and helps maintain the message receiving and sending efficiency and improve the data transmission performance. It should be understood that Figure 2 The first transaction layer data packet receiving queue 213 and the first transaction layer data packet sending queue 215 are located in the frame of the message transceiving hardware 211. In some embodiments, considering that the storage resources of the message transceiving hardware 211 itself are limited, the first transaction layer data packet receiving queue 213 and the first transaction layer data packet sending queue 215 corresponding to the first root port 203 managed by the message transceiving hardware 211 are actually located in the memory used to support the operation of the system simulator software 221. Through the negotiation between the system simulator software 221 and the message transceiving hardware 211, the starting address and length of the memory allocated to the first transaction layer data packet receiving queue 213 and the first transaction layer data packet sending queue 215 are notified to the message transceiving hardware 211, so that the message transceiving hardware 211 manages them. In other embodiments, the first transaction layer data packet receiving queue 213 and the first transaction layer data packet sending queue 215 managed by the message transceiver hardware 211 are actually allocated storage resources of the message transceiver hardware 211, and therefore are actually located in the memory of the message transceiver hardware 211 itself.

[0035] See also Figure 1 and Figure 2In a possible implementation, through the interaction between the system simulator software and the message transceiver hardware, the first transaction layer data packet receiving queue is used to implement the message reception associated with the first quick peripheral device interconnection topology, including: storing the transaction layer data packet message sent by the host machine to the first transaction layer data packet receiving queue through the message transceiver hardware; detecting whether there is a transaction layer data packet message to be received in the first transaction layer data packet receiving queue according to a preset detection strategy through the system simulator software, and, when the transaction layer data packet message to be received is detected, parsing the message header of the transaction layer data packet message to be received to determine the message type of the transaction layer data packet message to be received, and then, selecting a routing method based on the message type of the transaction layer data packet message to be received, and forwarding the transaction layer data packet message to be received to the destination quick peripheral device interconnection device through the selected routing method. In this way, through the overall optimization design, the decoupled software and hardware are divided into two parts, the system simulator software is responsible for simulating and generating the first quick peripheral device interconnection topology corresponding to the first root port of the host machine, and the message transceiver hardware is responsible for providing the message forwarding hardware engine function, and is also responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue. For the message reception associated with the first quick peripheral device interconnection topology, on the basis that the message transceiver hardware is responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue, the system simulator software detects whether there is a transaction layer data packet message to be received in the first transaction layer data packet receiving queue according to the preset detection strategy, and if there is a transaction layer data packet message to be received, the transaction layer data packet message to be received is taken out from it for processing. The system simulator software parses the message header of the transaction layer data packet message to be received, obtains the message type of the transaction layer data packet message to be received, and then selects a suitable routing method according to the message type of the transaction layer data packet message to be received, thereby realizing routing path selection. In this way, the first express peripheral device interconnection topology can be flexibly and dynamically modified according to needs, and there is no need to update the hardware logic, so as to ensure that the routing and response of the transaction layer data packet message are adjusted in time with the modification of the first express peripheral device interconnection topology, which helps to maintain the message sending and receiving efficiency and improve the data transmission performance.

[0036] In some embodiments, selecting a routing mode based on the message type of the transaction layer data packet to be received includes: when the message type of the transaction layer data packet to be received indicates reading and writing of the configuration space, selecting an identification routing mode, and the identification routing mode uses the bus-device-function identification information in the message header of the transaction layer data packet to be received to forward the transaction layer data packet to be received to the destination quick peripheral device interconnect device. As mentioned above, the system simulator software parses the message header of the transaction layer data packet to be received, obtains the message type of the transaction layer data packet to be received, and then selects a suitable routing mode according to the message type of the transaction layer data packet to be received, thereby realizing routing selection. Generally, the reading and writing of the configuration space of the quick peripheral device interconnection bridge device and the quick peripheral device interconnection terminal device are suitable for adopting the identification routing mode, that is, the configuration request message uses the identification (ID)-based routing mode, and the ID-based routing mode generally uses the bus-device-function (BFD) identification information for routing selection, and finally reaches the destination. Here, the BFD identification information is used to address according to the device ID number. In this way, the first express peripheral device interconnect topology can be flexibly and dynamically modified according to needs, and there is no need to update the hardware logic, so that the routing and response of the transaction layer data packet message can be timely adjusted in coordination with the modification of the first express peripheral device interconnect topology, which helps to maintain the message sending and receiving efficiency and improve the data transmission performance.

[0037] In some embodiments, selecting a routing mode based on the message type of the transaction layer data packet to be received includes: when the message type of the transaction layer data packet to be received indicates the reading and writing of the base address register space, selecting an address routing mode, and the address routing mode uses the address information in the message header of the transaction layer data packet to be received to forward the transaction layer data packet to be received to the destination quick peripheral device interconnect device. As mentioned above, the system simulator software parses the message header of the transaction layer data packet to be received, obtains the message type of the transaction layer data packet to be received, and then selects a suitable routing mode according to the message type of the transaction layer data packet to be received, thereby realizing routing selection. Generally, the reading and writing of the base address register (Base Address Register, BAR) space of the quick peripheral device interconnect bridge device and the quick peripheral device interconnect terminal device are suitable for adopting the address routing mode, that is, the memory request message and the input and output request message use the address-based routing mode, and the address-based routing mode uses the address field in the TLP message for routing selection, and finally reaches the destination. Here, the address information contained in the address field in the TLP message refers to the mapping address of the internal space of the PCIE device in the memory. In this way, the first express peripheral device interconnection topology can be flexibly and dynamically modified according to needs, and there is no need to update the hardware logic, so as to ensure that the routing and response of the transaction layer data packet message are timely adjusted in coordination with the modification of the first express peripheral device interconnection topology, which helps to maintain the message sending and receiving efficiency and improve the data transmission performance.

[0038] In some embodiments, selecting a routing mode based on the message type of the transaction layer data packet message to be received includes: when the message type of the transaction layer data packet message to be received is a message type, selecting an implicit routing mode. As mentioned above, the system simulator software parses the message header of the transaction layer data packet message to be received, obtains the message type of the transaction layer data packet message to be received, and then selects a suitable routing mode according to the message type of the transaction layer data packet message to be received, thereby realizing routing path selection. Generally, only TLP messages of message type support implicit routing. In the PCIE bus, some messages communicate with the root complex (RC), where the root complex serves as a bridge between the PCIE bus and the front-end bus for access transaction conversion and storage address space conversion. One end of the RC can be connected to a central processing unit (CPU), and the other end can be connected to a quick peripheral device interconnection bridge device such as a PCIE switch. Therefore, the RC is the sender or receiver of the TLP message of this message type, and there is no need to specify an address or ID, that is, an implicit routing mode is adopted. TLP messages of message type can also support address routing mode and identification routing mode. In this way, the first express peripheral device interconnection topology can be flexibly and dynamically modified according to needs, and there is no need to update the hardware logic, so as to ensure that the routing and response of the transaction layer data packet message are adjusted in time with the modification of the first express peripheral device interconnection topology, which helps to maintain the message sending and receiving efficiency and improve the data transmission performance.

[0039] In some embodiments, the destination quick peripheral device interconnect device is a destination quick peripheral device interconnect bridge device in the at least one quick peripheral device interconnect bridge device, or a destination quick peripheral device interconnect terminal device in the at least one quick peripheral device interconnect terminal device. In this way, the first quick peripheral device interconnect topology can be flexibly and dynamically modified according to needs, and there is no need to update the hardware logic, so as to ensure that the routing and response of the transaction layer data packet message are timely adjusted in coordination with the modification of the first quick peripheral device interconnect topology, which helps to maintain the message sending and receiving efficiency and improve the data transmission performance.

[0040] In some embodiments, the system simulator software detects whether there is the transaction layer data packet message to be received in the first transaction layer data packet receiving queue according to the preset detection strategy, including: when the preset detection strategy is an interrupt mode strategy, the message transceiver hardware sends an interrupt signal to the system simulator software each time it stores the transaction layer data packet message sent by the host machine to the first transaction layer data packet receiving queue, and the system simulator software, in response to receiving the interrupt signal, detects whether there is the transaction layer data packet message to be received in the first transaction layer data packet receiving queue. In this way, through the overall optimization design, the decoupled division of labor between software and hardware is realized, the system simulator software is responsible for simulating and generating the first quick peripheral device interconnection topology corresponding to the first root port of the host machine, and the message transceiver hardware is responsible for providing the message forwarding hardware engine function, and is also responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue. Regarding the message reception associated with the first quick peripheral device interconnection topology, on the basis that the message transceiver hardware is responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue, the system simulator software detects whether there is a transaction layer data packet message to be received in the first transaction layer data packet receiving queue according to a preset detection strategy. If a transaction layer data packet message to be received is found, the transaction layer data packet message to be received is taken out from the first transaction layer data packet message for processing. The system simulator software parses the message header of the transaction layer data packet message to be received, obtains the message type of the transaction layer data packet message to be received, and then selects a suitable routing method according to the message type of the transaction layer data packet message to be received, thereby realizing routing path selection. Here, by adopting an interruption method strategy, that is, the message transceiver hardware sends an interruption signal to the system simulator software each time it stores the transaction layer data packet message sent by the host machine to the first transaction layer data packet receiving queue. The system simulator software, in response to receiving the interruption signal, detects whether there is the transaction layer data packet message to be received in the first transaction layer data packet receiving queue. In this way, it is helpful to reduce the system burden and improve resource utilization. Taking into account the processing time requirements of TLP messages, some servers require a higher response speed, for example, processing TLP messages within 50 milliseconds, otherwise it may cause a timeout. Some servers have lower response speed requirements and are suitable for adopting an interrupt strategy to reduce the system burden on the ECPU side.

[0041] In some examples, the system simulator software detects whether there is the transaction layer data packet message to be received in the first transaction layer data packet receiving queue according to the preset detection strategy, including: when the preset detection strategy is a polling mode strategy, the system simulator software polls to detect whether there is the transaction layer data packet message to be received in the first transaction layer data packet receiving queue. In this way, through the overall optimization design, the decoupled software and hardware are responsible for their respective division of labor, the system simulator software is responsible for simulating and generating the first fast peripheral device interconnection topology corresponding to the first root port of the host machine, and the message transceiver hardware is responsible for providing the message forwarding hardware engine function, and is responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue. For the message reception associated with the first fast peripheral device interconnection topology, on the basis that the message transceiver hardware is responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue, the system simulator software detects whether there is a transaction layer data packet message to be received in the first transaction layer data packet receiving queue according to the preset detection strategy, and if a transaction layer data packet message to be received is found, the transaction layer data packet message to be received is taken out from it for processing. The system simulator software parses the message header of the transaction layer data packet to be received, obtains the message type of the transaction layer data packet to be received, and then selects a suitable routing method according to the message type of the transaction layer data packet to be received, thereby realizing routing selection. Here, a polling strategy is adopted, that is, the system simulator software polls to detect whether there is the transaction layer data packet to be received in the first transaction layer data packet receiving queue, thereby ensuring the timely processing of the TLP message and the correctness of the function.

[0042] In some examples, when the data processor is used in an application scenario with high response speed requirements, the preset detection strategy is a polling mode strategy, and when the data processor is used in an application scenario with low response speed requirements, the preset detection strategy is an interruption mode strategy. Considering the requirements of TLP messages for processing time, some servers require a higher response speed, such as processing the TLP message within 50 milliseconds, otherwise a timeout may occur. These servers are suitable for adopting a polling mode strategy to ensure that the TLP message is processed in time and the correctness of the function. Some servers have lower requirements for response speed, so it is suitable to adopt an interruption mode strategy to reduce the system burden on the ECPU side.

[0043] In a possible implementation, the message sending associated with the first quick peripheral device interconnection topology is implemented by using the first transaction layer data packet sending queue through the interaction between the system simulator software and the message transceiver hardware, including: storing the transaction layer data packet message to be sent to the first transaction layer data packet sending queue through the system simulator software; and sending the transaction layer data packet message to be sent or the transaction layer data packet message to be responded to to the host machine through the message transceiver hardware when detecting that the transaction layer data packet message to be sent or the transaction layer data packet message to be responded to exists in the first transaction layer data packet sending queue. In this way, through the overall optimization design, the division of labor between the decoupled software and the hardware is realized, the system simulator software is responsible for simulating and generating the first quick peripheral device interconnection topology corresponding to the first root port of the host machine, and the message transceiver hardware is responsible for providing the message forwarding hardware engine function, and is also responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue. As for the message sending associated with the first quick peripheral device interconnection topology, on the basis that the message transceiver hardware is responsible for managing the first transaction layer data packet receiving queue and the first transaction layer data packet sending queue, the system simulator software stores the transaction layer data packet message to be sent to the first transaction layer data packet sending queue, so that, through the message transceiver hardware, when the transaction layer data packet message to be sent or the transaction layer data packet message to be responded is detected, the transaction layer data packet message to be sent or the transaction layer data packet message to be responded is sent to the host machine. In this way, if the transaction layer data packet message needs to be responded, or the system simulator software actively wants to send the transaction layer data packet message to the host machine, the transaction layer data packet message to be responded or the transaction layer data packet message to be sent is cached in the first transaction layer data packet sending queue, so that when the message transceiver hardware detects that there is a corresponding TLP message in the first transaction layer data packet sending queue, the TLP message can be taken out and sent to the host machine. In this way, the first express peripheral device interconnection topology can be flexibly and dynamically modified according to needs, and there is no need to update the hardware logic, so as to ensure that the routing and response of the transaction layer data packet message are adjusted in time with the modification of the first express peripheral device interconnection topology, which helps to maintain the message sending and receiving efficiency and improve the data transmission performance.

[0044] In a possible implementation, the software simulation method further includes: changing the first quick peripheral device interconnect topology through the configuration interface of the system simulator software, wherein the changing of the first quick peripheral device interconnect topology includes one or more of the following: increasing the number of downstream ports, reducing the number of downstream ports, using a multi-stage switch structure, increasing the functional characteristics of the quick peripheral device interconnect, reducing the functional characteristics of the quick peripheral device interconnect, increasing the quick peripheral device interconnect terminal devices, and reducing the quick peripheral device interconnect terminal devices. In this way, the first quick peripheral device interconnect topology can be flexibly and dynamically modified according to demand, and there is no need to update the hardware logic, so as to ensure that the routing and response of the transaction layer data packet message are timely adjusted in coordination with the modification of the first quick peripheral device interconnect topology, which helps to maintain the message sending and receiving efficiency and improve the data transmission performance.

[0045] In a possible implementation, the system simulator software completes the simulation and generation of the first peripheral device interconnection express topology, including allocating memory space for all peripheral device interconnection express bridge devices and all peripheral device interconnection express end devices in the first peripheral device interconnection express topology to store associated bus-device-function identification information and configuration space information. In this way, the first peripheral device interconnection express topology can be flexibly and dynamically modified according to needs, and without updating the hardware logic, it can ensure that the routing and response of the transaction layer data packet message is timely adjusted in coordination with the modification of the first peripheral device interconnection express topology, which helps to maintain the message sending and receiving efficiency and improve the data transmission performance.

[0046] In one possible implementation, the present application proposes a solution for implementing PCIE topology in software under a DPU scenario. Specifically, the ECPU simulator initializes the PCIE topology, and allocates memory space for all PCIE devices in the PCIE topology to store BDF information and configuration space information, and negotiates with the hardware to obtain a TLP receive queue and a TLP send queue. The hardware is responsible for caching the received TLP message on the host side into the TLP receive queue, and is also responsible for sending the TLP message in the TLP send queue to the host. The ECPU simulator is responsible for obtaining and processing TLP messages from the TLP receive queue, and is also responsible for caching TLP messages to be sent to the host side into the TLP send queue. The ECPU simulator parses the TLP message header and routes it to the PCIE bridge device or PCIE end device through ID routing or address routing according to the TLP message type. In this way, the PCIE topology can be flexibly and dynamically modified according to user needs, as well as new PCIE functions can be added.

[0047] Figure 33 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 300 includes: one or more processors 310, a communication interface 320 and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected via a bus 340. Optionally, the computing device 300 may also include an input / output interface 350, and the input / output interface 350 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 310 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 300 can refer to the specific details in the above-mentioned embodiments, such as the processor 310 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 300 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 320 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 310 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0048] It should be understood that Figure 3 The computing device 300 may include one or more processors 310, and the multiple processors 310 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 310 may form a processor sequence or a processor array, or the multiple processors 310 may be divided into a main processor and an auxiliary processor, or the multiple processors 310 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 3 The computing device 300 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 may include Figure 3 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0049] The processor 310 may have a variety of specific implementation forms. For example, the processor 310 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 310 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 320 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0050] The memory 330 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 330 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 330 may also be used to store program codes and data, so that the processor 310 calls the program codes stored in the memory 330 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 3 Show more or fewer components, or have different component configurations.

[0051] The bus 340 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 340 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 340 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0052] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0053] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0054] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0055] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0056] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A software simulation method for a data processor, characterized in that: The software simulation method comprises: Simulate and generate a first peripheral device interconnection express topology corresponding to a first root port of a host machine through system simulator software of a data processor, wherein the first peripheral device interconnection express topology includes at least one peripheral device interconnection express bridge device and at least one peripheral device interconnection express terminal device; At least before the system simulator software completes the simulation and generation of the first peripheral device interconnect express topology, the system simulator software negotiates with the message transceiver hardware to generate a first transaction layer data packet receiving queue and a first transaction layer data packet sending queue corresponding to the first root port managed by the message transceiver hardware, wherein the system simulator software completes the simulation and generation of the first peripheral device interconnect express topology including, respectively allocating memory space for storing associated bus-device-function identification information and configuration space information to all peripheral device interconnect express bridge devices and all peripheral device interconnect express end devices in the first peripheral device interconnect express topology; The method includes: using the first transaction layer data packet receiving queue to realize the message reception associated with the first fast peripheral device interconnection topology, and using the first transaction layer data packet sending queue to realize the message sending associated with the first fast peripheral device interconnection topology, including: The transaction layer data packet message sent by the host machine is stored in the first transaction layer data packet receiving queue through the message receiving and sending hardware; Through the system simulator software, a preset detection strategy is used to detect whether there is a transaction layer data packet message to be received in the first transaction layer data packet receiving queue, and when the transaction layer data packet message to be received is detected, the message header of the transaction layer data packet message to be received is parsed to determine the message type of the transaction layer data packet message to be received, and then a routing method is selected based on the message type of the transaction layer data packet message to be received, and the transaction layer data packet message to be received is forwarded to the destination quick peripheral device interconnection device through the selected routing method.

2. The software simulation method according to claim 1, characterized in that: A routing method is selected based on the message type of the transaction layer data packet message to be received, including: when the message type of the transaction layer data packet message to be received indicates reading and writing of the configuration space, an identification routing method is selected, and the identification routing method uses the bus-device-function identification information in the message header of the transaction layer data packet message to be received to forward the transaction layer data packet message to be received to the destination quick peripheral device interconnect device.

3. The software simulation method according to claim 1, characterized in that: A routing method is selected based on the message type of the transaction layer data packet message to be received, including: when the message type of the transaction layer data packet message to be received indicates reading and writing of the base address register space, an address routing method is selected, and the address routing method uses the address information in the message header of the transaction layer data packet message to be received to forward the transaction layer data packet message to be received to the destination quick peripheral device interconnect device.

4. The software simulation method according to claim 1, characterized in that: Selecting a routing mode based on the message type of the transaction layer data packet to be received includes: when the message type of the transaction layer data packet to be received is a message type, selecting an implicit routing mode.

5. The software simulation method according to claim 1, characterized in that: The destination peripheral device interconnect express device is a destination peripheral device interconnect express bridge device in the at least one peripheral device interconnect express bridge device, or a destination peripheral device interconnect express terminal device in the at least one peripheral device interconnect express terminal device.

6. The software simulation method according to claim 1, characterized in that: Detecting, by the system simulator software, whether there is the transaction layer data packet message to be received in the first transaction layer data packet receiving queue according to the preset detection strategy includes: When the preset detection strategy is an interrupt mode strategy, the message sending and receiving hardware sends an interrupt signal to the system simulator software each time it stores the transaction layer data packet message sent by the host machine to the first transaction layer data packet receiving queue. In response to receiving the interrupt signal, the system simulator software detects whether there is the transaction layer data packet message to be received in the first transaction layer data packet receiving queue.

7. The software simulation method according to claim 6, characterized in that: Detecting, by the system simulator software, whether there is the transaction layer data packet message to be received in the first transaction layer data packet receiving queue according to the preset detection strategy includes: When the preset detection strategy is a polling strategy, the system simulator software polls to detect whether there is the to-be-received transaction layer data packet message in the first transaction layer data packet receiving queue.

8. The software simulation method according to claim 7, characterized in that: When the data processor is used in an application scenario with high response speed requirements, the preset detection strategy is a polling mode strategy, and when the data processor is used in an application scenario with low response speed requirements, the preset detection strategy is an interruption mode strategy.

9. The software simulation method according to claim 1, characterized in that: The method of implementing the message sending associated with the first fast peripheral device interconnection topology by using the first transaction layer data packet sending queue through the interaction between the system simulator software and the message sending and receiving hardware includes: By means of the system simulator software, storing the transaction layer data packet message to be sent in the first transaction layer data packet sending queue; Through the message receiving and sending hardware, when it is detected that the transaction layer data packet message to be sent or the transaction layer data packet message to be responded to exists in the first transaction layer data packet sending queue, the transaction layer data packet message to be sent or the transaction layer data packet message to be responded to is sent to the host machine.

10. The software simulation method according to claim 1, characterized in that: The software simulation method further comprises: The first quick peripheral device interconnect topology is changed through the configuration interface of the system simulator software, wherein the changing of the first quick peripheral device interconnect topology includes one or more of the following: increasing the number of downstream ports, reducing the number of downstream ports, using a multi-stage switch structure, increasing quick peripheral device interconnect functional characteristics, reducing quick peripheral device interconnect functional characteristics, increasing quick peripheral device interconnect terminal devices, and reducing quick peripheral device interconnect terminal devices.

11. A computer device, characterized in that: The computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 10 when executing the computer program.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 10.

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