Display device and electronic terminal

Abstract

The present invention provides a display device and an electronic terminal, wherein a first output control module in a gate driving unit can control the electrical connection or disconnection of a stage transmission module and an output module according to a frequency division signal transmitted by a frequency division line, the output module is used to generate a gate signal transmitted to the gate line of the current stage, and a second output control module is electrically connected to the output module and is used to transmit a first signal to the output module when the stage transmission module and the output module are electrically disconnected, so as to control the gate signal output by the output module to maintain a second signal, thereby achieving differentiated settings of refresh rates in different areas of the display device while avoiding erroneous light emission of sub-pixels within the surface.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device and an electronic terminal. Background Art

[0002] Because the content of a display screen varies across different regions, the refresh rate requirements for each region also vary. However, traditional gate drive circuits can only switch the refresh rate for the entire panel and cannot differentiate refresh rates by region, hindering the realization of low power consumption for the display. Summary of the Invention

[0003] The present invention provides a display device and an electronic terminal to improve the problem that a gate driving circuit cannot realize differentiated settings of refresh rates in different areas of a display screen.

[0004] An embodiment of the present invention provides a display device, comprising a plurality of sub-pixels and a gate driving circuit electrically connected to the plurality of sub-pixels, wherein the gate driving circuit comprises a plurality of cascaded gate driving units, and the gate driving unit comprises:

[0005] a level transmission module, electrically connected to a frame start line or a level transmission line of the upper-level gate driving unit, for generating a level transmission signal transmitted to the level transmission line of the current level according to a frame start signal transmitted by the frame start line or a level transmission signal transmitted by the level transmission line of the upper-level gate driving unit;

[0006] Output module;

[0007] a first output control module, electrically connected to the frequency division line, and further electrically connected to the stage transmission module via a first node and electrically connected to the output module via a second node, for controlling the electrical connection or disconnection between the first node and the second node according to the frequency division signal transmitted by the frequency division line, and the output module for generating a gate signal of the current stage to be transmitted to the gate line of the current stage according to the signal of the second node;

[0008] A second output control module is electrically connected to the output module through the second node, and is used to transmit the first signal to the second node when the first node is electrically disconnected from the second node, so as to control the gate signal output by the output module to be a second signal to control the corresponding multiple sub-pixels not to emit light.

[0009] In some embodiments, the stage transmission module is electrically connected to a third node, and a signal of the third node is inversely proportional to a signal of the first node;

[0010] The second output control module is also electrically connected to the frequency division line, and the second output control module is also electrically connected to the stage transmission module through at least one of the first node and the third node. The second output control module is used to control the signal of the second node according to the signal of the first node, at least one of the signal of the third node and the frequency division signal.

[0011] In some embodiments, the output module is further electrically connected to the stage transmission module via the third node, and the output module is further configured to generate the gate signal according to a signal of the third node.

[0012] In some embodiments, the second output control module includes:

[0013] a first transistor, wherein one of a source and a drain of the first transistor is electrically connected to a first voltage line for transmitting the first signal, the other of the source and the drain of the first transistor is electrically connected to the second node, and the gate of the first transistor is electrically connected to a fourth node;

[0014] The signal of the first node, at least one of the signals of the third node, and the frequency-divided signal control the signal of the fourth node, and the first transistor is used to control the first voltage line to be electrically connected or electrically disconnected with the second node according to the signal of the fourth node.

[0015] In some embodiments, the second output control module further includes:

[0016] a second transistor, wherein one of a source and a drain of the second transistor is electrically connected to the second voltage line, the other of the source and the drain of the second transistor is electrically connected to the fourth node, and the gate of the second transistor is electrically connected to the third node;

[0017] a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to a third voltage line, the other of the source and the drain of the third transistor is electrically connected to the fourth node, and a gate of the third transistor is connected to the fourth node;

[0018] a fourth transistor, wherein one of the source and the drain of the fourth transistor is electrically connected to the first node, the other of the source and the drain of the fourth transistor is electrically connected to the gate of the third transistor, and the gate of the fourth transistor is electrically connected to the frequency division line.

[0019] In some embodiments, the second output control module further includes:

[0020] a fifth transistor, wherein one of the source and the drain of the fifth transistor is electrically connected to the fourth voltage line, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, and the gate of the fifth transistor is electrically connected to the third node.

[0021] In some embodiments, the first output control module includes:

[0022] a sixth transistor, wherein one of the source and the drain of the sixth transistor is electrically connected to the first node, the other of the source and the drain of the sixth transistor is electrically connected to the second node, and the gate of the sixth transistor is electrically connected to the frequency division line.

[0023] In some embodiments, the stage transmission module includes:

[0024] a level transmission input module, electrically connected to the frame start line or the level transmission line of the upper gate driving unit, for controlling the signal of the first node according to the frame start signal or the upper level transmission signal;

[0025] a level transmission output module, electrically connected to the level transmission input module via the first node, and configured to generate the level transmission signal of the current level according to the signal of the first node;

[0026] In which, the stage transmission output module includes a seventh transistor and a first capacitor, one of the source and the drain of the seventh transistor is electrically connected to the first signal line, the other of the source and the drain of the seventh transistor is electrically connected to the stage transmission line of the current level, the gate of the seventh transistor is electrically connected to the first node, and the first capacitor is electrically connected between the source and the drain of the seventh transistor.

[0027] In some embodiments, at least within one frame, the frequency-divided signal is used to control the gate signal output by at least one gate driving unit to cause the corresponding multiple sub-pixels to emit light, and is used to control the gate signal output by at least one gate driving unit to cause the corresponding multiple sub-pixels not to emit light.

[0028] In some embodiments, the stage transmission module is electrically connected to a third node, the second output control module includes a first transistor, one of a source and a drain of the first transistor is electrically connected to a first voltage line for transmitting a low-voltage signal, the other of the source and the drain of the first transistor is electrically connected to the second node, and the gate of the first transistor is electrically connected to a fourth node;

[0029] The working period of the gate drive circuit includes:

[0030] In the first stage, for the gate drive unit of the current stage, the frequency-divided signal is used to control the electrical connection between the first node and the second node, the stage transmission signal of the previous stage is used to control the positive scanning signal to be transmitted to the first node to pull up the potential of the first node, and the low-voltage signal to be transmitted to the third node to pull down the potential of the third node;

[0031] wherein the low voltage signal is transmitted to the fourth node to turn off the first transistor;

[0032] Wherein, a third clock signal of low potential is transmitted to the stage transmission line and the gate line.

[0033] In some embodiments, the gate drive circuit's operating period further includes:

[0034] In a second stage following the first stage, for the gate driving unit of this stage, the divided frequency signal is used to control the first node and the second node to be electrically disconnected, and the first node and the third node are respectively maintained at their potentials in the first stage to turn off the first transistor;

[0035] The third clock signal, which is a high-voltage signal, is transmitted to the stage transmission line, the gate line, and the stage transmission line.

[0036] In some embodiments, in the second stage, for the gate driving unit of the next stage, the stage transmission signal of the current stage is used to control the positive scan signal to be transmitted to the first node to pull up the potential of the first node, and the low voltage signal to be transmitted to the third node to pull down the potential of the third node;

[0037] Wherein, the first transistor is turned on, and the potential of the second node is pulled down by the low-voltage signal;

[0038] Wherein, a first clock signal of low potential is transmitted to the stage transmission line, and the gate line is maintained at a low potential.

[0039] In some embodiments, the gate drive circuit's operating period further includes:

[0040] In a third stage following the second stage, for the gate driving unit of this stage, the divided frequency signal is used to control the electrical disconnection of the first node and the second node, and the low voltage signal is transmitted to the first node, the stage transmission line, and the gate line to pull down the potentials of the three.

[0041] wherein a high voltage signal is transmitted to the fourth node to turn off the first transistor, thereby pulling down the potential of the second node;

[0042] Wherein, the low voltage signal is transmitted to the stage transmission line and the gate line.

[0043] In some embodiments, in the third stage, for the gate driving unit of the next stage, the first node maintains a previous high potential, and the third node maintains a previous low potential;

[0044] Wherein, the potential of the second node is pulled down by the low voltage signal;

[0045] The first clock signal of high potential is transmitted to the stage transmission line, and the gate line is maintained at a low potential.

[0046] An embodiment of the present invention further provides an electronic terminal, comprising any display device as described above.

[0047] The present invention provides a display device and an electronic terminal, which are based on a first output control module electrically connected to a stage transmission module through a first node and electrically connected to an output module through a second node, and is used to control the electrical connection or electrical disconnection of the first node and the second node according to a frequency division signal transmitted by a frequency division line, and the output module is used to generate a gate signal transmitted to the gate line of this level according to the signal of the second node. A second output control module electrically connected to the output module through a second node is also provided, and is used to transmit the first signal to the second node when the first node and the second node are electrically disconnected, so as to control the gate signal output by the output module to be a second signal to control the corresponding multiple sub-pixels not to emit light, thereby achieving differentiated settings of the refresh rates of different areas of the display device while avoiding the sub-pixels within the surface from emitting light by mistake. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A schematic diagram of the structure of a display device provided by an embodiment of the present invention.

[0049] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of the present invention.

[0050] Figure 3 This is a waveform diagram of some signals in the pixel driving circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0052] In the description of the present invention, the terms "first", "second" and the like are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In this article, no distinction is made between the source and drain of the transistor, and the two can be set interchangeably. In addition, it should be noted that the drawings only provide structures that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings so that the invention points are clear at a glance, rather than to indicate that the actual device is the same as the attached drawings. Figure 1 The same is not a limitation of the actual device.

[0053] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0054] The present invention provides a display device, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0055] In one embodiment, if Figure 1 As shown, the display device 100 includes a plurality of sub-pixels Pi, a gate driving circuit 10 electrically connected to the plurality of sub-pixels Pi, and the gate driving circuit 10 includes a plurality of cascaded gate driving units 20, as shown in FIG. Figure 2As shown, the gate driving unit 20 (taking the n-th stage gate driving unit 20 as an example, where n is a positive integer) includes: a level transmission module 201, electrically connected to the frame start line L1 (when n=1) or the level transmission line L2(n-1) of the upper stage (i.e., the (n-1)-th stage, where n≥2), for generating a level transmission signal Carry(n) transmitted to the level transmission line L2(n) of the current stage (i.e., the n-th stage) according to the frame start signal STV transmitted by the frame start line L1 or the level transmission signal Carry(n-1) transmitted by the level transmission line L2(n-1) of the upper stage gate driving unit 20; an output module 202; a first output control module 203, electrically connected to the frequency dividing line L3, and further electrically connected to the level transmission module 201 through a first node Q and electrically connected to the output module 202 through a second node N, for The first node Q and the second node N are electrically connected or disconnected according to the frequency division signal SW transmitted by the frequency division line L3. The output module 202 is used to generate a gate signal OUT(n) of the current level (when n=1, it is referred to as the gate line L4(1) output gate signal OUT(1)) transmitted to the gate line L4(n) of the current level according to the signal of the second node N; the second output control module 204 is electrically connected to the output module 202 through the second node N, and is used to transmit a first signal (for example, a low voltage signal VGL) to the second node N when the first node Q and the second node N are electrically disconnected, so as to control the gate signal OUT(n) output by the output module 202 to be a second signal (for example, a low potential signal of the gate signal OUT(n)) so as to control the corresponding multiple sub-pixels Pi not to emit light.

[0056] in, Figure 1 In the description, the gate driving circuit 10 includes N (N≥2) stages of cascaded gate driving units 20 as an example. The first-stage gate driving unit 20 can output the first-stage level transmission signal Carry(1) to the second-stage gate driving unit 20 according to the frame start signal STV, and transmit the first-stage gate signal OUT(1) to the corresponding multiple sub-pixels Pi. Similarly, the (N-1)-th stage gate driving unit 20 can output the (N-1)-th level transmission signal Carry(n-1) to the N-th stage gate driving unit 20 according to the (N-2)-th level transmission signal Carry(N-2), and transmit the (N-1)-th level gate signal OUT(N-1) to the corresponding multiple sub-pixels Pi. The (N)-th stage gate driving unit 20 can transmit the (N)-th level gate signal OUT(N) to the corresponding multiple sub-pixels Pi according to the (N-1)-th level transmission signal Carry(N-1).

[0057] in, Figure 2Taking the n-th stage gate driving unit 20 as an example, since the first output control module 203 is connected between the stage transmission module 201 and the output module 202, and can control the electrical connection or disconnection of the first node Q and the second node N according to the frequency division signal SW, thereby controlling whether the signal of the second node N electrically connected to the output module 202 can be controlled by the stage transmission module 201, and further controlling whether the output module 202 normally outputs the gate signal OUT(n). However, since the stage transmission line L2(n) is electrically connected to the stage transmission module 201, the stage transmission signal Carry(n) can be normally output. The first output control module 203 includes: a sixth transistor NT19, one of the source and the drain of the sixth transistor NT19 is electrically connected to the first node Q, the other of the source and the drain of the sixth transistor NT19 is electrically connected to the second node N, and the gate of the sixth transistor NT19 is electrically connected to the frequency division line L3.

[0058] Specifically, here, taking the high potential signal and the low potential signal of the frequency-divided signal SW as an example to control the electrical connection and disconnection of the first node Q and the second node N, respectively, by controlling the time period of the high potential signal of the frequency-divided signal SW acting simultaneously on the multiple-stage gate driving unit 20, it is possible to control which stages of the gate driving unit 20 have the first node Q and the second node N electrically connected. If the time when the first node Q and the second node N are electrically connected is before the effective potential of the first node Q, the gate driving unit 20 of that stage can normally output the gate signal OUT(n), thereby controlling the light emission of the corresponding multiple sub-pixels Pi. That is, within at least one frame, the frequency-divided signal SW is used to control the gate signal OUT(i) (N≥i≥1) output by at least one gate driving unit 20 to cause the corresponding multiple sub-pixels Pi to emit light, and to control the gate signal OUT(j) (N≥j≥1, and j is not equal to i) output by at least one gate driving unit 20 to cause the corresponding multiple sub-pixels Pi to not emit light.

[0059] In summary, if the frequency-dividing signal SW is always at its high potential signal in a frame, it is considered that the N-level gate driving units 20 in the frame can normally output the gate signal OUT(1) to the gate signal OUT(N); if the frequency-dividing signal SW is at its low potential signal in part of the time period in a frame, it is considered that the several levels of gate driving units 20 in the frame whose first node Q is the effective potential only in the "part of the time period" cannot normally output their corresponding several levels of gate signals, so that the corresponding several rows of sub-pixels Pi do not emit light. Then, when performing continuous multi-frame display, the refresh rate of the area where the several rows of sub-pixels Pi that do not emit light in several frames are located is lower than that of the area where the row of sub-pixels Pi that emit light in all frames are located, thereby achieving differentiated setting of the refresh rates of different areas of the display device 100 and reducing power consumption.

[0060] Among them, Figure 2 As shown, taking the n-th stage gate driving unit 20 as an example, the stage transmission module 201 includes: a stage transmission input module 2011, electrically connected to the frame start line L1 or the stage transmission line L2 (n-1) of the upper gate driving unit 20, for controlling the signal of the first node Q according to the frame start signal STV or the stage transmission signal Carry (n-1) of the upper stage; a stage transmission output module 2012, electrically connected to the stage transmission input module 2011 through the first node Q, for generating the stage transmission signal Carry (n) of this stage according to the signal of the first node Q; wherein the stage transmission output module 2012 includes a seventh transistor NT15 and a first capacitor C1, one of the source and the drain of the seventh transistor NT15 is electrically connected to a signal line (for example, L9 for transmitting the first clock signal CK1, L10 for transmitting the second clock signal CK2, or L11 for transmitting the third clock signal CK3), the other of the source and the drain of the seventh transistor NT15 is electrically connected to the stage transmission line L2(n) of the current stage, the gate of the seventh transistor NT15 is electrically connected to the first node Q, and the first capacitor C1 is electrically connected between the source and the drain of the seventh transistor NT15.

[0061] Furthermore, the first node Q can be electrically connected to the gate of the seventh transistor NT15 through the normally-on eighth transistor NT7, one of the source and the drain of the eighth transistor NT7 can be electrically connected to the first node Q, the gate of the seventh transistor NT15 and the other of the source and the drain of the eighth transistor NT7 can be electrically connected to the fifth node Qa, the gate of the eighth transistor NT7 can be loaded with, for example, a high-voltage signal VGH to maintain its normal conduction, and the eighth transistor NT7 can reduce the influence of the ultra-high or ultra-low potential of the fifth node Qa on the potential of the first node Q, so as to improve the stability of the operation of the gate drive unit 20.

[0062] It can be understood that the stage transfer input module 2011 controls the signal of the first node Q according to the frame start signal STV or the stage transfer signal Carry(n-1) of the upper stage. The first node Q is electrically connected to the gate of the seventh transistor NT15, so the seventh transistor NT15 can be controlled by the signal of the first node Q to generate the stage transfer signal Carry(n) of this stage, and the first capacitor C1 electrically connected between the source and the drain of the seventh transistor NT15 can make the frequency division signal SW change from its low potential signal to a high potential signal. Even if the sixth transistor NT19 divides the voltage of the first node Q, it will not have a significant impact on the potential of the fifth node Qa, thereby reducing the impact on the working state of the seventh transistor NT15.

[0063] Based on the setting of the above-mentioned first output control module 203, a second output control module 204 electrically connected to the output module 202 through the second node N is set in this embodiment. Since it is set to transmit the first signal (for example, the low-voltage signal VGL) to the second node N when the first node Q and the second node N are electrically disconnected, it prevents the second node N from being in a suspended state when it is not controlled by the signal of the first node Q, and thereafter the second node N potential cannot be restored to a specific potential or is coupled by the potential of other nodes. Instead, the second node N can be loaded as the first signal (for example, the low-voltage signal VGL) output by the second output control module 204, thereby controlling the gate signal OUT(n) output by the output module 202 to be the second signal (for example, the low-voltage signal of the gate signal OUT(n)), so as to control the corresponding multiple sub-pixels Pi to not emit light, thereby avoiding false light emission.

[0064] In some embodiments, as Figure 2 As shown, the stage transmission module 201 is electrically connected to the third node P, and the signal of the third node P is inverted with the signal of the first node Q; the second output control module 204 is also electrically connected to the frequency division line L3, and the second output control module 204 is also electrically connected to the stage transmission module 201 through at least one of the first node Q and the third node P. The second output control module 204 is used to control the signal of the second node N according to the signal of the first node Q, at least one of the signal of the third node P and the frequency division signal SW.

[0065] Specifically, the stage transmission input module 2011 in the stage transmission module 201 may include a ninth transistor NT1 and a tenth transistor NT16, the gate of the ninth transistor NT1 may be electrically connected to the frame start line L1 or the stage transmission line L2(n-1) of the upper gate driving unit 20, one of the source and the drain of the ninth transistor NT1 may be electrically connected to the positive scan line for transmitting the positive scan signal U2D, the other of the source and the drain of the ninth transistor NT1 and the gate of the tenth transistor NT16 may all be electrically connected to the first node Q, one of the source and the drain of the tenth transistor NT16 may be loaded with the low voltage signal VGL, and the other of the source and the drain of the tenth transistor NT16 may be electrically connected to the third node P.

[0066] During the forward scanning process, the forward scanning signal U2D can be a corresponding high-voltage signal that is transmitted to the first node Q when the ninth transistor NT1 is turned on to control the seventh transistor NT15 and the tenth transistor NT16 to be turned on, thereby transmitting the low-voltage signal VGL to the third node P. Furthermore, the stage transmission module 201 can also include an eleventh transistor NT5 and a twelfth transistor NT8. One of the source and the drain of the eleventh transistor NT5 is respectively loaded with the low-voltage signal VGL and electrically connected to the first node Q. The gate of the eleventh transistor NT5 is electrically connected to the third node P. One of the source and the drain of the twelfth transistor NT8 is respectively loaded with the high-voltage signal VGH and electrically connected to the third node P. When the first node Q and the twelfth transistor NT8 are turned on to pull up the potential of the third node P and the eleventh transistor NT5 is turned on, the potential of the first node Q is pulled down. Therefore, the signal at the third node P is in phase with the signal at the first node Q.

[0067] It can be understood that in this embodiment, the second output control module 204 is used to control the signal of the second node N according to at least one of the signal of the first node Q, the signal of the third node P, and the frequency division signal SW. On the one hand, the signal of the second node N can at least change with the change of the frequency division signal SW, and at least transmit the first signal (for example, the low voltage signal VGL) to the second node N when the first node Q and the second node N are electrically disconnected. On the other hand, the signal of the second node N is also controlled by the signal of the first node Q (regardless of whether the second output control module 204 is electrically connected to the first node Q or the third node P), so as to set the potential of the second node N to be related to the potential of the first node Q at least when the first node Q and the second node N are electrically connected, thereby controlling the gate signal OUT(n).

[0068] Further, such as Figure 2As shown, taking the n-th stage gate driving unit 20 as an example, the output module 202 is further electrically connected to the stage transmission module 201 via the third node P, and the output module 202 is further configured to generate the gate signal OUT(n) according to the signal of the third node P. Specifically, the stage transmission module 201 may further include a thirteenth transistor NT16, and the output module 202 may further include a fourteenth transistor NT10, the gates of the two transistors being electrically connected to the third node P, one of the source and drain of the two transistors being loaded with the low voltage signal VGL, and the other of the source and drain of the two transistors being electrically connected to the stage transmission line L2(n) and the gate line L4(n), respectively. That is, the working processes of the two transistors are the same, and the stage transmission signal Carry(n) and the gate signal OUT(n) are both related to the signal of the third node P.

[0069] In some embodiments, as Figure 2 As shown, the second output control module 204 includes: a first transistor NT20, one of the source and the drain of the first transistor NT20 is electrically connected to the first voltage line L5 for transmitting the first signal (for example, the low voltage signal VGL), the other of the source and the drain of the first transistor NT20 is electrically connected to the second node N, and the gate of the first transistor NT20 is electrically connected to the fourth node F; wherein, the signal of the first node N, at least one of the signal of the third node P and the frequency division signal SW control the signal of the fourth node F, and the first transistor NT20 is used to control the first voltage line L5 to be electrically connected or electrically disconnected with the second node N according to the signal of the fourth node F.

[0070] That is, in this embodiment, the signal at the gate of the first transistor NT20 (electrically connected to the fourth node F) is controlled by at least one of the signal at the first node N, the signal at the third node P, and the frequency-divided signal SW, thereby controlling whether the first transistor NT20 is turned on, and further controlling whether the first signal (e.g., the low-voltage signal VGL) is transmitted to the second node N.

[0071] Specifically, such as Figure 2As shown, the second output control module 204 further includes: a second transistor NT24, one of the source and the drain of the second transistor NT24 is electrically connected to the second voltage line L6 (for example, for transmitting the high-voltage signal VGH), the other of the source and the drain of the second transistor NT24 is electrically connected to the fourth node F, and the gate of the second transistor NT24 is electrically connected to the third node P; a third transistor NT23, one of the source and the drain of the third transistor NT23 is electrically connected to the third voltage line L7 (for example, for transmitting the low-voltage signal VGL), the other of the source and the drain of the third transistor NT23 is electrically connected to the fourth node F; a fourth transistor NT21, one of the source and the drain of the fourth transistor NT21 is electrically connected to the first node Q, the other of the source and the drain of the fourth transistor NT21 is electrically connected to the gate of the third transistor NT23, and the gate of the fourth transistor NT21 is electrically connected to the frequency dividing line L3.

[0072] It can be seen that the second transistor NT24 in this embodiment can control whether to transmit the high-voltage signal VGH to the fourth node F according to the signal of the third node P so as to lower the potential of the second node N, and the fourth transistor NT21 can jointly control whether to transmit the low-voltage signal VGL to the fourth node F according to the frequency division signal SW and the signal of the first node Q so as to maintain the potential of the first node N at the original potential.

[0073] Further, such as Figure 2 As shown, the second output control module 204 also includes: a fifth transistor NT22, one of the source and the drain of the fifth transistor NT22 is electrically connected to the fourth voltage line L8 (for example, for transmitting the low voltage signal VGL), and the other of the source and the drain of the fifth transistor NT22 is electrically connected to the gate of the third transistor NT23, and the gate of the fifth transistor NT22 is electrically connected to the third node P.

[0074] In particular, since the gate of the fifth transistor NT22 is also electrically connected to the third node P, it can be considered that the fifth transistor NT22 and the second transistor NT24 are of the same type. Therefore, it can be considered that the conduction condition of the fifth transistor NT22 is the same as the conduction condition of the second transistor NT24. When the second transistor NT24 is turned on, since the fifth transistor NT22 is also turned on, the low-voltage signal VGL can be transmitted to the gate of the third transistor NT23 to turn off the third transistor NT23, thereby avoiding the third transistor NT23 from being turned on when the second transistor NT24 is turned on, thereby avoiding the second transistor NT24 from being unable to pull up the potential of the fourth node F, and reducing the risk that the potential of the first node N cannot be pulled down.

[0075] In order to better illustrate the function of the gate driving unit 20 in the present invention, the details of the gate driving unit 20 are further described here.

[0076] like Figure 2 As shown, the level transmission input module 2011 may further include a fifteenth transistor NT3, one of the source and the other of the drain of the fifteenth transistor NT3 being loaded with a clock signal (the first clock signal CK1, the second clock signal CK2, or the third clock signal CK3), respectively, and electrically connected to the gate of the twelfth transistor NT8, and the gate of the fifteenth transistor NT3 being electrically connected to the positive scan line. The output module 202 also includes a sixteenth transistor NT9 corresponding to the seventh transistor NT15 in the level transmission module 201. The difference between the sixteenth transistor NT9 and the seventh transistor NT15 is that the gate of the sixteenth transistor NT9 is electrically connected to the second node N instead of the fifth node Qa (electrically connected to the first node Q). Therefore, the gate signal OUT(n) output by the output module 202 can be controlled by the second node N, and thus controlled by the frequency division signal SW, ultimately achieving differentiated refresh rate settings for different areas of the display device 100.

[0077] In order to realize the reverse scan function, the level transfer input module 2011 can also include a seventeenth transistor NT4 corresponding to the fifteenth transistor NT3 and an eighteenth transistor NT2 corresponding to the ninth transistor NT1. The difference is that the gate of the seventeenth transistor NT4 is electrically connected to the reverse scan line for transmitting the reverse scan signal D2U instead of the positive scan line, and one of the source and the drain of the seventeenth transistor NT4 is loaded with another clock signal different from the clock signal loaded by one of the source and the drain of the fifteenth transistor NT3. Correspondingly, one and the other of the source and the drain of the eighteenth transistor NT2 are electrically connected to the reverse scan line and the first node Q respectively, and the gate of the eighteenth transistor NT2 is loaded with the level transfer signal Carry(n-1) of the next level.

[0078] Combined with the above discussion, during the forward scanning process, the forward scanning signal U2D is the corresponding high-potential signal, the reverse scanning signal D2U is the corresponding low-potential signal, and the valid pulse in the frame start signal STV or the upper-level transmission signal Carry(n-1) can control the first node Q to be the corresponding potential, thereby realizing step-by-step forward scanning. During the reverse scanning process, the forward scanning signal U2D is the corresponding high-potential signal, the reverse scanning signal D2U is the corresponding low-potential signal, and the valid pulse in the lower-level transmission signal Carry(n+1) can control the first node Q to be the corresponding potential, thereby realizing step-by-step reverse scanning.

[0079] In order to realize the reset function, the stage transmission module 201 can also include a nineteenth transistor NT13. The source, one of the drain and the gate of the nineteenth transistor NT13 can be loaded with the reset signal Reset. Before performing forward scanning or reverse scanning, the reset signal Reset can be a corresponding high-voltage signal to turn on the nineteenth transistor NT13, thereby resetting the potential of the third node P.

[0080] In order to realize the test function, the stage transmission module 201 may further include a twentieth transistor NT11, a twenty-first transistor NT12, and a twenty-fifth transistor NT14, and the output module 202 may further include a twenty-second transistor NT18. The specific connection mode and the loaded signal may refer to Figure 2 During the test, the first touch control signal GAS1 is at a corresponding high potential to turn on the twentieth transistor NT11, the twenty-first transistor NT12, the twenty-fifth transistor NT14, and the twenty-second transistor NT18, thereby turning off the twelfth transistor NT8, the thirteenth transistor NT16, and the fourteenth transistor NT10. Therefore, the level transfer signal Carry(n) and the gate signal OUT(n) are both corresponding high potential signals, enabling level transfer, and ultimately causing all row sub-pixels Pi to emit light for testing.

[0081] In order to realize the touch function, the output module 202 may further include a twenty-third transistor NT99. The specific connection method and the loaded signal may refer to Figure 2 During the touch process, the second touch control signal GAS2 may be at a corresponding high level to turn on the twenty-third transistor NT99 so as to stop normally outputting the gate signal OUT(n) of this stage.

[0082] In the non-touch and test (ie, forward scanning or reverse scanning) process, the first touch control signal GAS1 and the second touch control signal GAS2 are both at corresponding low levels.

[0083] Furthermore, the stage transmission module 201 may further include a second capacitor C2 and a third capacitor C3. The specific connection method and the loaded signal can be referred to Figure 2 The second capacitor C2 can maintain the stability of the potential of the first node Q, and the third capacitor C3 can maintain the potential of the third node P.

[0084] In order to better illustrate the function of the gate driving unit 20 in the present invention, Figure 3 The timing diagram further illustrates the working phases of the gate driving unit 20. It can be considered that the three clock signals in the 1st, 4th, 7th, etc. (3k+1)th level gate driving unit 20 can be as follows: Figure 2The three clock signals in the 2nd, 5th, 8th and other (3k+2)th level gate driving units 20 can be understood as Figure 2 The first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 in the gate driving unit 20 are replaced by the second clock signal CK2, the third clock signal CK3, and the first clock signal CK1 in sequence. The three clock signals in the 3rd, 6th, and 9th (3k+3)th level gate driving units 20 can be understood as Figure 2 The first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 in the clock signal CK1 are replaced by the third clock signal CK3, the first clock signal CK1, and the second clock signal CK2 in sequence.

[0085] Figure 3 In this example, the frequency-divided signal SW changes from a high potential signal to a low potential signal at least at the falling edge of the level transfer signal Carry (3) of the third level within a frame. The forward scanning process may include the following working stages.

[0086] In the first stage t1, the frequency division signal SW is at a corresponding high potential (i.e., the second node N is electrically connected to the first node Q). For the fourth-stage gate driving unit 20, the third-stage stage transmission signal Carry (3) is at a corresponding high potential signal to turn on the ninth transistor NT1. The positive scanning signal U2D, which is a high potential signal, is transmitted to the first node Q and the fifth node Qa. The fifteenth transistor NT3 is turned on, and the first clock signal CK1 is transmitted to the gate of the twelfth transistor NT8. The twelfth transistor NT8 is turned off. At the same time, the twenty-fourth transistor NT6 is turned on by the positive scanning signal U2D. The low-voltage signal VGL is transmitted to the third node P, so that the eleventh transistor NT5, the thirteenth transistor NT16, and the fourteenth transistor NT10 are all turned off.

[0087] At this time, in the second output control module 204, the second transistor NT24 and the fifth transistor NT22 are both turned off, the fourth transistor NT21 and the third transistor NT23 are turned on, the low voltage signal VGL is transmitted to the fourth node F, and the first transistor NT20 is turned off, which does not affect the potential of the second node N.

[0088] Therefore, the seventh transistor NT15 and the sixteenth transistor NT9 are respectively controlled by the signal of the fifth node Qa and the signal of the second node N and are turned on. At this time, the third clock signal CK3, which is a low-level signal, is transmitted to the stage transmission line L2(n) and the gate line L4(n). At this time, the stage transmission signal Carry(4) and the gate signal OUT(4) are both corresponding low-level signals.

[0089] In the second phase t2, the frequency-divided signal SW is at a corresponding low potential (i.e., the second node N is electrically disconnected from the first node Q). For the fourth-stage gate driver unit 20, the ninth transistor NT1 is turned off, and the twelfth transistor NT8 is still turned off. Therefore, the first node Q and the third node P maintain their previous potentials, and the third clock signal CK3 jumps to a corresponding high potential signal. Due to the coupling effect of the internal parasitic capacitance of the seventh transistor NT15, the potential of the fifth node Qa rises, and the conduction degree of the seventh transistor NT15 increases.

[0090] At this time, in the second output control module 204, although the fourth transistor NT21 is turned off, the potential of the second node N is still not affected because the first node Q and the third node P maintain their previous potentials.

[0091] Therefore, the seventh transistor NT15 and the sixteenth transistor NT9 are still turned on. At this time, the third clock signal CK3, which is a high-level signal, is transmitted to the stage transmission line L2(n) and the gate line L4(n). At this time, the stage transmission signal Carry(4) and the gate signal OUT(4) are both corresponding high-level signals.

[0092] In this stage, for the fifth-stage gate driving unit 20, the fourth-stage stage transfer signal Carry (4) is a corresponding high-voltage signal to turn on the ninth transistor NT1. Similarly, referring to the analysis of the working process of the fourth-stage gate driving unit 20 in the first stage t1, the first node Q and the fifth node Qa of the fifth-stage gate driving unit 20 are corresponding high-voltage, and the third node P is corresponding low-voltage.

[0093] However, at this time, in the second output control module 204 of the fifth-stage gate driving unit 20, the second transistor NT24, the fifth transistor NT22, and the fourth transistor NT21 are all turned off, so the third transistor NT23 remains turned off, and the first transistor NT20 remains turned on, so the potential of the second node N is pulled down by the low-voltage signal VGL.

[0094] Therefore, the stage transfer signal Carry(5) of the fifth stage gate driving unit 20 is output normally, but since the sixteenth transistor NT9 is turned off, the gate signal OUT(5) can only maintain the previous low potential signal;

[0095] In the third phase t3, the frequency-dividing signal SW is at a corresponding low potential (i.e., the second node N is electrically disconnected from the first node Q). For the fourth-stage gate driving unit 20, the first clock signal CK1 is at a corresponding high potential signal, turning on the twelfth transistor NT8. The high-voltage signal VGH is transmitted to the third node P, turning on the eleventh transistor NT5, the thirteenth transistor NT16, and the fourteenth transistor NT10. The low-voltage signal VGL is transmitted to the first node Q, the stage transmission line L2(n), and the gate line L4(n) to pull down the potentials of the three.

[0096] At this time, in the second output control module 204, the second transistor NT24 and the fifth transistor NT22 are both turned on. Even though the fourth transistor NT21 is turned off, the low-voltage signal VGL can be transmitted to the gate of the third transistor NT23 through the fifth transistor NT22 to control the third transistor NT23 to be turned off. Therefore, the high-voltage signal VGH is transmitted to the fourth node F to turn on the first transistor NT20 and turn it off, thereby pulling down the potential of the second node N.

[0097] It should be noted that, if the second output control module 204 does not pull down the potential of the second node N, the second node N electrically disconnected from the first node Q will still maintain its original high potential, causing the sixteenth transistor NT9 to continue to be turned on. When the third clock signal CK3 is at a corresponding high potential again, the gate signal OUT(4) will output a corresponding high potential signal again, resulting in abnormal luminance of the sub-pixel Pi in the corresponding row.

[0098] Therefore, the seventh transistor NT15 and the sixteenth transistor NT9 are both turned off, and the thirteenth transistor NT16 and the fourteenth transistor NT10 are both turned on. At this time, the stage transfer signal Carry (4) and the gate signal OUT (4) are both corresponding low-level signals;

[0099] In this stage, for the fifth-stage gate driving unit 20, similarly, referring to the analysis of the operation process of the fourth-stage gate driving unit 20 in the second stage t2, the first node Q and the third node P maintain their previous high and low potentials, respectively. Similarly, since the third clock signal CK3 jumps to the corresponding high potential signal, the potential of the fifth node Qa rises, and the conduction degree of the seventh transistor NT15 increases.

[0100] At this time, in the second output control module 204, since the fourth transistor NT21 is turned off, and the first node Q and the third node P respectively maintain their previous potentials, the potential of the second node N is still pulled down by the low voltage signal VGL.

[0101] It should be noted that, if the second output control module 204 is not used to pull down the potential of the second node N, the second node N electrically disconnected from the first node Q will be coupled by the first clock signal CK1 (applied to one of the source and drain of the sixteenth transistor NT9 of the fifth-stage gate driving unit 20) becoming a high potential signal, and the potential will rise, that is, it will appear as Figure 3 The rise of the N1 waveform in the third stage t3;

[0102] Therefore, the stage transfer signal Carry(5) of the fifth stage gate driving unit 20 is output normally. However, due to the cut-off of the sixteenth transistor NT9 and the pull-down of the potential of the second node N, the gate signal OUT(5) can only maintain the previous low potential signal.

[0103] The present invention provides a display electronic terminal, comprising any display device as described above. The electronic terminal may further comprise an input device and an output device electrically connected to the display device.

[0104] The present invention provides a display device and an electronic terminal, which are based on a first output control module electrically connected to a stage transmission module through a first node and electrically connected to an output module through a second node, and is used to control the electrical connection or electrical disconnection of the first node and the second node according to a frequency division signal transmitted by a frequency division line, and the output module is used to generate a gate signal transmitted to the gate line of this level according to the signal of the second node. A second output control module electrically connected to the output module through a second node is also provided, and is used to transmit the first signal to the second node when the first node and the second node are electrically disconnected, so as to control the gate signal output by the output module to be a second signal to control the corresponding multiple sub-pixels not to emit light, thereby achieving differentiated settings of the refresh rates of different areas of the display device while avoiding the sub-pixels within the surface from emitting light by mistake.

[0105] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A display device, characterized in that: The invention comprises a plurality of sub-pixels and a gate driving circuit electrically connected to the plurality of sub-pixels, wherein the gate driving circuit comprises a plurality of cascaded gate driving units, and the gate driving unit comprises: a level transmission module, electrically connected to a frame start line or a level transmission line of the upper-level gate driving unit, for generating a level transmission signal transmitted to the level transmission line of the current level according to a frame start signal transmitted by the frame start line or a level transmission signal transmitted by the level transmission line of the upper-level gate driving unit; Output module; a first output control module, electrically connected to the frequency division line, and further electrically connected to the stage transmission module via a first node and electrically connected to the output module via a second node, for controlling the electrical connection or disconnection between the first node and the second node according to the frequency division signal transmitted by the frequency division line, and the output module for generating a gate signal transmitted to the gate line of the current stage according to the signal of the second node; A second output control module is electrically connected to the output module through the second node, and is used to transmit the first signal to the second node when the first node is electrically disconnected from the second node, so as to control the gate signal output by the output module to be a second signal to control the corresponding multiple sub-pixels not to emit light.

2. The display device according to claim 1, wherein The stage transmission module is electrically connected to a third node, and a signal of the third node is inversely proportional to a signal of the first node; The second output control module is also electrically connected to the frequency division line, and the second output control module is also electrically connected to the stage transmission module through at least one of the first node and the third node. The second output control module is used to control the signal of the second node according to the signal of the first node, at least one of the signal of the third node and the frequency division signal.

3. The display device according to claim 2, wherein: The output module is also electrically connected to the stage transmission module through the third node, and the output module is further configured to generate the gate signal according to the signal of the third node.

4. The display device according to claim 2, wherein: The second output control module includes: a first transistor, wherein one of a source and a drain of the first transistor is electrically connected to a first voltage line for transmitting the first signal, the other of the source and the drain of the first transistor is electrically connected to the second node, and the gate of the first transistor is electrically connected to a fourth node; The signal of the first node, at least one of the signals of the third node, and the frequency-divided signal control the signal of the fourth node, and the first transistor is used to control the first voltage line to be electrically connected or electrically disconnected with the second node according to the signal of the fourth node.

5. The display device according to claim 4, wherein: The second output control module further includes: a second transistor, wherein one of a source and a drain of the second transistor is electrically connected to the second voltage line, the other of the source and the drain of the second transistor is electrically connected to the fourth node, and the gate of the second transistor is electrically connected to the third node; a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to a third voltage line, the other of the source and the drain of the third transistor is electrically connected to the fourth node, and a gate of the third transistor is connected to the fourth node; a fourth transistor, wherein one of the source and the drain of the fourth transistor is electrically connected to the first node, the other of the source and the drain of the fourth transistor is electrically connected to the gate of the third transistor, and the gate of the fourth transistor is electrically connected to the frequency division line.

6. The display device according to claim 5, wherein: The second output control module further includes: a fifth transistor, wherein one of the source and the drain of the fifth transistor is electrically connected to the fourth voltage line, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, and the gate of the fifth transistor is electrically connected to the third node.

7. The display device according to claim 1, wherein The first output control module includes: a sixth transistor, wherein one of the source and the drain of the sixth transistor is electrically connected to the first node, the other of the source and the drain of the sixth transistor is electrically connected to the second node, and the gate of the sixth transistor is electrically connected to the frequency division line.

8. The display device according to claim 7, wherein: The level transmission module includes: a level transmission input module, electrically connected to the frame start line or the level transmission line of the upper gate driving unit, for controlling the signal of the first node according to the frame start signal or the upper level transmission signal; a level transmission output module, electrically connected to the level transmission input module via the first node, and configured to generate the level transmission signal of the current level according to the signal of the first node; In which, the stage transmission output module includes a seventh transistor and a first capacitor, one of the source and the drain of the seventh transistor is electrically connected to the signal line, the other of the source and the drain of the seventh transistor is electrically connected to the stage transmission line of the current level, the gate of the seventh transistor is electrically connected to the first node, and the first capacitor is electrically connected between the source and the drain of the seventh transistor.

9. The display device according to claim 1, wherein In at least one frame, the frequency-divided signal is used to control the gate signal output by at least one gate driving unit to make the corresponding multiple sub-pixels emit light, and to control the gate signal output by at least one gate driving unit to make the corresponding multiple sub-pixels not emit light.

10. The display device according to claim 1, wherein The stage transmission module is electrically connected to a third node. The second output control module includes a first transistor, one of a source and a drain of the first transistor is electrically connected to a first voltage line for transmitting a low-voltage signal, the other of the source and the drain of the first transistor is electrically connected to the second node, and the gate of the first transistor is electrically connected to a fourth node. The working period of the gate drive circuit includes: In the first stage, for the gate drive unit of the current stage, the frequency-divided signal is used to control the electrical connection between the first node and the second node, the stage transmission signal of the previous stage is used to control the positive scanning signal to be transmitted to the first node to pull up the potential of the first node, and the low-voltage signal to be transmitted to the third node to pull down the potential of the third node; wherein the low voltage signal is transmitted to the fourth node to turn off the first transistor; Wherein, a third clock signal of low potential is transmitted to the stage transmission line and the gate line.

11. The display device according to claim 10, wherein: The working period of the gate drive circuit also includes: In a second stage following the first stage, for the gate driving unit of this stage, the divided frequency signal is used to control the first node and the second node to be electrically disconnected, and the first node and the third node are respectively maintained at their potentials in the first stage to turn off the first transistor; The third clock signal, which is a high-voltage signal, is transmitted to the stage transmission line, the gate line, and the stage transmission line.

12. The display device according to claim 11, wherein In the second stage, for the gate driving unit of the next stage, the stage transmission signal of the current stage is used to control the positive scanning signal to be transmitted to the first node to pull up the potential of the first node, and the low voltage signal to be transmitted to the third node to pull down the potential of the third node; Wherein, the first transistor is turned on, and the potential of the second node is pulled down by the low-voltage signal; Wherein, a first clock signal of low potential is transmitted to the stage transmission line, and the gate line is maintained at a low potential.

13. The display device according to claim 12, wherein: The working period of the gate drive circuit also includes: In a third stage following the second stage, for the gate driving unit of this stage, the divided frequency signal is used to control the electrical disconnection of the first node and the second node, and the low voltage signal is transmitted to the first node, the stage transmission line, and the gate line to pull down the potentials of the three. wherein a high voltage signal is transmitted to the fourth node to turn off the first transistor, thereby pulling down the potential of the second node; Wherein, the low voltage signal is transmitted to the stage transmission line and the gate line.

14. The display device according to claim 13, wherein: In the third stage, for the gate driving unit of the next stage, the first node maintains the previous high potential, and the third node maintains the previous low potential; Wherein, the potential of the second node is pulled down by the low voltage signal; The first clock signal of high potential is transmitted to the stage transmission line, and the gate line is maintained at a low potential.

15. An electronic terminal, characterized in that: The device comprises the display device according to any one of claims 1 to 14.

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