Word line driver circuit and memory

Abstract

The disclosed embodiments relate to the field of semiconductor technology and provide a wordline driver circuit and a memory. The wordline driver circuit includes: a wordline driver controller configured to receive a first power supply voltage, the level of which is adjustable, and output a first control signal, the level of which is equal to a ground voltage or the level of the first power supply voltage; a wordline driver configured to receive a second power supply voltage and the first control signal and output a wordline control signal, the wordline control signal controlling the opening or closing of a wordline in a target memory array, the wordline driver corresponding to each wordline; and the wordline drivers corresponding to the wordlines in the target memory array being connected to the same second power supply voltage. The disclosed embodiments at least help reduce power consumption of the wordline driver circuit.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a word line driving circuit and a memory. Background Art

[0002] Key factors considered in current integrated circuit design include, but are not limited to, performance, power consumption, and scalability. In memory circuits, such as dynamic random access memory (DRAM), it's often necessary to activate a local circuit while keeping surrounding circuits in "sleep mode" to reduce overall circuit power consumption.

[0003] For example, a portion of the memory circuitry can be configured to enter a sleep mode with low power consumption if it remains idle for a predetermined period of time. However, when the portion of the memory circuitry is in normal active mode, the power consumption required is still high. Summary of the Invention

[0004] The embodiments of the present disclosure provide a word line driving circuit and a memory, which are at least beneficial to reducing the power consumption of the word line driving circuit.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a word line driving circuit, including: a word line driver controller, configured to receive a first power supply voltage, the level of which is adjustable, and output a first control signal, the level of which is equal to the ground voltage or the level of the first power supply voltage; a word line driver, configured to receive a second power supply voltage and the first control signal and output a word line control signal, the word line control signal controls the opening or closing of a word line in a target storage array, the word line driver corresponding to the word line one-to-one; the word line drivers corresponding to all the word lines in the target storage array are connected to the same second power supply voltage.

[0006] In some embodiments, the word line driver controller is further configured to, if one of the word lines in the target storage array is turned on, provide the first control signal at a first level value to the multiple word line drivers corresponding to the remaining word lines in the target storage array; if all the word lines in the target storage array are turned off, provide the first control signal at a second level value to the multiple word line drivers corresponding to all the word lines in the target storage array, the second level value is less than the first level value, and the first level value and the second level value are both within the adjustable range of the level value of the first supply voltage.

[0007] In some embodiments, the word line driving circuit further includes: a voltage regulating unit configured to output the first supply voltage with an adjustable level in response to an enable signal and a third control signal.

[0008] In some embodiments, the voltage regulation unit includes: a first branch and a second branch connected in parallel between a power supply node and a first node, the first branch being turned on or off in response to the enable signal, and the second branch being turned on or off in response to the third control signal; when the enable signal is in a valid state, the first branch is turned on and outputs the first supply voltage at the first level through the first node; when the enable signal is in an invalid state and the third control signal is in a valid state, the second branch is turned on and the first branch is turned off, and outputs the first supply voltage at the second level through the first node; wherein, the enable signal being in a valid state indicates that one of the word lines in the target memory array is turned on and the remaining word lines in the target memory array are turned off, and the enable signal being in an invalid state indicates that all the word lines in the target memory array are turned off.

[0009] In some embodiments, the level of the third control signal is adjustable, and the second level changes with the change of the level of the third control signal.

[0010] In some embodiments, when the second branch is turned on in response to the third control signal, the degree of conduction of the second branch decreases as the level value of the third control signal decreases; the first branch includes: a first PMOS transistor, the source of the first PMOS transistor is electrically connected to the power supply node, the drain of the first PMOS transistor is electrically connected to the first node, and the gate of the first PMOS transistor receives the enable signal; the second branch includes: a first NMOS transistor, the drain of the first NMOS transistor is electrically connected to the power supply node, the source of the first NMOS transistor is electrically connected to the first node, and the gate of the first NMOS transistor receives the third control signal.

[0011] In some embodiments, the word line driving circuit further includes: a third control signal generating circuit configured to provide the third control signal with an adjustable level to the second branch; the third control signal generating circuit includes a digital-to-analog converter.

[0012] In some embodiments, the word line drive circuit further includes: a third control signal generating circuit, configured to provide the third control signal with an adjustable level value to the second branch; the third control signal generating circuit includes an adaptive bias circuit, and the adaptive bias circuit includes: a current mirror, one end of the current mirror receives a reference current, and the other end of the current mirror is electrically connected to a second node, and the second node outputs the third control signal; a voltage regulator, electrically connected between the second node and a ground node, and configured to adjust the voltage at the second node based on changes in the performance of the voltage regulator itself, so that the level value of the third control signal is adjustable.

[0013] In some embodiments, the voltage regulator includes: a second NMOS transistor, wherein the drain of the second NMOS transistor is electrically connected to the second node, the drain of the second NMOS transistor is electrically connected to the gate of the second NMOS transistor, and the threshold voltage of the second NMOS transistor decreases as the temperature of the second NMOS transistor increases; and a third NMOS transistor, wherein the drain of the third NMOS transistor is electrically connected to the source of the second NMOS transistor, the drain of the third NMOS transistor is electrically connected to the gate of the third NMOS transistor, and the source of the third NMOS transistor is electrically connected to the ground node, and the threshold voltage of the third NMOS transistor decreases as the temperature of the third NMOS transistor increases.

[0014] In some embodiments, the word line drive circuit further includes: a third control signal generating circuit, configured to provide the third control signal with an adjustable level value to the second branch; the third control signal generating circuit includes an adaptive bias circuit, and the adaptive bias circuit includes: a bias voltage generating circuit, configured to generate a bias voltage; an error amplifier, configured to receive the bias voltage and the feedback voltage, and output an output voltage, the level value of the output voltage has a changing trend that is the same as the level value of the feedback voltage; a second-stage amplification circuit, configured to receive the output voltage and output the third control signal, the level value of the third control signal has a changing trend that is opposite to the level value of the output voltage; and a feedback circuit, configured to receive the third control signal and output the feedback voltage, the level value of the feedback voltage has a changing trend that is the same as the level value of the third control signal.

[0015] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a memory, comprising the word line driving circuit as described in any one of the above items, and a memory array, wherein the memory array includes the target memory array.

[0016] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0017] The level of the first supply voltage is adjustable, and the level of the first control signal can be equal to the level of the first supply voltage. In this way, the level of the first control signal output by the word line driver controller to the word line driver can also be adjusted. That is, when the target memory array is in different working states, the word line driver controller can provide the word line driver with first control signals of different levels to reduce the power consumption of the word line driver circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 and Figure 2 Two functional block diagrams of a word line driver circuit provided in one embodiment of the present disclosure;

[0020] Figure 3 A functional block diagram of a voltage regulating unit in a word line driving circuit provided in an embodiment of the present disclosure;

[0021] Figure 4 for Figure 3 A schematic diagram of a circuit structure of a medium voltage regulation unit;

[0022] Figure 5 and Figure 6 Two functional block diagrams of a voltage regulating unit and a third control signal generating circuit in a word line driving circuit provided in an embodiment of the present disclosure;

[0023] Figure 7 A functional block diagram of an adaptive bias circuit in a word line driver circuit provided in an embodiment of the present disclosure;

[0024] Figure 8 for Figure 7 A schematic diagram of a circuit structure of an adaptive bias circuit;

[0025] Figure 9 Another functional block diagram of an adaptive bias circuit in a word line driver circuit provided in an embodiment of the present disclosure;

[0026] Figure 10 for Figure 9A schematic diagram of a circuit structure of an adaptive bias circuit;

[0027] Figure 11 A functional block diagram of a word line driver in a word line driver circuit provided in an embodiment of the present disclosure;

[0028] Figure 12 for Figure 11 A circuit diagram of a word line driver. DETAILED DESCRIPTION

[0029] As known from the background technology, the power consumption of memory needs to be reduced.

[0030] Analysis reveals that a DRAM can have multiple memory arrays, each of which can correspond to multiple wordline drivers. These drivers are used to control the multiple wordlines in the memory array. When a wordline in a memory array needs to be activated, the power supply to the circuit associated with that wordline is turned on. At this point, the other wordlines in the memory array surrounding that wordline need to be kept off. Because the wordline to be activated and the surrounding wordlines in the memory array share a common power supply, a higher voltage control signal, such as a high-level signal with a voltage level of A, needs to be input to the wordline drivers corresponding to these off-state wordlines. However, when all wordlines in a memory array do not need to be activated, the wordline drivers in that memory array are powered off. At this point, a lower voltage control signal, such as a high-level signal with a voltage level of B (where B is less than A), is required to ensure that the wordlines in the memory array are stably off.

[0031] As can be seen, the logic high signal level required to turn off the corresponding word line driver in different operating states of the memory array varies. Therefore, to save power, the level of the control signal given to the word line driver needs to be variable to adapt to different operating states.

[0032] The present disclosure provides a word line driver circuit and a memory. In the word line driver circuit, the level of a first control signal output by a word line driver controller to a word line driver is adjustable. That is, when a target memory array is in different operating states, the word line driver controller can provide the word line driver with first control signals of different levels to reduce the power consumption of the word line driver circuit.

[0033] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0034] An embodiment of the present disclosure provides a word line driving circuit. The word line driving circuit provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 and Figure 2 Two functional block diagrams of a word line driver circuit provided in one embodiment of the present disclosure; Figure 3 A functional block diagram of a voltage regulating unit in a word line driving circuit provided in an embodiment of the present disclosure; Figure 4 for Figure 3 A schematic diagram of a circuit structure of a medium voltage regulation unit; Figure 5 and Figure 6 Two functional block diagrams of a voltage regulating unit and a third control signal generating circuit in a word line driving circuit provided in an embodiment of the present disclosure; Figure 7 A functional block diagram of an adaptive bias circuit in a word line driver circuit provided in an embodiment of the present disclosure; Figure 8 for Figure 7 A schematic diagram of a circuit structure of an adaptive bias circuit; Figure 9 Another functional block diagram of an adaptive bias circuit in a word line driver circuit provided in an embodiment of the present disclosure; Figure 10 for Figure 9 A schematic diagram of a circuit structure of an adaptive bias circuit; Figure 11 A functional block diagram of a word line driver in a word line driver circuit provided in an embodiment of the present disclosure; Figure 12 for Figure 11 A circuit diagram of a word line driver.

[0035] refer to Figure 1 The word line driving circuit 100 includes: a word line driver controller 101, configured to receive a first power supply voltage VariablePwr, the level of which is adjustable, and output a first control signal WLctrl, the level of which is equal to the ground voltage or the level of the first power supply voltage VariablePwr; a word line driver 102, configured to receive a second power supply voltage Pwr and the first control signal WLctrl and output a word line control signal WL, the word line control signal WL controls the opening or closing of a word line in a target memory array, and the word line drivers 102 correspond one-to-one to each word line; the word line drivers 102 corresponding to all word lines in the target memory array are connected to the same second power supply voltage Pwr.

[0036] In this way, the level of the first control signal WLctrl is adjustable, that is, when the target memory array is in different working states, the word line driver controller 101 can provide the first control signal WLctrl with different level values ​​to the word line driver 102 to reduce the power consumption of the word line driver circuit 100.

[0037] It is understood that, from the perspective of digital circuits, the first control signal WLctrl output by the wordline driver controller 101 can have two states: logic level "0" and logic level "1." However, when the first control signal WLctrl is at logic level "1," the specific level of the first control signal WLctrl is uncertain. To accommodate different operating states of the circuit, the level of the first control signal WLctrl at logic level "1" varies in different operating states. In practical applications, the first control signal WLctrl is grounded when it is at logic level "0."

[0038] It should be noted that a DRAM may have multiple memory arrays. The target memory array is not included in the word line driver circuit 100. The target memory array is a specific memory array in the DRAM, and the word line driver 102 is used to control the opening or closing of the word lines in the target memory array. Specifically, one word line driver controller 101 may correspond to multiple word line drivers 102. That is, one word line driver controller 101 may output a first control signal WLctrl to multiple word line drivers 102. However, the multiple word line drivers 102 receive different second power supply voltages Pwr. Therefore, one word line driver controller 101 and one second power supply voltage Pwr can select one word line driver 102, and the corresponding word line can be controlled to be opened or closed by this word line driver 102.

[0039] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0040] In some embodiments, the word line driver controller 101 is further configured to, if a word line in the target storage array is turned on, provide a first control signal WLctrl at a first level value to multiple word line drivers 102 corresponding to the remaining word lines in the target storage array; if all word lines in the target storage array are turned off, provide a first control signal WLctrl at a second level value to multiple word line drivers 102 corresponding to all word lines in the target storage array, the second level value is less than the first level value, and both the first level value and the second level value are within the adjustable range of the level value of the first power supply voltage VariablePwr.

[0041] It is understandable that when the target memory array is in different working states, the word line driver controller 101 provides different levels of the first control signal WLctrl to the word line drivers 102 corresponding to the word lines that do not need to be activated in the target memory array. In this way, while ensuring that the target memory array can be in different working states, the level of the first control signal WLctrl can be reduced as much as possible when shutting down all word lines in the target memory array, thereby reducing leakage of the word line driver circuit 100 and reducing the overall power consumption of the word line driver circuit 100.

[0042] In some embodiments, reference Figure 2 The word line driving circuit 100 may further include: a voltage regulating unit 103 configured to output a first power supply voltage VariablePwr with an adjustable level in response to the enable signal SectionEnN and the third control signal idleVctrl.

[0043] In some embodiments, reference Figure 3 The voltage regulation unit 103 may include: a first branch 113 and a second branch 123 connected in parallel between the power supply node VPP and the first node net1, the first branch 113 being turned on or off in response to the enable signal SectionEnN, and the second branch 123 being turned on or off in response to the third control signal idleVctrl; when the enable signal SectionEnN is in an active state, the first branch 113 is turned on and outputs the first power supply voltage VariablePwr at a first level through the first node net1; when the enable signal SectionEnN is in an inactive state and the third control signal idleVctrl is in an active state, the second branch 123 is turned on and the first branch 113 is turned off, and outputs the first power supply voltage VariablePwr at a second level through the first node net1; wherein, the active state of the enable signal SectionEnN indicates that a certain word line in the target memory array is turned on and the remaining word lines in the target memory array are turned off, and the inactive state of the enable signal SectionEnN indicates that all word lines in the target memory array are turned off.

[0044] In this manner, by changing the conductive branch between power node VPP and first node net1, the level of first supply voltage VariablePwr output at first node net1 is changed, thereby achieving adjustable level of first supply voltage VariablePwr. Furthermore, voltage adjustment unit 103 utilizes an existing power rail, namely, the power rail corresponding to power node VPP, eliminating the need for additional power rails. Only first branch 113 and second branch 123 are required to provide adjustable level of first supply voltage VariablePwr to word line driver controller 101, thereby reducing the manufacturing cost of word line driver circuit 100.

[0045] It can be understood that the resistance value of the first branch 113 when conducting is a first resistance value, and the resistance value of the second branch 123 when conducting is a second resistance value, and the first resistance value and the second resistance value are different.

[0046] In some embodiments, the first resistance value is smaller than the second resistance value, and the first resistance value is very small. When the first branch 113 is turned on, the level value of the first supply voltage VariablePwr output through the first node net1 is close to the level value of the power supply node VPP, that is, the first level value is close to the level value of the power supply node VPP. At this time, whether the second branch 123 is turned on or off, it has almost no effect on the level value of the first supply voltage VariablePwr output at the first node net1; when the second branch 123 is turned on and the first branch 113 is turned off, since the second resistance value is greater than the first resistance value, the level value of the first supply voltage VariablePwr output through the first node net1 is less than the level value of the power supply node VPP, and the second level value is less than the first level value.

[0047] In some embodiments, the level of the power node VPP and the level of the second power voltage pwr may be the same.

[0048] In some embodiments, the level of the third control signal idleVctrl is adjustable, and the second level changes with the change of the level of the third control signal idleVctrl.

[0049] It is understood that when different target memory arrays are in the same operating state, for example, when all word lines in the target memory array need to be turned off, the required level of the first control signal WLctrl may be different, that is, the required level of the first power supply voltage VariablePwr may also be different. Alternatively, when the target memory array is in the same operating state at different times, the temperature is different, and the required level of the first control signal WLctrl may also be different. Therefore, the value of the second level itself may also vary, which helps the word line driver controller 101 adapt to different target memory arrays and target memory arrays at different times. While ensuring that the target memory array can be in different operating states, the level of the first control signal WLctrl is minimized when turning off all word lines in the target memory array, thereby reducing leakage of the word line driver circuit 100 and reducing the overall power consumption of the word line driver circuit 100.

[0050] In addition, the level value of the third control signal idleVctrl is adjustable, so that the second branch 123 has different resistance values ​​when it is turned on based on the third control signal idleVctrl with different level values, so as to change the level value of the first power supply voltage VariablePwr output at the first node net1, thereby realizing that the second level value changes with the change of the level value of the third control signal idleVctrl.

[0051] In some embodiments, when the second branch 123 is turned on in response to the third control signal idleVctrl, the degree of conduction of the second branch 123 decreases as the level of the third control signal idleVctrl decreases; Figure 4 The first branch 113 may include: a first PMOS transistor MP1, a source of the first PMOS transistor MP1 electrically connected to the power supply node VPP, a drain of the first PMOS transistor MP1 electrically connected to the first node net1, and a gate of the first PMOS transistor MP1 receiving an enable signal SectionEnN; the second branch 123 may include: a first NMOS transistor MN1, a drain of the first NMOS transistor MN1 electrically connected to the power supply node VPP, a source of the first NMOS transistor MN1 electrically connected to the first node net1, and a gate of the first NMOS transistor MN1 receiving a third control signal idleVctrl.

[0052] It can be understood that when the enable signal SectionEnN is in an active state, i.e., the enable signal SectionEnN is at a logic level of "0," the first PMOS transistor MP1 is turned on, and the level of the first supply voltage VariablePwr output at the first node net1 is close to the level of the power supply node VPP. At this time, regardless of the level of the third control signal idleVctrl, that is, regardless of whether the first NMOS transistor MN1 is on or off, the level of the first supply voltage VariablePwr output at the first node net1 is almost unchanged. When the enable signal SectionEnN is in an inactive state, i.e., the enable signal SectionEnN is at a logic level of "1," the first PMOS transistor MP1 is turned off, and the degree of conduction of the first NMOS transistor MN1 decreases as the level of the third control signal idleVctrl decreases. Different degrees of conduction of the first NMOS transistor MN1 result in different levels of the first supply voltage VariablePwr output at the first node net1.

[0053] In some embodiments, reference Figures 5 to 10 , word line driving circuit 100 (reference Figure 1 ) may further include: a third control signal generating circuit 104 configured to provide a third control signal idleVctrl with an adjustable level to the second branch 123. The third control signal generating circuit 104 includes but is not limited to the following three embodiments.

[0054] First, in some embodiments, reference Figure 5 The third control signal generating circuit 104 may include a digital-to-analog converter 114. The digital-to-analog converter 114 is a device that converts digital signals into analog signals (in the form of current, voltage, or charge). This facilitates the manual configuration of the third control signal idleVctrl. Specifically, the level of the third control signal idleVctrl can be manually designed based on the actual operating state of the word line driver circuit 100, and the designed third control signal idleVctrl can be output to the second branch 123 via the digital-to-analog converter 114. A common digital-to-analog converter can be a resistor voltage divider circuit, which can manually control the resistor voltage divider ratio through coding, thereby controlling the level of the output third control signal idleVctrl.

[0055] In other embodiments, reference Figures 6 to 10 The third control signal generating circuit 104 may include an adaptive bias circuit 124. The adaptive bias circuit 124 includes but is not limited to the following two embodiments.

[0056] Second, in some embodiments, reference Figure 7 and Figure 8The adaptive bias circuit 124 may include: a current mirror 134, one end of the current mirror 134 receives a reference current Iref, the other end of the current mirror 134 is electrically connected to the second node net2, and the second node net2 outputs a third control signal idleVctrl; a voltage regulator 144 is electrically connected between the second node net2 and the ground node VSS, and is configured to adjust the voltage at the second node net2 based on changes in the performance of the voltage regulator 144 itself, so that the level value of the third control signal idleVctrl is adjustable.

[0057] It is understood that the performance of the voltage regulator 144 refers to the performance of the voltage regulator 144 under various factors, including process corners, temperature, and voltage. The current mirror 134 can provide a stable current to the voltage regulator 144 based on the received reference current Iref. When the performance of the voltage regulator 144 changes, that is, when factors such as the process corners, temperature, and voltage of the voltage regulator 144 change, the resistance value of the branch in which the voltage regulator 144 is located will change, thereby changing the voltage at the second node net2. In this way, the voltage at the second node net2 can be adjusted based on the change in the performance of the voltage regulator 144, so that the level of the third control signal idleVctrl can be adjusted.

[0058] In some embodiments, reference Figure 8 The voltage regulator 144 may include: a second NMOS transistor MN2, wherein a drain of the second NMOS transistor MN2 is electrically connected to the second node net2, the drain of the second NMOS transistor MN2 is electrically connected to the gate of the second NMOS transistor MN2, and a threshold voltage of the second NMOS transistor MN2 decreases as the temperature of the second NMOS transistor MN2 increases; and a third NMOS transistor MN3, wherein a drain of the third NMOS transistor MN3 is electrically connected to the source of the second NMOS transistor MN2, the drain of the third NMOS transistor MN3 is electrically connected to the gate of the third NMOS transistor MN3, and the source of the third NMOS transistor MN3 is electrically connected to the ground node VSS, and the threshold voltage of the third NMOS transistor MN3 decreases as the temperature of the third NMOS transistor MN3 increases.

[0059] It can be understood that, under the action of the reference current Iref provided by the current mirror 134, the potential of the drain of the second NMOS transistor MN2 is the same as the potential of the gate of the second NMOS transistor MN2, and the second NMOS transistor MN2 operates in the saturation region. The potential of the drain of the third NMOS transistor MN3 is the same as the potential of the gate of the third NMOS transistor MN3, and the third NMOS transistor MN3 operates in the saturation region.

[0060] Moreover, the threshold voltage of the second NMOS transistor MN2 decreases as the temperature of the second NMOS transistor MN2 increases, and the threshold voltage of the third NMOS transistor MN3 decreases as the temperature of the third NMOS transistor MN3 increases. Therefore, when the temperature of the adaptive bias circuit 124 increases, the threshold voltage of the second NMOS transistor MN2 and the threshold voltage of the third NMOS transistor MN3 both decrease. Since the current mirror 134 provides a stable current to the voltage regulator 144 based on the received reference current Iref, the potential at the second node net2 decreases as the threshold voltages of the second NMOS transistor MN2 and the third NMOS transistor MN3 decrease. That is, the level of the third control signal idleVctrl decreases as the temperature of the adaptive bias circuit 124 increases, thereby achieving self-regulation of the third control signal idleVctrl by the adaptive bias circuit 124. Moreover, it can be understood that generally, the word line driver The temperature of the circuit 100 is consistent with the temperature of the adaptive bias circuit 124. That is, when the temperature of the adaptive bias circuit 124 increases, the temperature of the word line driver circuit 100 also increases. The leakage in the word line driver circuit 100 increases with the increase in temperature. At this time, the level of the third control signal idleVctrl decreases as the temperature of the adaptive bias circuit 124 increases, which helps to reduce the level of the first power supply voltage VariablePwr, thereby reducing the second level of the first control signal WLctrl. This helps to minimize the level of the first control signal WLctrl when turning off all word lines in the target memory array, thereby reducing the leakage of the word line driver circuit 100 and preventing the leakage in the word line driver circuit 100 from increasing excessively with increasing temperature. This enables the word line driver circuit 100 to self-regulate the level of its internal voltage according to its temperature to reduce leakage.

[0061] In some embodiments, the base of the second NMOS transistor MN2 and the base of the third NMOS transistor MN3 are both electrically connected to the ground node VSS.

[0062] It should be noted that the voltage regulator 144 may also include only one NMOS transistor, the drain of which is electrically connected to the second node net2, the drain of which is electrically connected to the gate of which is electrically connected, the source of which is electrically connected to the ground node VSS, and the threshold voltage of which decreases as the temperature of the NMOS transistor increases. In practical applications, the voltage regulator 144 may include multiple NMOS transistors connected in series between the second node net2 and the ground node VSS, with the drain of each NMOS transistor electrically connected to its gate, and the threshold voltage of each NMOS transistor decreasing as the temperature thereof increases. One embodiment of the present disclosure does not limit the number of NMOS transistors included in the voltage regulator 144. In one example, the base of each NMOS transistor in the voltage regulator 144 is electrically connected to the ground node VSS.

[0063] In some embodiments, continue to refer to Figure 8 The current mirror 134 may include: a second PMOS transistor MP2, wherein the source and base of the second PMOS transistor MP2 are both electrically connected to the power supply node VPP, the drain of the second PMOS transistor MP2 receives the reference current Iref, and the gate and drain of the second PMOS transistor MP2 are electrically connected; a third PMOS transistor MP3, wherein the source and base of the third PMOS transistor MP3 are both electrically connected to the power supply node VPP, the drain of the third PMOS transistor MP3 is electrically connected to the second node net2, and the gate of the third PMOS transistor MP3 is electrically connected to the gate of the second PMOS transistor MP2.

[0064] Third, in other embodiments, reference Figure 9 and Figure 10 The adaptive bias circuit 124 includes: a bias voltage generating circuit 154, configured to generate a bias voltage bias; an error amplifier 164, configured to receive the bias voltage bias and the feedback voltage fb, and output an output voltage Vout, wherein the change trend of the level value of the output voltage Vout is the same as the change trend of the level value of the feedback voltage fb; a second-stage amplifying circuit 174, configured to receive the output voltage Vout and output a third control signal idleVctrl, wherein the change trend of the level value of the third control signal idleVctrl is opposite to the change trend of the level value of the output voltage Vout; and a feedback circuit 184, configured to receive the third control signal idleVctrl and output a feedback voltage fb, wherein the change trend of the level value of the feedback voltage fb is the same as the change trend of the level value of the third control signal idleVctrl.

[0065] It can be understood that if the level of the third control signal idleVctrl increases, the feedback circuit 184 outputs an increased feedback voltage fb based on the increased level of the third control signal idleVctrl. The error amplifier 164 outputs an increased output voltage Vout based on the increased level of the feedback voltage fb. Finally, the second-stage amplifier circuit 174 outputs a decreased third control signal idleVctrl based on the increased level of the output voltage Vout. In this way, the adaptive bias circuit 124 can adjust the level of the third control signal idleVctrl.

[0066] In some embodiments, reference Figure 10 The error amplifier 164 may include: a fourth PMOS transistor MP4, electrically connected between the power supply node VPP and the third node net3, with a gate of the fourth PMOS transistor MP4 receiving a bias voltage bias; a fifth PMOS transistor MP5, electrically connected between the power supply node VPP and the fourth node net4, with a gate of the fifth PMOS transistor MP5 receiving a feedback voltage fb; a fourth NMOS transistor MN4, electrically connected between the ground node VSS and the fourth node net4; and a fifth NMOS transistor MN5, electrically connected between the ground node VSS and the third node net3, with gates of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 both electrically connected to the fourth node net4; wherein the third node net3 outputs the output voltage Vout.

[0067] It can be understood that when the level of the bias voltage bias generated by the bias voltage generating circuit 154 remains unchanged, in the error amplifier 164, the level of the output voltage Vout increases as the level of the feedback voltage fb increases, and decreases as the level of the feedback voltage fb decreases.

[0068] In some embodiments, the base of the fourth NMOS transistor MN4 and the base of the fifth NMOS transistor MN5 are both electrically connected to the ground node VSS.

[0069] In some embodiments, the second-stage amplifier circuit 174 may include: a load unit 105, electrically connected between the power supply node VPP and the fifth node net5, and the resistance of the load unit 105 remains unchanged; an amplifier unit 115, electrically connected between the fifth node net5 and the ground node VSS, and the fifth node net5 outputs a third control signal idleVctrl; wherein the amplifier unit 115 is configured to receive the output voltage Vout, and the change trend of the equivalent resistance of the amplifier unit 115 is opposite to the change trend of the level value of the output voltage Vout, so that the change trend of the level value of the third control signal idleVctrl is opposite to the change trend of the level value of the output voltage Vout.

[0070] It can be understood that if the resistance of the load unit 105 remains unchanged, the load unit 105 can be a resistor with a constant resistance, multiple resistors connected in series or in parallel, at least one resistor and a MOS transistor with a gate receiving a fixed voltage connected in series or in parallel, a MOS transistor with a gate receiving a fixed voltage, or a circuit in which multiple MOS transistors with a gate receiving a fixed voltage are connected in series or in parallel.

[0071] Furthermore, the equivalent resistance of the amplifier unit 115 changes in a trend opposite to the level of the output voltage Vout. Therefore, when the level of the output voltage Vout increases, the conduction level of the amplifier unit 115 increases, the equivalent resistance decreases, and the potential at the fifth node net5 decreases, i.e., the level of the third control signal idleVctrl decreases. It should be noted that any circuit that satisfies the requirement that the equivalent resistance of the amplifier unit 115 changes in a trend opposite to the level of the output voltage Vout can be used as the amplifier unit 115.

[0072] In some examples, continue to refer to Figure 10 The bias voltage generating circuit 154 is further configured to generate a fourth control signal fourVctrl; the load unit 105 may include: a sixth PMOS transistor MP6, electrically connected between the power supply node VPP and the fifth node net5, and a gate of the sixth PMOS transistor MP6 receives the fourth control signal fourVctrl; the amplifying unit 115 may include: a sixth NMOS transistor MN6, electrically connected between the fifth node net5 and the ground node VSS, and a gate of the sixth NMOS transistor MN6 receives the output voltage Vout.

[0073] In some embodiments, the feedback circuit 184 may include: a seventh NMOS transistor MN7, electrically connected between the power supply node VPP and the sixth node net6, and the gate of the seventh NMOS transistor MN7 receives the third control signal idleVctrl; an eighth NMOS transistor MN8, electrically connected between the sixth node net6 and the ground node VSS, and the gate of the eighth NMOS transistor MN8 receives the bias voltage bias; wherein the sixth node net6 outputs the feedback voltage fb.

[0074] It can be understood that, as the level of the third control signal idleVctrl increases, the conduction degree of the seventh NMOS transistor MN7 increases, so that the potential at the sixth node net6 increases, that is, the level of the feedback voltage fb increases, so that the change trend of the level of the feedback voltage fb is the same as the change trend of the level of the third control signal idleVctrl.

[0075] In some embodiments, continue to refer to Figure 10On the basis that the feedback circuit 184 includes the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8, the feedback circuit 184 may further include: a seventh PMOS transistor MP7 electrically connected between the power supply node VPP and the drain of the seventh NMOS transistor MN7, and the gate of the seventh PMOS transistor MP7 is electrically connected to the drain of the seventh PMOS transistor MP7.

[0076] The following reference Figure 10 The working principle of the adaptive bias circuit 124 is described in detail.

[0077] When the potential at the fifth node net5 increases, that is, the level of the third control signal idleVctrl increases, the conductivity of the seventh NMOS transistor MN7, whose gate receives the third control signal idleVctrl, increases, causing the potential at the sixth node net6 to increase, that is, the level of the feedback voltage fb to increase. Then, the conductivity of the fifth PMOS transistor MP5, whose gate receives the feedback voltage fb, decreases, causing the potential at the fourth node net4 to decrease. Then, the conductivity of the fifth NMOS transistor MN5, whose gate receives the potential at the fourth node net4, decreases, causing the potential at the third node net3 to increase, that is, the level of the output voltage Vout to increase. Finally, the conductivity of the sixth NMOS transistor MN6, whose gate receives the output voltage Vout, increases, causing the potential at the fifth node net5 to decrease, that is, the level of the third control signal idleVctrl to decrease. Similarly, when the potential at the fifth node net5 decreases, that is, when the level of the third control signal idleVctrl decreases, the level of the output voltage Vout decreases. The conduction level of the sixth NMOS transistor MN6, whose gate receives the output voltage Vout, decreases, causing the potential at the fifth node net5 to increase, that is, the level of the third control signal idleVctrl to increase. In this way, the adaptive bias circuit 124 implements negative feedback regulation of the level of the third control signal idleVctrl.

[0078] In some embodiments, continue to refer to Figure 10The bias voltage generating circuit 154 is further configured to generate a fourth control voltage fourVctrl and a fifth control voltage fiveVctrl. In addition to including the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5, the error amplifier 164 may further include an eighth PMOS transistor MP8 and a ninth PMOS transistor MP9. The source of the eighth PMOS transistor MP8 is electrically connected to the power supply node VPP, the drain of the eighth PMOS transistor MP8 is electrically connected to the source of the ninth PMOS transistor MP9, the gate of the eighth PMOS transistor MP8 receives the fourth control signal fourVctrl, the drain of the ninth PMOS transistor MP9 is electrically connected to the source of the fifth PMOS transistor MP5, and the gate of the ninth PMOS transistor MP9 receives the fifth control voltage fiveVctrl.

[0079] In some embodiments, continue to refer to Figure 10 The bias voltage generating circuit 154 may include: a ninth NMOS transistor MN9, electrically connected between the seventh node net7 and the ground node VSS, with the gate of the ninth NMOS transistor MN9 electrically connected to the seventh node net7; a first current source 194, electrically connected between the eighth node net8 and the ground node VSS; a tenth PMOS transistor MP10, electrically connected between the eighth node net8 and the ninth node net9, with the gate of the tenth PMOS transistor MP10 electrically connected to the eighth node net8; an eleventh PMOS transistor MP11, with the drain of the eleventh PMOS transistor MP11 electrically connected to the seventh node net8; a first current source 194, electrically connected between the eighth node net8 and the ground node VSS; a tenth PMOS transistor MP10, electrically connected between the eighth node net8 and the ninth node net9, with the gate of the tenth PMOS transistor MP10 electrically connected to the eighth node net8; and a first current source 194, electrically connected between the eighth node net8 and the ninth node net9, with the gate of the tenth PMOS transistor MP10 electrically connected to the eighth node net8. The first PMOS transistor MP11 is electrically connected to the eighth node net7, the gate of the eleventh PMOS transistor MP11 is electrically connected to the eighth node net8; the twelfth PMOS transistor MP12 has a drain electrically connected to the source of the eleventh PMOS transistor MP11, the gate of the twelfth PMOS transistor MP12 is electrically connected to the ninth node net9, and the source of the twelfth PMOS transistor MP12 is electrically connected to the power supply node VPP; the thirteenth PMOS transistor MP13 is electrically connected between the ninth node net9 and the power supply node VPP, and the gate of the thirteenth PMOS transistor MP13 is electrically connected to the ninth node net9.

[0080] Among them, the seventh node net7 outputs the bias voltage bias, that is, the gate of the fourth PMOS transistor MP4 is electrically connected to the seventh node net7; the ninth node net9 outputs the fourth control signal fourVctrl, that is, the gate of the sixth PMOS transistor MP6 and the gate of the eighth PMOS transistor MP8 are both electrically connected to the ninth node net9; the eighth node net8 outputs the fifth control voltage fiveVctrl, that is, the gate of the ninth PMOS transistor MP9 is electrically connected to the eighth node net8.

[0081] In some embodiments, the base of the ninth NMOS transistor MN9 is electrically connected to the ground node VSS, and the bases of the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, and the thirteenth PMOS transistor MP13 are all electrically connected to the power node VPP.

[0082] In some embodiments, reference Figure 11 The word line driver 102 may include: a pull-up unit 112, which receives the second power supply voltage pwr and is electrically connected to the tenth node net10, and is configured to be turned on or off in response to the first control signal WLctrl, and pull up the potential at the tenth node net10 when the pull-up unit 112 is turned on; a first pull-down unit 122, which is electrically connected between the ground node VSS and the tenth node net10, and is configured to be turned on or off in response to the first control signal WLctrl, and pull down the potential at the tenth node net10 when the first pull-down unit 122 is turned on; wherein, one of the pull-up unit 112 and the first pull-down unit 122 is turned on based on the first control signal WLctrl.

[0083] In an example, the first control signal WLctrl is at a high level, the pull-up unit 112 is turned off, and the first pull-down unit 122 is turned on, pulling the potential at the tenth node net10 to a low level, that is, the word line control signal WL is at a low level, so that the word line corresponding to the word line driver 102 is closed; when the first control signal WLctr is at a low level, the first pull-down unit 122 is turned off, and the pull-up unit 112 is turned on, pulling the potential at the tenth node net10 to a high level, that is, the word line control signal WL is at a high level, so that the word line corresponding to the word line driver 102 is opened.

[0084] In some embodiments, continue to refer to Figure 11 In addition to the fact that word line driver 102 includes pull-up unit 112 and first pull-down unit 122, word line driver 102 may further include a second pull-down unit 132 electrically connected between ground node VSS and tenth node net10. In response to the sixth control signal PwrOff being turned on or off, second pull-down unit 132 is configured to pull down the voltage at tenth node net10 when turned on. The level of sixth control signal PwrOff changes in a similar manner to the level of first control signal WLctrl. Thus, when first pull-down unit 122 is turned on, second pull-down unit 132 is also turned on. This facilitates ensuring that word line control signal WL is at a low level through second pull-down unit 132, thereby ensuring that the word line corresponding to word line driver 102 is turned off.

[0085] In some embodiments, reference Figure 12The pull-up unit 112 may include a fourteenth PMOS transistor MP14, a source of which receives the second power supply voltage pwr, a drain of which is electrically connected to the tenth node net10, and a gate of which receives the first control signal WLctrl; the first pull-down unit 122 may include a tenth NMOS transistor MN10, which is electrically connected between the ground node VSS and the tenth node net10, and a gate of which receives the first control signal WLctrl; the second pull-down unit 132 may include an eleventh NMOS transistor MN11, which is electrically connected between the ground node VSS and the tenth node net10, and a gate of which receives the sixth control signal PwrOff.

[0086] It can be understood that when the word line corresponding to the word line driver 102 is turned off, in the word line driver 102, the first control signal WLctrl and the sixth control signal PwrOff are both high, the fourteenth PMOS transistor MP14 is turned off, the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are both turned on, and the potential at the tenth node net10 is pulled down to a low level, that is, the word line control signal WL is low, so that the word line corresponding to the word line driver 102 is turned off; when the first control signal WLctrl and the sixth control signal PwrOff are both low, the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are both turned off, and the fourteenth PMOS transistor MP14 is turned on, and the potential at the tenth node net10 is pulled up to a high level, that is, the word line control signal WL is high, so that the word line corresponding to the word line driver 102 is turned on.

[0087] The working principle of the word line driving circuit 100 provided in an embodiment of the present disclosure is described in detail below through a specific example.

[0088] If all word lines in the target memory array are turned off, the second power supply voltage Pwr is grounded, and the first control signal WLctrl is at logic level "1." Since the second power supply voltage Pwr does not supply power to the fourteenth PMOS transistor MP14, the first control signal WLctrl only needs to turn on the tenth NMOS transistor MN10 to keep the word line control signal WL at a low level. Therefore, the level of the first control signal WLctrl does not need to be very high. For example, the level of the first control signal WLctrl can be 1V. If a word line in the target memory array is turned on and other word lines in the target memory array are turned off, the second power supply voltage Pwr is required. For example, the level of the second power supply voltage Pwr is approximately 3.3V. Since the second power supply voltage Pwr not only supplies power to one word line driver 102 but is also connected to other nearby word line drivers 102, while ensuring that the tenth NMOS transistor MN10 in the word line driver 102 corresponding to the word line to be turned on is turned on, the fourteenth PMOS transistor MP14 in the word line drivers 102 corresponding to the word lines to be turned off must be turned off. In this case, the level of the first control signal WLctrl is 1V, which cannot ensure that the fourteenth PMOS transistor MP14 is turned off. Therefore, the level of the first control signal WLctrl needs to be the same as the level of the second power supply voltage Pwr, for example, 3.3V.

[0089] From the above analysis, it can be seen that when the target memory array is in different operating states, the word line driver circuit 100 provided in an embodiment of the present disclosure provides different levels of the first control signal WLctrl to the word line drivers 102 corresponding to the word lines that do not need to be activated in the target memory array. In this way, while ensuring that the target memory array can be in different operating states, the level of the first control signal WLctrl can be reduced as much as possible when shutting down all word lines in the target memory array, thereby reducing leakage of the word line driver circuit 100 and reducing the overall power consumption of the word line driver circuit 100.

[0090] It should be noted that in the above description of high level and low level, the high level can be a level value greater than or equal to the power supply voltage, and the low level can be a level value less than or equal to the ground voltage. Moreover, the high level and the low level are relative, and the specific level value ranges included in the high level and the low level can be determined according to the specific device. For example, for an NMOS transistor, the high level refers to the level value range of the gate voltage that can turn on the NMOS transistor, and the low level refers to the level value range of the gate voltage that can turn off the NMOS transistor; for a PMOS transistor, the low level refers to the level value range of the gate voltage that can turn on the PMOS transistor, and the high level refers to the level value range of the gate voltage that can turn off the PMOS transistor. In addition, the high level can be the logic level "1" in the above description, and the low level can be the logic level "0" in the above description.

[0091] In summary, the level of the first control signal WLctrl output by the word line driver controller 101 to the word line driver 102 is adjustable. That is, when the target memory array is in different operating states, the word line driver controller 101 can provide the first control signal WLctrl with different levels to the word line driver 102, thereby reducing the power consumption of the word line driver circuit 100 and reducing the overall leakage of the word line driver circuit 100.

[0092] Another embodiment of the present disclosure provides a memory including the aforementioned word line driver circuit and a memory array, wherein the memory array includes a target memory array. In this way, the power consumption and leakage of the word line driver circuit 100 are reduced, thereby facilitating the reduction of power consumption and leakage.

[0093] In some embodiments, the memory may be a DDR memory, for example, a DDR5 memory.

[0094] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A word line driving circuit, characterized in that: include: a word line driver controller configured to receive a first power supply voltage, wherein the level of the first power supply voltage is adjustable, and output a first control signal, wherein the level of the first control signal is equal to the ground voltage or the level of the first power supply voltage; a word line driver configured to receive a second power supply voltage and the first control signal and output a word line control signal, wherein the word line control signal controls opening or closing of a word line in a target memory array, wherein the word line driver corresponds to the word line in a one-to-one manner; The word line drivers corresponding to all the word lines in the target memory array are connected to the same second supply voltage.

2. The word line driving circuit according to claim 1, wherein: The word line driver controller is further configured to, if one of the word lines in the target storage array is turned on, provide the first control signal at a first level value to the multiple word line drivers corresponding to the remaining word lines in the target storage array; if all the word lines in the target storage array are turned off, provide the first control signal at a second level value to the multiple word line drivers corresponding to all the word lines in the target storage array, the second level value is less than the first level value, and the first level value and the second level value are both within the adjustable range of the level value of the first supply voltage.

3. The word line driving circuit according to claim 2, wherein: Also includes: The voltage regulating unit is configured to output the first supply voltage with an adjustable level value in response to an enable signal and a third control signal.

4. The word line driving circuit according to claim 3, wherein: The voltage regulating unit includes: a first branch and a second branch connected in parallel between the power supply node and the first node, the first branch being turned on or off in response to the enable signal, and the second branch being turned on or off in response to the third control signal; When the enable signal is in a valid state, the first branch is turned on and the first supply voltage at the first level is output through the first node; When the enable signal is in an invalid state and the third control signal is in a valid state, the second branch is turned on and the first branch is turned off, and the first supply voltage at the second level is output through the first node; The enable signal being in a valid state indicates that one of the word lines in the target storage array is turned on and the remaining word lines in the target storage array are turned off, and the enable signal being in an invalid state indicates that all the word lines in the target storage array are turned off.

5. The word line driving circuit according to claim 4, wherein: The level of the third control signal is adjustable, and the second level changes with the change of the level of the third control signal.

6. The word line driving circuit according to claim 4, wherein: When the second branch is turned on in response to the third control signal, the degree of conduction of the second branch decreases as the level of the third control signal decreases; The first branch includes: a first PMOS transistor, wherein a source of the first PMOS transistor is electrically connected to the power supply node, a drain of the first PMOS transistor is electrically connected to the first node, and a gate of the first PMOS transistor receives the enable signal; The second branch includes: A first NMOS transistor, wherein a drain of the first NMOS transistor is electrically connected to the power supply node, a source of the first NMOS transistor is electrically connected to the first node, and a gate of the first NMOS transistor receives the third control signal.

7. The word line driving circuit according to claim 5, wherein: Also includes: a third control signal generating circuit, configured to provide the third control signal with an adjustable level to the second branch; The third control signal generating circuit includes a digital-to-analog converter.

8. The word line driving circuit according to claim 5, wherein: Also includes: a third control signal generating circuit, configured to provide the third control signal with an adjustable level to the second branch; The third control signal generating circuit includes an adaptive bias circuit, and the adaptive bias circuit includes: a current mirror, wherein one end of the current mirror receives a reference current, the other end of the current mirror is electrically connected to a second node, and the second node outputs the third control signal; The voltage regulator is electrically connected between the second node and a ground node, and is configured to adjust the voltage at the second node based on a change in performance of the voltage regulator itself, so that the level of the third control signal is adjustable.

9. The word line driving circuit according to claim 8, wherein: The voltage regulator comprises: a second NMOS transistor, wherein a drain of the second NMOS transistor is electrically connected to the second node, the drain of the second NMOS transistor is electrically connected to the gate of the second NMOS transistor, and a threshold voltage of the second NMOS transistor decreases as the temperature of the second NMOS transistor increases; a third NMOS transistor, wherein the drain of the third NMOS transistor is electrically connected to the source of the second NMOS transistor, the drain of the third NMOS transistor is electrically connected to the gate of the third NMOS transistor, the source of the third NMOS transistor is electrically connected to the ground node, and the threshold voltage of the third NMOS transistor decreases as the temperature of the third NMOS transistor increases.

10. The word line driving circuit according to claim 5, wherein: Also includes: a third control signal generating circuit, configured to provide the third control signal with an adjustable level to the second branch; The third control signal generating circuit includes an adaptive bias circuit, and the adaptive bias circuit includes: A bias voltage generating circuit is configured to generate a bias voltage; an error amplifier configured to receive the bias voltage and the feedback voltage and output an output voltage, wherein a change trend of a level value of the output voltage is the same as a change trend of a level value of the feedback voltage; The second-stage amplifier circuit is configured to receive the output voltage and output the third control signal, wherein a change trend of a level value of the third control signal is opposite to a change trend of a level value of the output voltage; The feedback circuit is configured to receive the third control signal and output the feedback voltage, wherein a change trend of a level value of the feedback voltage is the same as a change trend of a level value of the third control signal.

11. A memory, characterized in that: The method comprises the word line driving circuit according to any one of claims 1 to 10, and a memory array, wherein the memory array comprises the target memory array.

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