Array substrate and manufacturing method thereof, and display panel

Abstract

The present application provides an array substrate, a manufacturing method thereof, and a display panel; the array substrate includes a substrate, an active layer, a gate insulating layer, a conductive layer, and a first electrode; the active layer includes a channel portion, a first conductor portion, and a second conductor portion; the conductive layer includes a gate and a drain; the orthographic projection of the gate on the active layer is located in the channel portion; the drain overlaps a portion of the first conductor portion; the first electrode is connected to the second conductor portion; in the direction from the first conductor portion to the second conductor portion, the first conductor portion has a first length, the second conductor portion has a second length, and the first length is greater than the second length; the drain of the present application is connected to the first conductor portion, and the first electrode is directly connected to the second conductor portion, thereby reducing the provision of a source electrode and a source contact hole; at the same time, the second length of the second conductor portion is less than the first length of the first conductor portion, thereby reducing the length of the active layer and the size of the transistor in the array substrate, and improving the technical problem of low pixel density in the product.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] Current display panels use top-gate indium gallium zinc oxide thin-film transistors (IGZO TFTs) to reduce parasitic capacitance. However, the number of masks required to form top-gate thin-film transistors is greater than that required to form bottom-gate thin-film transistors, resulting in increased costs and more processes.

[0003] In order to reduce the number of masks required in the preparation process of top-gate thin-film transistors, existing display panels use the same metal layer to form the gate, source and drain layers, thereby reducing the number of masks. However, this structure requires vias to be opened on both sides of the gate insulating layer so that the source and drain are electrically connected to the corresponding conductive active layer, which increases the size of the thin-film transistor and prevents the pixel density of the display panel from being further increased. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate and a manufacturing method thereof, and a display panel, to solve the technical problem of low pixel density in existing display panels.

[0005] An embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] an active layer disposed on one side of the substrate, the active layer comprising a channel portion and a first conductor portion and a second conductor portion disposed on both sides of the channel portion;

[0008] a gate insulating layer comprising a first insulating portion and a second insulating portion spaced apart from each other, wherein the first insulating portion is disposed on a side of the active layer away from the substrate, and the second insulating portion is disposed at one end of the active layer;

[0009] a conductive layer disposed on a side of the gate insulating layer away from the substrate, the conductive layer comprising a gate and a drain disposed separately, the gate being located on the first insulating portion, an orthographic projection of the gate on the active layer being located within the channel portion; the drain being located on the second insulating portion, and overlapping a portion of the first conductive portion; and

[0010] a first electrode, disposed on a side of the conductive layer away from the substrate, the first electrode being connected to the second conductor portion;

[0011] In the direction from the first conductor portion to the second conductor portion, the first conductor portion has a first length, the second conductor portion has a second length, and the first length is greater than the second length.

[0012] In the array substrate of the present application, the ratio of the first length to the second length ranges from 1.2 to 2.

[0013] In the array substrate of the present application, a first via hole is provided between the first insulating portion and the second insulating portion, the drain contacts the side wall of the second insulating portion and extends along the side wall to the surface of the first conductor portion away from the substrate.

[0014] In the array substrate of the present application, the drain electrode includes an overlapping surface in contact with the first conductor portion, and a length of the overlapping surface in a direction from the first conductor portion to the channel portion is 2 micrometers to 8 micrometers.

[0015] In the array substrate of the present application, the array substrate further includes:

[0016] a first passivation layer, disposed on a side of the conductive layer away from the substrate;

[0017] a planarization layer, disposed on a side of the first passivation layer away from the substrate;

[0018] a common electrode, disposed on a side of the planar layer away from the substrate;

[0019] a second passivation layer, provided on a side of the common electrode away from the substrate;

[0020] The array substrate is further provided with a second via hole penetrating the second passivation layer, the flat layer and the first passivation layer. The first electrode is provided on a side of the second passivation layer away from the substrate, and the first electrode is connected to the second conductor portion through the second via hole.

[0021] In the array substrate of the present application, the inclination angle of the second via hole is less than 70°.

[0022] In the array substrate of the present application, the array substrate further includes:

[0023] a buffer layer, disposed between the substrate and the active layer;

[0024] At least one transmission line for transmitting a voltage signal, wherein the transmission line and the active layer are both arranged on a surface of the buffer layer away from the substrate.

[0025] In the array substrate of the present application, the material of the transmission line is the same as the material of the first conductor part and / or the second conductor part.

[0026] This application also proposes a method for manufacturing an array substrate, which includes:

[0027] providing a substrate;

[0028] forming an active layer on the substrate;

[0029] forming a gate insulating layer on the active layer, and opening a first via hole in the gate insulating layer;

[0030] performing a first conductorization process on the active layer not covered by the gate insulating layer;

[0031] forming a conductive material layer on the gate insulating layer, and patterning the conductive material layer so that the conductive material layer forms a conductive layer including a gate electrode and a drain electrode, wherein the gate electrode and the drain electrode are separately arranged;

[0032] Using a self-aligned process, etching the gate insulating layer not covered by the gate and the drain to form a first insulating portion and a second insulating portion spaced apart from each other in the gate insulating layer, wherein the first insulating portion is disposed on a side of the active layer away from the substrate, and the second insulating portion is disposed at one end of the active layer, the gate is located on the first insulating portion, the drain is located on the second insulating portion, and the drain overlaps the active layer corresponding to the first via hole;

[0033] Performing a second conductorization process on the active layer not covered by the gate and the drain, so that the active layer corresponding to the gate forms a channel portion, the active layer connected to the channel portion and close to the drain forms a first conductor portion, and the active layer connected to the channel portion and away from the drain forms a second conductor portion;

[0034] forming a first electrode connected to the second conductor portion on a side of the conductive layer away from the substrate;

[0035] In the direction from the first conductor portion to the second conductor portion, the first conductor portion has a first length, the second conductor portion has a second length, and the first length is greater than the second length.

[0036] The present application also proposes a display panel, which includes the above-mentioned array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0038] Figure 1 This is a first structural diagram of the array substrate provided in this application.

[0039] Figure 2 This is a second structural diagram of the array substrate provided in this application.

[0040] Figure 3 This is a top view of the active layer in the array substrate provided in this application.

[0041] Figure 4 This is a structural diagram of the display panel provided in this application.

[0042] Figure 5 This is a step diagram of the method for manufacturing the array substrate provided in this application.

[0043] Figures 6A to 6H This is a structural diagram of each step in the method for manufacturing the array substrate provided in this application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application and are not intended to limit the present application.

[0045] In the description of this application, it should be understood that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, and "at least one" means one, two, or more, unless otherwise specifically defined.

[0047] See also Figures 1 to 4An embodiment of the present application provides an array substrate 100, which includes a substrate 110, an active layer 140, a gate insulating layer 150, a conductive layer 160 and a first electrode PE. The active layer 140 is arranged on one side of the substrate 110, the gate insulating layer 150 is arranged on the side of the active layer 140 away from the substrate 110, the conductive layer 160 is arranged on the side of the gate insulating layer 150 away from the substrate 110, and the first electrode PE is arranged on the side of the conductive layer 160 away from the substrate 110.

[0048] In this embodiment, the active layer 140 includes a channel portion 141 and a first conductor portion 142 and a second conductor portion 143 arranged on both sides of the channel portion 141; the gate insulating layer 150 includes a first insulating portion 151 and a second insulating portion 152 arranged at intervals, the first insulating portion 151 is arranged on a side of the active layer 140 away from the substrate 110, and the second insulating portion 152 is arranged at one end of the active layer 140; the conductive layer 160 includes a gate 161 and a drain 162 arranged separately, the gate 161 is located on the first insulating portion 151, and the orthographic projection of the gate 161 on the active layer 140 is located in the channel portion 141; the drain 162 is located on the second insulating portion 152, and the drain 162 overlaps a portion of the first conductor portion 142; the first electrode PE is connected to the second conductor portion 143.

[0049] In this example, see Figure 3 In the direction from the first conductor portion 142 to the second conductor portion 143 , the first conductor portion 142 has a first length L1 , and the second conductor portion 143 has a second length L2 , and the first length L1 is greater than the second length L2 .

[0050] In an embodiment, the ratio of the first length L1 to the second length L2 ranges from 1.2 to 2.

[0051] See also Figures 1 to 3 Since the drain electrode 162 is connected to the first conductor portion 142 and the first electrode PE is directly connected to the second conductor portion 143, the second conductor portion 143 can be reused as a source electrode, eliminating the need for a source electrode. The gate insulating layer 150 does not need to be provided with a source contact hole for connecting the drain electrode 162 in the region where the second conductor portion 143 is located. Furthermore, the second length L2 of the second conductor portion 143 is less than the first length L1 of the first conductor portion 142, thereby reducing the length of the active layer 140. This is equivalent to reducing the size of the transistors in the array substrate 100, allowing for more transistors to be arranged in the product, thereby improving the pixel density of the product.

[0052] The technical solution of this application is now described in conjunction with specific embodiments.

[0053] See also Figure 1 and Figure 2The material of the substrate 110 can be a rigid substrate, such as glass, quartz and other rigid materials; the material of the substrate 110 can be a flexible substrate, such as polyimide and other flexible materials.

[0054] See also Figure 1 and Figure 2 The array substrate 100 includes a light shielding layer 120 provided on one side of the substrate 110 , and the active layer 140 is projected on the light shielding layer 120 and located within the light shielding layer 120 , so as to prevent the device effect of the transistor from being reduced due to light entering the channel portion 141 .

[0055] See also Figure 1 and Figure 2 The light-shielding layer 120 may be a light-shielding metal or other material with light-shielding properties, such as molybdenum, aluminum, copper, titanium, or alloys of the above materials or stacked layers of the above materials.

[0056] In this embodiment, the thickness of the light shielding layer 120 ranges from 1000 angstroms to 8000 angstroms.

[0057] See also Figure 1 and Figure 2 The array substrate 100 also includes a buffer layer 130 arranged on the side of the light-shielding layer 120 away from the substrate 110. The buffer layer 130 covers the light-shielding layer 120 and is laid on the entire array substrate 100. The material of the buffer layer 130 may include a compound composed of nitrogen, silicon and oxygen elements. For example, the material of the buffer layer 130 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0058] In this embodiment, the buffer layer 130 has a thickness ranging from 6000 angstroms to 10000 angstroms.

[0059] See also Figure 1 and Figure 2 The array substrate 100 further includes an active layer 140 disposed on a side of the buffer layer 130 away from the substrate 110 . The active layer 140 includes a channel portion 141 and a first conductor portion 142 and a second conductor portion 143 disposed on both sides of the channel portion 141 .

[0060] In this embodiment, the active layer 140 can be formed by physical vapor deposition and patterned by yellow light process and etching process; the material of the active layer 140 can be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides. The following embodiments of this application take IGZO as an example for illustration.

[0061] In this embodiment, the thickness of the active layer 140 ranges from 400 angstroms to 1000 angstroms.

[0062] See also Figure 1 and Figure 2 The array substrate 100 further includes a gate insulating layer 150 disposed on a side of the active layer 140 away from the substrate 110. The gate insulating layer 150 includes a first insulating portion 151 and a second insulating portion 152 spaced apart from each other. A first via hole HL1 is provided between the first insulating portion 151 and the second insulating portion 152. The first via hole HL1 exposes a portion of the first conductor portion 142.

[0063] In this embodiment, the material of the gate insulating layer 150 may include a compound composed of nitrogen, silicon and oxygen. For example, the material of the gate insulating layer 150 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0064] In this embodiment, the gate insulating layer 150 has a thickness ranging from 1000 angstroms to 3000 angstroms.

[0065] See also Figure 1 and Figure 2 The array substrate 100 further includes a conductive layer 160 disposed on the gate insulating layer 150. The material of the conductive layer 160 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the material of the conductive layer 160 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0066] In this embodiment, the thickness of the conductive layer 160 ranges from 2000 angstroms to 8000 angstroms.

[0067] In this embodiment, the conductive layer 160 can be patterned using a yellow light process and an etching process to form a pattern of the conductive layer 160 including a gate 161 and a drain 162. Then, the gate insulation layer 150 is self-aligned using the pattern of the conductive layer 160 to complete the pattern processing of the gate insulation layer 150.

[0068] In this embodiment, the gate 161 is located on the first insulating portion 151, the drain 162 is located on the second insulating portion 152, and the gate 161 corresponds to the channel portion 141, that is, the orthographic projection of the gate 161 on the active layer 140 overlaps with the channel portion 141; the drain 162 contacts the side wall of the second insulating portion 152 and extends along the side wall to the surface of the first conductor portion 142 away from the substrate 110, so that the drain 162 is electrically connected to the first conductor portion 142.

[0069] See also Figure 1 and Figure 2 The array substrate 100 further includes a first passivation layer 170 disposed on a side of the conductive layer 160 away from the substrate 110 . The first passivation layer 170 is laid as a whole layer. The thickness of the first passivation layer 170 ranges from 1000 angstroms to 5000 angstroms.

[0070] See also Figure 1 and Figure 2 The array substrate 100 further includes a flat layer 180 disposed on a side of the first passivation layer 170 away from the substrate 110, and the flat layer 180 is laid as a whole layer; the material of the flat layer 180 includes a flexible material such as polytetrafluoroethylene, and the thickness of the flat layer 180 ranges from 10,000 angstroms to 30,000 angstroms.

[0071] See also Figure 1 The array substrate 100 further includes a common electrode AE ​​disposed on a side of the planar layer 180 away from the substrate 110 . The material of the common electrode AE ​​may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0072] See also Figure 1 The array substrate 100 further includes a second passivation layer 190 disposed on a side of the common electrode AE ​​away from the substrate 110. The second passivation layer 190 is laid as a whole layer; the thickness of the second passivation layer 190 ranges from 1000 angstroms to 5000 angstroms.

[0073] In this embodiment, the materials of the first passivation layer 170 and the second passivation layer 190 can be the same. The materials of the first passivation layer 170 and the second passivation layer 190 can include compounds composed of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0074] See also Figure 1 The array substrate 100 further includes a first electrode PE disposed on a side of the second passivation layer 190 away from the substrate 110 . The material of the first electrode PE may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0075] In this embodiment, a second via hole HL2 is further provided on the array substrate 100, penetrating the second passivation layer 190, the flat layer 180 and a portion of the first passivation layer 170. The first electrode PE is provided on a side of the second passivation layer 190 away from the substrate 110, and the first electrode PE is connected to the second conductor portion 143 through the second via hole HL2.

[0076] exist Figure 1 and Figure 2 In the structure, since the thickness of the flat layer 180 is large, the depth of the second via hole HL2 is large. In order to avoid the first electrode PE being disconnected on the side wall of the second via hole HL2, the inclination angle of the second via hole HL2 of the present application cannot be too large. For example, the inclination angle a of the second via hole HL2 of the present application can be less than 70°.

[0077] See also Figure 2 The first electrode PE may be directly disposed on the side of the planar layer 180 away from the substrate 110 , and the first electrode PE may pass through the second via hole HL2 and be connected to the second conductor portion 143 .

[0078] It should be noted that Figure 1 and Figure 2 The structures in the embodiment can be applied to liquid crystal display panels, and the first electrode PE can be a pixel electrode; Figure 2 The structure in the embodiment can also be applied to organic light emitting diode display panels or MiniLED, MicroLED, etc. Figure 2 When the structure in FIG. 1 is applied to an organic light emitting diode display panel, the first electrode PE may be an anode.

[0079] It should be noted that since the drain electrode 162 extends to the active layer 140 corresponding to the first via hole HL1, and in the subsequent conductorization process, the active layer 140 in contact with the drain electrode 162 cannot be conductorized due to the obstruction of the drain electrode 162, therefore, after the first via hole HL1 is opened on the gate insulating layer 150, the present application needs to perform a first conductorization process on the active layer 140 corresponding to the first via hole HL1; at the same time, after completing the patterning process of the conductive layer 160, the active layer 140 not blocked by the drain electrode 162, the gate electrode 161 and the gate insulating layer needs to be subjected to a second conductorization process.

[0080] In this embodiment, the first conductive treatment and the second conductive treatment of the present application may both be plasma treatments to remove oxygen elements in the active layer 140 .

[0081] It should be noted that, since the area of ​​the first conductor portion 142 not blocked by the drain electrode 162 undergoes the conductorization treatment twice, while the second conductor portion 143 undergoes the conductorization treatment only once, the oxygen content of the first conductor portion 142 not blocked by the drain electrode 162 of the present application can be less than the oxygen content of the second conductor portion 143, that is, the resistivity of the first conductor portion 142 is less than the resistivity of the second conductor portion 143; Figure 1 and Figure 2In the structure, the first conductor portion 142 includes an adjacent first portion 142a and a second portion 142b. The first portion 142a corresponds to the first via HL1. Since the first portion 142a undergoes two conductorization treatments, the oxygen content of the first portion 142a of the present application is less than the oxygen content of the second portion 142b, that is, the resistivity of the first portion 142a is less than the resistivity of the second portion 142b.

[0082] In this embodiment, to ensure electrical connection between the drain electrode 162 and the first conductor portion 142, the contact area between the drain electrode 162 and the first conductor portion 142 cannot be too small. For example, the drain electrode 162 includes an overlapping surface in contact with the first conductor portion 142, and the length L3 of the overlapping surface in the direction from the first conductor portion 142 to the channel portion 141 is 2 microns to 8 microns.

[0083] Since the gate 161 and the drain 162 are both made of the same metal layer, it is equivalent to reducing one metal layer and the insulating layer between the two metal layers. This process can reduce the number of masks, but due to the reduction in the number of metal layers, the wiring space of the metal lines in the product is limited.

[0084] In this example, see Figure 1 and Figure 2 The array substrate 100 further includes at least one transmission line 143 for transmitting a voltage signal. The transmission line 143 and the active layer 140 are both disposed on the surface of the buffer layer 130, and the material of the transmission line 143 is the same as that of the first conductor portion 142 and / or the second conductor portion 143. In other words, the present application can simultaneously utilize the material of the active layer 140 when preparing the active layer 140 to prepare the transmission line 143 for transmitting voltage signals in the display panel, such as a high potential line, a low potential line, a clock signal line, a start signal line, a data signal line, and the like.

[0085] See also Figure 4 This application also proposes a display panel 200, which includes the above-mentioned array substrate 100 and a light-emitting component 300 disposed on one side of the array substrate 100. When the display panel 200 is a liquid crystal display panel, the light-emitting component 300 can be a backlight module, and the side of the display panel 200 facing away from the light-emitting component 300 is the light-emitting side; when the display panel 200 is an organic light-emitting diode display panel, the light-emitting component 300 can be an organic light-emitting diode; when the display panel 200 is a direct display panel, the light-emitting component 300 can be MiniLED, MicroLED, etc.

[0086] See also Figure 5 , the present application also proposes a method for manufacturing the array substrate 100, which includes:

[0087] S101 , providing a substrate 110 .

[0088] See also Figure 6A The material of the substrate 110 can be a rigid substrate, such as glass, quartz and other rigid materials; the material of the substrate 110 can be a flexible substrate, such as polyimide and other flexible materials.

[0089] Before step S102 , the process further includes forming a light shielding layer 120 and a buffer layer 130 on the substrate 110 .

[0090] See also Figure 6A The light shielding layer 120 can be a light shielding metal or other materials with light shielding properties. The light shielding layer 120 is patterned to form Figure 6A In the structure shown, the buffer layer 130 covers the light shielding layer 120 and is laid on the entire array substrate 100 .

[0091] S102 , forming an active layer 140 on the substrate 110 .

[0092] See also Figure 6B The active layer 140 can be formed by physical vapor deposition and patterned by yellow light process and etching process; the material of the active layer 140 can be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides. The following embodiments of this application take IGZO as an example for illustration.

[0093] See also Figure 6B When the active layer 140 is formed on the buffer layer 130 , at least one active line 143 a is also formed on the buffer layer 130 . The material of the active line 143 a is the same as that of the active layer 140 , and the active line 143 a and the active layer 140 are formed in the same photomask process.

[0094] S103 , forming a gate insulating layer 150 on the active layer 140 , and opening a first via hole HL1 in the gate insulating layer 150 .

[0095] See also Figure 6C The gate insulating layer 150 is laid as a whole layer to completely cover the active layer 140 . Meanwhile, for the purpose of subsequent conductor processing, the first via hole HL1 in this step exposes a portion of the active layer 140 .

[0096] S104 , performing a first conductorization process on the active layer 140 not covered by the gate insulating layer 150 .

[0097] See also Figure 6CThe first conductive treatment of the present application may be a plasma treatment to remove oxygen elements in the active layer 140 not covered by the gate insulating layer 150 , so as to make the active layer 140 not covered by the gate insulating layer 150 conductive.

[0098] S105 , forming a conductive material layer on the gate insulating layer 150 , and patterning the conductive material layer to form a conductive layer 160 including a gate electrode 161 and a drain electrode 162 , wherein the gate electrode 161 and the drain electrode 162 are separately provided.

[0099] See also Figure 6D Step S105 includes: forming a conductive material layer on the gate insulating layer 150; and patterning the conductive layer 160 using a photolithography process and an etching process, so that the conductive layer 160 forms a pattern including a gate electrode 161 and a drain electrode 162.

[0100] In this embodiment, the material of the conductive layer 160 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0101] S106. Using a self-alignment process, the gate insulating layer 150 that is not covered by the gate 161 and the drain 162 is etched to form a first insulating portion 151 and a second insulating portion 152 that are spaced apart from each other in the gate insulating layer 150. The first insulating portion 151 is arranged on a side of the active layer 140 away from the substrate 110, and the second insulating portion 152 is arranged at one end of the active layer 140. The gate 161 is located on the first insulating portion 151, and the drain 162 is located on the second insulating portion 152. The drain 162 overlaps the active layer 140 corresponding to the first via hole HL1.

[0102] See also Figure 6E , using the patterns of the gate electrode 161 and the source electrode 162 in the conductive layer 160 as a mask, and performing a self-alignment process on the gate insulating layer 150 to remove the gate insulating layer 150 not covered by the gate electrode 161 and the drain electrode 162, so that the gate insulating layer 150 forms a first insulating portion 151 and a second insulating portion 152 that are spaced apart.

[0103] S107. Perform a second conductorization treatment on the active layer 140 not covered by the gate 161 and the drain 162, so that the active layer 140 corresponding to the gate 161 forms a channel portion 141, the active layer 140 connected to the channel portion 141 and close to the drain 162 forms a first conductor portion 142, and the active layer 140 connected to the channel portion 141 and away from the drain 162 forms a second conductor portion 143.

[0104] See also Figure 6FThe second conductorization treatment of the present application may be a plasma treatment to remove oxygen elements in the active layer 140 that are not blocked by the drain electrode 162, the gate electrode 161, and the gate insulation, so that the portion of the active layer 140 close to the drain electrode 162 forms the first conductor portion 142, and the portion of the active layer 140 away from the drain electrode 162 forms the second conductor portion 143.

[0105] In this embodiment, since the area of ​​the first conductor portion 142 not blocked by the drain electrode 162 is subjected to the conductorization process twice, and the second conductor portion 143 is subjected to the conductorization process only once, the oxygen content of the first conductor portion 142 not blocked by the drain electrode 162 can be less than the oxygen content of the second conductor portion 143, that is, the resistivity of the first conductor portion 142 is less than the resistivity of the second conductor portion 143; at the same time, Figure 6F In the structure, the first conductor portion 142 includes an adjacent first portion 142a and a second portion 142b. The first portion 142a corresponds to the first via HL1. Since the first portion 142a undergoes both the first and second conductorization processes, while the second portion 142b undergoes only the first and second conductorization processes, the oxygen content of the first portion 142a of the present application is less than that of the second portion 142b, that is, the resistivity of the first portion 142a is less than that of the second portion 142b.

[0106] In the step, in the direction from the first conductor portion 142 to the second conductor portion 143 , the first conductor portion 142 has a first length L1 , and the second conductor portion 143 has a second length L2 , and the first length L1 is greater than the second length L2 .

[0107] At the same time, since the drain 162 is connected to the first conductor portion 142, the first electrode PE is directly connected to the second conductor portion 143, and the second conductor portion 143 can be reused as a source, eliminating the need for a source. The gate insulating layer 150 does not need to be provided with a source contact hole for connecting the drain 162 in the area where the second conductor portion 143 is located. At the same time, the second length L2 of the second conductor portion 143 is less than the first length L1 of the first conductor portion 142, thereby reducing the length of the active layer 140, which is equivalent to reducing the size of the transistors in the array substrate 100, so that more transistors can be arranged in the product, thereby improving the pixel density of the product.

[0108] In this step, since the active line 143a is not blocked by the gate insulation layer 150, the active line 143a is formed into a transmission line 143 for transmitting a voltage signal through the second conductorization process. For example, the transmission line 143 can be a high potential line, a low potential line, a clock signal line, a start signal line, a data signal line, etc.

[0109] S108 , forming a first electrode PE connected to the second conductor portion 143 on a side of the conductive layer 160 away from the substrate 110 .

[0110] See also Figure 6G Before step S108, the process also includes: forming a first passivation layer 170 on a side of the conductive layer 160 away from the substrate 110; forming a planarization layer 180 on a side of the first passivation layer 170 away from the substrate 110; forming a common electrode AE ​​on a side of the planarization layer 180 away from the substrate 110; and forming a second passivation layer 190 on a side of the common electrode AE ​​away from the substrate 110.

[0111] It should be noted that during the processes of the first passivation layer 170 , the planar layer 180 and the second passivation layer 190 , via holes are required to expose part of the second conductor portion 143 . The via holes in the first passivation layer 170 , the planar layer 180 and the second passivation layer 190 are continuous and form the second via hole HL2 .

[0112] See also Figure 6G The first electrode PE is electrically connected to the second conductor portion 143 through the second via hole HL2 .

[0113] In this embodiment, the materials of the buffer layer 130, the gate insulation layer 150, the first passivation layer 170 and the second passivation layer 190 may include compounds composed of nitrogen, silicon and oxygen, such as a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0114] In this embodiment, the material of the planar layer 180 includes flexible materials such as polytetrafluoroethylene.

[0115] In this embodiment, the materials of the first electrode PE and the common electrode AE ​​may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0116] See also Figure 6H Before step S108 , the method further includes: forming a first passivation layer 170 on a side of the conductive layer 160 away from the substrate 110 ; and forming a planarization layer 180 on a side of the first passivation layer 170 away from the substrate 110 .

[0117] See also Figure 6H The first electrode PE may be directly disposed on the side of the planar layer 180 away from the substrate 110 , and the first electrode PE may pass through the second via hole HL2 and be connected to the second conductor portion 143 .

[0118] exist Figure 6G and Figure 6HIn the structure, since the thickness of the flat layer 180 is large, the depth of the second via hole HL2 is large. In order to avoid the first electrode PE being disconnected on the side wall of the second via hole HL2, the inclination angle of the second via hole HL2 of the present application cannot be too large. For example, the inclination angle a of the second via hole HL2 of the present application can be less than 70°.

[0119] It should be noted that Figure 6G and Figure 6H The structures in the embodiment can be applied to liquid crystal display panels, and the first electrode PE can be a pixel electrode; Figure 6H The structure in the embodiment can also be applied to organic light emitting diode display panels or MiniLED, MicroLED, etc. Figure 6H When the structure in FIG. 1 is applied to an organic light emitting diode display panel, the first electrode PE may be an anode.

[0120] This application also proposes a mobile terminal comprising a terminal body and the aforementioned display panel, the terminal body and display panel being integrated into one body. The terminal body may comprise a component such as a circuit board bound to the display panel, and a cover plate disposed on the display panel. Mobile terminals may include electronic devices such as mobile phones, televisions, and laptop computers.

[0121] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0122] The above is a detailed introduction to the technical solutions provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; an active layer disposed on one side of the substrate, the active layer comprising a channel portion and a first conductor portion and a second conductor portion disposed on both sides of the channel portion; a gate insulating layer comprising a first insulating portion and a second insulating portion spaced apart from each other, wherein the first insulating portion is disposed on a side of the active layer away from the substrate, the second insulating portion is disposed at one end of the active layer, and a first via hole is disposed between the first insulating portion and the second insulating portion; a conductive layer disposed on a side of the gate insulating layer away from the substrate, the conductive layer comprising a gate and a drain disposed separately, the gate being located on the first insulating portion, an orthographic projection of the gate on the active layer being located within the channel portion; the drain being located on the second insulating portion, overlapping a portion of the first conductive portion, contacting a sidewall of the second insulating portion, and extending along the sidewall to a surface of the first conductive portion away from the substrate; as well as a first electrode, disposed on a side of the conductive layer away from the substrate, the first electrode being connected to the second conductor portion; In a direction from the first conductor portion to the second conductor portion, the first conductor portion has a first length, the second conductor portion has a second length, and the first length is greater than the second length; The first conductor portion includes a first portion and a second portion that are adjacent to each other, the first portion corresponds to the first via hole, and the resistivity of the first portion is smaller than the resistivity of the second portion.

2. The array substrate according to claim 1, wherein: The ratio of the first length to the second length ranges from 1.2 to 2.

3. The array substrate according to claim 1, wherein: The drain electrode includes an overlapping surface in contact with the first conductor portion, and a length of the overlapping surface in a direction from the first conductor portion to the channel portion is 2 micrometers to 8 micrometers.

4. The array substrate according to any one of claims 1 to 3, characterized in that: The array substrate further includes: a first passivation layer, disposed on a side of the conductive layer away from the substrate; a planarization layer, disposed on a side of the first passivation layer away from the substrate; a common electrode, disposed on a side of the planar layer away from the substrate; a second passivation layer, provided on a side of the common electrode away from the substrate; The array substrate is further provided with a second via hole penetrating the second passivation layer, the flat layer and the first passivation layer. The first electrode is provided on a side of the second passivation layer away from the substrate, and the first electrode is connected to the second conductor portion through the second via hole.

5. The array substrate according to claim 4, wherein: The inclination angle of the second via hole is less than 70°.

6. The array substrate according to any one of claims 1 to 3, characterized in that: The array substrate further includes: a buffer layer, disposed between the substrate and the active layer; At least one transmission line for transmitting a voltage signal, wherein the transmission line and the active layer are both arranged on a surface of the buffer layer away from the substrate.

7. The array substrate according to claim 6, wherein: The material of the transmission line is the same as that of the first conductor part and / or the second conductor part.

8. A method for preparing the array substrate according to any one of claims 1 to 7, characterized in that: include: providing a substrate; forming an active layer on the substrate; forming a gate insulating layer on the active layer, and opening a first via hole in the gate insulating layer; performing a first conductorization process on the active layer not covered by the gate insulating layer; forming a conductive material layer on the gate insulating layer, and patterning the conductive material layer so that the conductive material layer forms a conductive layer including a gate electrode and a drain electrode, wherein the gate electrode and the drain electrode are separately arranged; Using a self-aligned process, etching the gate insulating layer not covered by the gate and the drain to form a first insulating portion and a second insulating portion spaced apart from each other in the gate insulating layer, wherein the first insulating portion is disposed on a side of the active layer away from the substrate, and the second insulating portion is disposed at one end of the active layer, the gate is located on the first insulating portion, the drain is located on the second insulating portion, and the drain overlaps the active layer corresponding to the first via hole; Performing a second conductorization process on the active layer not covered by the gate and the drain, so that the active layer corresponding to the gate forms a channel portion, the active layer connected to the channel portion and close to the drain forms a first conductor portion, and the active layer connected to the channel portion and away from the drain forms a second conductor portion; forming a first electrode connected to the second conductor portion on a side of the conductive layer away from the substrate; In the direction from the first conductor portion to the second conductor portion, the first conductor portion has a first length, the second conductor portion has a second length, and the first length is greater than the second length.

9. A display panel, characterized in that: Comprising the array substrate according to any one of claims 1 to 7.

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