A process for reducing dislocation density in PN junction region of planar junction HgCdTe devices

Abstract

The present invention provides a process for reducing the dislocation density in the PN junction region of a planar junction HgCdTe device, comprising the following steps: S1) annealing a planar junction HgCdTe semi-finished product and mercury in a closed space, and the planar junction HgCdTe semi-finished product and mercury do not contact each other, to obtain an annealed semi-finished product; the planar junction HgCdTe semi-finished product comprises a silicon substrate, a CdTe buffer layer, a HgCdTe layer and a CdTe passivation layer arranged in sequence, an injection region is arranged in the CdTe passivation layer; the bottom of the injection region does not contain a CdTe passivation layer; S2) preparing a PN junction on the annealed semi-finished product. Compared with the prior art, the present invention utilizes the stress between the CdTe passivation layer and the HgCdTe layer in the non-injection region, the driving force of the dislocation movement is insufficient to overcome the resistance, and the dislocations moved during the high-temperature annealing process will be locked in the non-injection region without openings, thereby reducing the dislocation density in the PN junction region, thereby improving the PN junction performance.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a process for reducing the dislocation density in a PN junction region of a planar junction mercury cadmium telluride device. Background Art

[0002] Mercury cadmium telluride is an important material for preparing infrared detectors. Due to its adjustable bandgap width, the detection spectrum range extends from the shortwave band to the longwave band, and it has the advantages of high photoelectric detection efficiency. It is widely used in military and civilian fields such as early warning detection, infrared reconnaissance, and imaging guidance.

[0003] Dislocation is a common defect in HgCdTe materials, which usually extends from the substrate through the PN junction depletion region to the HgCdTe surface, affecting the performance of HgCdTe PN junction devices in the form of parallel resistance, recombination centers, and defect-assisted tunneling centers.

[0004] The common method of reducing dislocations in HgCdTe materials is high-temperature annealing, which allows dislocations to move and merge at high temperatures, thereby reducing the dislocation density on the surface of HgCdTe. However, the PN junction depletion region of the HgCdTe detector is generally only 1 to 3 μm below the surface, and the reduction in dislocation density in the depletion region caused by high-temperature annealing is not particularly ideal. In addition, there is a process for reducing dislocations by annealing mesa-junction HgCdTe, which can move dislocations to the side walls of the mesa-junction HgCdTe structure at high temperatures, reducing the impact of dislocations on the PN junction, but it is not suitable for planar-junction HgCdTe devices. Summary of the invention

[0005] In view of this, the technical problem to be solved by the present invention is to provide a process for reducing the dislocation density in the PN junction region of a planar junction HgCdTe device.

[0006] The present invention provides a process for reducing the dislocation density in the PN junction region of a planar junction HgCdTe device, comprising the following steps:

[0007] S1) annealing a planar junction HgCdTe semi-finished product and mercury in a closed space, wherein the planar junction HgCdTe semi-finished product and mercury do not contact each other, to obtain an annealed semi-finished product; the planar junction HgCdTe semi-finished product comprises a silicon substrate, a cadmium telluride buffer layer, a HgCdTe layer and a cadmium telluride passivation layer arranged in sequence, wherein an injection region is arranged in the cadmium telluride passivation layer; and the bottom of the injection region does not contain the cadmium telluride passivation layer;

[0008] S2) forming a PN junction on the annealed semi-finished product.

[0009] Preferably, the temperature of the annealing treatment is 200° C. to 550° C.; and the time of the annealing treatment is 5 to 60 minutes.

[0010] Preferably, the annealing treatment is specifically: firstly heating up to a high temperature condition for heat preservation treatment, and then cooling down to a low temperature condition for heat preservation treatment;

[0011] The temperature of the high temperature condition is 400°C to 550°C; the temperature of the low temperature condition is 200°C to 300°C; the time of the heat preservation treatment under the high temperature condition and the time of the heat preservation treatment under the low temperature condition are each independently 1 to 10 minutes.

[0012] Preferably, the heating time is 5 to 10 minutes; the cooling time is 5 to 30 minutes.

[0013] Preferably, the thickness of the cadmium telluride buffer layer is 6-10 μm; the thickness of the mercury cadmium telluride layer is 5-10 μm; the thickness of the cadmium telluride passivation layer is 100-500 nm; the bottom shape of the injection region is circular; the diameter of the circle is 25%-60% of the pixel pitch.

[0014] Preferably, the planar structured HgCdTe semi-finished product is prepared according to the following steps:

[0015] A1) growing a cadmium telluride buffer layer on the surface of a silicon substrate;

[0016] A2) growing a mercury cadmium telluride layer on the surface of the cadmium telluride buffer layer;

[0017] A3) growing a cadmium telluride passivation layer on the surface of the mercury cadmium telluride layer by molecular beam epitaxy;

[0018] A4) etching the surface of the cadmium telluride passivation layer to form an implantation region, and leaving the bottom of the implantation region bare to expose the mercury cadmium telluride layer.

[0019] Preferably, in step A2), a mercury cadmium telluride layer is grown by molecular beam epitaxy; the mercury cadmium telluride layer is (HgTe) 1-x (CdTe) x ; x is 0.2~0.4.

[0020] Preferably, the step S2) is specifically:

[0021] B1) growing a zinc sulfide passivation layer on the surface of the annealed semi-finished product to obtain a semi-finished product with a grown zinc sulfide passivation layer;

[0022] B2) vacuum annealing the semi-finished product having the zinc sulfide passivation layer grown thereon to obtain a semi-finished product having a P layer formed thereon;

[0023] B3) removing the zinc sulfide passivation layer within the implantation region of the semi-finished product forming the P layer, and implanting a trivalent element to form an N-type region to obtain a PN junction.

[0024] Preferably, the thickness of the zinc sulfide passivation layer is 100-500 nm.

[0025] Preferably, the dislocation density in the PN junction region in step S2) is 0.5×10 6 ~5×10 6 cm -2 .

[0026] The present invention provides a process for reducing the dislocation density in the PN junction region of a planar junction HgCdTe device, comprising the following steps: S1) annealing a planar junction HgCdTe semi-finished product and mercury in a closed space, and the planar junction HgCdTe semi-finished product and mercury do not contact each other, to obtain an annealed semi-finished product; the planar junction HgCdTe semi-finished product comprises a silicon substrate, a CdTe buffer layer, a HgCdTe layer and a CdTe passivation layer arranged in sequence, an injection region is arranged in the CdTe passivation layer; the bottom of the injection region does not contain a CdTe passivation layer; S2) preparing a PN junction on the annealed semi-finished product. Compared with the prior art, the present invention utilizes the stress between the CdTe passivation layer and the HgCdTe layer in the non-injection region, the driving force of the dislocation movement is insufficient to overcome the resistance, and the dislocations moved during the high-temperature annealing process will be locked in the non-injection region without openings, thereby reducing the dislocation density in the PN junction region, thereby improving the PN junction performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A process flow chart for reducing the dislocation density in the PN junction region of a planar junction HgCdTe device provided by the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] The invention provides a process for reducing the dislocation density in the PN junction region of a planar junction HgCdTe device, comprising the following steps: S1) subjecting a planar junction HgCdTe semi-finished product and mercury to an annealing treatment in a closed space, wherein the planar junction HgCdTe semi-finished product and the mercury do not contact each other, to obtain an annealed semi-finished product; the planar junction HgCdTe semi-finished product comprises a silicon substrate, a cadmium telluride buffer layer, a HgCdTe layer and a cadmium telluride passivation layer which are arranged in sequence, an injection region is arranged in the cadmium telluride passivation layer; and the bottom of the injection region does not contain the cadmium telluride passivation layer; S2) preparing a PN junction on the annealed semi-finished product.

[0030] The present invention has no particular limitation on the sources of all raw materials, and any raw materials available on the market can be used.

[0031] The present invention uses a planar junction HgCdTe semi-finished product as the object of annealing treatment; the planar junction HgCdTe semi-finished product comprises a silicon substrate, a CdTe buffer layer, a HgCdTe layer and a CdTe passivation layer arranged in sequence; wherein the silicon substrate can be a silicon substrate well known to those skilled in the art without any special limitation, and in the embodiments provided by the present invention, a (211) crystal orientation silicon substrate is specifically used as an example for explanation; a CdTe buffer layer is arranged on the surface of the silicon substrate; the thickness of the CdTe buffer layer is preferably 6 to 10 μm; a HgCdTe layer is arranged on the surface of the CdTe buffer layer away from the silicon substrate; The thickness of the mercury cadmium telluride layer is preferably 5-10 μm, more preferably 6-9 μm, and more preferably 8 μm; a cadmium sulfide passivation layer is provided on the surface of the mercury cadmium telluride layer away from the cadmium telluride buffer layer; the thickness of the cadmium sulfide passivation layer is preferably 100-500 nm, more preferably 100-400 nm, more preferably 200-300 nm, and most preferably 200 nm; an injection region is provided in the cadmium telluride passivation layer; the bottom of the injection region does not contain the cadmium telluride passivation layer; in a specific embodiment provided by the present invention, the mercury cadmium telluride layer is exposed at the bottom of the injection region. The present invention has no special requirements for the shape of the injection zone. In a specific embodiment provided by the present invention, the bottom shape of the injection zone is preferably circular; the diameter of the circle is preferably 25% to 60% of the pixel pitch, more preferably 30% to 50%, more preferably 35% to 45%, and most preferably 40%; in a specific embodiment provided by the present invention, taking a 15μm×15μm square pixel pitch as an example, the injection zone size is preferably a 4-9μm diameter circle, more preferably a 5-8μm diameter circle, and more preferably a 6μm diameter circle.

[0032] The planar junction HgCdTe semi-finished product can be prepared according to a method well known to those skilled in the art without any special limitation. In a specific embodiment provided by the present invention, the planar junction HgCdTe semi-finished product is prepared according to the following steps: A1) growing a cadmium telluride buffer layer on the surface of a silicon substrate; A2) growing a HgCdTe layer on the surface of the cadmium telluride buffer layer; A3) growing a cadmium telluride passivation layer on the surface of the HgCdTe layer by molecular beam epitaxy; A4) etching the surface of the cadmium telluride passivation layer to form an injection region, and leaving the bottom of the injection region bare to expose the HgCdTe layer. In the step A1), the cadmium telluride buffer layer is preferably grown by molecular beam epitaxy; the temperature of the molecular beam epitaxy for growing the cadmium telluride buffer layer is preferably 280°C to 350°C, more preferably 280°C to 320°C, and more preferably 300°C; in the step A2), the mercury cadmium telluride layer is preferably grown by molecular beam epitaxy; the temperature of the molecular beam epitaxy is preferably 170°C to 190°C, more preferably 180°C to 190°C, and more preferably 185°C; the mercury cadmium telluride layer is (HgTe) 1-x (CdTe) x; x is preferably 0.2-0.4, more preferably 0.25-0.35, and more preferably 0.29-0.31; in the step A3), a cadmium telluride passivation layer is grown on the surface of the mercury cadmium telluride layer by molecular beam epitaxy, so that a higher crystal quality can be obtained, and thus the mismatch stress between the cadmium telluride passivation layer and the mercury cadmium telluride epitaxial layer is greater, and dislocations can be better locked; the temperature for growing the cadmium telluride passivation layer by molecular beam epitaxy is preferably 170°C-190°C, more preferably 180°C-190°C, and more preferably 185°C; the cadmium telluride passivation layer may be a single crystal cadmium telluride passivation layer or a polycrystalline cadmium telluride passivation layer, and there is no special restriction; in the step A4), an implantation region is formed by etching the surface of the cadmium telluride passivation layer, and the etching method is a method well known to those skilled in the art, and there is no special restriction. In the present invention, dry etching and / or wet etching may be used.

[0033] The planar-junction HgCdTe semi-finished product and mercury are annealed in a closed space without contacting each other to obtain an annealed semi-finished product; in a specific embodiment provided by the present invention, the planar-junction HgCdTe semi-finished product and mercury are preferably sealed in a quartz tube, and then placed in an annealing furnace for annealing; mercury metal can prevent the surface of HgCdTe from deteriorating during high-temperature annealing; the annealing temperature is preferably 200°C to 550°C; the annealing time is preferably 5 to 60 minutes; in a specific embodiment provided by the present invention, the annealing is specifically: first heating to a high temperature condition for heat preservation treatment, and then cooling to a low temperature condition for heat preservation treatment; the heating time is preferably 5 to 10 minutes, more preferably 5 to 8 minutes, and more preferably 5 minutes; the high The temperature of the high temperature condition is preferably 400℃~550℃, more preferably 400℃~500℃, and more preferably 450℃; the time of the heat preservation treatment under the high temperature condition is preferably 1~10min, more preferably 1~8min, more preferably 1~5min, and most preferably 2~3min; then the temperature is reduced to the low temperature condition, and the cooling time is preferably 5~30min, more preferably 10~25min, more preferably 10~20min, and most preferably 15min; the temperature of the low temperature condition is preferably 200℃~300℃, more preferably 250℃; the time of the heat preservation treatment under the low temperature condition is preferably 1~10min, more preferably 1~8min, more preferably 1~5min, and most preferably 2~3min; after the heat preservation treatment under the low temperature condition, it is preferably reduced to room temperature.

[0034] In a specific embodiment provided by the present invention, the process flow for reducing the dislocation density in the PN junction region of the planar junction HgCdTe device is as follows: Figure 1 shown.

[0035] A PN junction is formed on the annealed semi-finished product, specifically, a PN junction is formed in the injection region; the steps of preparing the formed PN junction are steps well known to those skilled in the art and are not particularly limited. In a specific embodiment provided by the present invention, the steps are specifically: B1) growing a zinc sulfide passivation layer on the surface of the annealed semi-finished product to obtain a semi-finished product with a grown zinc sulfide passivation layer; B2) vacuum annealing the semi-finished product with the grown zinc sulfide passivation layer to obtain a semi-finished product with a P layer; B3) removing the zinc sulfide passivation layer within the injection region of the semi-finished product with the P layer, and injecting a trivalent element to form an N-type region to obtain a PN junction. Wherein, in the step B1), the zinc sulfide passivation layer is preferably grown by magnetron sputtering or thermal evaporation; the temperature for growing the zinc sulfide passivation layer is preferably 70°C to 90°C, more preferably 80°C; the thickness of the zinc sulfide passivation layer is preferably 100 to 500 nm, more preferably 100 to 400 nm, more preferably 200 to 300 nm, and most preferably 200 nm; the temperature for vacuum annealing in the step B2) is preferably 200°C to 400°C, more preferably 200°C to 350°C, more preferably 250°C to 300°C, and most preferably 250°C; the time for vacuum annealing is preferably 4 to 8 hours, more preferably 5 to 7 hours, and more preferably 6 hours; the vacuum degree of vacuum annealing is preferably less than 1×10 -4 Torr; in the step B3), the zinc sulfide passivation layer in the injection region of the semi-finished product forming the P layer is preferably removed by etching; the etching method is a method well known to those skilled in the art, which can be dry etching or wet etching; the trivalent element in the step B3) is preferably element B; in a specific embodiment provided by the present invention, the dislocation density in the PN junction region is preferably 0.5×10 6 ~5×10 6 cm -2 .

[0036] In another specific embodiment provided by the present invention, after the PN junction is prepared and formed, an electrode is preferably grown and then interconnected with a readout circuit to form a planar junction HgCdTe device.

[0037] The present invention utilizes the stress between the cadmium telluride passivation layer and the mercury cadmium telluride layer in the non-injection area, and the driving force for dislocation movement is insufficient to overcome the resistance. The dislocations that move during the high-temperature annealing process will be locked in the non-injection area without openings, thereby reducing the dislocation density in the PN junction area and further improving the PN junction performance.

[0038] In order to further illustrate the present invention, a process for reducing the dislocation density in the PN junction region of a planar junction HgCdTe device provided by the present invention is described in detail below in conjunction with an embodiment.

[0039] The reagents used in the following examples are all commercially available.

[0040] Example 1

[0041] 1.1 A cadmium telluride buffer layer with a thickness of 10 μm was grown by molecular beam epitaxy at 300°C on a (211) oriented silicon substrate;

[0042] 1.2 Growth of HgCdTe layer by molecular beam epitaxy at 185°C 1-x (CdTe) x , component x = 0.3 ± 0.01, thickness 8 μm);

[0043] 1.3 Using molecular beam epitaxy to epitaxially grow a 200nm cadmium telluride passivation layer at 185°C after HgCdTe epitaxy;

[0044] 1.4 Etching the implantation area (taking a 15μm×15μm square pixel as an example, the implantation area size is a 6μm diameter circle);

[0045] 1.5 High and low temperature annealing of sealed tube with mercury saturation, using high and low temperature cycle annealing, high temperature 450℃, low temperature 250℃, heating time 5 minutes, high temperature holding 2 minutes, cooling time 15 minutes, low temperature holding 2 minutes, and then cooling to room temperature;

[0046] 1.6 Magnetron sputtering was used to grow a 200 nm zinc sulfide passivation layer at 80 °C;

[0047] 1.7 Vacuum annealing to form the P layer; the vacuum annealing temperature is 250°C; the vacuum annealing time is 6 hours, and the vacuum degree of vacuum annealing is less than 1×10 -4 Torr;

[0048] 1.8 Etch the implanted area again to etch away the zinc sulfide in the implanted area;

[0049] 1.9 Ion implantation of element B forms an n-type region to form a PN junction;

[0050] 1.10 The grown electrodes are then interconnected with the readout circuit to form a HgCdTe device.

[0051] There is stress between the CdTe passivation layer and HgCdTe. The driving force of dislocation movement is insufficient to overcome the resistance. The dislocations that move during high-temperature annealing will be locked in the unopened area, thus reducing the dislocation density in the PN junction area to 0.5×10 6 ~5×10 6 cm -2 level.

[0052] Comparative Example 1

[0053] 1.1 A cadmium telluride buffer layer with a thickness of 10 μm was grown by molecular beam epitaxy at 300°C on a (211) oriented silicon substrate;

[0054] 1.2 Growth of HgCdTe layer by molecular beam epitaxy at 185°C 1-x (CdTe) x , component x = 0.3 ± 0.01, thickness 8 μm);

[0055] 1.3 Using molecular beam epitaxy to epitaxially grow a 200nm cadmium telluride passivation layer at 185°C after HgCdTe epitaxy;

[0056] 1.4 Magnetron sputtering was used to grow a 200 nm zinc sulfide passivation layer at 80 °C;

[0057] 1.5 Vacuum annealing to form the P layer; the vacuum annealing temperature is 250°C; the vacuum annealing time is 6 hours, and the vacuum degree of vacuum annealing is less than 1×10 -4 Torr;

[0058] 1.6 Etching the implantation area (taking a 15μm×15μm square pixel as an example, the implantation area size is a 6μm diameter circle);

[0059] 1.7 Ion implantation of element B forms an n-type region to form a PN junction;

[0060] 1.8 The grown electrodes are then interconnected with the readout circuit to form a HgCdTe device.

[0061] Due to the 19% lattice mismatch between silicon substrate and HgCdTe, the dislocation density of HgCdTe on silicon is generally 1×10 7 ~5×10 7 cm -2 Such a high dislocation density affects the performance of silicon-based HgCdTe devices.

[0062] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A process for reducing the dislocation density in the PN junction region of a planar junction HgCdTe device, characterized in that: The following steps are involved: S1) annealing a planar junction HgCdTe semi-finished product and mercury in a closed space, wherein the planar junction HgCdTe semi-finished product and mercury do not contact each other, to obtain an annealed semi-finished product; the planar junction HgCdTe semi-finished product comprises a silicon substrate, a cadmium telluride buffer layer, a HgCdTe layer and a cadmium telluride passivation layer arranged in sequence, wherein an injection region is arranged in the cadmium telluride passivation layer; and the bottom of the injection region does not contain the cadmium telluride passivation layer; S2) forming a PN junction on the annealed semi-finished product.

2. The process according to claim 1, characterized in that The temperature of the annealing treatment is 200° C. to 550° C.; the time of the annealing treatment is 5 to 60 minutes.

3. The process according to claim 1, characterized in that The annealing treatment is specifically: firstly heating the temperature to a high temperature condition for heat preservation treatment, and then cooling the temperature to a low temperature condition for heat preservation treatment; The temperature of the high temperature condition is 400°C to 550°C; the temperature of the low temperature condition is 200°C to 300°C; The time of the heat preservation treatment under the high temperature condition and the time of the heat preservation treatment under the low temperature condition are each independently 1 to 10 minutes.

4. The process according to claim 3, characterized in that The heating time is 5 to 10 minutes; the cooling time is 5 to 30 minutes.

5. The process according to claim 1, characterized in that The thickness of the cadmium telluride buffer layer is 6-10 μm; the thickness of the mercury cadmium telluride layer is 5-10 μm; the thickness of the cadmium telluride passivation layer is 100-500 nm; the bottom shape of the injection region is circular; the diameter of the circle is 25%-60% of the pixel pitch.

6. The process according to claim 1, characterized in that The planar structured HgCdTe semi-finished product is prepared according to the following steps: A1) growing a cadmium telluride buffer layer on the surface of a silicon substrate; A2) growing a mercury cadmium telluride layer on the surface of the cadmium telluride buffer layer; A3) growing a cadmium telluride passivation layer on the surface of the mercury cadmium telluride layer by molecular beam epitaxy; A4) etching the surface of the cadmium telluride passivation layer to form an implantation region, and leaving the bottom of the implantation region bare to expose the mercury cadmium telluride layer.

7. The process according to claim 6, characterized in that In the step A2), a mercury cadmium telluride layer is grown by molecular beam epitaxy; the mercury cadmium telluride layer is (HgTe) 1-x (CdTe) x ; x is 0.2~0.

4.

8. The process according to claim 1, characterized in that The step S2) is specifically as follows: B1) growing a zinc sulfide passivation layer on the surface of the annealed semi-finished product to obtain a semi-finished product with a grown zinc sulfide passivation layer; B2) vacuum annealing the semi-finished product having the zinc sulfide passivation layer grown thereon to obtain a semi-finished product having a P layer formed thereon; B3) removing the zinc sulfide passivation layer within the implantation region of the semi-finished product forming the P layer, and implanting a trivalent element to form an N-type region to obtain a PN junction.

9. The process according to claim 8, characterized in that The thickness of the zinc sulfide passivation layer is 100-500 nm.

10. The process according to claim 1, characterized in that The dislocation density in the PN junction region in step S2) is 0.5×10 6 ~5×10 6 cm -2 .

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