Programmable channel equalization of multi-level signals

Abstract

This application relates to programmable channel equalization for multi-level signaling. A memory interface can include a transmitter that generates a multi-level signal. The transmitter can employ channel equalization to improve the quality and robustness of the multi-level signal. Channel equalization can be controlled independently of the drive strength of the multi-level signal. For example, a first control signal can control de-emphasis or pre-emphasis applied to a multi-level signal, and a second control signal can control the drive strength of the multi-level signal. The first control signal can control a channel equalization driver circuit, and the second control signal can control a driver circuit.

Description

[0001] Related application information

[0002] This application is a divisional application. The parent of this divisional application is the patent application entitled “Programmable Channel Equalization for Multi-Level Signaling” having an application date of July 30, 2018, application number 201880045062.0, assigned to the assignee of the present application and incorporated herein by reference in its entirety.

[0003] Cross-reference to related applications

[0004] This patent application claims priority to Lin’s PCT Application No. PCT / US2018 / 044381 entitled “Programmable Channel Equalization for Multi-Level Signaling” filed July 30, 2018, which claims priority to Lin’s U.S. Patent Application No. 15 / 885,532 entitled “Programmable Channel Equalization for Multi-Level Signaling” filed January 31, 2018, which claims the benefit of Lin’s U.S. Provisional Patent Application No. 62 / 542,263 entitled “Programmable Channel Equalization for Multi-Level Signaling” filed August 7, 2017, each of which is assigned to the assignee of the present application and each of which is expressly incorporated herein by reference in its entirety. TECHNICAL FIELD

[0005] The technical field relates to programmable channel equalization for multi-level signaling.

[0006] Related applications

[0007] This patent application is related to Lin et al.’s U.S. Patent Application No. 15 / 885,536 entitled “Channel Equalization for Multi-Level Signaling” filed January 31, 2018, and Lin et al.’s U.S. Provisional Patent Application No. 62 / 542,166 entitled “Channel Equalization for Multi-Level Signaling” filed August 7, 2017, assigned to the assignee of the present application and each of which is expressly incorporated herein by reference in its entirety. BACKGROUND

[0008] The following generally relates to channel equalization, and more specifically to programmable channel equalization of multi-level signaling.

[0009] Memory devices are widely used in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like to store information. Information is stored by programming different states into memory cells of the memory devices. For example, binary devices have two states, typically represented by a logical "1" or a logical "0." In other systems, more than two states can be stored. To access stored information, components of the memory device can read or sense the stored states in the memory cells. To store information, components of the electronic device can write or program states in the memory cells.

[0010] There are a variety of types of memory devices, including magnetic hard disks, random access memory (RAM), dynamic access memory (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), read only memory (ROM), flash memory, phase change memory (PCM), self-organizing memory, and the like. Memory devices can be volatile or non-volatile. Non-volatile memory, such as flash memory, can retain their stored logic state for a longer period of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state over time unless they are periodically refreshed by an external power source. Improving memory devices can include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among others. SUMMARY

[0011] An apparatus is described. The apparatus can include a driver circuit in electronic communication with a first control line and a channel equalization driver circuit in electronic communication with a second control line different from the first control line, the driver circuit configured to modify its output current based at least in part on a first control signal received over the first control line, the channel equalization driver circuit configured to modify its output current based at least in part on a second control signal received over the second control line.

[0012] A method is described. The method can include receiving a first control signal at a driver circuit over a first control line, receiving a second control signal different from the first control signal at a channel equalization driver circuit over a second control line different from the first control line, modifying an output current of the driver circuit based at least in part on the first control signal, and modifying an output current of the channel equalization driver circuit based at least in part on the second control signal.

[0013] An apparatus is described. The apparatus can include a driver circuit including a first input in electronic communication with an output of a first pre-driver circuit and a second input in electronic communication with a first control line, the driver circuit configured to modify an intensity of a first output signal of the first pre-driver circuit based at least in part on a first control signal received over the first control line, and a channel equalization driver circuit including a third input in electronic communication with an output of a second pre-driver circuit and a fourth input in electronic communication with a second control line, the channel equalization driver circuit configured to modify an intensity of a second output signal of the second pre-driver circuit based at least in part on a second control signal received over the second control line.

[0014] An apparatus is described. The apparatus can include means for receiving a first control signal at a driver circuit over a first control line, means for receiving a second control signal different from the first control signal at a channel equalization driver circuit over a second control line different from the first control line, means for modifying an output current of the driver circuit based at least in part on the first control signal, and means for modifying an output current of the channel equalization driver circuit based at least in part on the second control signal. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 An example of a memory device that supports programmable channel equalization of multi-level signals is shown in accordance with various aspects of the present disclosure.

[0016] Figure 2 An example of an eye diagram that supports programmable channel equalization of multi-level signals is shown in accordance with various aspects of the present disclosure.

[0017] Figure 3 An example of a multi-level signal transmitter that supports programmable channel equalization of multi-level signals is shown in accordance with various aspects of the present disclosure.

[0018] Figure 4 A plot of a multi-level signal is shown in accordance with various aspects of the present disclosure.

[0019] Figure 5A portion of a multi-level signal transmitter that supports programmable channel equalization of multi-level signals is shown in accordance with various aspects of the present disclosure.

[0020] Figure 6 A portion of a multi-level signal transmitter that supports programmable channel equalization of multi-level signals is shown in accordance with various aspects of the present disclosure.

[0021] Figure 7 A flow diagram of a method of programmable channel equalization of multi-level signals is shown in accordance with various aspects of the present disclosure. DETAILED DESCRIPTION

[0022] Memory interfaces can enable communication of information stored by memory devices (e.g., for graphics). But in some cases, signals transmitted by memory interfaces can lose integrity due to distortions caused by the communication channel. For example, a signal can experience loss, delay, and reflections in the communication channel that change the signal. If a signal experiences too many changes, a receiver can be unable to decode the signal, and the information conveyed by the signal can be lost. When the signal is a multi-level signal (e.g., a multi-symbol signal) that conveys multiple bits of information per unit interval, even more information can be lost compared to a signal with fewer levels. The lost information can degrade system performance and overall user experience.

[0023] In some cases, de-emphasis or pre-emphasis can be applied to a multi-level signal to compensate for channel distortions. For example, a de-emphasis or pre-emphasis adjustment can be applied to a multi-level signal that is proportional to a drive strength used for the multi-level signal. Such de-emphasis (or pre-emphasis) can be implemented by using a single signal to control both the de-emphasis (or pre-emphasis) adjustment and the drive strength. But using a single signal to control both the de-emphasis (or pre-emphasis) and the drive strength can result in a ratio of de-emphasis (or pre-emphasis) to drive strength that is lower than an optimal ratio, which can degrade linearity of the multi-level signal. According to the techniques described herein, the de-emphasis (or pre-emphasis) and the drive strength can be independently controlled, such that an optimal ratio of de-emphasis (or pre-emphasis) to drive strength can be achieved, which in turn improves linearity of the multi-level signal. Improving linearity of the multi-level signal can improve a receiver’s ability to successfully obtain information conveyed by the multi-level signal.

[0024] The features of the disclosure introduced above are further described below in the context of a memory device. Particular examples of memory devices that support multi-level signaling with programmable de-emphasis or pre-emphasis are then described. These and other features of the disclosure are further shown and described with reference to device diagrams, system diagrams, and flow diagrams that relate to multi-level signaling (e.g., multi-symbol signaling). Multi-level signaling can refer to one or more signals having at least three levels that are modulated using a first modulation scheme.

[0025] Figure 1 An exemplary memory device 100 according to various examples of the disclosure is shown. The memory device 100 can also be referred to as an electronic storage. The memory device 100 can be configured to communicate data between various components of the memory device 100 using multi-level signaling. Multi-level signaling can also be referred to herein as multi-symbol signaling and can be implemented by a multi-level modulation scheme (e.g., PAM2, PAM4, PAM8, etc.). Thus, some examples of multi-level signaling can include PAM signaling, e.g., PAM4 signaling, PAM8 signaling, etc. The memory device 100 can include a memory cell array 105, a controller 110, a plurality of channels 115, a signaling interface 120, other components, or combinations thereof. The signaling interface 120 can also be referred to as a memory interface 120.

[0026] The memory device 100 can use multi-level signaling to increase the amount of information sent using a given frequency resource bandwidth. In binary level signaling, two symbols (e.g., two voltage levels) of a signal are used to represent up to two logic states (e.g., logic state ‘0’ or logic state ‘1’). In multi-level signaling, a larger library of symbols can be used to represent data. Each symbol can represent more than two logic states (e.g., logic states with multiple bits). For example, if a signal has four unique symbols, the signal can be used to represent up to four logic states (e.g., ‘00’, ‘01’, ‘10’, and ‘11’). Thus, multiple data bits can be compressed into a single symbol, increasing the amount of data communicated using a given bandwidth.

[0027] In some cases of multi-level signaling, the amplitude of a signal can be used to generate different symbols. For example, a first amplitude level can represent ‘00’, a second amplitude level can represent ‘01’, a third amplitude level can represent ‘10’, and a fourth amplitude level can represent ‘11’. One drawback of some multi-level signaling schemes is that the symbols can be separated by smaller voltage differences compared to symbols in other signaling schemes (e.g., binary level signaling schemes). Smaller voltage separations can make multi-level signaling schemes more susceptible to errors caused by noise or other factors. However, the voltage separation of symbols in a multi-level signaling scheme can be increased by increasing the peak-to-peak transmit power of the transmitted signal. However, in some cases, this increase in peak-to-peak transmit power can not be achievable or can be difficult to achieve due to a fixed power supply voltage, a fixed signal power requirement, or other factors. Thus, to implement multi-level signaling, a transmitter can use more power and / or a receiver can be more susceptible to increased error rates compared to binary level signaling schemes.

[0028] A multi-level signal (sometimes referred to as a multi-symbol signal) can be a signal modulated using a modulation scheme that includes three or more unique symbols to represent data (e.g., two or more data bits). A multi-level signal can be an example of an M-ary signal modulated using a modulation scheme, where M is greater than or equal to three, where M represents the number of unique symbols, levels, or conditions possible in the modulation scheme. In some cases, a multi-level signal or multi-level modulation scheme can be referred to as a non-binary signal or non-binary modulation scheme. Examples of multi-level (or M-ary) modulation schemes related to multi-level signals can include, but are not limited to, pulse amplitude modulation (e.g., PAM4, PAM8), quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others.

[0029] A binary-level signal (sometimes referred to as a binary-symbol signal) can be a signal modulated using a modulation scheme that includes two unique symbols to represent one data bit. A binary-level signal can be an example of an M-ary modulation scheme, where M is less than or equal to 2. Examples of binary-level modulation schemes related to binary-level signals include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, PAM2, and / or others.

[0030] In some cases, conditions of the channel 115 can further reduce voltage separation between multi-level signals and create inter-symbol interference (ISI), which can degrade the integrity of the multi-level signals and make them difficult to detect. The channel can affect the multi-level signals to the extent that the receiver 130 cannot successfully obtain the information conveyed by the multi-level signals, which can negatively impact the performance of the memory device 100. In some examples, the transmitter 125 can perform channel equalization before transmitting the multi-level signals through the channel 115. For example, the transmitter 125 can de-emphasize (or pre-emphasize) the multi-level signals before transmitting the signals through the channel 115. De-emphasizing or pre-emphasizing the multi-level signals can improve the separation between signal levels and increase detectability at the receiver 130. De-emphasizing or pre-emphasizing the signals can also be referred to herein as channel equalization. In some cases, the transmitter 125 can perform other types of channel equalization, such as feed-forward equalization (FFE). Although described with reference to de-emphasis and pre-emphasis, the channel equalization techniques disclosed herein are not limited to this aspect, but are related to the broader aspects associated with equalization.

[0031] In some cases, de-emphasis or pre-emphasis adjustment can be controlled by the same signal that controls the drive strength of the multi-level signal. However, using a single signal to control de-emphasis (or pre-emphasis) and drive strength can limit the de-emphasis (or pre-emphasis) to drive strength ratio that can be applied to a multi-level signal, which can result in undesirable characteristics of the signal (e.g., reduced linearity). According to the techniques described herein, de-emphasis (or pre-emphasis) adjustment applied to a multi-level signal can be controlled independently of the drive strength of the multi-level signal. For example, two separate signals can be used to control de-emphasis (or pre-emphasis) and drive strength. Using two separate signals can allow for flexible de-emphasis (or pre-emphasis) to drive strength ratios, which can improve linearity and output swing of the associated multi-level signal.

[0032] Each memory cell of the memory cell array 105 can be programmable to store different states. For example, each memory cell can be programmed to store two or more logic states (e.g., a logic '0', a logic'1 ', a logic '00', a logic '01', a logic'10', a logic'11 ', etc.). The memory cells can store electrical charges representing the programmable states in capacitors; for example, charged and uncharged capacitors represent two logic states, respectively. The memory cells of the memory cell array 105 can use any number of storage media, including DRAM, FeRAM, PCM, or other types of memory cells. DRAM memory cells can include capacitors with dielectric materials as insulating materials. For example, the dielectric materials can have linear or antiferroelectric polarization characteristics, and ferroelectric memory cells can include capacitors with ferroelectric materials as insulating materials. Where the storage media includes FeRAM, different charge levels of the ferroelectric capacitors can represent different logic states.

[0033] The memory cell array 105 can be or include a three-dimensional (3D) array, in which multiple two-dimensional (2D) arrays or multiple memory cells are formed on top of each other. Such a configuration can increase the number of memory cells that can be formed on a single die or substrate compared to 2D arrays. In turn, production costs can be reduced or performance of the memory array can be improved, or both. Each planar layer of the array can be aligned or positioned such that the memory cells can be approximately aligned with each other on each planar layer, forming a stack of memory cells.

[0034] In some examples, the array of memory cells 105 can include memory cells, word lines, digit lines, and sense components. In some examples, the array of memory cells 105 can include plate lines (e.g., in the case of FeRAM). The memory cells of the array of memory cells 105 can include a select component and a logic storage component, e.g., a capacitor including a first plate, a cell plate, a second plate, and a cell bottom. The cell plate and the cell bottom can be capacitively coupled by an insulating material (e.g., a dielectric, ferroelectric, or PCM material) located therebetween.

[0035] Various combinations of word lines, digit lines, and / or plate lines can be used to access memory cells of the array of memory cells 105 (e.g., during a read operation, a write operation, or other operations). In some cases, some memory cells can share access lines (e.g., digit lines, word lines, plate lines) with other memory cells. For example, a digit line can be shared with memory cells in the same column, a word line can be shared with memory cells in the same row, and a plate line can be shared with memory cells in the same section, tile, deck, or multiple decks. As described above, various states can be stored by charging or discharging the capacitor of a memory cell.

[0036] The stored state of a capacitor of a memory cell can be read or sensed by operating various elements. The capacitor can be in electronic communication with a digit line. When a select component is deactivated, the capacitor can be isolated from the digit line, while when the select component is activated (e.g., by a word line), the capacitor can be connected to the digit line. Activating a select component can be referred to as selecting a memory cell. In some cases, the select component can be a transistor, and its operation can be controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than a threshold magnitude of the transistor. A word line can activate the select component; for example, a voltage applied to the transistor gate of the word line can connect the capacitor of a memory cell with a digit line.

[0037] In some examples, a voltage change of a digit line can depend on its intrinsic capacitance. That is, when charge flows through a digit line, some finite charge can be stored in the digit line, and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance can depend on physical characteristics of the digit line, including size. A digit line can connect many memory cells in the array of memory cells 105, so the length of the digit line can produce a non-negligible capacitance (e.g., in picofarads (pF)). The resulting voltage of the digit line can then be compared to a reference voltage (e.g., a voltage of a reference line) by a sense component to determine a stored logic state in a memory cell. Other sensing processes can be used.

[0038] The sense component can include various transistors or amplifiers to detect and amplify the difference in the signal, which can be referred to as latching. The sense component can include a sense amplifier that receives and compares the voltage of the digit line to a reference line, which can be a reference voltage. Based on the comparison, the sense amplifier output can be driven to a higher (e.g., positive) or lower (e.g., negative or ground) supply voltage. For example, if the voltage of the digit line is higher than the voltage of the reference line, the sense amplifier output can be driven to a positive supply voltage.

[0039] In some cases, the sense amplifier can drive the digit line to the supply voltage. The sense component can then latch the output of the sense amplifier and / or the voltage of the digit line, which can be used to determine the storage state (e.g., logic ‘1’) in the memory cell. Alternatively, for example, if the voltage of the digit line is lower than the voltage of the reference line, the sense amplifier output can be driven to a negative or ground voltage. The sense component can similarly latch the sense amplifier output to determine the storage state (e.g., logic ‘0’) in the memory cell. The latched logic state of the memory cell can then be output, for example, by a column decoder.

[0040] To write to the memory cell, a voltage can be applied across the capacitor of the memory cell. Various methods can be used to write to the memory cell. In one example, the select component can be activated by the word line to electrically connect the capacitor to the digit line. The voltage can be applied across the capacitor by controlling the voltage of the cell plate (e.g., by the plate line) and the cell bottom (e.g., by the digit line). To write a logic ‘0’, the cell plate can be pulled high (e.g., the voltage level can be increased to above a predetermined voltage, which is a “high” voltage). That is, a positive voltage can be applied to the plate line and the cell bottom can be pulled low (e.g., virtually grounded or a negative voltage is applied to the digit line). The opposite process can be performed to write a logic ‘1’, where the cell plate is pulled low and the cell bottom is pulled high.

[0041] The controller 110 can control the operation (e.g., read, write, rewrite, refresh, precharge, etc.) of memory cells in the memory cell array 105 through various components (e.g., row decoders, column decoders, and sense components). In some cases, one or more of the row decoders, column decoders, and sense components can be co-located with the controller 110. The controller 110 can generate row and column address signals to activate desired word lines and digit lines. In other examples, the controller 110 can generate and control various voltages or currents used during operation of the memory device 100. For example, the controller 110 can apply a discharge voltage to a word line or digit line after accessing one or more memory cells. Generally, the amplitude, shape, or duration of applied voltages or currents discussed herein can be adjusted or varied and can be different for various operations discussed in operating the memory device 100. Moreover, one, more, or all memory cells in the memory cell array 105 can be accessed simultaneously. For example, during a reset operation in which a plurality of memory cells or all memory cells can be set to a single logic state (e.g., logic ‘0’), a plurality of memory cells or all memory cells in the memory cell array 105 can be accessed simultaneously.

[0042] In some examples, at least some (and in some cases, each) signaling interface 120 can generate and / or decode signals communicated using the plurality of channels 115. The signaling interface 120 can be associated with each interface coupled with the plurality of channels 115. The signaling interface 120 can be configured to generate and / or decode multi-level signals, binary level signals, or both (e.g., simultaneously). Each signaling interface 120 can include a transmitter 125 and a receiver 130. In some examples, each transmitter 125 can be referred to as a multi-branch driver.

[0043] Each transmitter 125 can be configured to generate a multi-level signal based on a logic state including a plurality of bits. For example, the transmitter 125 can use PAM4 signaling techniques (or other types of multi-level signaling techniques) to generate a signal having an amplitude corresponding to the logic state. The transmitter 125 can be configured to receive data using a single input line. In some cases, the transmitter 125 can include a first input line for a first data bit (e.g., a most significant bit) and a second input line for a second data bit (e.g., a least significant bit). In some environments, the transmitter 125 can be configured to generate a binary level signal (e.g., an NRZ signal). In some cases, the transmitter 125 can use single-ended signaling to generate the multi-level signal. In such cases, the multi-level signal can be transmitted without differential.

[0044] Each receiver 130 can be configured to determine a logical state represented by a symbol of a multi-level signal received using the plurality of channels 115. In some cases, a receiver 130 can determine an amplitude of a received multi-level signal. Based on the determined amplitude, the receiver 130 can determine a logical state represented by a symbol of the multi-level signal. The receiver 130 can be configured to output data using a single output line. In some cases, a receiver 130 can include a first output line for a first data bit (e.g., a most significant bit) and a second output line for a second data bit (e.g., a least significant bit). In some environments, a receiver 130 can be configured to decode a binary level signal (e.g., an NRZ signal). For example, each of the receivers 130 can be coupled with a transmitter (not shown) through the plurality of channels 115. Each of the channels 115 can be configured to output data including a plurality of bits, and the controller 110 can be configured to determine an output impedance offset between the data outputs. One or more transistors (not shown individually) can be configured to adjust a resistance level of one or more of the plurality of channels 115. This adjustment can be based at least in part on the determined output impedance offset.

[0045] In some cases, each of the signaling interfaces 120 can be configured to selectively generate and / or decode different types of signals (e.g., NRZ signals, PAM4 signals, PAM8 signals, etc.). Different types of signals can be used based on an operating environment of the memory device 100. For example, binary level signaling can use less power than multi-level signaling, and can be used when power consumption is a primary consideration for performance. Other performance factors that can be used to determine which type of signaling should be used can include clock considerations, data strobe (DQS) considerations, circuit capabilities, bandwidth considerations, jitter considerations, or combinations thereof. In some cases, the controller 110 can be configured to select a type of signal, and the signaling interfaces 120 can be configured to implement the selection based on instructions received from the controller 110. In some cases, each of the signaling interfaces 120 can be configured to implement encoding functions, such as error detection procedures, error correction procedures, data bus inversion procedures, or combinations thereof.

[0046] In some cases, a signaling interface 120 can be configured to communicate both multi-level signals and binary level signals simultaneously. In such cases, a signaling interface 120 can include more than one set of transmitters 125 and receivers 130. For example, a signaling interface 120 can be configured to communicate a first set of data using a binary level signal (using a first set of channels 115) at the same time as a second set of data (e.g., user information) using a multi-level signal (using a second set of channels 115).

[0047] Figure 2An example of an eye diagram 200 representing a multi-level signal is shown in accordance with various embodiments of the present disclosure. The eye diagram 200 can be used to indicate signal quality in high-speed transmission and can represent four symbols (e.g., ‘00’, ‘01’, ‘10’, or ‘11’) of a signal. In some examples, each of the four symbols can be represented by a different voltage amplitude (e.g., amplitudes 205-a, 205-b, 205-c, 205-d). In other examples, the eye diagram 200 can represent a PAM4 signal, which can be used to communicate data in a memory device (e.g., refer to Figure 1 The memory device 100 described). The eye diagram 200 can be used to provide a visual indication of the health of signal integrity and can indicate a noise margin of a data signal. The noise margin can refer, for example, to an amount by which a signal exceeds an ideal boundary of the amplitudes 205.

[0048] To generate the eye diagram 200, an oscilloscope or other computing device can sample a digital signal according to a sampling period 210 (e.g., a unit interval or bit period). The sampling period 210 can be defined by a clock associated with transmission of the signal being measured. In some examples, the oscilloscope or other computing device can measure a voltage level of the signal during the sampling period 210 to form a trace 215. Noise and other factors can cause the traces 215 measured from the signal to deviate from a set of ideal step functions. By overlaying multiple traces 215, various characteristics about the signal being measured can be determined. For example, the eye diagram 200 can be used to identify several characteristics of a communication signal, such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. A closed eye can indicate a noisy and / or unpredictable signal or other problems.

[0049] In some examples, the eye diagram 200 can indicate a width 220. The width 220 of an eye in the eye diagram 200 can be used to indicate timing synchronization of the signal being measured or effects of jitter on the signal being measured. In some examples, comparing the width 220 to the sampling period 210 can provide a measure of the SNR of the signal being measured. Each eye in the eye diagram can have a unique width based on characteristics of the signal being measured. Various encoding and decoding techniques can be used to modify the width 220 of the signal being measured.

[0050] In other examples, the eye diagram 200 can indicate a sampling time 225 (e.g., an ideal sampling time) for determining a value of a logic state represented by a symbol of the signal under test. For example, determining a correct time to sample data (e.g., timing synchronization) of the signal under test can be important to minimize an error rate in signal detection. For example, if a computing device samples a signal during a transition time (e.g., a rise time 230 or a fall time 235), a decoder can introduce errors into data represented by a symbol of the signal. Various encoding and decoding techniques can be used to modify the ideal sampling time 225 of the signal under test.

[0051] The eye diagram 200 can be used to identify a rise time 230 and / or a fall time 235 of a transition from a first amplitude 205 to a second amplitude 205. In other aspects, a slope of the trace 215 during the rise time 230 or the fall time 235 can indicate a sensitivity of the signal to timing errors. For example, the higher the slope of the trace 215 (e.g., the smaller the rise time 230 and / or the fall time 235), the more ideal the transition between amplitudes 205. Various encoding and decoding techniques can be used to modify the rise time 230 and / or the fall time 235 of the signal under test.

[0052] In some examples, the eye diagram 200 can be used to identify an amount of jitter 240 in the signal under test. The jitter 240 can refer to a timing error due to misalignment of rise and fall times. The jitter 240 occurs when a rising edge or a falling edge occurs at a time other than an ideal time defined by a data clock. The jitter 240 can be caused by signal reflections, intersymbol interference, crosstalk, process-voltage-temperature (PVT) variations, random jitter, additive noise, or a combination thereof. Various encoding and decoding techniques can be used to modify the jitter 240 of the signal under test. In some cases, the jitter 240 can be different for each signal level or for each eye.

[0053] In other examples, the eye diagram 200 can indicate an eye opening 245, which can represent a peak-to-peak voltage difference between respective amplitudes 205. The eye opening 245 can be related to a voltage margin used to distinguish between different amplitudes 205 of the signal under test. The smaller the margin, the more difficult it is to distinguish between adjacent amplitudes and the more errors that can be introduced due to noise. In some cases, a receiver of the signal (e.g., a reference Figure 1The described receiver 130 can compare the signal with one or more threshold voltages located between various amplitudes 205. In other cases, the larger the eye opening 245, the less likely noise is to cause one or more voltage thresholds to be incorrectly met. The eye opening 245 can be used to indicate the amount of additive noise in the measured signal and can be used to determine the SNR of the measured signal. Various encoding and decoding techniques can be used to modify the eye opening 245 of the measured signal. In some cases, the eye opening 245 of each eye can be different. In such cases, the eyes of multi-level signals may differ.

[0054] In other instances, eye diagram 200 may indicate distortion 250. Distortion 250 may represent overshoot and / or undershoot of the measured signal due to noise or interruptions in the signal path. When a signal stabilizes from an old amplitude (e.g., amplitude 205-c) to a new amplitude (e.g., amplitude 205-b), the signal may overshoot and / or undershoot the new amplitude level. In some instances, distortion 250 may be caused by such overshoot and / or undershoot, or by additive noise in the signal or interruptions in the signal path. Each eye in the eye diagram can have a unique opening based on the characteristics of the measured signal. Various encoding and decoding techniques can be used to modify the distortion 250 of the measured signal. In some cases, the distortion 250 may differ for each signal level or for each eye.

[0055] Figure 2 The locations of the characteristics shown in eye diagram 200 are for illustrative purposes only. Characteristics such as width 220, sampling time 225, rise time 230, fall time 235, jitter 240, eye opening 245, and / or distortion 250 may appear in eye diagram 200 where they are not explicitly shown. Figure 2 In other parts that are explicitly indicated in the document.

[0056] According to the techniques described herein, programmable channel equalization (e.g., de-emphasis, pre-emphasis, FFE, etc.) can be applied to multi-level signals to compensate for the aforementioned negative effects and increase output linearity.

[0057] Figure 3 A multilevel signal transmitter 300 supporting multilevel signaling and programmable channel equalization is illustrated according to an example of this disclosure. The transmitter 300 may be a reference... Figure 1A portion of the signaling interface 120 is described (e.g., the transmitter 300 can be a portion of the transmitter 125). The transmitter 300 can also be referred to herein as a device. The transmitter 300 can contain two partitions: a first partition 305 that contains components and data paths for one bit (e.g., the least significant bit (LSB)) in a multi-level signal (e.g., a PAM4 symbol), and a second partition 310 that contains components and data paths for a second bit (e.g., the most significant bit (MSB)) in the multi-level signal (e.g., a PAM4 symbol). Each partition can be connected to a different data line (e.g., the first partition 305 can be in electronic communication with data line DO, while the second partition 310 can be in electronic communication with data line Dl). A data line can be an electrically conductive path that is capable of transferring an electrical charge from one component to another component.

[0058] The first and second partitions can output signals that can be combined (e.g., added or superimposed) to produce a PAM4 symbol. The first partition 305 can correspond to the LSB in a PAM4 symbol, and can be configured to drive a DQ level at one amplitude when the LSB is 1, and at another amplitude when the LSB is 0. For example, when the LSB is 1, the first partition can be configured to provide or output a signal that ultimately raises the resulting symbol by a predetermined amount (e.g., by the amount necessary to distinguish amplitude 205-b from amplitude 205-a in FIG. 5). Figure 2 Similarly, the second partition 310 can correspond to the MSB in a PAM4 symbol, and can be configured to drive a DQ level at one amplitude when the MSB is 1, and at another amplitude when the MSB is 0. For example, when the MSB is 1, the second partition 310 can be configured to provide or output a signal that ultimately raises the resulting symbol by a predetermined amount (e.g., by the amount necessary to distinguish amplitude 205-d from amplitude 205-b in FIG. 5). Figure 2

[0059] Thus, the DQ levels output by the partitions can be different when the respective bits are 1. For example, the first partition 305 can drive the DQ level to an amplitude corresponding to the LSB, while the second partition can drive the DQ level to an amplitude corresponding to the MSB. So, a PAM4 symbol can be generated by adding the LSB to the MSB. In this context, the second partition 310 can be configured to drive the DQ level to twice the amplitude output by the first partition 305, which can be accomplished by using twice the components (e.g., twice the pre-driver and driver circuits) in the second partition 310 as compared to the first partition 305. Although this configuration is shown in FIG. 5, the techniques described herein are compatible with alternative configurations. Figure 3

[0060] ​​The transmitter may also include or be in electronic communication with data array path 340. Data from a data array (e.g., data array 365) can be passed through data array path 340 to one or more components of transmitter 300, which may include one or more sense amplifiers, data lines, data latches, multiplexing circuitry, or serialization circuitry. Thus, data (e.g., one or more data signals or bits) can be transmitted from data array 365 to first partition 305 and second partition 310 via data array path 340.

[0061] Each partition may contain a main data path and a channel equalization path (e.g., a de-emphasis path or a pre-emphasis path). When de-emphasis is used, the channel equalization path may contain at least one de-emphasis buffer circuit 315, a pre-driver circuit 320, and a de-emphasis driver circuit 325-a. When pre-emphasis is used, the channel equalization path may contain at least one pre-emphasis buffer circuit, a pre-driver circuit, and a pre-emphasis driver circuit. The main data path may contain at least one data buffer circuit 330, a pre-driver circuit 320, and a driver circuit 335. According to the techniques described herein, a first data signal (e.g., a bit or bit stream) may be transmitted from data array 365 (e.g., via data array path 340) to de-emphasis buffer circuit 315-a and data buffer circuit 330-a. The first data signal may be transmitted via a first data line D0. The second data signal (e.g., the second bit or bit stream) can be transmitted from the data array path 340 to the deemphasis buffer circuit 315-b (or, in the preemphasis embodiment, to the preemphasis buffer circuit 315-b) and the data buffer circuit 330-b. In some cases, the data buffer circuit 330-b may consist of a pair of data buffers.

[0062] The data buffer circuit 330 can temporarily store the received data signals before transmitting them to the pre-driver circuit 320. Thus, the signal output by the data buffer circuit 330 can be a delayed version of the data signal received from the data array path 340. The duration of the time that the data signal is delayed can be referred to herein as a data buffer delay. The data buffer delay can be less than the delay introduced by the de-emphasis (or pre-emphasis) buffer circuit 315. The data buffer circuit 330 can contain several transistors configured such that the voltage and current of the signal output by the data buffer circuit matches the voltage and current of the input signal. Here, the data buffer circuit 330-a can transmit the first data signal to the pre-driver circuit 320-b, while the data buffer circuit 330-b can transmit the second data signal to the pre-driver circuit 320-c and the pre-driver circuit 320-d. Although a single data buffer circuit 330-a and data buffer circuit 330-b are shown, the transmitter 300 can contain multiple data buffer circuits 330-a and multiple data buffer circuits 330-b.

[0063] The de-emphasis buffer circuit 315 can generate a de-emphasis control signal based on the received data signal and transmit the control signal to the pre-driver 320. Similarly, when using a pre-emphasis implementation, the pre-emphasis buffer circuit 315 can generate a pre-emphasis control signal based on the received data signal and transmit the control signal to the pre-driver 320. The de-emphasis (or pre-emphasis) control signal can then be propagated through the pre-driver 320 (possibly with some modifications) to the final driver (e.g., the de-emphasis or pre-emphasis driver circuit 325). Based on the control signal, the de-emphasis driver circuit 325 (or the pre-emphasis driver circuit 325) can generate, drive, output, or modify a signal that de-emphasizes (or pre-emphasizes) the final output signal. So, when the buffer circuit 315 generates the control signal, the buffer circuit 315 is modifying (e.g., delaying and inverting) the data signal to control the de-emphasis or pre-emphasis of the signal output by the transmitter 300. Thus, the buffer circuit 315 can generate an appropriate control signal for de-emphasis or pre-emphasis based on the input data signal.

[0064] In general, “de-emphasis” is associated with reducing the amplitude of a signal after a signal transition. In this context, de-emphasis can be achieved by reducing the low frequency components of a signal, which reduces the overall amplitude of the signal. For example, the low frequency components of a signal after a signal transition can be reduced by adding an inverted and delayed version of the signal to the original signal. As used herein, “de-emphasis” can also refer to manipulating a signal such that when it is added to an original signal, the resulting signal is de-emphasized in the first sense.

[0065] According to the techniques described herein, de-emphasis buffer circuit 315-a can modify (e.g., delay and invert) a first data signal received from data array path 340 (e.g., over first data line D0), while de-emphasis buffer circuit 315-b can modify (e.g., delay and invert) a second data signal received from data array path 340 (e.g., over second data line Dl). The modified data signals can be used as control signals as described above. For example, a first control signal can control aspects of de-emphasis applied by de-emphasis driver circuit 325-a, while a second control signal can control aspects of de-emphasis applied by de-emphasis driver circuit 325-b. The delay τ can be used to determine how long de-emphasis lasts (e.g., for a full UI, for a portion of a UI), and the ratio between each de-emphasis driver circuit 325 and its corresponding driver circuit 335 can determine the amplitude of equalization. So, the de-emphasis applied by the de-emphasis driver circuits can be the same or different, and can be scaled based on the control of the first and second data signals. The amount of delay used in de-emphasis and the scaling factor can be referred to herein as de-emphasis adjustments. Similar processes can be used in pre-emphasis implementations. For example, in some cases, de-emphasis buffer circuit 315 is a pre-emphasis buffer circuit that pre-emphasizes a received data signal or an FFE component that shapes a received signal based on a channel response.

[0066] As mentioned, de-emphasizing a signal can include suppressing low frequency components of the signal to compensate for a drop in high frequency components of the signal due to channel loss. Pre-emphasizing a signal can include enhancing high frequency components of the signal to compensate for channel attenuation caused. De-emphasis buffer circuit 315 can include delay component 345, inverter 350, and multiplexer 355. Delay component 345 can receive a data signal from data array path 340 and delay it by delay τ. Delay τ can be selected such that the propagation delay through de-emphasis buffer circuit 315-a represents how long de-emphasis will last. Inverter 350 can receive the delayed data signal, invert it, and pass the inverted signal to multiplexer 355.

[0067] The multiplexer 355 can activate and deactivate (e.g., turn on and off) the de-emphasis buffer circuit 315-a under the control of the selection signal EnDe. Each de-emphasis or pre-emphasis buffer circuit can have a selection signal EnDe (e.g., a first selection signal D0 EnDe for the de-emphasis buffer circuit 315-a and a second selection signal D1 EnDe for the de-emphasis buffer circuit 315-b). The selection signals D0 EnDe and D1 EnDe, also referred to as enable signals D0 EnDe and D1 EnDe, can convey different control information so that the de-emphasis buffer circuits 315 (or pre-emphasis buffer circuits 315) can be activated independently.

[0068] When the de-emphasis buffer circuit 315-a is enabled or activated, the data signal can pass through the delay component 345 and the inverter 350. When the de-emphasis buffer circuit 315-a is deactivated, the data signal can bypass the delay component 345 and the inverter 350 (e.g., through the bypass path 360). As discussed above, the delayed and inverted data signal can control de-emphasis, which can increase the detectability of the multi-level signal at the receiver. The de-emphasis buffer circuit 315-b can be implemented in a similar manner as the de-emphasis buffer circuit 315-a. Although a single de-emphasis buffer circuit 315-a and a single de-emphasis buffer circuit 315-b are shown, the transmitter 300 can include multiple de-emphasis buffer circuits 315-a and multiple de-emphasis buffer circuits 315-b.

[0069] As discussed above, the de-emphasis buffer circuit 315-a can transmit a first control signal to the pre-driver 320-a, while the de-emphasis buffer circuit 315-b can transmit a second control signal to the pre-driver 320-c and the pre-driver 320-d. The pre-drivers 320 can condition or modify the received control signals before passing them to their respective driver circuits (e.g., the pre-driver circuits 320 can modify the signals output by the de-emphasis driver circuits 325 to improve the characteristics or quality of the communication signal). The pre-drivers 320 can additionally or alternatively act as selectors. For example, each pre-driver circuit 320 can select and control a corresponding driver circuit. The pre-driver circuits 320 in turn can be controlled by a selection signal (e.g., EnPUP / EnDN), which can activate the pre-driver circuits 320 and control which driver circuits can be selected.

[0070] Although a single pre-driver circuit 320 is shown for each data path, each data path can have multiple pre-driver circuits 320. For example, each data path can include two pre-driver circuits, one being a pull-up pre-driver circuit and one being a pull-down pre-driver circuit. Thus, the pre-driver circuits 320 can be pull-up or pull-down pre-driver circuits.

[0071] Each pre-driver 320 can transmit or output a modified version of its input signal to a driver circuit. For example, pre-driver 320-a can transmit a modified version of the delayed and inverted first data signal (e.g., a first de-emphasis control signal) to de-emphasis driver circuit 325-a, and pre-driver 320-b can transmit a modified version of the first data signal (e.g., a first driver control signal) to driver circuit 335-a. Similarly, pre-driver 320-e can transmit a modified version of the delayed and inverted second signal (e.g., a second de-emphasis control signal) to de-emphasis driver circuit 325-b, and pre-driver 320-f can transmit a modified version of the delayed and inverted second signal (e.g., a third de-emphasis control signal) to de-emphasis driver circuit 325-c. Pre-driver 320-c can transmit a modified version of the second data signal (e.g., a second driver control signal) to driver circuit 335-b, and pre-driver 320-d can transmit a modified version of the second data signal (e.g., a third driver control signal) to driver circuit 335-c. The modified versions of the signals sent through the paths corresponding to data buffer circuit 330 can not be inverted or delayed. Although described with reference to de-emphasis, the signal transmission in transmitter 300 can be similar for pre-emphasis implementations.

[0072] De-emphasis driver circuits 325 and driver circuits 335 can increase or decrease the drive strength (e.g., voltage or current) of the signals they receive from pre-driver circuits 320. For example, de-emphasis driver circuit 325-a (or pre-emphasis driver circuit 325-a) can increase or decrease the drive strength of the modified version of the first data signal received from pre-driver circuit 320-a. When using de-emphasis driver circuits, the drive strength of the output signal can decrease. When using pre-emphasis driver circuits, the drive strength of the output signal can increase. The outputs of driver circuits 325 and driver circuits 335 can be combined (e.g., superimposed) to produce a de-emphasized or pre-emphasized symbol represented by DQ. As discussed above, the amount by which the driver circuits modify or adjust the signal strength can be controlled by or based on control signals (e.g., control signals from controller 370 and / or control signals from pre-drivers 320). According to the techniques described herein, different (e.g., separate or independent) control signals can be used to control de-emphasis driver circuits 325 and driver circuits 335.

[0073] In one example, the de-emphasis (or pre-emphasis) driver circuit 325-a can be controlled in part or in whole by a control signal (e.g., DeEnF0) received from the controller 370, and the driver circuit 335-a can be controlled in part or in whole by a control signal (e.g., DrEnF0) received from the controller 370. Similarly, the de-emphasis (or pre-emphasis) driver circuits 325-b and 325-c can be controlled in part or in whole by a control signal (e.g., an enable signal DeEnFl) received from the controller 370, and the driver circuits 335-b and 335-c can be controlled in part or in whole by a control signal (e.g., an enable signal DrEnFl) received from the controller 370. Other individual control signals for the driver circuits 335 and the de-emphasis (or pre-emphasis) driver circuits 325 can enable the de-emphasis (or pre-emphasis) adjustments to be tuned to provide improved signal linearity and output swing. In some cases, the control signals generated by the controller 370 can be enable signals that activate the de-emphasis (or pre-emphasis) drivers 325 and the driver circuits 335.

[0074] In another example, the de-emphasis (or pre-emphasis) drivers 325 and the driver circuits 335 can be controlled in part or in whole by control signals from the pre-driver 320. For example, the de-emphasis (or pre-emphasis) driver 325-a can be controlled in part or in whole by a first control signal from the pre-driver 320-a, and the driver circuit 335-a can be controlled in part or in whole by a second control signal from the pre-driver 320-b. In some cases, the de-emphasis (or pre-emphasis) drivers 325 and the driver circuits 335 can be controlled by control signals from the controller 370 and control signals from the pre-driver 320. For example, the control signals from the controller 370 can control certain aspects of the de-emphasis (or pre-emphasis) drivers 325 and the driver circuits 335, and the control signals from the pre-driver 320 can control different aspects of the de-emphasis (pre-emphasis) drivers 325 and the driver circuits 335.

[0075] In some cases, the controller 370 can control aspects of the de-emphasis (or pre-emphasis) buffer circuit 315. For example, the controller 370 can enable or disable the de-emphasis (or pre-emphasis) buffer circuit 315 using the enable signals D0EnDe and DlEnDe. Additionally or alternatively, the controller 370 can control aspects of the de-emphasis (or pre-emphasis) buffer 315, such as the duration of the delay τ. So in some cases, the controller 370 can use a control signal to control the output of the de-emphasis (or pre-emphasis) buffer circuit 315.

[0076] The outputs of the de-emphasis (or pre-emphasis) driver circuits 325 and the driver circuits 335 can be combined (e.g., superimposed) to produce a de-emphasized (or pre-emphasized) symbol (e.g., a PAM4 symbol) represented by DQ. For example, the de-emphasis (or pre-emphasis) driver circuit 325-a can be configured to drive a signal that is delayed and inverted compared to the signal output by the driver circuit 335-a. When the signal output by the de-emphasis driver circuit 325-a is combined with the signal output by the driver circuit 335-a, the resulting signal represents an LSB, but contains low frequency components that have been reduced compared to other frequency components (e.g., to compensate for expected loss of high frequency components through the channel). Similarly, the de-emphasis driver circuits 325-b and 325-c can be configured to drive signals that are delayed and inverted compared to the signals output by the driver circuits 335-b and 335-c. When the signals output by the de-emphasis driver circuits 325-b and 325-c are combined with the signals output by the driver circuits 335-b and 335-c, the resulting signals represent MSBs, but contain low frequency components that have been reduced compared to other frequency components (e.g., to compensate for expected loss of high frequency components through the channel).

[0077] When the signal output by the pre-emphasis driver circuit 325-a is combined with the signal output by the driver circuit 335-a, the resulting signal represents an LSB, but contains high frequency components that have been amplified or increased compared to other frequency signals (e.g., to compensate for expected loss of high frequency components through the channel). Similarly, the pre-emphasis driver circuits 325-b and 325-c can be configured to drive signals that are delayed and inverted compared to the signals output by the driver circuits 335-b and 335-c. When the signals output by the pre-emphasis driver circuits 325-b and 325-c are combined with the signals output by the driver circuits 335-b and 335-c, the resulting signals represent MSBs, but contain high frequency components that have been amplified or increased compared to other frequency components (e.g., to compensate for expected loss of high frequency components through the channel).

[0078] The combination of all of the signals output by the de-emphasis driver circuits 325 and the driver circuits 335 can represent a de-emphasized PAM4 symbol. Similarly, the combination of all of the signals output by the pre-emphasis driver circuits 325 and the driver circuits 335 can represent a pre-emphasized PAM4 symbol. The symbol can represent or convey a first data signal (e.g., a logic state associated with the first data signal, such as an LSB) and a second data signal (e.g., a logic state associated with the second data signal, such as an MSB), as described in, for example Figure 1 and 2 Thus, the transmitter 300 can generate a multi-level signal containing multiple superimposed signals (e.g., a first data signal and a second data signal represented by a single symbol).

[0079] Although a single driver circuit 335 and de-emphasis driver circuit 325 are shown for each data path, there can be multiple driver circuits 335 and multiple de-emphasis (or pre-emphasis) driver circuits 325 for each data path. For example, there can be multiple pre-driver circuits 320 and one driver circuit 335 or de-emphasis driver circuit 325 for each pre-driver circuit 320. The driver circuits 335 and de-emphasis driver circuits 325 can be pull-up driver circuits or pull-down driver circuits. For example, pull-up driver circuits can be used in conjunction with pull-up pre-driver circuits, and pull-down driver circuits can be used in conjunction with pull-down pre-driver circuits. In some cases, the de-emphasis driver circuit 325 is a pre-emphasis driver circuit or an FFE driver circuit that is configured to receive a signal that is pre-emphasized (or shaped by an FFE circuit) by a pre-emphasis buffer circuit (and modify its strength).

[0080] Although described in the context of de-emphasis, channel equalization as described herein can also be implemented through pre-emphasis. Generally, "pre-emphasis" refers to increasing the amplitude of a signal after a signal transition. In this context, pre-emphasis can be implemented by amplifying the high frequency components of a signal (e.g., increasing the energy content of the high frequency components to compensate for the drop in those components due to channel loss), which increases the overall amplitude of the signal. For example, the high frequency components of a signal can be amplified after a signal transition by adding an inverted and delayed version of the signal to the original signal. As used herein, "pre-emphasis" can also refer to manipulating one signal such that when it is added to an original signal, the resulting signal is pre-emphasized in the first sense.

[0081] To implement pre-emphasis in the transmitter 300, the de-emphasis buffer circuit 315 can be replaced with a pre-emphasis buffer circuit 315, and the de-emphasis driver 325 can be replaced with a pre-emphasis driver 325. Similar to the de-emphasis buffer circuit, the pre-emphasis buffer circuit can generate a control signal that controls the behavior of its associated pre-emphasis driver circuit. The control signal can be a pulse that is less than the width of the input data signal and is an inverted and delayed version of the input data signal.

[0082] To generate such control signals, the pre-emphasis buffer circuits can be configured differently than the de-emphasis buffer circuits shown in transmitter 300. For example, the pre-emphasis buffer circuits can not include multiplexer 355 or bypass path 360. Also, each pre-emphasis buffer circuit can include a pulse generator circuit (e.g., an AND gate at the output of the pre-emphasis buffer circuit). The inputs of the pulse generator can be an enable signal (e.g., EnDe) and a delayed and inverted version of the data signal received by the pre-emphasis buffer circuit. When disabled, the pre-emphasis buffer circuits, pre-driver circuits, and pre-emphasis driver circuits can be turned off. This is in contrast to the de-emphasis implementation, in which disabling the de-emphasis buffer circuits, pre-driver circuits, and de-emphasis driver circuits does not turn them off.

[0083] The pre-emphasis driver circuits used in the pre-emphasis implementation can be the same as the de-emphasis driver circuits used in the de-emphasis implementation. Alternatively, the pre-emphasis driver circuits can be different than the de-emphasis driver circuits (e.g., to prevent the control pulse from being attenuated as it propagates through the pre-driver circuits). In one pull-down driver example, the pre-emphasis driver circuit can include two NMOS devices in series. One NMOS device can be controlled by an enable signal, while the other can be controlled by a delayed and inverted version of the data signal output by the pre-emphasis buffer circuit. When using such a configuration, the pre-emphasis buffer circuit can not include an AND gate.

[0084] Figure 4 A plot 400 of a multi-level signal 405 generated by a multi-level signal transmitter is shown. The transmitter can be an example of the transmitter 300 described with reference to Figure 3 The plot 400-a represents a signal 405-a generated without de-emphasis, while the plot 400-b represents a multi-level signal 405-b generated with de-emphasis. Both plots 400 show the multi-level signal 405 transitioning from a low output voltage level (V OL ) to a high output voltage level (V OH ) and back to the low output voltage level V OL . The low output voltage level V OL may be low compared to a reference voltage signal V REF , while the high voltage level V OH may be high compared to the reference voltage signal V REF . The high voltage level V OH may be associated with a first symbol value (e.g., 0b11), while the low voltage level V OL may be associated with a second symbol value (e.g., 0b10). Although only one set of V OH / VREF / V OL but three different sets of V OH / V REF / V OL (i.e., two signaling levels are shown instead of four.

[0085] As Figure 4 shown, signal 405 can transition from below V REF to V OH . At the time of the transition (e.g., upon detecting crossing V REF ), de-emphasis can be enabled on signal 405-b (but not on signal 405-a). For example, de-emphasis buffer circuit 315 can be enabled as described with reference to Figure 3 However, de-emphasis can not be applied until τ expires, τ being the delay associated with corresponding delay component 345. So, due to delay τ, the disabling of de-emphasis buffer circuit 315 can coincide with the application of de-emphasis. Here, τ is a fraction of a unit interval (UI) (which can also be referred to as bit time). However, in some cases, τ is a full UI. Although the UI is shown as extending from the start of one transition to the start of the subsequent transition, the UI can be defined by different time periods. When de-emphasis is applied, the amplitude of signal 405-b can decrease from V OH to the de-emphasized amplitude V DEH . This is different from signal 405-a, which remains at V OH until the next transition.

[0086] When signal 405-b crosses V REF during the next transition, de-emphasis on signal 405-b can again be enabled. But again, because de-emphasis buffer circuit 315 introduces delay τ, de-emphasis is not applied until τ time has passed. At this time, de-emphasis buffer circuit can also be disabled. When de-emphasis is applied, the amplitude of signal 405-b can increase from V OL to the de-emphasized amplitude V DEL (i.e., the absolute magnitude of the amplitude of signal 405 can decrease, just as it did when de-emphasis was applied to signal 405 at V OH ). This is different from signal 405-a, which remains at V OL until the next transition. Thus, when de-emphasis is used, the amplitude of signal 405-b can start at V OH or V OL and then only at a lower amplitude (than V OH or V OLCompared to before, it stabilizes. However, when using pre-emphasis, the amplitude of signal 405-b may stabilize at V. OH or V OL Previously temporarily reached V OH or V OL (For example, during the transition). Amplitude exceeds V OH or V OL The amount of time can be equal to the time delay τ. Furthermore, under the control of the pre-emphasis buffer circuit, the amplitude exceeds V. OH or V OL The amount can be determined by the pre-emphasis driver.

[0087] De-emphasis or pre-emphasis on a signal can improve signal integrity, which increases the likelihood that the receiver can successfully receive and decode the signal. This improvement can be easily seen in eye diagram comparisons.

[0088] Figure 5 A portion of a multilevel signal transmitter 500 supporting multilevel signaling and programmable channel equalization, according to an example of this disclosure, is shown. The transmitter 500 may be a reference... Figure 3 An example of a transmitter 300 is described. Transmitter 500 may include one or more channel equalization driver circuits 545 and one or more driver circuits 335-d, which may be referenced. Figure 3 Examples of de-emphasis driver circuit 325 and driver circuit 335 are described. In some cases, channel equalization driver circuit 545 is a pre-emphasis driver circuit or an FFE driver circuit. As described herein, channel equalization circuit 545 and driver circuit 335-d can be independently controlled by controller 530. However, the programmable channel equalization techniques described herein are not limited to... Figure 5 The depicted channel equalization circuit 545 and driver circuit 335-d are in a specific configuration. The controller 530 may be a reference. Figure 3 An example of the controller 370 described. Alternatively, the controller 530 may include multiple pre-driver circuits 320 (e.g., the control signal output by the controller 530 may be a modified version of the data signal output by the pre-driver 320).

[0089] Although shown as pull-up driver circuits, channel equalization driver circuits 545 and driver circuits 335-d can be pull-up or pull-down driver circuits. Additionally or alternatively, channel equalization driver circuits 545 and driver circuits 335-d can be implemented using NMOS transistors. Transmitter 500 can also include a controller 530. Controller 530 can control channel equalization driver circuits 545 independent of driver circuits 335-d (e.g., using first control line 535 and second control line 540). Thus, channel equalization driver circuits 545 can provide programmable channel equalization, and driver circuits 335-d can provide programmable signal drive strength.

[0090] Channel equalization driver circuits 545 can include a plurality of sub-circuits 505. Each sub-circuit 505 can be identical (except for sub-circuit 505-c) and can be part of a circuit group including a plurality (e.g., n) of sub-circuits 505 connected in parallel. For example, there can be a+1 sub-circuits 505-a connected in parallel in circuit group 510-a, b+1 sub-circuits connected in parallel in circuit group 510-b, and c+1 sub-circuits 505-c connected in parallel in circuit group 510-c. When equalization driver circuit 545 is a pull-up driver, each sub-circuit 505 (or circuit group 510) can provide a predetermined amount of current to a signal at an output of equalization driver circuit 545 (e.g., output current I eq may be increased). When equalization driver circuit 545 is a pull-down driver circuit, each sub-circuit 505 (or circuit group 510) can sink a predetermined amount of current from a signal at an output of equalization driver circuit 545 (e.g., output current I eq may be decreased). Thus, activating sub-circuits 505 (and circuit groups 510) can modify output current I eq .

[0091] Each sub-circuit 505-a can include a transistor 515 connected in series with a resistive component 520 (e.g., a resistor). When the equalization driver circuit 545 is a pull-up driver circuit, the transistor 515 can be a PMOS transistor. The transistor 515 and the resistive component 520 can have the same values for each sub-circuit 505, or values within a predetermined range of each other (e.g., within ±x%). When the equalization driver circuit 545 is a pull-up driver circuit, the source of the transistor 515 can be connected to (e.g., shorted to or in electronic communication with) a positive voltage (e.g., the voltage source 525 can be +p V), and the drain of the transistor 515 can be connected to the resistive component 520. Thus, the sub-circuit 505, when activated as part of a pull-up driver circuit, can provide current. The additional current can amplify the drive strength of a signal (e.g., a modified data signal output from the pre-driver circuit 320). In some cases, the modified data signal can be used as an input to the equalization driver circuit 545. Thus, the pull-up equalization driver circuit 545 can modify the strength of the output signal by increasing the output current I eq modifying the strength of the output signal.

[0092] Although sub-circuits 505-a through 505-c are shown with the transistor 515 connected in series with a resistive component, the sub-circuits can be implemented using alternative (e.g., non-series) configurations. In some cases (e.g., in mobile drivers), the sub-circuits 505 can include configurations of NMOS transistors and no resistive components. When the transmitter 500 includes a mobile driver, the termination topology can be different than that depicted in FIG. 6 (e.g., the circuit can be terminated at VSSQ instead of at VDDQ). Figure 5

[0093] When the equalization driver circuit 545 is a pull-down driver circuit, the transistor 515 can be an NMOS transistor. When the equalization driver circuit 545 is a pull-down driver circuit, the source of the transistor 515 can be connected to ground (e.g., the voltage source 525 can be 0 V), and the drain of the transistor 515 can be connected to the resistive component 520. Thus, the sub-circuit 505, when activated as part of a pull-down driver circuit, can sink current. The current that is sunk can decrease the drive strength of a signal (e.g., a modified data signal output from the pre-driver circuit 320). In some cases, the modified data signal can be used as an input to the equalization driver circuit 545. Thus, the pull-down equalization driver circuit 545 can modify the strength of the output signal by decreasing the output current I eq modifying the strength of the output signal. Thus, each sub-circuit 505 can be configured to modify the output current I Ieq .

[0094] ​The amount of current provided or sunk by the circuit group 510 can be a function of the number of sub-circuits 505 in the circuit group 510. For example, if a = 7 and b = 3, activating b + 1 (e.g., 4) sub-circuits 505-b in parallel can provide / sink x mA of current, while activating a + 1 (e.g., 8) sub-circuits 505-a in parallel can provide / sink more than x mA of current. The sub-circuits 505-c can include additional resistive components 520 (compared to sub-circuits 505-a and 505-b) such that the amount of current provided / sunk by the sub-circuits 505-c is half the amount of current provided / sunk by the sub-circuits 505-b. This configuration can enable better tuning of the equalization driver circuit 545.

[0095] The driver circuit 335-d can be similar to the channel equalization driver circuit 545. For example, the driver circuit 335-d can include multiple circuit groups 510 (e.g., three circuit groups, such as 510-b, 510-c, and 510-d), and the equalization driver circuit 545 can also include multiple circuit groups (e.g., five circuit groups, such as 510-d through 510-h). In some cases, the number of circuit groups 510 included in the channel equalization driver circuit 545 can be less than the number of circuit groups 510 included in the driver circuit 335-d. Thus, the channel equalization driver circuit 545 can be a partial replication of the driver circuit 335-d. Regardless of the number of circuit groups, the function of the driver circuit 335-d can be similar to the equalization driver circuit 545.

[0096] Like the channel equalization driver circuit 545, the driver circuit 335-d can include multiple groups of sub-circuits 505. For example, the driver circuit 335-d can include d + 1 sub-circuits in circuit group 510-d, e + 1 sub-circuits in circuit group 510-e, f + 1 sub-circuits in circuit group 510-f, g + 1 sub-circuits in circuit group 510-g, and h + 1 sub-circuits in circuit group 510-h. The sub-circuits 505 in each circuit group 510 can be connected in parallel, and each sub-circuit 505 can be configured to modify the output current (I dr ) of the driver circuit by a predefined amount when activated. Activating a sub-circuit 505 can include turning on a transistor 515 (e.g., biasing the transistor 515) such that current can flow between the drain and the source. Deactivating a sub-circuit 505 can include turning off the transistor 515 such that current can not flow between the drain and the source. Although the sub-circuits 505-d through 505-h are shown with the transistor 550 connected in series with the resistive component, the sub-circuits can be implemented using alternative (e.g., non-series) configurations.

[0097] Similar to channel equalization driver circuit 545, when driver circuit 335-d is a pull-up driver, each sub-circuit 505 (or circuit group 510) can provide a predetermined amount of current to the signal at the output of driver circuit 335-d (e.g., the output current I dr of the equalization driver circuit can be increased). And, when driver circuit 335-d is a pull-down driver, each sub-circuit 505 (or circuit group 510) can sink a predetermined amount of current from the signal at the output of driver circuit 335-d (e.g., the output current I dr of the equalization driver circuit can be decreased). Thus, activating sub-circuit 505 (and circuit group 510) can modify the output current I dr of driver circuit 335-d. The output current I dr of driver circuit 335-d can be associated with a signal representing a bit (e.g., LSB or MSB) in a symbol (e.g., PAM4 symbol) of a multi-level signal. And, the output current I eq of channel equalization driver circuit 545 can be associated with a delayed and inverted version of the signal.

[0098] When driver circuit 335-d is a pull-up driver circuit, the source of transistor 550 can be connected to (e.g., shorted to or in electronic communication with) a positive voltage (e.g., voltage source 565 can be +p V), and the drain of transistor 550 can be connected to resistive component 555. Thus, sub-circuit 505 can provide current when activated as part of a pull-up driver circuit. The additional current can amplify the drive strength of a signal (e.g., a modified data signal output from pre-driver circuit 320). In some cases, the data signal can be used as an input to driver circuit 335-d. Thus, pull-up driver circuit 335-d can modify the strength of the output signal by increasing the output current I dr .

[0099] Similarly, and similar to channel equalization driver circuit 545, when driver circuit 335-d is a pull-down driver circuit, transistor 550 can be an NMOS transistor. When driver circuit 335-d is a pull-down driver circuit, the source of transistor 550 can be connected to ground (e.g., voltage source 565 can be 0 V), and the drain of transistor 550 can be connected to resistive component 555. Thus, sub-circuit 505 can sink current when activated as part of a pull-down driver circuit. The current sunk can decrease the drive strength of a signal (e.g., a modified data signal output from pre-driver circuit 320). In some cases, the modified signal can be used as an input to driver circuit 335-d.

[0100] Each circuit group 510 (and thus each sub-circuit 505) can be activated by a control signal sent by the controller 530. For example, the circuit groups 510 (and sub-circuits 505) in the channel equalization driver circuit 545 can be controlled by a first control signal, while the circuit groups 510 (and sub-circuits 505) in the driver circuit 335-d can be controlled by a second control signal. The control signals can be received at the gates of the transistors by control lines. For example, the first control signal can be received by a first control line 535, and the second control signal can be received by a second control line 540. In some cases, the control lines can be electrically isolated from one another. In other cases, the control lines can be separated by switching components (e.g., transistors). The channel equalization driver circuit 545 can be in electronic communication with the first control line 535, while the driver circuit 335-d can be in electronic communication with the second control line 540.

[0101] The channel equalization driver circuit 545 can be configured to modify its output current I eq , based on the first control signal, while the driver circuit 335-d can be configured to modify its output current I dr , based on the second control signal. For example, the first control signal can activate one or more circuit groups 510 in the channel equalization circuit 545, while the second control circuit can activate one or more circuit groups in the driver circuit 335-d. In some cases, the first control signal includes multiple signals, and each control signal controls one of the sub-circuits 505 in the channel equalization driver circuit 545. Thus, the first control signal can include a first set of signals, and the second control signal can include a second set of signals that is different from the first set of signals. In some cases, the second control signal includes multiple signals, and each signal controls one of the sub-circuits 505 in the driver circuit 335-d. In some cases, the first control signal is a binary-weighted control signal, and the second control signal is a binary-weighted control signal.

[0102] The first control signal and the second control signal can be different, such that the ratio of drive strength to channel equalization can be tailored to an application. That is, the ratio can be flexible, as the channel equalization can be selected independently of the drive strength. For example, the channel equalization can be selected to remain fixed even as the drive strength is increased. Alternatively, the channel equalization can be dynamically controlled such that it is increased as the drive strength is increased, or decreased as the drive strength is increased. Or the channel equalization can be dynamically controlled such that it is decreased as the drive strength is decreased, or increased as the drive strength is decreased. This flexibility is avoided when a single control signal is used to control both the channel equalization driver circuit 545 and the driver circuit 335-d.

[0103] In some cases, the output signal of channel equalization driver circuit 545 can be combined with the output signal of driver circuit 335-d (e.g., DQ eq may be combined with DQ dr ). The output signal of channel equalization driver circuit 545 can be associated with an output current I eq , while the output signal of driver circuit 335-d can be associated with an output current I dr . The combined signal can be superimposed with other signals from transmitter 500 to produce a multi-level signal (e.g., a PAM4 signal) with programmable drive strength and channel equalization. The combined signal can be transmitted to a receiver circuit (e.g., receiver 130, e.g., as described with reference to Figure 1 ).

[0104] In some cases, the control signals can be selected to adjust or modify the effective output impedance of channel equalization driver circuit 545 and driver circuit 335-d. The effective output impedance can be a combination of the output impedance (e.g., output impedance 560-a) as seen from channel equalization driver circuit 545 and the output impedance (e.g., output impedance 560-b) as seen from driver circuit 335-d. Since the symmetry (or linearity) of the output swing of a multi-level signal is a function of the effective output impedance, the control signals can be selected so that the effective impedance matches a target impedance determined to improve linearity. This is because the effective impedance is a function of output current I eq and output current I dr (e.g., output impedance 560-a is a function of modified output current I eq , while output impedance 560-b is a function of modified output current I dr ). Thus, the first control signal can be selected based on the target impedance, and the second control signal can be selected based on the target impedance. For example, the control signals can be selected so that the output currents result in an effective impedance that is within a predetermined range (e.g., ± s %) of the target impedance.

[0105] Although shown with similar exemplary circuit structures, channel equalization driver circuit 545 and driver circuit 335-d perform different functions and can differ in configuration. For example, the output current I dr provided by driver circuit 335-d can modify the drive strength of the signal superimposed with other signals to produce a PAM4 symbol. Similarly, the output current I eq provided by channel equalization driver circuit 545 can modify the drive strength of the output signal, which also contributes to the PAM4 symbol. As described above, the difference in drive strength provided by channel equalization driver circuit 545 and driver circuit 335-d can be achieved by using different control signals to the circuits.

[0106] In addition to being controlled by different control signals, the channel equalization driver circuits 545 and the driver circuits 335-d can differ in configuration such that a particular level of granularity, control, and drive strength can be implemented for each circuit. For example, the channel equalization driver circuits 545 and the driver circuits 335-d can contain different numbers of circuit groups 510, and / or different numbers of sub-circuits 505 per circuit group 510, and / or different values of components in each sub-circuit 505. Additionally or alternatively, the channel equalization driver circuits 545 can be connected to different voltage or current sources than the driver circuits 335-d (e.g., the voltage sources 525 can be different than the voltage sources 565).

[0107] Figure 6 A portion of a multi-level signal transmitter 600 that supports programmable channel equalization of multi-level signaling in accordance with examples of the present disclosure is shown. The transmitter 600 can be an example of the transmitter 300 described with reference to Figure 3 or the transmitter 500 described with reference to Figure 5 The transmitter 600 can contain a set of equalization driver circuits and a set of driver circuits. The equalization driver circuits can be examples of the channel equalization driver circuits 545 or circuit groups 510 within a single channel equalization driver circuit 545. The driver circuits can be examples of the driver circuits 335-d or circuit groups 510 within a single driver circuit 335-d.

[0108] In some cases, the equalization driver circuits are pre-emphasis driver circuits or FFE driver circuits. The channel equalization driver circuits and the driver circuits can be pull-up or pull-down driver circuits. The transmitter 600 can also contain a controller 530-a. The controller 530-a can use different control signals to control the equalization driver circuits and the driver circuits. The channel equalization driver circuits can provide programmable channel equalization, while the driver circuits can provide programmable signal drive strength.

[0109] The channel equalization driver circuits can be in electronic communication with a first control line 535-a, while the driver circuits can be in electronic communication with a second control line 540-a. The controller 530-a can transmit a first control signal to the channel equalization driver circuits and a second control signal to the driver circuits. The first control signal can activate one or more channel equalization driver circuits, while the second control signal can activate one or more driver circuits. The first control signal and the second control signal can be separate signals. In some cases, the control signals can also deactivate one or more driver circuits.

[0110] Each channel equalization driver circuit can be configured to provide a unique amount of current (or drive strength) to an equalized (e.g., de-emphasized or pre-emphasized) signal by modifying the output current of the channel equalization driver circuit. For example, channel equalization driver circuit N+n can be configured to provide an output current of I eqN+n , channel equalization driver circuit N+1 can be configured to provide an output current of I eqN+1 , and channel equalization driver circuit N can be configured to provide an output current of I eqN . Thus, channel equalization can be adaptively tuned or selected by activating one of the channel equalization driver circuits.

[0111] Similarly, each driver circuit can be configured to provide a unique amount of current (or drive strength) to a signal by modifying the output current of the driver circuit. For example, driver circuit N+n can be configured to provide an output current of I drN+n , driver circuit N+1 can be configured to provide an output current of I drN+1 , and driver circuit N can be configured to provide an output current of I drN . Thus, drive strength can be adaptively tuned or selected by activating one of the driver circuits. Accordingly, drive strength and equalization of a multi-level signal can be programmed by activating one of the channel equalization driver circuits and one of the driver circuits. In some cases, the techniques described with reference to Figure 3 may be combined with the techniques described with reference to Figure 5 to provide even more control.

[0112] In some cases, a subset of driver circuits within a group of driver circuits can be independently controlled relative to other driver circuits in the group. For example, controller 530-a can send a first control signal to driver circuit N and a second control signal to driver circuit N+1. The first control signal can activate or deactivate driver circuit N, while the second control signal can activate or deactivate driver circuit N+1. The first control signal and the second control signal can be different signals. Channel equalization driver circuits can similarly be controlled independently of one another. For example, different control signals can be sent to different channel equalization driver circuits, such that certain combinations of channel equalization driver circuits can be activated and deactivated during a period of time.

[0113] The first control line 535-a and the second control line 540-a can be conductive paths or lines. In some cases, the first control line 535-a and the second control line 540-a can be electrically isolated from each other or can be electrically isolatable (e.g., by one or more switches). Components or lines are isolated from each other if there is an open circuit between them. For example, two components that are physically connected by a switch can be isolated from each other when the switch is open. Isolating the control lines can enable the controller 530-a to individually control the channel equalization driver circuits and the driver circuits described herein. Additionally or alternatively, isolating the control lines can enable the controller 530-a to individually control individual (or a small group of) channel equalization driver circuits within a group of channel equalization driver circuits, or to individually control individual (or a small group of) driver circuits within a group of driver circuits.

[0114] Figure 7 A flow diagram illustrating a method 700 that supports programmable channel equalization with multi-level signaling in accordance with aspects of the present disclosure is shown. The operations of method 700 can be implemented by a transmitter or its components as described herein. For example, the operations of method 700 can be performed by the transmitter described with reference to FIGs. 1-6. Figure 3 、 5 and 6.

[0115] At 705, the method can include receiving, at a driver circuit, a first control signal over a first control line. In some cases, the driver circuit includes a plurality of sub-circuits, and the first control signal activates at least one of the sub-circuits. At 710, the method can include receiving, at a channel equalization driver circuit, a second control signal different from the first control signal over a second control line different from the first control line. In some cases, the channel equalization driver circuit includes a plurality of sub-circuits, and the second control signal activates at least one of the sub-circuits. At 715, the method can include modifying an output current of the driver circuit based at least in part on the first control signal. At 720, the method can include modifying an output current of the channel equalization driver circuit based on the second control signal.

[0116] In some cases, the method includes receiving, at a second driver circuit, the first control signal over the first control line. In such cases, the first control signal can deactivate the driver circuit and deactivate the second driver circuit. In some cases, the method can include receiving, at a second channel equalization driver circuit, the first control signal over the second control line. In such cases, the second control signal can activate the channel equalization driver circuit and deactivate the second channel equalization driver circuit.

[0117] In some cases, the method includes combining a first output signal associated with the output current of the driver circuit and a second output signal associated with the output current of the channel equalization driver circuit. In such cases, the method can further include transmitting or sending the combination of the output signals to a receiver circuit. In some cases, the method can include determining an input impedance of the receiver circuit. The receiver circuit can be in electronic communication with the driver circuit. In such cases, the method can further include selecting the first control signal based at least in part on the input impedance of the receiver circuit.

[0118] In some cases, the method can include receiving a data signal at the driver circuit and receiving a control signal at the channel equalization driver circuit. In such cases, modifying the output current of the driver circuit can be based at least in part on modifying an intensity of the data signal, and modifying the output current of the channel equalization driver circuit can be based at least in part on modifying an intensity of the channel equalized version of the data signal.

[0119] In some cases, the method can include determining a target impedance. In such cases, the method can further include selecting the first control signal based at least in part on the target impedance and selecting the second control signal based at least in part on the target impedance. In such cases, an output impedance of the driver circuit and an output impedance of the channel equalization driver circuit can provide an effective output impedance within a predetermined range of the target impedance. In some cases, the output impedance of the driver circuit is a function of the modified output current of the driver circuit, and the output impedance of the channel equalization driver circuit is a function of the modified output current of the channel equalizer driver circuit.

[0120] In some cases, the method can include activating at least one subcircuit of the driver circuit based at least in part on the first control signal. In such cases, modifying the output current of the driver circuit can be based at least in part on activating the at least one subcircuit of the driver circuit. In some cases, the method can include activating at least one subcircuit of the channel equalization driver circuit based at least in part on the second control signal. In such cases, modifying the output current of the channel equalization driver circuit can be based at least in part on activating the at least one subcircuit of the channel equalization driver circuit.

[0121] In some cases, the method can include receiving a data signal from a data array at a de-emphasis (or pre-emphasis) buffer circuit, and generating a control signal using the de-emphasis (or pre-emphasis) buffer circuit. In such cases, the method can also include transmitting the control signal from the de-emphasis (or pre-emphasis) buffer circuit to a pre-driver circuit, modifying the control signal at the pre-driver circuit, and transmitting the modified control signal to the channel equalization driver circuit.

[0122] The techniques described herein can be implemented by a transmitter. The transmitter can include a driver circuit having a first input in electronic communication with an output of a first pre-driver circuit. The driver circuit can also have a second input in electronic communication with a first control line. The driver circuit can be configured to modify a strength of a first output signal of the first pre-driver circuit based at least in part on a first control signal received over the first control line. The transmitter can also include a channel equalization driver circuit having a third input in electronic communication with an output of a second pre-driver circuit. The channel equalization driver circuit can also have a fourth input in electronic communication with a second control line. The channel equalization driver circuit can be configured to modify a strength of a second output signal of the second pre-driver circuit based at least in part on a second control signal received over the second control line. The channel equalization driver circuit can be a de-emphasis driver circuit or a pre-emphasis driver circuit.

[0123] In some cases, the driver circuit can be configured to modify the strength of the first output signal by increasing an output current of the driver circuit or decreasing an output current of the driver circuit. In some cases, the channel equalization driver circuit can be configured to modify the strength of the second output signal by increasing an output current of the channel equalization driver circuit or decreasing an output current of the channel equalization driver circuit.

[0124] In some cases, the transmitter can include a driver circuit in electronic communication with a first control line. The driver circuit can be configured to modify an output current thereof based at least in part on a first control signal received over the first control line. The transmitter can also include a channel equalization driver circuit in electronic communication with a second control line different from the first control line. The channel equalization driver circuit can be configured to modify an output current thereof based at least in part on a second control signal received over the second control line.

[0125] In some cases, the first control signal includes a first set of signals and the second control signal includes a second set of signals different from the first set of signals. In some cases, the first control signal and the second control signal include binary weighted control signals. In some cases, the first control signal and the second control signal are different signals.

[0126] In some cases, the transmitter includes a first pre-driver circuit configured to modify a data signal and transmit the modified data signal to a driver circuit, and a second pre-driver circuit configured to modify a control signal generated from the data signal. The second pre-driver circuit can be configured to transmit the modified control signal to the channel equalization driver circuit. In such cases, the driver circuit can be configured to modify its output current by modifying an intensity of an output signal, and the channel equalization driver circuit can be configured to modify its output current by modifying an intensity of an output signal.

[0127] In some cases, the driver circuit includes a plurality of sub-circuits, and each sub-circuit is controlled by the first control signal. Each sub-circuit can be configured to modify the output current of the driver circuit by a predefined amount when activated. In some cases, the channel equalization driver circuit includes a plurality of sub-circuits, and each sub-circuit is controlled by the second control signal. Each sub-circuit can also be configured to modify the output current of the channel equalization driver circuit by a predefined amount when activated.

[0128] In some cases, the method 700 can be performed at least in part by a device. The device can include means for receiving a first control signal at a driver circuit over a first control line, means for receiving a second control signal different from the first control signal at a channel equalization driver circuit over a second control line different from the first control line, means for modifying an output current of the driver circuit based at least in part on the first control signal, and means for modifying an output current of the channel equalization driver circuit based on the second control signal.

[0129] The apparatus can further include means for receiving the first control signal at a second driver circuit over the first control line, wherein the first control signal activates the driver circuit and deactivates the second driver circuit. The apparatus can further include means for receiving the first control signal at a second channel equalization driver circuit over the second control line, wherein the second control signal activates the channel equalization driver circuit and deactivates the second channel equalization driver circuit. The apparatus can further include means for combining a first output signal associated with the output current of the driver circuit and a second output signal associated with the output current of the channel equalization driver circuit, and means for transmitting the combined output signal to a receiver circuit.

[0130] The apparatus can further include means for receiving a data signal at the driver circuit, and means for receiving a delayed and inverted version of the data signal at the channel equalization driver circuit, wherein modifying the output current of the driver circuit is based at least in part on modifying an intensity of the data signal, and wherein modifying the output current of the channel equalization driver circuit is based at least in part on modifying an intensity of the delayed and inverted version of the data signal.

[0131] The apparatus can further include means for activating at least one subcircuit of the driver circuit based at least in part on the first control signal, wherein modifying the output current of the driver circuit is based at least in part on activating the at least one subcircuit of the driver circuit. The apparatus can further include means for activating at least one subcircuit of the channel equalization driver circuit based at least in part on the second control signal, wherein modifying the output current of the channel equalization driver circuit is based at least in part on activating the at least one subcircuit of the channel equalization driver circuit.

[0132] It should be noted that the methods described above describe possible implementations, and that the operations and the steps recited in the methods can be rearranged or modified and that other implementations are possible. Furthermore, aspects from two or more of the methods can be combined.

[0133] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signals can be represented by a bus of signals where the bus can have a variety of bit widths.

[0134] As used herein, the term“virtual ground” refers to a node of an electrical circuit that is held at a voltage of approximately zero volts (0 V) but is not directly connected to ground. Accordingly, the voltage of a virtual ground can temporarily fluctuate and then return to the steady state of approximately 0 V. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider composed of an operational amplifier and resistors. Other implementations are possible. “Virtual ground” or“virtually grounded” refers to a connection to approximately 0 V.

[0135] The terms“electronically communicate” and“coupled” refer to a relationship between components that supports the flow of electrons between the components. It can include a direct connection between the components, or it can include intervening components. Components that are electronically communicating or coupled to one another can be actively exchanging electrons or signals (e.g., in a powered circuit), or can not be actively exchanging electrons or signals (e.g., in an unpowered circuit), but can be configured and operable to exchange electrons or signals when the circuit is powered. For example, two components that are physically connected by a switch (e.g., a transistor) are electronically communicating or can be coupled regardless of the state of the switch (i.e., open or closed).

[0136] The term“isolated” refers to a relationship between components in which electrons are not currently able to flow between the components; they are isolated from one another if there is an open circuit between the components. For example, two components that are physically connected by a switch can be isolated from one another when the switch is open.

[0137] As used herein, the term“shorted” refers to a relationship between components in which an electrically conductive path is established between the components by activating a single intervening component between the two components in question. For example, a first component that is shorted to a second component can exchange electrons with the second component when a switch between the two components is closed. Thus, a short can be a dynamic operation that enables charge to flow between components (or lines) that are electronically communicating.

[0138] Devices discussed herein, including memory device 100, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)), or an epitaxial layer of semiconductor material on another substrate. The electrical conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemicals, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during initial formation or growth of the substrate, or by any other doping means.

[0139] One or more transistors discussed herein can represent a field effect transistor (FET) and include a three-terminal device that includes a source, a drain, and a gate. Terminals can be connected to other electronic components by conductive material (e.g., metal). The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to conduct. A transistor can be“turned on” or“activated” when a voltage greater than or equal to the transistor threshold voltage is applied to the transistor gate. A transistor can be“turned off’ or“deactivated” when a voltage less than the transistor threshold voltage is applied to the transistor gate.

[0140] The description set forth herein, in connection with the appended drawings, describes exemplary configurations and does not represent all of the instances that can be implemented or that are within the scope of the claims. The term“exemplary” used herein means“serving as an example, instance, or illustration,” and not“preferred” or“superior” over other instances. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0141] In the appended figures, similar components or features can have the same reference label. Further, various components of the same type can be distinguished by adding a dash and a second label that distinguishes among the components of the same type in each of the figures. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

[0142] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0143] The various illustrative blocks and modules described in connection with the disclosure can be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general purpose processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, e.g., a combination of a digital signal processor (DSP) and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0144] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed as sub-parts of a functional module to various hardware locations, and include implementing functions as a piece of code on a non-transitory medium that is in communication with the processor for execution. Moreover, as used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of’ indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, including in the claims, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0145] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0146] The description herein is presented to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: applying a first control signal having a first weight to a first driver; generating, by the first driver and based at least in part on the first control signal, a first electrical pulse representing a first bit of a first sign in a multi-level signal, wherein each level in the multi-level signal comprises signs representing a plurality of bits; applying a second control signal having a second weight different from the first weight and independent of the first control signal to a second driver; and partially reducing, by the second driver and based at least in part on the second control signal, an amplitude of the first electrical pulse to an intermediate level for a threshold duration midway through the first electrical pulse.

2. The method of claim 1, further comprising: generating, by a third driver, a second electrical pulse representing a second bit of the first sign, wherein the first sign is based at least in part on a combination of the first electrical pulse and the second electrical pulse; and partially reducing, by a fourth driver, an amplitude of the second electrical pulse to a second intermediate level for a second threshold duration midway through the second electrical pulse.

3. The method of claim 2, wherein the third driver generates the second electrical pulse based at least in part on a third control signal, and wherein the fourth driver partially reduces the amplitude of the second electrical pulse based at least in part on a fourth control signal.

4. The method of claim 1, further comprising: reducing, based at least in part on the second control signal, an amount of current generated by the second driver, wherein reducing the amount of current generated by the second driver partially reduces the amplitude of the first electrical pulse.

5. The method of claim 4, further comprising: establishing, prior to applying the second control signal, a conductive path between an output of the second driver and a voltage supply; and deactivating, based at least in part on the second control signal, a switching component that is part of the conductive path, wherein reducing the amount of current generated by the second driver is based at least in part on deactivating the switching component.

6. The method of claim 1, further comprising: increasing, by the second driver and based at least in part on the second control signal, an amount of current drawn from an output of the first driver, wherein increasing the amount of current drawn by the second driver partially reduces the amplitude of the first electrical pulse.

7. The method of claim 6, further comprising: establishing, by the second driver and based at least in part on the second control signal, a conductive path between the output of the first driver and a ground reference, wherein increasing the amount of current drawn from the output is based at least in part on establishing the conductive path.

8. The method of claim 1, further comprising: activating, based at least in part on the first control signal, a first plurality of circuits of the first driver, wherein generating the first electrical pulse is based at least in part on activating the first plurality of circuits; and deactivating, based at least in part on the second control signal, a second plurality of circuits of the second driver, wherein partially reducing the amplitude of the first electrical pulse is based at least in part on deactivating the second plurality of circuits. The second plurality of pull-up circuits of the second driver are deactivated at least in part based on the second control signal, wherein the amplitude of the first electrical pulse is reduced at least in part based on the deactivation of the second plurality of pull-up circuits compared to when the second plurality of pull-up circuits are activated; The third plurality of pull-down circuits of the second driver are activated at least in part based on the second control signal, wherein the amplitude of the first electrical pulse is reduced at least in part based on the activation of the third plurality of pull-down circuits.

9. The method of claim 1, wherein the first electrical pulse comprises a current pulse and a voltage pulse, and wherein during the threshold duration, the amplitude of the first electrical pulse is within the threshold range of the intermediate level.

10. An apparatus comprising: A first driver is configured to receive a first control signal having a first weight and, in response to the first control signal, generate a first electrical pulse representing the first bit of a first symbol in a multilevel signal, wherein each level in the multilevel signal includes a symbol representing a plurality of bits. A second driver is configured to receive a second control signal having a second weight different from the first weight and, in response to the second control signal, partially reduce the amplitude of the electrical pulse to an intermediate level during a threshold duration midway through the electrical pulse. and A controller coupled to the first driver and the second driver and configured to supply the first control signal to the first driver independently of the second control signal.

11. The device according to claim 10, further comprising: A third driver is configured to generate a second electrical pulse representing a second bit of the first symbol, wherein the first symbol is based at least in part on a combination of the first electrical pulse and the second electrical pulse; and A fourth driver is configured to partially reduce the amplitude of the second electrical pulse to a second intermediate level during a second threshold duration midway through the second electrical pulse.

12. The device of claim 10, wherein the second driver comprises: A circuit system configured to increase the amplitude of the first electrical pulse when activated.

13. The device of claim 10, wherein the second driver comprises: A circuit system configured to draw current when activated, wherein when the second driver is activated, the amplitude of the first electrical pulse is reduced.

14. The device of claim 10, wherein the second driver comprises: A first switching assembly coupled to a first resistive component and a voltage power supply, wherein the second driver is configured to partially reduce the amplitude of the first electrical pulse when the first switching assembly is deactivated, compared to when the first switching assembly is activated.

15. The device of claim 10, wherein the second driver comprises: A first switching assembly coupled to a first resistive assembly and a ground reference, wherein the second driver is configured to partially reduce the amplitude of the first electrical pulse when the first switching assembly is activated.

16. An apparatus comprising: First driver; A second driver, which is coupled to the first driver; and A controller, coupled to the first driver and the second driver, wherein the controller is configured to: A first control signal with a first weight is applied to the first driver, such that the first driver generates a first electrical pulse representing the first bit of a first symbol in a multilevel signal, wherein each level in the multilevel signal includes a symbol representing a plurality of bits; and A second control signal, having a second weight different from the first weight and independent of the first control signal, is applied to the second driver, such that the second driver partially reduces the amplitude of the first electrical pulse to an intermediate level during the threshold duration midway through the first electrical pulse.

17. The device according to claim 16, further comprising: A third driver is configured to generate a second electrical pulse representing a second bit of the first symbol, wherein the first symbol is based at least in part on a combination of the first electrical pulse and the second electrical pulse; and A fourth driver is configured to partially reduce the amplitude of the second electrical pulse to a second intermediate level during a second threshold duration midway through the second electrical pulse.

18. The device of claim 16, wherein the first driver comprises: A first plurality of circuits connected in parallel, the first plurality of circuits being configured to output current when activated by the first control signal, and wherein the second driver comprises: A second plurality of circuits connected in parallel, the second plurality of circuits being configured to output current when activated by the second control signal.

19. The device of claim 16, wherein the first driver comprises: A first plurality of circuits connected in parallel, the first plurality of circuits being configured to output current when activated by the first control signal, and wherein the second driver comprises: A second plurality of circuits connected in parallel, the second plurality of circuits being configured to draw current from the first driver when activated by the second control signal.

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