Side scan circuit and chip based on special scan chain architecture characteristics

Abstract

The present invention is mainly used in the field of digital circuit technology. The present invention discloses a side scan circuit and chip based on special scan chain architecture features. The side scan circuit includes a connection component and multiple scan chains; each scan chain includes at least one node connection end in a first state or a second state; the node connection ends in the first state of each scan chain are interconnected according to a preset connection relationship; the node connection ends in the second state of each scan chain are connected to the node connection ends in the first state or the second state of the target scan chain through the connection component. The technical solution of the present invention can provide a new hardware circuit solution for implementing side scan chain fault diagnosis, thereby performing fault diagnosis more flexibly.

Description

Technical Field

[0001] The present invention relates to the field of digital circuit technology, and in particular to a side scan circuit and chip based on special scan chain architecture features. Background Art

[0002] In existing side scan chain fault diagnosis solutions, side scan chains can be divided into multiple groups based on clock domain or layout constraints. By inserting looping side transmission paths into the scan chains within each group, this ensures that test vectors from each faulty scan chain (referred to as a bad chain) can be transmitted to one or more fault-free scan chains (referred to as good chains), and that the bad chains also capture test vectors transmitted from the good chains. This solution achieves manageable hardware overhead, efficient and accurate fault diagnosis, and flexible adaptive diagnosis.

[0003] In a side scan circuit composed of multiple side scan chains, optimal circuit design specifies a specific limit on the number of scan chains, and each scan chain is of the same length. This facilitates the formation of a loop transmission path at each unit connection without adding additional circuitry. However, in practice, it is impossible for a side scan circuit to fully achieve the optimal circuit design. When objective constraints prevent the optimal circuit design from being achieved, how to provide a side scan circuit that can perform fault diagnosis remains a challenge for those skilled in the art. Summary of the Invention

[0004] The present invention provides a side scan circuit and chip based on special scan chain architecture features, which can provide a new hardware circuit solution for implementing side scan chain fault diagnosis, thereby performing fault diagnosis more flexibly.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a side scan circuit based on a special scan chain architecture feature, the side scan circuit comprising a connection component and a plurality of scan chains;

[0006] Each of the scan chains includes at least one node connection terminal in a first state or a second state;

[0007] The node connection ends of each scan chain in the first state are connected to each other according to a preset connection relationship;

[0008] The node connection end in the second state of each scan chain is connected to the node connection end in the first state or the second state of the target scan chain through the connection component.

[0009] Optionally, the number of scan chains in the side scan circuit is any odd number greater than 1;

[0010] The connection component includes at least one first inverter;

[0011] The node connection end of the scan chain in the second state is connected to the node connection end of the target scan chain in the first state through the first inverter.

[0012] Optionally, the connection component includes a plurality of first inverters;

[0013] Each of the scan chains includes a plurality of scan units connected in series, and each of the scan units includes a first connection end and a second connection end;

[0014] The first connection end of the scanning unit in the scan chain serves as a node connection end of the scan chain in a first state, and the second connection end of the scanning unit in the scan chain serves as a node connection end of the scan chain in a second state;

[0015] The input end of each first inverter is used to be connected to the second connection end of the target scanning unit, and the output end of each first inverter is used to be connected to the first connection end of the target scanning unit.

[0016] Optionally, each of the scan chains includes a first node connection end in a first state or a second state, and a second node connection end in the first state or the second state;

[0017] Each of the scan chains is sorted according to a first preset order;

[0018] The first node connection end of the last scan chain in the first preset order, which is in the first state, is connected to the second node connection end of the previous scan chain, which is in the first state;

[0019] The second node connection end of the last scan chain in the first preset order, which is in the second state, is connected to the input end of the first inverter;

[0020] The output terminal of the first inverter is connected to the first node connection terminal of the first scan chain in the first preset order which is in the first state.

[0021] Optionally, the side scan circuit includes a long scan chain and a short scan chain, and the length of the long scan chain is greater than the length of the short scan chain;

[0022] The long scan chain includes a node connection end in a first state and a node connection end in a second state;

[0023] Each node connection end in the short scan chain is a node connection end in a first state;

[0024] The node connection end of the long scan chain in the second state is used to connect to the node connection end of the short scan chain in the first state through the connection component.

[0025] Optionally, the connection component includes at least one XEN-OR gate logic operator;

[0026] The long scan chain or the short scan chain includes a plurality of scanning units connected in series, and each of the scanning units includes a first connection end and a second connection end;

[0027] The second connection end of the target scan unit in the long scan chain serves as a node connection end of the long scan chain in the second state and is connected to the input end of the XNOR gate logic operator;

[0028] The first connection end of each scanning unit in the short scan chain serves as a node connection end of the short scan chain in the first state;

[0029] The output end of the XNOR logic operator is connected to the first connection end of the target scan unit in the short scan chain.

[0030] Optionally, each of the scan chains is sorted according to a second preset order, and each scan unit in the scan chain is sorted according to a third preset order;

[0031] In the second preset order, the previous scan chain is a long scan chain, and the next scan chain is a short scan chain, and the second connection ends of the last three scan units in the previous scan chain arranged according to the third preset order are all connected to the first connection end of the last scan unit in the next scan chain arranged according to the third preset order through the XNOR gate logic operator, or,

[0032] In the second preset order, the previous scan chain is a short scan chain, the next scan chain is a long scan chain, and the second connection end of the last scan unit in the previous scan chain sorted according to the third preset order is connected to the first connection ends of the last two scan units in the next scan chain sorted according to the third preset order.

[0033] Optionally, the side scan circuit further includes a plurality of the long scan chains;

[0034] The node connection end of the long scan chain in the second state is further used to connect to the node connection end of the target long scan chain in the second state through the connection component;

[0035] The connection component includes at least one second inverter;

[0036] Each of the long scan chains includes a plurality of scan units connected in series, and each of the scan units includes a first connection end and a second connection end;

[0037] The second connection terminal of the target scan unit in the long scan chain, serving as a node connection terminal of the long scan chain in the second state, is connected to the input terminal of the second inverter;

[0038] The first connection end of the target scan unit in the target long scan chain serves as a node connection end of the target long scan chain in the second state and is connected to the output end of the second inverter.

[0039] Optionally, each of the scan chains is sorted according to a fourth preset order, and each scan unit in the scan chain is sorted according to a fifth preset order;

[0040] In the fourth preset order, at least one short scan chain is arranged between two long scan chains, and the second connection end of the last scan unit in the previous long scan chain arranged according to the fifth preset order is connected to the first connection end of the last scan unit in the next long scan chain arranged according to the fifth preset order through the second inverter.

[0041] In a second aspect, the present invention further provides a chip comprising any one of the above-mentioned side scan circuits based on the special scan chain architecture features.

[0042] The present invention has at least the following beneficial effects:

[0043] The technical solution of the present application provides a side scan circuit based on a special scan chain architecture feature, the side scan circuit includes a connecting component and multiple scan chains; each scan chain includes at least one node connection end in a first state or a second state; the node connection ends in the first state of each scan chain are connected to each other according to a preset connection relationship; the node connection end in the second state of each scan chain is connected to the node connection end in the first state or the second state of the target scan chain through the connecting component. It can be seen that the new side scan circuit provided by the technical solution of the present application has a small number of components, which is conducive to reducing hardware overhead, and the connection relationship between the components is simple, which is conducive to simplifying wiring. At the same time, the input signal for diagnosing faults can be transmitted between each scan chain and the connecting component. In the event of a fault in any part of any scan chain, the fault can still be accurately identified and located based on the input signals that are freely transmitted without obstacles in each part, thereby realizing side scan chain fault diagnosis. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solution of the present invention and do not constitute a limitation to the technical solution of the present invention.

[0045] Figure 1It is a structural diagram of a side scan circuit based on the special scan chain architecture feature;

[0046] Figure 2 It is a structural schematic diagram of a first side scanning circuit including a plurality of scanning units;

[0047] Figure 3 A schematic structural diagram of a first side scanning circuit including a single-bit trigger and a connector;

[0048] Figure 4 It is a structural schematic diagram of a second side scanning circuit including a plurality of scanning units;

[0049] Figure 5 A schematic structural diagram of a second side scanning circuit including a single-bit trigger and a connector;

[0050] Figure 6 It is a structural schematic diagram of a third side scanning circuit including a plurality of scanning units;

[0051] Figure 7 The present invention is a schematic structural diagram of a third side scanning circuit including a single-bit trigger and a connector;

[0052] Figure 8 The present invention is a schematic diagram of the structure of a chip including a side scan circuit based on special scan chain architecture features. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0054] Before explaining the embodiments of the present application in detail, some of the nouns and terms involved in the embodiments of the present application are first explained. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0055] In a side scan circuit consisting of multiple side scan chains, when the side scan architecture divides the multiple scan chains into multiple scan chain groups, the following recommendations should be followed to maximize test coverage:

[0056] All chains in a group should have the same length so that a cyclic transmission path at each cell index can be easily implemented without adding additional circuits.

[0057] The number of chains in each chain group should be an even number, and the number of chains should be equal to or greater than 4.

[0058] This circuit design facilitates the formation of a loop transmission path at each unit connection without adding additional circuitry. However, in practice, it's impossible for a side scanning circuit to fully achieve the optimal circuit design. When objective constraints prevent the optimal circuit design, how to provide a side scanning circuit capable of fault diagnosis remains a challenge for those skilled in the art.

[0059] In order to solve the above problems, the technical solution of the present application provides a side scan circuit based on the special scan chain architecture feature, the side scan circuit includes a connecting component and multiple scan chains; each scan chain includes at least one node connection end in a first state or a second state; the node connection ends in the first state of each scan chain are connected to each other according to a preset connection relationship; the node connection end in the second state of each scan chain is connected to the node connection end in the first state or the second state of the target scan chain through the connecting component. It can be seen that the new side scan circuit provided by the technical solution of the present application has a small number of components, which is conducive to reducing hardware overhead, and the connection relationship between the components is simple, which is conducive to simplifying wiring. At the same time, the input signal for diagnosing faults can be transmitted between each scan chain and the connecting component. In the event of a fault in any part of any scan chain, the fault can still be accurately identified and located based on the input signals that are freely transmitted without obstacles in each part, thereby realizing side scan chain fault diagnosis.

[0060] The embodiments provided by the technical solution of this application are as follows:

[0061] Please refer to Figure 1 , Figure 1 The present invention is a structural diagram of a side scan circuit based on special scan chain architecture characteristics.

[0062] In a first aspect, the present invention provides an embodiment, which provides a side scanning circuit based on special scan chain architecture characteristics, wherein the side scanning circuit includes a connecting component and multiple scan chains; each scan chain includes at least one node connection end in a first state or a second state; the node connection ends in the first state of each scan chain are connected to each other according to a preset connection relationship; the node connection ends in the second state of each scan chain are connected to the node connection ends in the first state or the second state of the target scan chain through the connecting component.

[0063] In this embodiment, the first state means that the current node connection end has a corresponding connection relationship with another node connection end and can be connected normally, so it is in a normal connection state; the second state means that the current node connection end has no corresponding connection relationship with other node connection ends, and will be in an abnormal state when connected to other node connection ends and cannot be connected normally.

[0064] In one specific embodiment, the side scan circuit includes a connection component and three scan chains, wherein all node connection ends in two scan chains are in a first state. In the two scan chains, each node connection end is connected in a corresponding relationship. For example, if each of the three scan chains has only one node connection end, the node connection end of the first scan chain is connected to the second scan chain, and the node connection end of the second scan chain is connected to the third scan chain. In this specific embodiment, the node connection end of the third scan chain is a node connection end in the second state. After the node connection end of the third scan chain is connected to the connection component, the connection component is then connected to the first scan chain or the second scan chain.

[0065] In some embodiments, the number of scan chains in the side scan circuit is any odd number greater than 1; the connecting component includes at least one first inverter; the node connection end of the scan chain in the second state is connected to the node connection end of the target scan chain in the first state through the first inverter.

[0066] In some embodiments, the side scan circuit includes three scan chains, the node connection end of the first scan chain in the second state is connected to one end of the first inverter, the other end of the first inverter is connected to the node connection end of the second scan chain in the first state, and the node connection end of the third scan chain is connected to the second scan chain.

[0067] It can be understood that the use of inverters as connecting components in this embodiment reduces hardware overhead, simplifies wiring, reduces signal delay and interference, improves signal integrity, and thus reduces power consumption compared to a complex XOR gate structure.

[0068] In some embodiments, the scan chain has multiple node connection terminals. For example, node connection terminal A1 in scan chain A is connected to node connection terminal B1 in scan chain B, node connection terminal A2 in scan chain A is connected to node connection terminal B2 in scan chain B, and so on. Each node connection terminal on scan chains A and B is connected according to the above connection relationship. If each node connection terminal in scan chain C is a node connection terminal in the second state, then each node connection terminal in scan chain C needs to be connected to a plurality of inverters in a one-to-one correspondence, and then each inverter is connected to each node connection terminal on scan chain A or B in a one-to-one correspondence. For example, the node connection end C1 in the scan chain C is connected to the inverter D1, the node connection end C2 in the scan chain C is connected to the inverter D2, and so on. Each node connection end in the scan chain C is connected to the corresponding inverter. Then, the inverter D1 is connected to the node connection end A1 in the scan chain A or the node connection end B1 in the scan chain B, the inverter D2 is connected to the node connection end A2 in the scan chain A or the node connection end B2 in the scan chain B, and so on, until each node connection end in the scan chain C is connected to the node connection end of the scan chain A or the scan chain B through the inverter.

[0069] In some embodiments, each scan chain includes a first node connection end in a first state or a second state, and a second node connection end in the first state or the second state; each scan chain is sorted according to a first preset order; the first node connection end in the first state of the last scan chain in the first preset order is connected to the second node connection end in the first state of the previous scan chain; the second node connection end in the second state of the last scan chain in the first preset order is connected to the input end of the first inverter; and the output end of the first inverter is connected to the first node connection end in the first state of the first scan chain in the first preset order.

[0070] In some embodiments, the connection component includes multiple first inverters; each scan chain includes multiple scanning units connected in series, and each scanning unit includes a first connection end and a second connection end; the first connection end of the scanning unit in the scan chain serves as the node connection end of the scan chain in the first state, and the second connection end of the scanning unit in the scan chain serves as the node connection end of the scan chain in the second state; the input end of each first inverter is used to connect to the second connection end of the target scanning unit, and the output end of each first inverter is used to connect to the first connection end of the target scanning unit.

[0071] It is understood that in a scan chain, each series-connected scan unit is arranged in a specific series order. For example, in a scan chain with five scan units, these five scan units are connected in series so that the output of the preceding scan unit is connected to the input of the following scan unit. In this order, the input of the first scan unit serves as the input of the scan chain. The input signal is input from the input of the scan chain and then transmitted to each scan unit in sequence. Finally, the input signal is output from the output of the last scan unit, i.e., from the output of the scan chain.

[0072] It can be understood that this embodiment divides the scan chain into multiple scan units, and the first connection end and the second connection end of each scan unit serve as node connection ends of the scan chain. At the same time, an equal number of inverters are configured based on the correspondence between the scan units and the inverters. This is beneficial for the input signal to be transmitted in each scan unit in the scan chain. By detecting the faulty scan unit, it is easier to lock the faulty part in the scan chain.

[0073] See Figure 2The sideway scan circuit in this embodiment includes five scan chains, arranged from top to bottom in a first preset order: scan chain Chain 10, scan chain Chain 11, scan chain Chain 12, scan chain Chain 13, and scan chain Chain 14. Scan_in0, Scan_in1, Scan_in2, Scan_in3, and Scan_in4 are the fault diagnosis input signals to scan chains Chain 10, Chain 11, Chain 12, Chain 13, and Chain 14, respectively. Scan_en and sideway_tr are the enable and sideway selection signals transmitted to each scan unit, respectively. Each scan chain includes eight scan units. As shown from left to right in the figure, the input of the first scan unit serves as the input of the scan chain, the output of the previous scan unit is connected to the input of the next scan unit, and the output of the last scan unit serves as the output of the scan chain. Therefore, each scan unit is connected in series. Each scan chain includes multiple first node connection terminals and multiple second node connection terminals. The first connection terminal of each scan unit serves as the first node connection terminal, and the second connection terminal of each scan unit serves as the second node connection terminal. The first node connection terminals and second node connection terminals of scan chains Chain 10, Chain 11, Chain 12, and Chain 13 are all in the first state. Only the first node connection terminal of scan chain Chain 14 is in the first state, while the second node connection terminal of scan chain Chain 14 is in the second state. As shown in the figure, from top to bottom, the second node connection terminal of the first scan chain Chain 10 is connected to the first node connection terminal of scan chain Chain 11, and so on, until the second node connection terminal of the last scan chain Chain 14 is connected to the first node connection terminal of the first scan chain Chain 10 through the first inverter.

[0074] It can be understood that, in this embodiment, since each scan chain and each scan unit are arranged in sequence, when a part of the scan chain (scan unit) fails, it is easier to locate the location where the failure occurs.

[0075] In some embodiments, each scanning unit includes a single-bit trigger and a connector; the input end of the single-bit trigger is connected to the output end of the connector, and the input end of the single-bit trigger serves as the second connection end of the scanning unit; the input end of the connector serves as the first connection end of the scanning unit.

[0076] See Figure 3 , Figure 3 The invention is a structural diagram of a first side scanning circuit including a single-bit trigger and a connector.

[0077] This application also provides a method for utilizing Figure 3 The sideway scanning circuit shown in the figure implements a specific embodiment of fault diagnosis. In this embodiment, the sideway scanning circuit includes five scan chains of equal length, designated Scan Chain 0, Scan Chain 1, Scan Chain 2, Scan Chain 3, and Scan Chain 4. Each scan chain contains eight scan cells. Scan_in0, Scan_in1, Scan_in2, Scan_in3, and Scan_in4 are the test vectors input to the five scan chains for fault diagnosis. Scan_en and sideway_tr are the enable and sideway selection signals transmitted to each scan cell, respectively. An inverter is inserted in the sideway transmission path from Scan Chain 4 to Scan Chain 1. To verify the effectiveness of this structure, assume a stuck-at-0 fault occurs in Scan Cell 3 of Scan Chain 4. This location is affected by the inverter in its path during sideway transmission. Fault diagnosis is then performed using the method described in the prior art. The test vectors for each process are shown in Table 1. The relevant derivation demonstrates that all faults can be accurately diagnosed and located.

[0078] Table 1 - Test vector table for the first fault diagnosis case

[0079]

[0080] In some embodiments, the side scan circuit includes a long scan chain and a short scan chain, the length of the long scan chain is greater than that of the short scan chain; the long scan chain includes a node connection end in a first state and a node connection end in a second state; each node connection end in the short scan chain is a node connection end in the first state; the node connection end of the long scan chain in the second state is used to connect to the node connection end of the short scan chain in the first state through a connecting component.

[0081] In a specific embodiment, the side scan circuit includes a connection component and three scan chains, two of which are long scan chains, and one scan chain is a short scan chain and all the node connection ends thereof are in a first state. In the two long scan chains, each node connection end is in a corresponding relationship. For example, the three scan chains each have only one node connection end, then the node connection end of the first long scan chain is a node connection end in the first state and is connected to the second long scan chain; the node connection end of the second long scan chain is a node connection end in the second state and is connected to the short scan chain through the connection component, and the node connection end of the short scan chain is connected to the first long scan chain.

[0082] It can be understood that the side scanning circuit of this embodiment is a solution that optimizes the structure of processing unequal length scan chains in the existing technical solution. In physical implementation, it occupies less chip area, reduces hardware overhead, simplifies circuit layout and wiring, reduces potential signal delays and interference problems, thereby improving signal integrity. Since electrons are transmitted through fewer gates, the power consumption of the overall circuit will be reduced.

[0083] In some embodiments, the connection component includes at least one XEN-OR gate logic operator; the long scan chain or the short scan chain includes multiple scanning units connected in series, and each scanning unit includes a first connection end and a second connection end; the second connection end of the target scanning unit in the long scan chain serves as the node connection end in the second state of the long scan chain, and is connected to the input end of the XEN-OR gate logic operator; the first connection end of each scanning unit in the short scan chain serves as the node connection end in the first state of the short scan chain; the output end of the XEN-OR gate logic operator is connected to the first connection end of the target scanning unit in the short scan chain.

[0084] In a specific embodiment, the side scan circuit includes four scan chains, namely, long scan chain A, long scan chain B, short scan chain C, and short scan chain D. In these four scan chains, the first connection end of each scan unit serves as the first node connection end of the scan chain, and the second connection end of each scan unit serves as the second node connection end of the scan chain. For example, in long scan chain A, there are first node connection ends A11, A12, A13, ..., and second node connection ends A21, A22, A23, .... Node connection end A11 in long scan chain A is connected to node connection end B11 in long scan chain B, and node connection end A12 in long scan chain A is connected to node connection end B12 in long scan chain B, and so on. Each node connection end in long scan chains A and B is connected according to the above connection relationship. Node connection terminal B21 in long scan chain B is connected to node connection terminal C11 in short scan chain C. Node connection terminal B22 in long scan chain B is connected to node connection terminal C12 in short scan chain C, and so on. Because long scan chain B and short scan chain C are of different lengths, long scan chain B has more scan cells than short scan chain C. Therefore, some scan cells in long scan chain B cannot be connected to scan cells in the short scan chain according to the above method. These scan cells that cannot be connected according to the above method are designated as target scan cells. The second connection terminal of the target scan cell serves as a node connection terminal in the second state and is connected to the first node connection terminal in short scan chain C via an XNOR logic operator. Since short scan chain C and short scan chain D have the same length and the same scan cells, they are connected according to the above method and will not be further described.

[0085] It can be understood that this embodiment uses an XOR gate logic operator as a connection component, which reduces hardware overhead, simplifies wiring, reduces signal delay and interference, improves signal integrity, and thus reduces power consumption compared to a complex XOR gate structure.

[0086] In some embodiments, each scan chain is sorted according to a second preset order, and each scan unit in the scan chain is sorted according to a third preset order; in the second preset order, the previous scan chain is a long scan chain, the next scan chain is a short scan chain, and the second connection ends of the last three scan units sorted according to the third preset order in the previous scan chain are connected to the first connection end of the last scan unit sorted according to the third preset order in the next scan chain through an exclusive-OR gate logic operator, or, in the second preset order, the previous scan chain is a short scan chain, the next scan chain is a long scan chain, and the second connection end of the last scan unit sorted according to the third preset order in the previous scan chain is connected to the first connection ends of the last two scan units sorted according to the third preset order in the next scan chain.

[0087] Preferably, the XEN-NOR logic operator is a three-input XEN-NOR logic operator.

[0088] See Figure 4The side scan circuit of this embodiment includes four scan chains. These four scan chains are arranged from top to bottom in a second preset order, namely, scan chain Chain 20, scan chain Chain 21, scan chain Chain 22, and scan chain Chain 23. Each scan chain includes eight scan units. As shown from left to right in the figure, the input end of the first scan unit serves as the input end of the scan chain, the output end of the previous scan unit is connected to the input end of the next scan unit, and the output end of the last scan unit serves as the output end of the scan chain. Thus, each scan unit is connected in series. Each scan chain includes multiple first node connection ends and multiple second node connection ends. The first connection end of each scan unit serves as the first node connection end, and the second connection end of each scan unit serves as the second node connection end. In particular, scan chains Chain 20, scan chain 21, and scan chain 23 are all long scan chains, while scan chain Chain 22 is a short scan chain. In scan chain Chain21, the second connection ends of the last three scan units (i.e., the third from the left to the right in the second row in the figure) of the scan units connected in series according to the third preset order serve as the node connection ends of scan chain Chain21 in the second state, and are connected to the input end of the three-input XNOR gate logic operator, and the output end of the XNOR gate logic operator is connected to the first connection end of the last scan unit in scan chain Chain22 (i.e., the first from the left to the right in the third row in the figure); the second connection end of the last scan unit in scan chain Chain22 is respectively connected to the first connection ends of the last two scan units in scan chain Chain23 (i.e., the first from the left to the right in the fourth row in the figure), and the first connection ends of the last two scan units in scan chain Chain23 serve as the node connection ends in the second state of scan chain Chain23.

[0089] It can be understood that, in this embodiment, since each scan chain and each scan unit are arranged in sequence, when a part of the scan chain (scan unit) fails, it is easier to locate the location where the failure occurs.

[0090] In some embodiments, each scanning unit includes a single-bit trigger and a connector; the input end of the single-bit trigger is connected to the output end of the connector, and the input end of the single-bit trigger serves as the second connection end of the scanning unit; the input end of the connector serves as the first connection end of the scanning unit.

[0091] See Figure 5 , Figure 5 The invention is a structural diagram of a second side scanning circuit including a single-bit trigger and a connector.

[0092] This application also provides a method for utilizing Figure 5The sideway scan circuit shown in the figure implements a specific embodiment of fault diagnosis. In this embodiment, the sideway scan circuit includes four scan chains, designated scan chain 0, scan chain 1, scan chain 2, scan chain 3, and scan chain 4. Scan chains 0, 1, and 3 each contain eight scan cells, while scan chain 2 contains seven scan cells. Scan_in0, Scan_in1, Scan_in2, and Scan_in3 are the test vectors input to the four scan chains for fault diagnosis, respectively. Scan_en and sideway_tr are the enable and sideway select signals transmitted to each scan cell, respectively. A three-input XNOR logic operator is added to the sideway transmission path from the last three scan cells of long scan chain 1 to the last scan cell of short scan chain 2. To verify the effectiveness of this structure, assume a stuck-at-0 fault occurs in a scan cell of scan chain 1. This location is connected to the inserted three-input XNOR gate. When transmitting from short scan chain 2 to long scan chain 3, the signal from the scan cell of short scan chain 2 can be transmitted to the long-short scan chain 3. Then, the existing method was applied to perform fault diagnosis. The relevant test vectors for each process are shown in Table 2. The relevant derivation shows that (when three intersections occur, it is a marginal fault, in which case only the set of three intersections is sufficient). The results show that all faults can be accurately diagnosed and located.

[0093] Table 2 - Test vector table for the second fault diagnosis case

[0094]

[0095] In some embodiments, the side scan circuit also includes multiple long scan chains; the node connection end of the long scan chain in the second state is also used to connect to the node connection end of the target long scan chain in the second state through a connecting component; the connecting component includes at least one second inverter; each long scan chain includes multiple scanning units connected in series, and each scanning unit includes a first connection end and a second connection end; the second connection end of the target scanning unit in the long scan chain, as the node connection end of the long scan chain in the second state, is connected to the input end of the second inverter; the first connection end of the target scanning unit in the target long scan chain, as the node connection end of the target long scan chain in the second state, is connected to the output end of the second inverter.

[0096] In a specific embodiment, the side scan circuit includes four scan chains, namely, a long scan chain A, a short scan chain B, a short scan chain C, and a long scan chain D. In these four scan chains, the first connection end of each scan unit serves as the first node connection end of the scan chain, and the second connection end of each scan unit serves as the second node connection end of the scan chain. For example, in long scan chain A, there are first node connection ends A11, A12, A13, ..., and second node connection ends A21, A22, A23, .... Node connection end A11 in long scan chain A is connected to node connection end B11 in short scan chain B, and node connection end A12 in long scan chain A is connected to node connection end B12 in short scan chain B, and so on. Each node connection end in long scan chains A and B is connected according to the above connection relationship. Since the length of long scan chain A is longer than that of short scan chain B, Therefore, there must be at least one scanning unit in long scan chain A whose second connection end cannot be connected to the first connection end of a scanning unit in short scan chain B according to the aforementioned connection relationship. The second connection end of the scanning unit in long scan chain A serves as the node connection end of long scan chain A in the second state, and the scanning unit in long scan chain A serves as the target scanning unit of long scan chain A. Similarly, there is at least one scanning unit in long scan chain D whose first connection end cannot be connected to the second connection end of a scanning unit in short scan chain B according to the aforementioned connection relationship. The first connection end of this scanning unit serves as the node connection end of long scan chain D in the second state, and the scanning unit in long scan chain D serves as the target scanning unit of long scan chain D. The second connection end of the target scanning unit in long scan chain A is connected to the first connection end of the target scanning unit in long scan chain D via a second inverter.

[0097] It can be understood that the use of inverters as connecting components in this embodiment reduces hardware overhead, simplifies wiring, reduces signal delay and interference, improves signal integrity, and thus reduces power consumption compared to a complex XOR gate structure.

[0098] In some embodiments, each scan chain is sorted according to a fourth preset order, and each scan unit in the scan chain is sorted according to a fifth preset order; in the fourth preset order, at least one short scan chain is sorted between two long scan chains, and the second connection end of the last scan unit sorted according to the fifth preset order in the previous long scan chain is connected to the first connection end of the last scan unit sorted according to the fifth preset order in the next long scan chain through a second inverter.

[0099] See Figure 6The side scan circuit of this embodiment includes four scan chains. These four scan chains are arranged from top to bottom in a second preset order, namely, scan chain Chain 30, scan chain Chain 31, scan chain Chain 32, and scan chain Chain 33. Each scan chain includes eight scan units. As shown from left to right in the figure, the input end of the first scan unit serves as the input end of the scan chain, the output end of the previous scan unit is connected to the input end of the next scan unit, and the output end of the last scan unit serves as the output end of the scan chain. Thus, each scan unit is connected in series. Each scan chain includes multiple first node connection ends and multiple second node connection ends. The first connection end of each scan unit serves as the first node connection end, and the second connection end of each scan unit serves as the second node connection end. In particular, scan chains Chain 30, scan chain 31, and scan chain 33 are all long scan chains, while scan chain Chain 32 is a short scan chain. In scan chain Chain31, of the scan units connected in series according to the third preset order, the second connection end of the last scan unit (i.e., the first one from the left to the right in the second row in the figure) serves as the node connection end in the second state of scan chain Chain31 and is connected to the input end of the second inverter. The output end of the second inverter is connected to the first connection end of the last scan unit in scan chain Chain33 (i.e., the first one from the left to the right in the fourth row in the figure).

[0100] It can be understood that, in this embodiment, since each scan chain and each scan unit are arranged in sequence, when a part of the scan chain (scan unit) fails, it is easier to locate the location where the failure occurs.

[0101] In some embodiments, each scanning unit includes a single-bit trigger and a connector; the input end of the single-bit trigger is connected to the output end of the connector, and the input end of the single-bit trigger serves as the second connection end of the scanning unit; the input end of the connector serves as the first connection end of the scanning unit.

[0102] See Figure 7 , Figure 7 The present invention is a structural diagram of a third side scanning circuit including a single-bit trigger and a connector.

[0103] This application also provides a method for utilizing Figure 7The sideway scan circuit shown in the figure implements a specific embodiment of fault diagnosis. In this embodiment, the sideway scan circuit includes four scan chains, designated scan chain 0, scan chain 1, scan chain 2, and scan chain 3. Scan chains 0, 1, and 3 each contain eight scan cells, and scan chain 2 contains seven scan cells. Scan_in0, Scan_in1, Scan_in2, and Scan_in3 are test vectors input to the four scan chains for fault diagnosis, respectively. Scan_en and sideway_tr are enable signals and sideway select signals transmitted to each scan cell, respectively. When a signal is transmitted from short scan chain 2 to long scan chain 3, the signal from the scan cell in the short chain can be transmitted to the scan cell in long scan chain 3. When sideway transmission is performed from long scan chain 1 to short scan chain 2, the seven scan cells in long scan chain 1 are connected to the seven scan cells in the short scan chain. The last scan cell in long scan chain 1 skips short scan chain 2 and is connected to the last scan cell in the next long scan chain 3 of equal length via a second inverter. To verify the effectiveness of the proposed structure, assume that a stuck-at 0 fault occurs in the scan cell of scan chain 1, where the scan cell is connected to the inserted inverter.

[0104] When applying the existing fault diagnosis method, some modifications are required. If a fault is detected in long scan chain 1, and the two complementary test vectors transmitted and loaded during the side channel are both normal, the fault can be determined to be in the last scan unit of the long scan chain. The relevant test vectors for each process are shown in Table 3. The results demonstrate that the fault can be accurately diagnosed and located.

[0105] Table 3 - Test vector table for the third fault diagnosis case

[0106]

[0107] Second, see Figure 8 , Figure 8 The present invention is a schematic diagram of the structure of a chip including a side scan circuit based on special scan chain architecture features.

[0108] This embodiment provides a chip including the side scan circuit based on the special scan chain architecture feature of any of the above embodiments.

[0109] It can be understood that the contents of the above circuit embodiments are all applicable to this chip embodiment, the functions specifically implemented by this chip embodiment are the same as those of the above circuit embodiments, and the beneficial effects achieved are also the same as those achieved by the above circuit embodiments.

[0110] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0111] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0112] Although the description of the present application has been quite detailed and specifically describes several embodiments, it is not intended to be limited to any of these details or embodiments or any particular embodiment, but should be considered to provide a broad possible interpretation of these claims by reference to the appended claims, taking into account the prior art, so as to effectively cover the intended scope of the present application. In addition, the above description of the present application is based on the embodiments foreseen by the inventors, which is intended to provide a useful description, and those non-substantial changes to the present application that have not yet been foreseen may still represent equivalent changes to the present application.

Claims

1. A side scan circuit based on a special scan chain architecture, characterized in that: The side scan circuit includes a connection component and a plurality of scan chains; Each of the scan chains includes at least one node connection end in a first state or a second state; the first state is a normal connection state in which the current node connection end has a corresponding connection relationship with another node connection end; the second state is an abnormal connection state in which the current node connection end has no corresponding connection relationship with the other node connection end; The node connection ends of each scan chain in the first state are connected to each other according to a preset connection relationship; The node connection end of each scan chain in the second state is connected to the node connection end of the target scan chain in the first state or the second state through the connection component; The number of scan chains in the side scan circuit is any odd number greater than 1; The connection component includes at least one first inverter; The node connection end of the scan chain in the second state is connected to the node connection end of the target scan chain in the first state through the first inverter.

2. The side scan circuit based on the special scan chain architecture feature according to claim 1, characterized in that: The connection component includes a plurality of first inverters; Each of the scan chains includes a plurality of scan units connected in series, and each of the scan units includes a first connection end and a second connection end; The first connection end of the scanning unit in the scan chain serves as a node connection end of the scan chain in a first state, and the second connection end of the scanning unit in the scan chain serves as a node connection end of the scan chain in a second state; The input end of each first inverter is used to be connected to the second connection end of the target scanning unit, and the output end of each first inverter is used to be connected to the first connection end of the target scanning unit.

3. A side scan circuit based on a special scan chain architecture according to claim 1 or 2, characterized in that: Each of the scan chains includes a first node connection end in a first state or a second state, and a second node connection end in a first state or a second state; Each of the scan chains is sorted according to a first preset order; The first node connection end of the last scan chain in the first preset order, which is in the first state, is connected to the second node connection end of the previous scan chain, which is in the first state; The second node connection end of the last scan chain in the first preset order, which is in the second state, is connected to the input end of the first inverter; The output terminal of the first inverter is connected to the first node connection terminal of the first scan chain in the first preset order which is in the first state.

4. The side scan circuit based on the special scan chain architecture feature according to claim 1, characterized in that: The side scan circuit includes a long scan chain and a short scan chain, wherein the length of the long scan chain is greater than the length of the short scan chain; The long scan chain includes a node connection end in a first state and a node connection end in a second state; Each node connection end in the short scan chain is a node connection end in a first state; The node connection end of the long scan chain in the second state is used to connect to the node connection end of the short scan chain in the first state through the connection component.

5. The side scan circuit based on the special scan chain architecture feature according to claim 4, characterized in that: The connection component includes at least one XEN-NOR gate logic operator; The long scan chain or the short scan chain includes a plurality of scanning units connected in series, and each of the scanning units includes a first connection end and a second connection end; The second connection end of the target scan unit in the long scan chain serves as a node connection end of the long scan chain in the second state and is connected to the input end of the XNOR gate logic operator; The first connection end of each scanning unit in the short scan chain serves as a node connection end of the short scan chain in the first state; The output end of the XNOR logic operator is connected to the first connection end of the target scan unit in the short scan chain.

6. The side scan circuit based on the special scan chain architecture feature according to claim 5, characterized in that: Each of the scan chains is sorted according to a second preset order, and each scan unit in the scan chain is sorted according to a third preset order; In the second preset order, the previous scan chain is a long scan chain, and the next scan chain is a short scan chain, and the second connection ends of the last three scan units in the previous scan chain arranged according to the third preset order are all connected to the first connection end of the last scan unit in the next scan chain arranged according to the third preset order through the XNOR gate logic operator, or, In the second preset order, the previous scan chain is a short scan chain, the next scan chain is a long scan chain, and the second connection end of the last scan unit in the previous scan chain sorted according to the third preset order is connected to the first connection ends of the last two scan units in the next scan chain sorted according to the third preset order.

7. The side scan circuit based on the special scan chain architecture feature according to claim 4, characterized in that: The side scan circuit further includes a plurality of the long scan chains; The node connection end of the long scan chain in the second state is further used to connect to the node connection end of the target long scan chain in the second state through the connection component; The connection component includes at least one second inverter; Each of the long scan chains includes a plurality of scan units connected in series, and each of the scan units includes a first connection end and a second connection end; The second connection terminal of the target scan unit in the long scan chain, serving as a node connection terminal of the long scan chain in the second state, is connected to the input terminal of the second inverter; The first connection end of the target scan unit in the target long scan chain serves as a node connection end of the target long scan chain in the second state and is connected to the output end of the second inverter.

8. The side scan circuit based on the special scan chain architecture feature according to claim 7, characterized in that: Each of the scan chains is sorted according to a fourth preset order, and each scan unit in the scan chain is sorted according to a fifth preset order; In the fourth preset order, at least one short scan chain is arranged between two long scan chains, and the second connection end of the last scan unit in the previous long scan chain arranged according to the fifth preset order is connected to the first connection end of the last scan unit in the next long scan chain arranged according to the fifth preset order through the second inverter.

9. A chip, characterized in that: A side scan circuit based on a special scan chain architecture feature comprising any one of claims 1 to 8.

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