Inductively coupled wireless communication structure and method of making same, semiconductor package structure

Abstract

The present disclosure provides an inductive coupling wireless communication structure, a preparation method thereof and a semiconductor packaging structure. The inductive coupling wireless communication structure comprises a first chip and a plurality of second chips. The first chip comprises a bearing surface. The plurality of second chips are stacked on the bearing surface along a first direction, and the first direction is parallel to the bearing surface. A plurality of first coils are arranged on the first chip, and a plurality of second coils are arranged on each second chip. The plane of the first coil intersects the plane of the second coil. The first coil and the second coil are correspondingly arranged and inductively coupled, so that each second chip and the first chip can realize direct wireless communication. Therefore, the inductive coupling wireless communication structure, the preparation method thereof and the semiconductor packaging structure provided by the present disclosure can ensure the signal strength of the wireless communication between each second chip and the first chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an inductively coupled wireless communication structure, its fabrication method, and a semiconductor packaging structure. Background Technology

[0002] Inductively coupled interconnect is a wireless interconnect technology used in chip stacking packaging. Compared with traditional wired interconnect methods such as through silicon via (TSV) interconnect, micro-bump ball interconnect, and wire bonding interconnect, it has the advantages of low cost, high process compatibility, and high flexibility.

[0003] In related technologies, an inductively coupled wireless communication structure may include a logic chip and multiple memory chips. The multiple memory chips are disposed on the logic chip and are stacked along the thickness direction of the logic chip. A first coil is disposed on the logic chip, and a second coil may be disposed on the memory chip. The first coil and part of the second coil are inductively coupled, thereby realizing wireless communication between the logic chip and the memory chip.

[0004] However, the communication performance of the aforementioned inductively coupled wireless communication structure needs to be improved. Summary of the Invention

[0005] This disclosure provides an inductively coupled wireless communication structure and its fabrication method, as well as a semiconductor packaging structure, which can ensure the signal strength of wireless communication between each second chip and the first chip.

[0006] The embodiments disclosed herein provide the following technical solutions:

[0007] A first aspect of this disclosure provides an inductively coupled wireless communication structure, comprising: a first chip and a plurality of second chips. The first chip includes a carrier surface, and the plurality of second chips are stacked on the carrier surface along a first direction parallel to the carrier surface. The first chip is provided with a plurality of first coils, and each of the second chips is provided with a plurality of second coils. The planes where the first coils are located intersect the planes where the second coils are located, and the first coils and second coils are correspondingly arranged and inductively coupled.

[0008] The inductively coupled wireless communication structure provided in this embodiment may include a first chip and multiple second chips. The first chip may include a carrier surface that can support the multiple second chips. The multiple second chips may be stacked on the carrier surface along a first direction, which may be parallel to the carrier surface. The first chip may have multiple first coils, and each second chip may have multiple second coils. The planes of the first coils intersect with the planes of the second coils. The first and second coils are correspondingly arranged and inductively coupled, enabling direct wireless communication between the second coils on each second chip and the corresponding first coils on the first chip. This results in shorter transmission distances between the second chips and the first chip, thus ensuring the signal strength of the wireless communication between the second chips and the first chip.

[0009] In one possible implementation, the first coil has multiple turns, and there is a center line between the innermost and outermost turns of the first coil; the orthographic projection of the second coil on the bearing surface partially coincides with the center line.

[0010] By making the edges of the second coil and the first coil closer together, the coupling coefficient between the first coil and the second coil can be increased, thereby improving the signal strength of the first coil and the second coil.

[0011] In one possible implementation, the first coil is polygonal, the center line of one side of the first coil is the first center line, and the orthographic projection of the first coil on the bearing surface coincides with the first center line.

[0012] This minimizes the distance between the coupling turns of the second coil and the first coil, maximizes the mutual inductance signal between the first coil and the second coil, and maximizes the signal strength between the first coil and the second coil.

[0013] In one possible implementation, the plane containing the second coil is parallel to the front side of the second chip.

[0014] In one possible implementation, the plane containing the second coil is perpendicular to the front side of the second chip.

[0015] In one possible implementation, the plane containing the first coil and the plane containing the second coil are perpendicular to each other.

[0016] This makes it easier to control the angle between the plane containing the first coil and the plane containing the second coil.

[0017] In one possible implementation, the first coil and each of the second chips are located on the same side of the thickness direction of the first chip.

[0018] This ensures that the first coil and the second chip are not obstructed by the first chip, thereby mitigating the attenuation of the magnetic field lines of the first coil after passing through part of the first chip. In addition, it also helps to shorten the communication distance between the first coil and the second coil and improve the signal strength of the first coil and the second coil.

[0019] A second aspect of this disclosure provides a semiconductor packaging structure employing the inductively coupled wireless communication structure described in the first aspect above.

[0020] The semiconductor packaging structure provided in this disclosure includes an inductively coupled wireless communication structure. This structure includes a first chip and multiple second chips. The first chip includes a carrier surface that can support the multiple second chips. The multiple second chips can be stacked on the carrier surface along a first direction, which can be parallel to the carrier surface. The first chip can have multiple first coils, and each second chip can have multiple second coils. The planes of the first and second coils intersect, and the first and second coils are correspondingly arranged and inductively coupled. This allows direct wireless communication between the second coils on each second chip and the corresponding first coils on the first chip, resulting in shorter transmission distances between the second and first chips and ensuring strong signal strength.

[0021] In one possible implementation, the inductively coupled wireless communication structure has a gap between each pair of adjacent second chips, and an adhesive layer is disposed in the gap.

[0022] The adhesive layer can bond two adjacent second chips together, and in addition, the adhesive layer can electrically isolate two adjacent second chips.

[0023] A third aspect of this disclosure provides a method for fabricating an inductively coupled wireless communication structure, comprising:

[0024] A first chip and a plurality of second chips are provided. The first chip includes a carrier surface. A first dielectric layer is formed on the first chip and the second chips. A plurality of first coils are obtained by mask sputtering on the first dielectric layer of the first chip, and a plurality of second coils are obtained by mask sputtering on the first dielectric layer of the second chips. A second dielectric layer is formed, which covers the first coils and the second coils. Each of the second chips is stacked on the carrier surface along a first direction, which is parallel to the carrier surface. The plane where the first coil is located intersects the plane where the second coil is located, and the first coil and the second coil are correspondingly arranged and inductively coupled.

[0025] The method for fabricating an inductively coupled wireless communication structure provided in this disclosure includes a first chip and multiple second chips. The first chip may include a carrier surface that can support the multiple second chips. The multiple second chips can be stacked on the carrier surface along a first direction, which may be parallel to the carrier surface. The first chip may have multiple first coils, and each second chip may have multiple second coils. The planes of the first coils intersect with the planes of the second coils. The first and second coils are correspondingly arranged and inductively coupled, enabling direct wireless communication between the second coils on each second chip and the corresponding first coils on the first chip. This results in shorter transmission distances between the second chips and the first chip, thus ensuring the signal strength of the wireless communication between the second chips and the first chip.

[0026] The structure of this disclosure, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the inductively coupled wireless communication structure provided in the embodiments of this disclosure;

[0029] Figure 2 This is a schematic diagram of the split structure of the inductively coupled wireless communication structure provided in the embodiments of this disclosure;

[0030] Figure 3 A schematic diagram of the structure of the first chip and the second chip provided in this embodiment of the disclosure, which are inductively coupled through the first coil and the second coil;

[0031] Figure 4 A schematic diagram of a structure in which a first coil and a second coil are perpendicular to each other, provided in an embodiment of this disclosure;

[0032] Figure 5 This is a schematic diagram of a structure provided by an embodiment of the present disclosure, in which a first coil is disposed on a bearing surface and a second coil is disposed on a second side surface;

[0033] Figure 6 A schematic diagram of the structure in which the second coil and the first coil overlap in an embodiment of this disclosure;

[0034] Figure 7 A schematic diagram of a structure in which the innermost or outermost turn of the second coil coincides with the innermost or outermost turn of the first coil, as provided in an embodiment of this disclosure.

[0035] Figure 8 This is a schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure;

[0036] Figure 9 A schematic flowchart illustrating the fabrication method of the inductively coupled wireless communication structure provided in this embodiment of the disclosure;

[0037] Figure 10 This is a schematic diagram of the structure after providing the first chip and / or the second chip according to an embodiment of the present disclosure;

[0038] Figure 11 This is a schematic diagram of the structure after the formation of the first dielectric layer provided in an embodiment of the present disclosure;

[0039] Figure 12 This is a schematic diagram of the structure forming the first coil and / or the second coil provided in an embodiment of the present disclosure;

[0040] Figure 13 This is a schematic diagram of the structure after the formation of the second dielectric layer provided in an embodiment of the present disclosure;

[0041] Figure 14 This is a schematic diagram of the structure after removing a portion of the thickness of the second dielectric layer, as provided in an embodiment of this disclosure.

[0042] Explanation of reference numerals in the attached figures:

[0043] 10: Semiconductor packaging structure; 101: Inductively coupled wireless communication structure;

[0044] 110: First chip; 111: First side surface;

[0045] 112: Bearing surface; 113: Bottom surface;

[0046] 120: Second chip; 122: Second side surface;

[0047] 123: Front; 124: Back;

[0048] 131: First coil; 132: Second coil;

[0049] 140: Gap; 150: Adhesive layer;

[0050] 161: First dielectric layer; 162: Second dielectric layer. Detailed Implementation

[0051] In related technologies, an inductively coupled wireless communication structure may include a logic chip and multiple memory chips. The multiple memory chips may be stacked along the thickness direction of the logic chip. A first coil may be provided on the logic chip, and a second coil may be provided on each memory chip. The second coils of two adjacent memory chips can achieve wireless communication. The logic chip can achieve wireless communication with the memory chip closest to the logic chip through the corresponding first coil and second coil.

[0052] However, apart from the memory chip closest to the logic chip, which can communicate directly with the logic chip, other memory chips need to use the second coil of the memory chip located between them to achieve wireless communication. This results in a greater distance between the second coil of the other memory chip and the first coil of the logic chip, leading to a longer transmission distance for wireless communication between the other memory chip and the logic chip, and consequently, a weaker wireless communication signal between them.

[0053] This disclosure provides an inductively coupled wireless communication structure, its fabrication method, and a semiconductor packaging structure. The inductively coupled wireless communication structure may include a first chip and multiple second chips. The first chip may include a carrier surface, which can be used to support the multiple second chips. The multiple second chips may be stacked on the carrier surface along a first direction, which may be parallel to the carrier surface. The first chip may have multiple first coils, and each second chip may have multiple second coils. The planes of the first coils intersect with the planes of the second coils. The first and second coils are correspondingly arranged and inductively coupled, enabling direct wireless communication between the second coils on each second chip and the corresponding first coils on the first chip. This results in shorter transmission distances for wireless communication between each second chip and the first chip, thereby ensuring the signal strength of wireless communication between each second chip and the first chip.

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0055] The following will combine Figures 1-14 The inductively coupled wireless communication structure 101 provided in the embodiments of this disclosure will be described.

[0056] See Figure 1The first chip 110 may include a first direction X, a second direction Y, and a third direction Z, all of which are different. The first direction X and the second direction Y can be any two different directions parallel to the bearing surface 112, and the third direction Z can be any direction intersecting the bearing surface 112. For example, the first direction X, the second direction Y, and the third direction Z can be perpendicular to each other. For example, the first direction X can be the width direction of the first chip 110, the second direction Y can be the length direction of the first chip 110, and the third direction Z can be the thickness direction of the first chip 110. The length, width, and thickness in the embodiments of this application are merely for descriptive convenience and do not imply any limitation on the dimensions. For example, the width can be greater than, equal to, or less than the length.

[0057] See Figures 1-3 The inductively coupled wireless communication structure 101 provided in this embodiment may include a first chip 110 and a plurality of second chips 120. The first chip 110 may include a bearing surface 112, which may be a surface on the thickness direction (third direction Z) of the first chip 110. The first chip 110 may include a bottom surface 113 facing away from the bearing surface 112, and a first side surface 111 located between the bearing surface 112 and the bottom surface 113. The second chips 120 may include a front surface 123 and a back surface 124 disposed opposite to each other along a first direction X, and a second side surface 122 located between the front surface 123 and the back surface 124. The front surface 123 may be the device surface of the second chip 120, and the front surface 123 and the back surface 124 may be parallel to each other or intersect at an angle.

[0058] For example, multiple second chips 120 can be stacked on the bearing surface 112 along a first direction X, which can be parallel to the bearing surface 112. Stacking multiple second chips 120 along the first direction X allows for a larger number of second chips 120 to be disposed along this direction, while minimizing the area occupied by the multiple second chips 120 on the first chip 110. This improves the integration and storage capacity of the inductively coupled wireless communication structure 101. Furthermore, it avoids compressive forces on each second chip 120 along the thickness direction of the first chip 110, thus providing some protection for each second chip 120. For example, the number of second chips 120 can be two, three, four, or five or more.

[0059] For example, the first chip 110 can be a logic chip, and the second chip 120 can be a memory chip. The logic chip can be configured to wirelessly communicate with multiple memory chips to access data from and store data in the multiple memory chips. The logic chip can be, but is not limited to, a graphics processing unit (GPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a central processing unit (CPU), or other known electronic circuits used as processors. The memory chip can be, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, resistive random access memory, phase-change random access memory, or magnetoresistive non-volatile random access memory. At least one of the parameters such as type and model of any two second chips 120 can be the same or different.

[0060] See Figure 3 and Figure 4 The first chip 110 can be provided with multiple first coils 131, and each second chip 120 can be provided with multiple second coils 132. The first coils 131 and the second coils 132 are arranged in a one-to-one correspondence and are inductively coupled, so that the second coils 132 on each second chip 120 and the corresponding first coils 131 on the first chip 110 can achieve direct wireless communication. This makes the transmission distance of wireless communication between each second chip 120 and the first chip 110 relatively short, thereby ensuring the signal strength of wireless communication between each second chip 120 and the first chip 110.

[0061] In related technologies, a through-silicon via (TSV) technology is required to connect two adjacent second chips 120, resulting in significant process complexity and signal interference. In this embodiment, a TSV connection is not required between two adjacent second chips 120; each second chip 120 and the first chip 110 can communicate wirelessly directly, thereby reducing process complexity and signal interference.

[0062] The position of the first coil 131 on the first chip 110 provided in the embodiments of this disclosure will be described below.

[0063] In some embodiments, the first coil 131 may be located inside the first chip 110, thereby providing protection for the first coil 131.

[0064] In some embodiments, the first coil 131 may be located on the outer surface of the first chip 110, which can reduce the impact of the first coil 131 on the internal wiring layout of the first chip 110 and reduce the fabrication difficulty of the first coil 131. The first coil 131 may be located on at least one of the bearing surface 112, the bottom surface 113, and the first side surface 111.

[0065] For example, the first coil 131 can be located on the bearing surface 112. Both the first coil 131 and each of the second chips 120 are located on the bearing surface 112. This means that the first coil 131 and each of the second chips 120 are located on the same side of the thickness direction of the first chip 110, ensuring that the first coil 131 and the second chip 120 are not obstructed by the first chip 110. This alleviates the attenuation of the magnetic field lines of the first coil 131 after passing through part of the first chip 110. Furthermore, it helps to shorten the communication distance between the first coil 131 and the second coil 132, improving the signal strength of the first coil 131 and the second coil 132. Secondly, the bearing surface 112 has a large area, allowing for the placement of more first coils 131, thereby increasing the number of first coils 131 and improving the communication bandwidth of the first chip 110.

[0066] In some embodiments, a portion of the first coils 131 may be located inside the first chip 110, while another portion of the first coils 131 may be located on the outer surface of the first chip 110.

[0067] The position of the second coil 132 on the second chip 120 provided in the embodiments of this disclosure will be described below.

[0068] In some embodiments, the second coil 132 may be located inside the second chip 120, thereby providing protection for the second coil 132.

[0069] In some embodiments, the second coil 132 can be located on the outer surface of the second chip 120, which can reduce the impact of the second coil 132 on the internal wiring layout of the second chip 120 and reduce the fabrication difficulty of the second coil 132. The second coil 132 can be located on at least one of the front side 123, the back side 124, and the second side side 122. For example, the second coil 132 can be located at the end of the second chip 120 closer to the first chip 110, so that the second coil 132 is closer to the first chip 110, which is beneficial to shorten the communication distance between the first coil 131 and the second coil 132 and improve the signal strength of the first coil 131 and the second coil 132.

[0070] For example, the second coil 132 can be located on the front side 123. Since the front side 123 has a large area, more second coils 132 can be placed there, thereby increasing the number of second coils 132 and improving the communication bandwidth of the second chip 120. Furthermore, the position of the second coil 132 on the front side 123 can be arbitrarily adjusted, thereby arbitrarily adjusting the distance between the second coil 132 and the first chip 110 along the third direction Z, and thus arbitrarily adjusting the distance between the second coil 132 and the first coil 131. The second coil 132 has many possible placement positions, satisfying a wide range of scenarios. Additionally, the distance between the second coil 132 and the first coil 131 can be optimized. When the second coil 132 is located on the front side 123, the plane containing the second coil 132 is parallel to the front side 123 of the second chip 120.

[0071] For example, the second coil 132 can be located on the back side 124, which can improve the communication bandwidth of the second chip 120. In addition, the distance between the second coil 132 and the first coil 131 can be adjusted arbitrarily. The principle is similar to that of the second coil 132 being located on the front side 123, and will not be described again.

[0072] For example, the second coil 132 can be located on the second side surface 122, which can extend along the thickness direction of the first chip 110, thereby allowing the distance between the second coil 132 and the first coil 131 to be adjusted arbitrarily. The principle is similar to that of the second coil 132 located on the front surface 123, and will not be described again. The second side surface 122 can be perpendicular to the front surface 123, and the plane containing the second coil 132 can be parallel to the second side surface 122; that is, the plane containing the second coil 132 can be perpendicular to the front surface 123. The number of second coils 132 on a single second side surface 122 can be one or more.

[0073] It is understandable that when the second coil 132 is located inside the second chip 120, the plane on which the second coil 132 is located can also be parallel, perpendicular or oblique to the front side 123.

[0074] See Figure 3In an embodiment where the first coil 131 is disposed on the bearing surface 112 of the first chip 110, and the second coil 132 is disposed on the front side 123 (or back side 124) of the second chip 120: On the same second chip 120, the second coils 132 can be spaced apart along a second direction Y, which can be parallel to the front side 123. Multiple first coils 131 corresponding to multiple second coils 132 on the same second chip 120 can form a first coil group P, where multiple first coils 131 in the first coil group P can be spaced apart along the second direction Y. There can be multiple first coil groups P, which can be spaced apart along a first direction X, and one first coil group P corresponds to one second chip 120. This configuration allows for a larger number of second coils 132 to be disposed on the front side 123 of the second chip 120, thereby improving the communication bandwidth between the first chip 110 and the second chip 120. In addition, the first coil 131 and the second coil 132 are both located on the same side of the bearing surface. The distance between the first coil 131 and the second coil 132 is relatively close and there are fewer obstructing structures, which is beneficial to improving the signal strength of the first coil 131 and the second coil 132.

[0075] See Figure 5 In an embodiment where the first coil 131 is disposed on the bearing surface 112 of the first chip 110 and the second coil 132 is disposed on the second side surface 122 of the second chip 120: the bearing surface 112 may include an edge region and a middle region located inside the edge region, and the orthographic projection of the plurality of second chips 120 on the bearing surface 112 may all be located in the middle region. At least a portion of the first coil 131 may be disposed on the bearing surface 112 of the edge region. The second coil 132 may be located on at least one of the two second side surfaces 122 of the second chip 120 spaced apart along the second direction Y. This arrangement can reduce the influence of the first coil 131 on the layout of the plurality of second chips 120. In addition, since the first coil 131 and the second coil 132 are both located on the same side of the bearing surface 112, the distance between the first coil 131 and the second coil 132 is relatively small, and there are fewer obstructing structures, which is beneficial to improving the signal strength of the first coil 131 and the second coil 132.

[0076] In some embodiments, both the first coil 131 and the second coil 132 can be planar coils, and the plane containing the first coil 131 can intersect the plane containing the second coil 132. For example, the plane containing the first coil 131 and the plane containing the second coil 132 can be perpendicular to each other, thereby making it easier to control the angle between the planes containing the first coil 131 and the second coil 132. Alternatively, the planes containing the first coil 131 and the second coil 132 can intersect at an angle.

[0077] In some embodiments, see Figure 4The number of turns of the first coil 131 can be multiple, such as 2, 3, 4, 5, 6, or 7 or more.

[0078] In some embodiments, the general shape of the first coil 131 and / or the second coil 132 may be circular, elliptical, polygonal (e.g., rectangular), or other arbitrary shapes. The shape of the first coil 131 and / or the second coil 132 may be the general shape formed by the edges of the first coil 131 and / or the second coil 132.

[0079] This disclosure describes an embodiment where the first coil 131 is a polygon. The polygonal first coil 131 may include multiple sides. Taking a rectangular first coil 131 as an example, the first coil 131 may include four sides, which are located on the four sides of the rectangle. The magnetic field lines generated by the multiple sides of the first coil 131 can at least partially pass through the plane containing the second coil 132, thereby achieving inductive coupling between the first coil 131 and the second coil 132. Figure 4 Q in the diagram represents one of the sides of the first coil 131.

[0080] For example, the orthographic projection of the second chip 120 on the bearing surface 112 partially overlaps with one side of the first coil 131, and may not overlap with the other sides of the first coil 131, thereby reducing the overlap area of ​​the first coil 131 and the second chip 120 along the third direction Z, and reducing the impact of the first coil 131 on the devices within the second chip 120.

[0081] In the corresponding first coil 131 and second coil 132, one of the first coil 131 and the second coil 132 can be a transmitting coil, and the other of the first coil 131 and the second coil 132 can be a receiving coil. Setting the distance between either side of the second coil 132 and the first coil 131 closer can shorten the communication distance between the first coil 131 and the second coil 132, thereby improving the signal strength of the first coil 131 and the second coil 132.

[0082] In some embodiments, the innermost and outermost turns of the first coil 131 may have a center line, and the orthographic projection of the second coil 132 on the bearing surface 112 may be a straight line segment. The orthographic projection of the second coil 132 on the bearing surface 112 may partially coincide with the center line of the first coil 131, thereby making the distance between the edges of the second coil 132 and the first coil 131 closer, thus improving the signal strength of the first coil 131 and the second coil 132.

[0083] For example, the centerline of one side of the first coil 131 can be a first centerline. Multiple sides of the first coil 131 can have multiple first centerlines, which together form the centerline of the first coil 131. The orthographic projection of the second coil 132 onto the bearing surface 112 can at least partially coincide with one of the first centerlines, thereby making the distance between the second coil 132 and one side of the first coil 131 closer, which can improve the signal strength of the first coil 131 and the second coil 132. For instance, the orthographic projection of the second coil 132 onto the bearing surface 112 can coincide with one of the first centerlines, thereby minimizing the distance between the coupling turns of the second coil 132 and the first coil 131, maximizing the mutual inductance signal of the first coil 131 and the second coil 132, and maximizing the signal strength of the first coil 131 and the second coil 132.

[0084] See Figure 6 and Figure 7 Both the first coil 131 and the second coil 132 can have three turns. Figure 6 In the diagram: A1, A2, and A3 are three turns on one side of the second coil 132, and B1, B2, and B3 are three turns on one side of the first coil 131. The orthographic projection of the second coil 132 onto the bearing surface 112 coincides with B2. B2 can be an intermediate turn on one side of the first coil 131, and the centerline of one side of the first coil 131 can coincide with this intermediate turn (B2). This means that the orthographic projection of the second coil 132 onto the bearing surface 112 coincides with the intermediate turn on one side of the first coil 131. Let the distances between A1 and B1, B2, and B3 be A1B1, A1B2, and A1B3, respectively, and the sum of these distances be A1B1 + A1B2 + A1B3. Figure 7 In the diagram: M1, M2, and M3 are three turns on one side of the second coil 132, and N1, N2, and N3 are three turns on one side of the first coil 131. The orthographic projection of the second coil 132 onto the bearing surface 112 coincides with N3. N3 can be either the innermost or outermost turn on one side of the first coil 131. In other words, the orthographic projection of the second coil 132 onto the bearing surface 112 coincides with either the outermost or innermost turn on one side of the first coil 131. The distances between M1 and N1, N2, and N3 are M1N1, M1N2, and M1N3, respectively, and the sum of these distances is M1N1 + M1N2 + M1N3. Where A1B1+A1B2+A1B3<M1N1+M1N2+M1N3, it can be seen that when the center line of the second coil 132 coincides with that of the first coil 131, the distance between each coupling turn of the second coil 132 and the first coil 131 can be minimized, thereby maximizing the mutual inductance signal between the first coil 131 and the second coil 132.

[0085] The semiconductor packaging structure 10 provided in the embodiments of this disclosure will be described below.

[0086] See Figure 1 and Figure 8 The semiconductor package structure 10 may include the inductively coupled wireless communication structure 101 in the above embodiments. In some examples, the semiconductor package structure 10 may include an adhesive layer 150, and there may be a gap 140 between each two adjacent second chips 120. The adhesive layer 150 may be located in the gap 140 to bond each two adjacent second chips 120 together. In addition, the adhesive layer 150 may electrically isolate each two adjacent second chips 120. In other examples, each two adjacent second chips 120 may abut against each other, and the surface of each second chip 120 may be provided with an insulating material to electrically isolate each two adjacent second chips 120. With this arrangement, it is not necessary to control the size of the gap 140 between each two adjacent second chips 120, thereby reducing the difficulty of arranging multiple second chips 120.

[0087] The following describes the fabrication method of the inductively coupled wireless communication structure 101 provided in the embodiments of this disclosure.

[0088] The method for fabricating the inductively coupled wireless communication structure 101 provided in this disclosure can be used to fabricate the inductively coupled wireless communication structure 101 in the above embodiments. See also Figure 9 The preparation method may include:

[0089] S100: Provides a first chip and multiple second chips, the first chip including a carrier surface.

[0090] See Figure 10 A first chip 110 is provided, which can serve as a carrier for a first coil 131. For example, the first coil 131 can be fabricated on the outer surface of the first chip 110. A second chip 120 is provided, which can serve as a carrier for a second coil 132. For example, the second coil 132 can be fabricated on the outer surface of the second chip 120.

[0091] Alternatively, the first chip 110 can be provided first, followed by the second chip 120; or the second chip 120 can be provided first, followed by the first chip 110; or the first chip 110 and the second chip 120 can be provided simultaneously. The first chip 110 may include a bearing surface 112, which may be a surface on one side of the first chip 110 in the thickness direction.

[0092] S200: Forming a first dielectric layer, the first dielectric layer is located on the first chip and the second chip.

[0093] See Figure 11After providing the first chip 110, a first dielectric layer 161 may be deposited on the first chip 110, and the first dielectric layer 161 may be used to isolate the first chip 110 and the first coil 131; after providing the second chip 120, a first dielectric layer 161 may be deposited on the second chip 120, and the first dielectric layer 161 may be used to isolate the second chip 120 and the second coil 132.

[0094] Specifically, the first dielectric layer 161 can be formed on the first chip 110 first, and then on the second chip 120; alternatively, the first dielectric layer 161 can be formed on the second chip 120 first, and then on the first chip 110. Alternatively, the first dielectric layer 161 can be formed simultaneously on both the first chip 110 and the second chip 120. It is understood that the order in which other structural films are formed on the first chip 110 and the second chip 120 in this embodiment is similar in principle to that of the first dielectric layer 161, and will not be described again.

[0095] For example, the deposition process may include atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD).

[0096] S300: Multiple first coils are obtained by mask sputtering on the first dielectric layer of the first chip, and multiple second coils are obtained by mask sputtering on the first dielectric layer of the second chip.

[0097] See Figure 12 After forming the first dielectric layer 161 on the first chip 110, a plurality of first coils 131 may be obtained by mask sputtering on the first dielectric layer 161 of the first chip 110. After forming the first dielectric layer 161 on the second chip 120, a plurality of second coils 132 may be obtained by mask sputtering on the first dielectric layer 161 of the second chip 120.

[0098] S400: Form a second dielectric layer, which covers the first coil and the second coil.

[0099] See Figure 13 After forming the first coil 131 on the first chip 110, a second dielectric layer 162 may be formed on the first coil 131, which may cover the first coil 131. There may be multiple first coils 131, and the second dielectric layer 162 may be used to isolate two adjacent first coils 131 and provide certain support and protection for each first coil 131.

[0100] After forming the second coil 132 on the second chip 120, a second dielectric layer 162 may be formed on the second coil 132, which may cover the second coil 132. There may be multiple second coils 132, and the second dielectric layer 162 may be used to isolate two adjacent second coils 132 and provide certain support and protection for each second coil 132.

[0101] Alternatively, after forming the second dielectric layer 162 on the first coil 131 and / or the second coil 132, the second dielectric layer 162 above the first coil 131 and / or the second coil 132 may be thinned. Optionally, after partially thinning the second dielectric layer 162, the first coil 131 and / or the second coil 132 may not be exposed, thereby protecting the first coil 131 and / or the second coil 132. Alternatively, after partially thinning the second dielectric layer 162, the first coil 131 and / or the second coil 132 may be exposed. The step of exposing the first coil 131 and / or the second coil 132 is as follows:

[0102] See Figure 14 By removing a portion of the thickness of the second dielectric layer 162 along the top surface of the first coil 131, and exposing the top surface of the first coil 131, the impact of the second dielectric layer 162 on the communication capability of the first coil 131 can be mitigated. And / or, by removing a portion of the thickness of the second dielectric layer 162 along the top surface of the second coil 132, and exposing the top surface of the second coil 132, the impact of the second dielectric layer 162 on the communication capability of the second coil 132 can be mitigated.

[0103] For example, a portion of the thickness of the second dielectric layer 162 can be removed by chemical-mechanical planarization (CMP) or etching.

[0104] For example, at least one of the first dielectric layer 161 and the second dielectric layer 162 may be formed of an insulating material such as silicon dioxide or silicon nitride. The materials of the first dielectric layer 161 and the second dielectric layer 162 may be the same or different.

[0105] For example, at least one of the first coil 131 and the second coil 132 may be formed of a conductive material such as copper, silver, gold, or aluminum. The materials of the first coil 131 and the second coil 132 may be the same or different.

[0106] S500: Each second chip is stacked on the bearing surface along the first direction, which is parallel to the bearing surface.

[0107] See Figure 1Multiple second chips 120 are stacked on a bearing surface 112 along a first direction X, which can be parallel to the bearing surface 112. A first coil 131 and a second coil 132 are correspondingly arranged and inductively coupled, enabling direct wireless communication between the second coil 132 on each second chip 120 and the corresponding first coil 131 on the first chip 110. This results in a shorter transmission distance for wireless communication between each second chip 120 and the first chip 110, thus ensuring the signal strength of the wireless communication between them.

[0108] It is understood that any one of the first dielectric layer 161, the first coil 131, and the second dielectric layer 162 on the first chip 110 can be prepared before, after, or simultaneously with any one of the first dielectric layer 161, the second coil 132, and the second dielectric layer 162 on the second chip 120.

[0109] It should be noted that the numerical values ​​and ranges involved in the embodiments of this disclosure are approximate values. Due to the influence of the manufacturing process, there may be a certain range of errors, which can be considered negligible by those skilled in the art.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. An inductive coupling wireless communication structure, comprising: a first chip and a plurality of second chips, the first chip comprising a bearing surface, and the plurality of second chips being stacked along a first direction on the bearing surface, the first direction being parallel to the bearing surface; a plurality of first coils being disposed on the first chip, and a plurality of second coils being disposed on each of the second chips, a plane of the first coils intersecting a plane of the second coils, the first coils and the second coils being correspondingly disposed and inductively coupled; the first coils having a plurality of turns, and the first coils having a center line between an innermost turn and an outermost turn; and a projection of the second coils on the bearing surface partially overlapping the center line.

2. The inductive coupling wireless communication structure of claim 1, wherein: the first coils are polygonal, and a center line of a side of the first coils is a first center line, and a projection of the first coils on the bearing surface overlaps the first center line.

3. The inductive coupling wireless communication structure of any one of claims 1-2, wherein: the plane of the second coils is parallel to a front surface of the second chips.

4. The inductive coupling wireless communication structure of any one of claims 1-2, wherein: the plane of the second coils is perpendicular to a front surface of the second chips.

5. The inductive coupling wireless communication structure of any one of claims 1-2, wherein: the plane of the first coils and the plane of the second coils are perpendicular to each other.

6. The inductive coupling wireless communication structure of any one of claims 1-2, wherein: the first coils and the second chips are on a same side of a thickness direction of the first chip.

7. A semiconductor package structure, comprising: the inductive coupling wireless communication structure of any one of claims 1-6.

8. The semiconductor package structure of claim 7, wherein: a gap is between each of two adjacent second chips of the inductive coupling wireless communication structure, and an adhesive layer is disposed in the gap.

9. A method for manufacturing an inductive coupling wireless communication structure, comprising: providing a first chip and a plurality of second chips, the first chip comprising a bearing surface; forming a first dielectric layer on the first chip and the second chips; sputtering a plurality of first coils on the first dielectric layer of the first chip by masking, and sputtering a plurality of second coils on the first dielectric layer of the second chips by masking; forming a second dielectric layer covering the first coils and the second coils; and stacking the second chips along a first direction on the bearing surface, the first direction being parallel to the bearing surface, wherein the plane of the first coils intersects the plane of the second coils, and the first coils and the second coils are correspondingly disposed and inductively coupled, and wherein the first coils have a plurality of turns, and the first coils have a center line between an innermost turn and an outermost turn. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ A normal projection of the second coil onto the bearing surface coincides with the center line portion.

Images