Device and method for generating fine-grained flexible optical data unit signals based on FPGA

Abstract

The present application discloses a fine-grained flexible optical data unit signal generating device based on FPGA, wherein the cache module caches the client signal; the reference rate generating module includes a first counter and a second counter, and for each counting cycle of the first counter, when the first counter reaches the maximum value, a reference enable signal is generated in response to each count value, and the count value of the second counter is accumulated. When the second counter is full, the second counter is reset to obtain multiple reference enable signals; the frame structure generating module determines the container identification number based on the client signal, selects the reference enable signal identical to the container identification number in the reference enable signal as the channel enable signal, performs counting in response to each channel enable signal, and generates the fgODUflex frame structure; the signal mapping module maps the client signal to the frame structure to obtain the fgODUflex signal. The present application implements a multi-channel and multi-rate fgODUflex signal.

Description

Technical Field

[0001] The present application relates to the technical field of fine-grained optical transmission networks, and in particular to a fine-grained flexible optical data unit signal generation device and method based on FPGA. Background Art

[0002] Fine Grain Optical Transport Network (fgOTN) inherits the advantages of OTN (Optical Transport Network) and SDH (Synchronous Digital Hierarchy) in TDM (Time Division Multiplexing) technology, adopts a fixed time slot allocation design with 10M bandwidth as the unit, uses and optimizes the classic OTN frame structure to efficiently carry small-grain services, supports Ethernet, E1, SDH and other VBR (Variable Bit Rate) and CBR (Fixed Bit Rate) services, and can provide a secure hard isolation solution based on rigid hard pipes for quality connections. fgOTN proposes the fgODUflex flexible container (Fine Grain Optical Data Unit Flex) of P*10M, which provides efficient carrying capacity for multiple services.

[0003] How to map services to implement fgODUflex flexible containers has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The purpose of the present application is to provide a fine-grained flexible optical data unit signal generating device based on FPGA, which can generate fgODU (Fine Grain Optical Data Unit, fine-grained optical data unit) reference rate and realize multi-channel multi-rate fgODUflex (Fine Grain Optical Data Unit Flex, fine-grained flexible optical data unit) signal.

[0005] In a first aspect, the present application provides a fine-grained flexible optical data unit signal generation device based on FPGA, the device comprising:

[0006] A buffer module, used for buffering a received client signal;

[0007] A reference rate generating module, comprising a first counter and a second counter, for triggering the second counter to accumulate count values ​​for each counting cycle of the first counter when the first counter reaches a maximum value, and generating a corresponding reference enable signal in response to each count value of the first counter, and resetting the second counter when the second counter is full, thereby obtaining a plurality of reference enable signals, wherein each count value is defined as an identification number of the reference enable signal;

[0008] a frame structure generation module, configured to determine at least one configured container identification number based on a client signal, the container identification number being bound to the same channel number, selecting a reference enable signal identical to the container identification number from a plurality of reference enable signals, defining the selected reference enable signal as a channel enable signal corresponding to the channel number, performing byte counting in response to each channel enable signal, and generating an fgODUflex frame structure corresponding to the channel number;

[0009] The signal mapping module is used to map the client signal into the fgODUflex frame structure to obtain the fgODUflex signal corresponding to the channel number.

[0010] Furthermore, the reference rate generation module is specifically used for:

[0011] A first maximum value of the first counter in a first counting cycle and a second maximum value in a second counting cycle are set, and a third maximum value of the second counter in a third counting cycle is set, wherein the first maximum value, the second maximum value and the third maximum value are determined based on the system clock frequency and the data bus width of the FPGA, wherein:

[0012] Whenever a clock signal of the system clock arrives, the first counter is triggered to perform counting;

[0013] For each first counting cycle, in response to the count value of the first counter reaching a first maximum value, the count value of the second counter is increased by one, and the first counter is reset;

[0014] In response to the count value of the second counter reaching a count threshold, the count period of the first counter is a second count period, and for each second count period, in response to the count value of the first counter reaching a second maximum value, the count value of the second counter is increased by one, and the first counter is reset, and so on, until the count value of the second counter reaches a third maximum value, and the second counter is reset;

[0015] In each first counting cycle and / or second counting cycle, a corresponding reference enable signal is generated in response to each count value of the first counter, and each count value is indicated as an identification number of the reference enable signal.

[0016] Furthermore, the frame structure generation module includes:

[0017] A first storage unit is used to use each count value generated by the first counter in any counting cycle as a storage address, and store the channel number and the channel valid identifier into a storage space corresponding to each storage address;

[0018] A second storage unit is used to store a configuration table, the configuration table is used to indicate the mapping relationship between the channel number and the payload type;

[0019] a query unit, configured to determine at least one configured container identification number based on the client signal, use each container identification number as a read address of the first storage unit, read the channel number and the channel number valid identification of the corresponding storage space, and query the corresponding payload type in the second storage unit according to the read channel number, the container identification numbers corresponding to the same channel number;

[0020] an enable signal processing unit, configured to select, from the reference enable signals generated by the first counter in each counting cycle, a reference enable signal having the same identification number as the container based on the identification number of each reference enable signal, define the selected reference enable signal as a channel enable signal corresponding to the channel number, obtain all channel enable signals in each counting cycle, and so on, obtain all channel enable signals in M ​​counting cycles, where M is the maximum value of the second counter;

[0021] A frame structure counter is used to respond to each channel enable signal, perform byte cumulative counting based on a preset unit byte number, until the Nth channel enable signal stops counting, and obtain the fgODUflex frame structure corresponding to the channel number based on each acquired byte, wherein N is determined according to the total number of bytes and the number of unit bytes of the fgODUflex standard frame structure.

[0022] Furthermore, the frame structure generation module also includes a payload enabling processing unit, wherein:

[0023] A cache module, used for receiving a client signal, and based on a channel number corresponding to the client signal, storing the client signal in a storage space corresponding to the channel number;

[0024] A payload enable processing unit, configured to trigger a corresponding payload enable signal in response to each payload byte position according to the payload byte position of the payload area in the fgODUflex frame structure, thereby obtaining each payload enable signal in the fgODUflex frame structure;

[0025] The signal mapping module is used to respond to each of the payload enable signals, obtain the client signal from the cache module, write the client signal into the corresponding payload position in the fgODUflex frame structure in sequence, and then obtain the fgODUflex signal corresponding to the channel number.

[0026] Further, the signal mapping module includes a PRBS signal mapping unit, an Ethernet signal mapping unit and a CBR signal mapping unit, wherein:

[0027] The payload enable processing unit is used to input the payload enable signal to the corresponding mapping unit in the signal mapping module according to the payload type corresponding to the channel number, wherein:

[0028] If the payload type is a PRBS service, the payload enable processing unit inputs the payload enable signal to the PRBS signal mapping unit, and the PRBS signal mapping unit performs data mapping processing on the PRBS service;

[0029] If the payload type is an Ethernet service, the payload enable processing unit inputs a payload enable signal to the Ethernet signal mapping unit, and the Ethernet signal mapping unit performs data and overhead mapping processing on the Ethernet service;

[0030] If the payload type is CBR service, the payload enable processing unit inputs the payload enable signal to the CBR signal mapping unit, and the CBR signal mapping unit performs data and overhead mapping processing on the CBR service data, wherein the CBR service data is at least one of the following: CBR service, VC service, E1 service.

[0031] Furthermore, the signal mapping module also includes a PRBS service generation unit, wherein:

[0032] PRBS service generation unit, used to generate PRBS test signals,

[0033] The PRBS signal mapping unit is used to write the PRBS test signal into the corresponding payload position in the fgODUflex frame structure in sequence in response to each payload enable signal, thereby obtaining the fgODUflex signal carrying the PRBS test signal corresponding to the channel number.

[0034] Further, the Ethernet signal mapping unit includes:

[0035] The Ethernet counter is used to count the payload enable signal. In the first counting cycle of the Ethernet counter, in response to the count value 1-32, the corresponding 1st to 32nd Ethernet data enable signals are generated. The 33rd count value does not generate an enable signal, and the Ethernet counter is reset. The next count of the Ethernet counter starts from the 34th payload enable signal, and so on to obtain 32 Ethernet data enable signals in each count.

[0036] The Ethernet encoding subunit is used to read the Ethernet service data from the corresponding storage space in the cache module in sequence according to the 1st to 32nd Ethernet data enable signals generated by the Ethernet counter, perform 64 / 66b encoding on the read Ethernet service data to obtain a 66-code block stream, and insert the 66-code block stream into the corresponding payload position in the fgODUflex frame structure under the triggering of the 1st to 33rd payload enable signals, and so on, insert each 66-code block stream obtained by encoding into the payload position in the fgODUflex frame structure to obtain a first fgODUflex signal that completes payload data mapping;

[0037] The Ethernet FCS and overhead insertion subunit is used to perform CRC check based on the 66-code block stream to obtain the check information, write the check information into the corresponding position of the first fgODUflex signal, obtain the second fgODUflex signal, and insert the pre-generated first overhead byte into the corresponding overhead byte position of the second fgODUflex signal in sequence to obtain the fgODUflex signal carrying Ethernet service corresponding to the channel number.

[0038] Furthermore, the CBR signal mapping unit includes:

[0039] The GMP algorithm subunit is used to obtain each valid payload position of the valid payload area in the fgODUflex frame structure based on the GMP algorithm, and obtain each valid payload enable signal based on each valid payload position and each payload enable signal;

[0040] The overhead payload insertion subunit is used to obtain CBR service data from the cache module based on each valid payload enable signal, insert the CBR service data in the corresponding valid payload position in the fgODUflex frame structure in sequence, and insert the pre-generated second overhead byte into the corresponding overhead byte position in the fgODUflex frame structure, so as to obtain the fgODUflex signal carrying the CBR service data corresponding to the channel number.

[0041] In a second aspect, the present application provides a method for generating a fine-grained flexible optical data unit signal based on FPGA, the method comprising:

[0042] Buffering a received client signal;

[0043] For each counting cycle of the first counter, when the first counter reaches a maximum value, the second counter is triggered to accumulate the count value, and a corresponding reference enable signal is generated in response to each count value of the first counter, and the second counter is reset when the second counter is full, thereby obtaining a plurality of reference enable signals, wherein each count value is defined as an identification number of the reference enable signal;

[0044] Determine at least one configured container identification number based on the client signal, the container identification number is bound to the same channel number, select a reference enable signal identical to the container identification number from a plurality of reference enable signals, define the selected reference enable signal as a channel enable signal corresponding to the channel number, perform byte counting in response to each channel enable signal, and generate an fgODUflex frame structure corresponding to the channel number;

[0045] The client signal is mapped into the fgODUflex frame structure to obtain the fgODUflex signal corresponding to the channel number.

[0046] In a third aspect, the present application provides a communication device, including the FPGA-based fine-grained flexible optical data unit signal generating device as described above.

[0047] The present application obtains multiple reference enable signals through the first counter and the second counter, each reference enable signal can realize the reference rate of the container, and based on each reference enable signal, multiple reference enable signals with the same channel number are counted by bytes to generate corresponding fgODUflex frame structures, and the client signal is mapped to the fgODUflex frame structure, so that the fgODUflex signal corresponding to the channel can be realized, so that multi-channel and multi-rate fgODUflex signals can be flexibly realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A first system structure diagram of a fine-grained flexible optical data unit signal generating device based on FPGA provided in an embodiment of the present application;

[0049] Figure 2 A schematic diagram of a reference enable signal provided in the first embodiment of the present application;

[0050] Figure 3 A second system structure diagram of a fine-grained flexible optical data unit signal generating device based on FPGA provided in an embodiment of the present application;

[0051] Figure 4 A schematic diagram of frame structure counting provided in an embodiment of the present application;

[0052] Figure 5 A schematic diagram of the fgODUflex standard frame structure provided in an embodiment of the present application;

[0053] Figure 6 A schematic diagram of a cache module provided in an embodiment of the present application;

[0054] Figure 7 A schematic diagram of a payload enable signal provided in an embodiment of the present application;

[0055] Figure 8 A third system structure diagram of the fine-grained flexible optical data unit signal generating device based on FPGA provided in an embodiment of the present application;

[0056] Fig. 9 A schematic diagram of a payload enable signal of a PRBS signal provided in an embodiment of the present application;

[0057] Fig.10 A schematic diagram of an Ethernet data enable signal provided in an embodiment of the present application;

[0058] Fig.11A schematic diagram of Ethernet data reading provided in an embodiment of the present application;

[0059] Fig.12 A schematic diagram of the fgODUflex frame structure after being processed by the GMP algorithm provided in an embodiment of the present application;

[0060] Fig.13 A schematic diagram of a valid payload enable signal provided in an embodiment of the present application;

[0061] Fig.14 A schematic diagram of multiple channel signal transmission provided in an embodiment of the present application;

[0062] Fig.15 A schematic diagram of multiple payload enabling signal transmission provided in an embodiment of the present application;

[0063] Fig.16 A schematic diagram of a process of generating a fine-grained flexible optical data unit signal based on FPGA provided in an embodiment of the present application;

[0064] Fig.17 A system block diagram of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] The present application will be described in detail below in conjunction with the specific implementation modes shown in the accompanying drawings, but these implementation modes do not limit the present application. Structural, methodological, or functional changes made by ordinary technicians in the field based on these implementation modes are included in the protection scope of the present application.

[0066] like Figure 1As shown, a fine-grained flexible optical data unit signal generating device based on FPGA is provided in an embodiment of the present application, and the device includes a cache module 11, a reference rate generating module 12, a frame structure generating module 13 and a signal mapping module 14. The cache module 11 is used to cache the received client signal. The reference rate generating module 12 includes a first counter 121 and a second counter 122. For each counting cycle of the first counter 121, when the first counter 121 reaches the maximum value, the second counter 122 is triggered to accumulate the count value, and a corresponding reference enable signal is generated in response to each count value of the first counter 121. When the second counter 122 is full, the second counter 122 is reset, thereby obtaining a plurality of reference enable signals, wherein each count value is defined as an identification number of the reference enable signal. The frame structure generation module 13 determines at least one configured container identification number based on the client signal, the container identification number is bound to the same channel number, selects the reference enable signal identical to the container identification number from multiple reference enable signals, defines the selected reference enable signal as the channel enable signal corresponding to the channel number, performs byte counting in response to each channel enable signal, and generates the fgODUflex frame structure corresponding to the channel number. The signal mapping module 14 maps the client signal to the fgODUflex frame structure to obtain the fgODUflex signal. The reference rate of the standard fgODUflex is 10.409204Mbps. In this embodiment, multiple reference enable signals are obtained by the first counter 121 and the second counter 122, each of which can achieve the reference rate of the container. Based on each reference enable signal, multiple reference enable signals with the same channel number are counted by bytes to generate a corresponding fgODUflex frame structure, which meets the standard fgODUflex frame structure. Based on the acquired fgODUflex frame structure, the client signal is mapped into the fgODUflex frame structure, so that the fgODUflex signal corresponding to the channel can be realized. Since the number of containers selected for each channel is different, each container has the same reference rate, so that the signal rate transmitted by each channel can be different, and different client signals are configured with different channel numbers, so that signal transmission of different channels can be realized. Based on this, this embodiment can realize multi-rate and multi-channel fgODUflex signals based on flexible configuration, and can provide signal mapping containers with different rates for multiple channels for rich client-side signals.

[0067] As an optional implementation, the reference rate generation module 12 is specifically used to: set the first maximum value of the first counter 121 in the first counting cycle, and the second maximum value in the second counting cycle, and set the third maximum value of the second counter 122 in the third counting cycle, the first maximum value, the second maximum value and the third maximum value are determined based on the frequency of the system clock of the FPGA and the data bus bit width, wherein, Whenever the clock signal of the system clock arrives, the first counter 121 is triggered to perform counting; for each first counting cycle, in response to the count value of the first counter 121 reaching the first maximum value, the count value of the second counter 122 is increased by one, and the first counter 121 is reset; in response to the count value of the second counter 122 reaching the counting threshold, the counting cycle of the first counter 121 is the second counting cycle, and for each second counting cycle, in response to the count value of the first counter 121 reaching the second maximum value, the count value of the second counter 122 is increased by one, and the first counter 121 is reset, and so on, until the count value of the second counter 122 reaches the third maximum value, and the second counter 122 is reset; in each first counting cycle and / or second counting cycle, a corresponding reference enable signal is generated in response to each count value of the first counter 121, and each count value indicates an identification number of the reference enable signal. It should be noted that the first counter 121 and the second counter 122 are always counting.

[0068] In this embodiment, the reference rate of the standard fgODUflex is 10.409204Mbps. A counter is usually used to achieve the reference rate. However, in the hardware circuit of the FPGA design, if the counter counts to a decimal part, it will consume huge system resources. Therefore, this application uses decimal compensation to achieve the reference rate, that is, two counters are used to count to achieve the reference rate. The counting cycle and the maximum count value of the two counters are related to the system clock frequency and the system data bus of the FPGA system.

[0069] The implementation of the reference rate is described below with a specific embodiment. If the system clock frequency of the FPGA system is 200M, the clock period is 5ns, and the data bus width of the system is 64 bits, then the bus rate is 200M*64bit=12.8Gbps, and the reference rate is divided by the bus rate. The reference rate is 10.409204Mbps. If the reference rate is to be achieved, 12.8G*1000 / 10.409203≈1229.6911, and a counter of 1229.6911 is required. The decimal part of the counter consumes huge system resources. 0.6911 can be regarded as the result after 6911 / 10000. Based on this, the first counter 121 and the second counter 122 are designed in this embodiment. The first maximum value of the first counter 121 in the first counting cycle is 1230, the second maximum value of the first counter 121 in the second counting cycle is 1229, and the third maximum value of the second counter 122 in the third counting cycle is 10000. The counting threshold is set to 6911. The counting cycle is related to the cycle of the system clock signal. For example, the first counting cycle is 1230*5ns, the second counting cycle is 1229*5ns, and the third counting cycle is 10000*5ns. Specifically, when the clock signal 200M arrives, the first counter 121 is triggered to start counting. For each clock signal, the count value of the first counter 121 is increased by 1. When the count value of the first counter 121 reaches 1230, the first counter 121 is cleared, and the count value of the second counter 122 increases from 0 to 1. Similarly, the first counter 121 and the second counter 122 perform their respective counting. When the count value of the second counter 122 exceeds 6911, the count value of the first counter 121 counts from 0 to 1229, the first counter 121 is cleared, and the count value of the second counter 122 counts from 6911 to 6912, and so on, until the count value of the second counter 122 reaches 10000 and the second counter is cleared. Therefore, from a macroscopic point of view, the total average count value of the second counter 122 in 10000 cycles is (6911*1230+3089*1229) / 10000 = 1229.6911, thus realizing a counter of 1229.6911. Figure 2As shown in the schematic diagram of the reference enable signal, the first counter 121 generates a corresponding reference enable signal each time it is counted in the first counting cycle of the first counter 121, and the count value is defined as the identification number of the reference enable signal. For example, the count value 1 corresponds to the reference enable signal No. 1, and there is a reference enable signal No. 1 in each counting cycle. The rate of each reference enable signal is the reference rate, and the rate corresponding to the signal is 10.409118M. From the perspective of the entire large cycle (10000 in the figure), the macro rate of all the No. 1 reference enable signals combined is 10.409203Mbps, and the frequency deviation between 10.409118M and 10.409203M is 4.8ppm, which meets the tolerance requirement of ±20ppm required by the fgotn protocol specification.

[0070] As an optional implementation, Figure 3 As shown, the frame structure generation module 13 includes a first storage unit 131 , a second storage unit 132 , a query unit 133 , an enable signal processing unit 134 and a frame structure counter 135 .

[0071] The first storage unit 131 uses each count value generated by the first counter 121 in any count cycle as a storage address, and stores the channel number and the channel validity identifier in a storage space corresponding to each storage address.

[0072] Exemplarily, taking the above embodiment as an example, the first counter 121 generates a count value 1-1230 in the first counting cycle, and uses 1-1230 as the storage address of the first storage unit, and stores the channel number and the channel number valid identifier in the storage space corresponding to each storage address. The channel number valid identifier is used to indicate whether the channel number is used, for example, if it is used, the valid identifier is 1, and if it is not used, the valid identifier is 0. For example, using the count values ​​1, 2, 4, 5, 1024 as the storage address, the corresponding channel number is channel number 9, and the valid identifier is 1.

[0073] The second storage unit 132 stores a configuration table, which is used to indicate the mapping relationship between the channel number and the payload type. For example, taking the above example, the payload type corresponding to the channel number 9 is searched in the configuration table. 1, 2, 4, 5, 1024 are bound to the same channel number 9, and the corresponding payload types are also the same, such as Ethernet services. For example, the value of the payload type is a PT value, which is specified by the protocol. A PT value of 2 indicates Ethernet services, and a PT value of 3 indicates CBR services.

[0074] The query unit 133 determines at least one configured container identification number based on the client signal, takes each container identification number as the read address of the first storage unit, reads the channel number and the channel number valid identification of the corresponding storage space, and queries the corresponding payload type in the second storage unit according to the read channel number. The container identification number corresponds to the same channel number.

[0075] According to the received client signal, the container identification number corresponding to the client signal can be determined. It can be understood that, according to the client's demand for the number of containers, the system configures the number of containers required by the client in advance, and configures the corresponding container identification number, and configures the corresponding channel number based on the configured container identification number, so for the received client signal, the required number of containers and the configured container identification numbers can be determined, such as selecting containers with container identification numbers of 1, 2, 4, 5, and 1024, and these 5 containers are bound to the same channel number 9. Therefore, it can be understood that the mapping relationship between the count value and the channel number stored in the first storage unit 131 is pre-configured based on the client's needs.

[0076] Each container identification number is used as the read address of the first storage unit 131, the channel number and the valid identification of the channel number of the corresponding storage space are read, and the corresponding payload type is queried in the second storage unit 132 according to the read channel number, and the container identification number corresponds to the same channel number. Exemplarily, the container identification numbers 1, 2, 4, 5, and 1024 are used as the read addresses, that is, the storage spaces corresponding to the storage addresses 1, 2, 4, 5, and 1024 of the first storage unit 131 are read out as channel number 9, respectively, and the payload type corresponding to channel number 9 is found in the configuration table.

[0077] The enable signal processing unit 134 selects a reference enable signal having the same identification number as the container from among the reference enable signals generated by the first counter 121 in each counting cycle based on the identification number of each reference enable signal, defines the selected reference enable signal as the channel enable signal corresponding to the channel number, and obtains all channel enable signals in each counting cycle, and so on, to obtain all channel enable signals in M ​​counting cycles, where M is the maximum count value of the second counter.

[0078] Exemplarily, the container identification numbers corresponding to the customer signal are 1, 2, 4, 5, and 1024, and the channel number of these five identification numbers read from the first storage unit 131 is 9. The first counter 121 and the second counter 122 are always counting, so the reference enable signal is also always generated. Among the reference enable signals generated by the first counter 121 in the first counting cycle, that is, from the reference enable signals with identification numbers of 1-1230, the reference enable signals with identification numbers of 1, 2, 4, 5, and 1024 are selected, and these reference enable signals are defined as channel enable signals for channel 9. Similarly, in the second counting cycle, the reference enable signals with identification numbers of 1, 2, 4, 5, and 1024 are selected to obtain 5 channel enable signals for channel 9. And so on, 5 channel enable signals for channel 9 within 10,000 counting cycles are obtained. Figure 4 As shown in the schematic diagram of the channel enable signal, it can be seen that channel 9 includes 5 enable signals, the rate of each enable signal is 10.409118 Mbps, and the rate of the fgODUflex frame structure of channel 9 is 10.409118*5 Mbps. It can be seen that based on the different number of containers in the channel number, the rate of the fgODUflex frame structure of each channel number is also different.

[0079] The frame structure counter 15 responds to each channel enable signal, performs byte cumulative counting based on a preset unit byte number, until the Nth channel enable signal stops counting, and obtains the fgODUflex frame structure corresponding to the channel number based on the acquired bytes, where N is determined according to the byte number and unit byte number of the fgODUflex frame structure.

[0080] The standard frame structure of fgODUflex is as follows Figure 5 As shown, it is a 4-line and 3824-byte structure, which includes two main areas: an overhead area and a payload area. Based on the enable signal processing unit 134, the channel enable signal of the corresponding channel number is obtained, and the byte count is performed through the channel enable signal. For each channel enable signal, the byte count is performed, and according to the total number of bytes of the fgODUflex standard frame structure, it can be determined which channel enable signal is counted and the counting can be stopped. Based on this implementation, the generation of the fgODUflex frame structure is realized.

[0081] For example, assuming that each time the channel enable signal is triggered, 8 bytes are counted, that is, 8 bytes are counted each time. Each time the enable signal is triggered, 8 bytes of the fgODUflex frame structure can be generated. Therefore, 4x3824 / 8=1912. Therefore, only 1912 channel enable signals are needed. That is, when the 1912th channel enable signal is recorded, a 4x3824 frame structure can be counted. Figure 4As shown in the figure, the frame structure counting diagram of channel 9 shows that, at each triggering of the channel enable signal of channel 9, 8 bytes are accumulated until the 1912th channel enable signal is triggered, the last 8 bytes are accumulated, and the counting stops to obtain the fgODUflex frame structure of channel 9. It can be understood that the channel enable signal is always triggered, and the counting is repeated from 1 to 1912, so the fgODUflex frame structure can be obtained continuously.

[0082] It is understandable that the fgODUflex frame structure of different rates is the same, which is a 4-line and 3824-byte structure. The difference is that based on the different rates, the number of channel enable signals selected in the same counting cycle is different. Figure 4 As shown in channel 8, one channel enable signal is selected for each counting cycle in channel 8, so the frame structure rate corresponding to channel 8 is 1*10.409203Mbps. Under the triggering of the channel enable signal of channel 8, byte counting is performed to obtain the fgODUflex frame structure of channel 8. It can be seen that although the frame structure rates of the two are different, they both count themselves according to their respective channel enable signals. Therefore, based on this implementation, fgODUflex frame structures of different rates can be obtained. It should be noted that the channel enable signals of each channel can be processed simultaneously, so a multi-channel and multi-rate fgODUflex frame structure can be realized.

[0083] As an optional implementation, Figure 3 As shown, the frame structure generation module 13 also includes a payload enable processing unit 136, wherein the cache module 11 receives the client signal, and based on the channel number corresponding to the client signal, stores the client signal in the storage space corresponding to the channel number. The payload enable processing unit 136 triggers the corresponding payload enable signal in response to each payload byte position according to the payload byte position of the payload area in the fgODUflex frame structure, thereby obtaining each payload enable signal in the fgODUflex frame structure. The signal mapping module 14 obtains the client signal from the corresponding storage space in the cache module 11 in response to each payload enable signal, and writes the client signal into the corresponding payload position in the fgODUflex frame structure in sequence, thereby obtaining the fgODUflex signal.

[0084] The cache module 11 stores the received client signals based on the channel number. As described above, each client signal has a corresponding channel number, so all client signals are stored in the cache module 11, and the client signals are cached based on the cache space corresponding to each channel number. For example, Figure 6The schematic diagram of the cache module 11 shown in FIG. 1 shows, the cache module 11 can be a RAM. A space of 128 addresses is allocated to each channel number. The client signal of channel number 1 is sequentially written into the space corresponding to the cache address 1-128, each time according to 64 bits of data, and the client signal of channel number 2 is sequentially written into the space corresponding to the cache address 129-256, and so on. All client signals share a RAM for caching. When the client signal is taken out from the cache module 11, the data is read out from the corresponding space according to the address 1-128, and each time the data is read, it is also read according to 64 bits.

[0085] like Figure 5 The fgODUflex standard frame structure shown can determine the byte position of the payload area. For example, bytes 1-16 are the overhead byte area, bytes 17-1904 are the payload area, bytes 1905-1920 are the overhead byte area, and bytes 1921-3824 are the payload area. Therefore, based on the byte position of each payload area, during the frame structure counting process, when each byte position of the payload area is counted, an enable signal of the payload area is output, and the client signal can be read from the cache module 11 based on the enable signal. Figure 7 As shown in the payload enable signal diagram, the frame structure counter counts 8 bytes each time, so the 1st and 2nd positions (16 bytes in total) in the fgODUflex frame structure are for placing overhead bytes, so there is no corresponding payload enable signal, and the 3rd to 10th to 238th positions are for placing payload data, so there are corresponding payload enable signals, and the positions 241 to 478 are the payload area, so there are corresponding payload enable signals. Based on these payload enable signals, the client signals in the cache module 11 can be taken out in sequence so as to be placed in the payload area in the frame structure.

[0086] The signal mapping module 14 responds to each payload enable signal and obtains the client signal from the storage space corresponding to the channel number in the cache module 11. For each payload enable signal, the 8-byte data stored at each address in the cache module 11 is read from the cache module 11 according to 8 bytes, and the read data is written to the corresponding payload position in the fgODUflex frame structure, and so on, to obtain the fgODUflex signal with payload data.

[0087] As an optional implementation, Figure 8As shown, the signal mapping module 14 includes a PRBS (Pseudo Random Binary Sequence) signal mapping unit 141, an Ethernet signal mapping unit 142, and a CBR signal mapping unit 143. The payload enable processing unit 136 inputs the payload enable signal to the corresponding mapping unit in the signal mapping module 14 according to the payload type corresponding to the channel number. If the payload type is a PRBS service, the payload enable processing unit 136 inputs the payload enable signal to the PRBS signal mapping unit 141, and the PRBS signal mapping unit 141 performs data mapping processing on the PRBS service. If the payload type is an Ethernet service, the payload enable processing unit 136 inputs the payload enable signal to the Ethernet signal mapping unit 142, and the Ethernet signal mapping unit 142 performs data and overhead mapping processing on the Ethernet service. If the payload type is a CBR service, the payload enable processing unit 136 inputs the payload enable signal to the CBR signal mapping unit 143, and the CBR signal mapping unit 143 performs data and overhead mapping processing on the CBR service, and the CBR service is at least one of the following: CBR service, VC service, and E1 service. The signal mapping module 14 performs corresponding payload processing according to different payload types. The payload type can be at least one of the following: PRBS signal, Ethernet service, and CBR service.

[0088] As an optional implementation, Figure 8 As shown, the PRBS signal mapping unit 141 also includes a PRBS signal generating unit 1411. The PRBS signal generating unit 1411 generates a PRBS test signal. In response to each payload enable signal, the PRBS signal mapping unit 141 writes the PRBS test signal into the corresponding payload position in the fgODUflex frame structure in sequence, thereby obtaining the fgODUflex signal carrying the PRBS test signal. The fgOPUflex end-to-end or segment connection can be tested using the PRBS test signal as a client signal. The PRBS test signal is generated and does not need to be stored in the cache module 11. Therefore, the generated PRBS test signal is directly inserted into the payload position in the frame structure according to an 8-byte write data method under the triggering of each payload enable signal, thereby obtaining the fgODUflex signal carrying the PRBS test signal, as shown in FIG. Fig. 9 Schematic diagram of the payload enable signal of the PRBS signal shown.

[0089] As an optional implementation, Figure 8 As shown, the Ethernet signal mapping unit 142 includes an Ethernet counter 1421 , an Ethernet encoding subunit 1422 , an Ethernet FCS (Frame Check Sequence) and an overhead inserting subunit 1423 .

[0090] The Ethernet data needs to be first 64B / 66B encoded to form a 66B code block stream, and then the 66B code block stream is inserted into the frame structure. The Ethernet data stored in the cache module 11 has not been encoded, and the Ethernet data needs to be taken out from the cache module 11 for 64B / 66B encoding. After the 64-bit data is 64B / 66B encoded, additional data will be generated. The additional data generated by the encoding also needs to be inserted into the payload area of ​​the frame structure. Therefore, the data inserted into the payload area of ​​the frame structure cannot be obtained from the cache module 11. Therefore, this embodiment designs an Ethernet counter 1421.

[0091] The Ethernet counter 1421 counts the payload enable signal. During the counting cycle of the Ethernet counter 1421, when the payload enable signal counts from 1 to 33, the counting stops. In response to the count values ​​1-32, the corresponding 1st to 32nd Ethernet data enable signals are generated. The 33rd count value does not generate an enable signal, and the Ethernet counter 1421 is reset. The next count of the Ethernet counter 1421 starts from the 34th payload enable signal, and so on to obtain 32 Ethernet data enable signals at each count. Fig.10 The schematic diagram of Ethernet data enable signal is shown in FIG. 1 . In this embodiment, an Ethernet counter 1421 with a count value of 33 is used to count the payload enable signal. After the count reaches 33, the counter is reset. Among the 33 count values, the first 32 count values ​​generate 32 Ethernet data enable signals, and the 33rd count value does not generate an enable signal. Because the 64-bit data obtained from the cache module 11 generates redundant 2-bit data after encoding, the 2-bit data is cached, and 64-bit data is generated after 32 cycles, that is, 32 Ethernet data enable signals obtain 64*32-bit data from the cache module 11, and generate 66*32-bit data after encoding, and there is redundant 66*32-64*32=64-bit data. Therefore, the redundant 64-bit data is inserted into the payload area of ​​the frame structure at the 33rd count value.

[0092] The Ethernet encoding subunit 1422 reads the Ethernet service data from the corresponding storage space in the cache module 11 in turn according to the 1st to 32nd Ethernet data enable signals generated by the Ethernet counter, performs 64b / 66b encoding on the read Ethernet service data to obtain a 66-code block stream, and inserts the 66-code block stream into the corresponding payload position in the fgODUflex frame structure under the triggering of the 1st to 33rd payload enable signals, and so on, inserts each 66-code block stream obtained by encoding into the payload position in the fgODUflex frame structure to obtain the first fgODUflex signal that completes the payload data mapping. Fig.11The Ethernet data reading schematic diagram shown in FIG. 1 reads data data1-data32 from the corresponding addresses 1-32 in the cache module 11 based on the 1st to 32nd Ethernet data enable signals. When the count value is 33, no Ethernet data enable signal is generated, so the data cannot be read. Wait until the next counting cycle, that is, counting starts from the 34th payload enable signal, and the first Ethernet data enable signal is generated. Data data33 is read from address 33 of the cache module 11, and so on. Data reading is performed.

[0093] The Ethernet FCS and overhead insertion subunit 1423 performs CRC check (Cyclic Redundancy Check) based on the 66-code block stream to obtain check information, writes the check information into the corresponding position of the frame structure of the first fgODUflex signal, obtains the second fgODUflex signal, and sequentially inserts the pre-generated first overhead byte into the corresponding overhead byte position in the frame structure of the second fgODUflex signal to obtain the fgODUflex signal carrying the Ethernet service. Figure 6 In the standard frame structure of fgODUflex shown in the figure, the overhead bytes are at bytes 1-16 and bytes 1905-1920, and the pre-generated first overhead byte is inserted into the overhead byte position to obtain a complete fgODUflex signal.

[0094] As an optional implementation, the CBR signal mapping unit 143 includes a GMP (Generic Mapping Procedure) algorithm subunit 1431 and an overhead payload insertion subunit 1432. The GMP algorithm subunit 1431 obtains each valid payload position of the valid payload area in the fgODUflex frame structure based on the GMP algorithm, and obtains each valid payload enable signal based on each valid payload position and each payload enable signal. The overhead payload insertion subunit 1432 obtains CBR service data from the corresponding storage space in the cache module 11 based on each valid payload enable signal, inserts the CBR service data into the corresponding valid payload position in the fgODUflex frame structure in sequence, and inserts the pre-generated second overhead byte into the corresponding overhead byte position in the fgODUflex frame structure, thereby obtaining an fgODUflex signal carrying CBR service data.

[0095] For CBR service data, the position of the payload area in the fgODUflex frame structure is calculated based on the GMP algorithm. The principle of the GMP algorithm is as follows: the size of the payload area is fixed, that is, Pserver. The payload area is divided into N small grids, j represents the position number of the small grid, and Cn is an algorithm factor. The remainder is obtained by multiplying the algorithm factor Cn and j and dividing it by Pserver. The remainder is compared with the algorithm factor Cn. If it is less than the algorithm factor Cn, the corresponding grid must be filled with real data. If it is greater than or equal to the algorithm factor Cn, the corresponding grid is an area where no data is placed. The Cn operator is a reference value calculated in advance by a formula. If the rate of the client signal is less than the rate of the fgODUflex container payload area, the GMP algorithm can be used to disperse the client signal into the fgODUflex container so that the client signal is sent evenly. Fig.12 The schematic diagram of the fgODUflex frame structure after the GMP algorithm is shown. The blue grid area in the payload area is the valid payload area, that is, the area where data needs to be placed. For example, Fig.13 The effective payload enable signal diagram shown in FIG. Fig.12 The 17th to 32nd bytes of the blue area are the valid payload area, and the 33rd to 48th bytes are the non-valid payload area. Fig.13 In the figure, the 3rd and 4th payload enable signals are still enabled, that is, they are effective payload enable signals (blue boxes), and data can be inserted into the 3rd and 4th bytes of the effective payload position. The corresponding settings of the 5th and 6th payload enable signals are disabled, that is, there are no payload enable signals (yellow boxes) for the 5th and 6th bytes, and data cannot be inserted into the 5th and 6th bytes of the effective payload position.

[0096] As an optional implementation, the channel number enable signal corresponding to each channel number is transmitted on the first data bus, such as Fig.14 As shown in the schematic diagram of multiple channel signal transmission, the channel number 1 enable signal, the channel number 2 enable signal and the channel number 3 enable signal are aggregated and transmitted on the first data bus, and the channel number enable signals are independent of each other. The payload enable signal corresponding to each channel number is transmitted on the second data bus. Fig.15 As shown in the schematic diagram of transmission of multiple payload enable signals, the payload enable signal of channel 1, the payload enable signal of channel 2 and the payload enable signal of channel 3 are converged on the second data bus for transmission. Each payload enable signal is independent of each other. Although transmitted on one data bus, based on the payload enable signal of each channel number, the corresponding data is read in the cache space corresponding to each channel number in the cache module 11, thereby realizing multi-channel fgODUflex signals at the same time.

[0097] Please refer to Fig.16The present application provides a method for generating fine-grained flexible optical data units based on FPGA, the method comprising the steps of:

[0098] S1601, buffering a received client signal;

[0099] S1602, for each counting cycle of the first counter, when the first counter reaches a maximum value, triggering the second counter to accumulate the count value, and generating a corresponding reference enable signal in response to each count value of the first counter, and resetting the second counter when the second counter is full, thereby obtaining a plurality of reference enable signals, wherein each count value is defined as an identification number of the reference enable signal;

[0100] S1603. Determine at least one configured container identification number based on the client signal, the container identification number is bound to the same channel number, select a reference enable signal identical to the container identification number from multiple reference enable signals, define the selected reference enable signal as a channel enable signal corresponding to the channel number, perform byte counting in response to each channel enable signal, and generate an fgODUflex frame structure corresponding to the channel number;

[0101] S1604: Map the client signal into the fgODUflex frame structure to obtain the fgODUflex signal corresponding to the channel number.

[0102] In this embodiment, by acquiring multiple reference enable signals, each reference enable signal can achieve the reference rate of the container, and based on each reference enable signal, multiple reference enable signals with the same channel number are counted by bytes to generate a corresponding fgODUflex frame structure. Based on the acquired fgODUflex frame structure, the client signal is mapped to the fgODUflex frame structure, so that the fgODUflex signal corresponding to the channel can be achieved. It can be achieved that the signal rate transmitted by each channel is different, and different client signals are configured with different channel numbers, and signal transmission of different channels can be achieved, so that multi-rate and multi-channel fgODUflex signal transmission can be achieved.

[0103] Optionally, the step of generating the reference enable signal includes:

[0104] A first maximum value of the first counter in a first counting cycle and a second maximum value in a second counting cycle are set, and a third maximum value of the second counter in a third counting cycle is set, wherein the first maximum value, the second maximum value and the third maximum value are determined based on the system clock frequency and the data bus width of the FPGA, wherein:

[0105] Whenever a clock signal of the system clock arrives, the first counter is triggered to perform counting;

[0106] For each first counting cycle, in response to the count value of the first counter reaching a first maximum value, the count value of the second counter is increased by one, and the first counter is reset;

[0107] In response to the count value of the second counter reaching a count threshold, the count period of the first counter is a second count period, and for each second count period, in response to the count value of the first counter reaching a second maximum value, the count value of the second counter is increased by one, and the first counter is reset, and so on, until the count value of the second counter reaches a third maximum value, and the second counter is reset;

[0108] In each first counting cycle and / or second counting cycle, a corresponding reference enable signal is generated in response to each count value of the first counter, and each count value is indicated as an identification number of the reference enable signal.

[0109] Optionally, the steps of generating the fgODUflex frame structure include:

[0110] Using each count value generated by the first counter in any count cycle as a storage address of the first storage unit, storing the channel number and the channel valid identifier in a storage space corresponding to each storage address;

[0111] A configuration table is stored in the second storage unit, the configuration table is used to indicate the mapping relationship between the channel number and the payload type;

[0112] Determine at least one configured container identification number based on the client signal, use each container identification number as a read address of the first storage unit, read the channel number and the channel number valid identification of the corresponding storage space, and query the corresponding payload type in the second storage unit according to the read channel number, the container identification numbers correspond to the same channel number;

[0113] Among the reference enable signals generated by the first counter in each counting cycle, based on the identification number of each reference enable signal, a reference enable signal having the same identification number as the container is selected, the selected reference enable signal is defined as a channel enable signal corresponding to the channel number, and all channel enable signals in each counting cycle are obtained, and so on, all channel enable signals in M ​​counting cycles are obtained, where M is the maximum value of the second counter;

[0114] In response to each channel enable signal, byte cumulative counting is performed based on a preset unit byte number until the Nth channel enable signal stops counting, and the fgODUflex frame structure corresponding to the channel number is obtained based on the acquired bytes, where N is determined according to the total number of bytes and the unit byte number of the fgODUflex standard frame structure.

[0115] Optionally, the steps of generating the fgODUflex frame structure include:

[0116] Based on the channel number corresponding to the client signal, storing the client signal in a storage space corresponding to the channel number;

[0117] According to the payload byte position of the payload area in the fgODUflex frame structure, in response to each payload byte position, triggering a corresponding payload enable signal, thereby obtaining each payload enable signal in the fgODUflex frame structure;

[0118] In response to each payload enable signal, the client signal is obtained from the cache module, and the client signal is sequentially written into the corresponding payload position in the fgODUflex frame structure, thereby obtaining the fgODUflex signal corresponding to the channel number.

[0119] Optionally, the method further includes:

[0120] Get the payload type corresponding to the channel number;

[0121] If the payload type is a PRBS service, data mapping processing is performed on the PRBS service based on the payload enable signal;

[0122] If the payload type is an Ethernet service, performing data and overhead mapping processing on the Ethernet service based on the payload enable signal;

[0123] If the payload type is a CBR service, data and overhead mapping processing is performed on the CBR service based on the payload enable signal.

[0124] Optionally, the step of performing data mapping processing on the PRBS service based on the payload enable signal includes:

[0125] Generate PRBS test signal,

[0126] In response to each payload enable signal, the PRBS test signal is sequentially written into the corresponding payload position in the fgODUflex frame structure, thereby obtaining the fgODUflex signal carrying the PRBS test signal corresponding to the channel number.

[0127] Optionally, the step of performing data and overhead mapping on the Ethernet service based on the payload enable signal includes:

[0128] Counting the payload enable signal, generating corresponding 1st to 32nd Ethernet data enable signals in response to the count value 1-32 in the first counting cycle of the Ethernet counter, generating no enable signal for the 33rd count value, resetting the Ethernet counter, and starting the next count of the Ethernet counter from the 34th payload enable signal, and so on to obtain 32 Ethernet data enable signals for each count;

[0129] According to the 1st to 32nd Ethernet data enable signals generated by the Ethernet counter, the Ethernet service data is read from the corresponding storage space in the cache module in sequence, the read Ethernet service data is 64 / 66b-encoded to obtain a 66-code block stream, and the 66-code block stream is inserted into the corresponding payload position in the fgODUflex frame structure under the triggering of the 1st to 33rd payload enable signals, and so on, each 66-code block stream obtained by encoding is inserted into the payload position in the fgODUflex frame structure to obtain the first fgODUflex signal that completes the payload data mapping;

[0130] A CRC check is performed based on the 66-code block stream to obtain check information, and the check information is written into the corresponding position of the first fgODUflex signal to obtain the second fgODUflex signal. The pre-generated first overhead byte is sequentially inserted into the corresponding overhead byte position of the second fgODUflex signal to obtain the fgODUflex signal carrying Ethernet service corresponding to the channel number.

[0131] Optionally, the step of performing data and overhead mapping processing on the CBR service based on the payload enable signal includes:

[0132] Obtain each valid payload position in the valid payload area of ​​the fgODUflex frame structure based on the GMP algorithm, and obtain each valid payload enable signal based on each valid payload position and each payload enable signal;

[0133] Based on each valid payload enable signal, CBR service data is obtained from the cache module, the CBR service data is sequentially inserted into the corresponding valid payload position in the fgODUflex frame structure, and the pre-generated second overhead byte is inserted into the corresponding overhead byte position in the fgODUflex frame structure, so as to obtain the fgODUflex signal carrying the CBR signal corresponding to the channel number, and the CBR service data is at least one of the following: CBR service data, VC service data, and E1 service data.

[0134] The embodiment of the present application further provides a communication device, which includes the above-mentioned fine-grained flexible optical data unit signal generating device based on FPGA, for example, the network device includes Figure 1 The FPGA-based fine-grained flexible optical data unit signal generation device shown. The communication device can be any communication device used for service forwarding in a communication network.

[0135] As an example, see Fig.17, which shows a schematic diagram of the structure of a communication device provided by an embodiment of the present application. The network device includes a fine-grained flexible optical data unit signal generating device 1701 based on FPGA, a communication interface 1702, a processor 1703, a memory 1704 and a bus 1705. The processor 1703, the memory 1704, the communication interface 1702 and the fine-grained flexible optical data unit signal generating device 1701 based on FPGA are connected to each other through the bus 1705. Among them, Fig.17 The connection method between the processor 1703, memory 1704, communication interface 1702 and FPGA-based fine-grained flexible optical data unit signal generating device 1701 shown is merely exemplary. During implementation, the processor 1703, memory 1704, communication interface 1702 and FPGA-based fine-grained flexible optical data unit signal generating device 1701 may also be connected to each other in communication with each other using other connection methods besides the bus 1705.

[0136] The memory 1704 may be used to store computer programs, which may include instructions and data. In an embodiment of the present application, the memory 1704 may be various types of storage media, such as random access memory (RAM), static random access memory (SRAM), non-volatile RAM (NVRAM), DDR (Double Data Rate SDRAM), etc. The memory 1704 may include a hard disk and / or a memory.

[0137] The processor 1703 may be a general-purpose processor, which may be a processor that performs specific steps and / or operations by reading and executing a computer program stored in a memory (e.g., memory 1704), and the general-purpose processor is used to process the signal output by the fine-grained flexible optical data unit signal generating device 1701. The general-purpose processor may be, for example, but not limited to, a central processing unit (CPU). In addition, the processor 1703 may also be a dedicated processor, which may be a processor specially designed to perform specific steps and / or operations, and the dedicated processor may be, for example, but not limited to, an ASIC and an FPGA, etc. In addition, the processor 1703 may also be a combination of multiple processors, such as a multi-core processor.

[0138] The communication interface 1702 may include an input / output (I / O) interface, a physical interface, and a logical interface, etc., which are used to interconnect devices within the network device, and an interface for interconnecting the network device with other devices (such as network devices). The physical interface may be a Gigabit Ethernet interface (GE), which may be used to interconnect the network device with other devices, and the logical interface is an interface within the network device, which may be used to interconnect devices within the network device. It is easy to understand that the communication interface 1702 may be used for the network device to communicate with other devices, for example, the communication interface 1702 is used to send and receive messages between the network device and other devices.

[0139] The bus 1705 may be any type of communication bus for interconnecting the processor 1703 , the memory 1704 , the communication interface 1702 , and the FPGA-based fine-grained flexible optical data unit signal generating device 1701 , such as a system bus.

[0140] The structure of the FPGA-based fine-grained flexible optical data unit signal generating device 1701 can be referred to Figure 1 The illustrated embodiments are not described in detail here. The interconnection between any device among the processor 1703, the memory 1704 and the communication interface 1702 and the fine-grained flexible optical data unit signal generating device 1701 based on FPGA may specifically refer to the interconnection between any device and the device in the fine-grained flexible optical data unit signal generating device 1701 based on FPGA. In some embodiments, the above-mentioned processor 1703, the memory 1704 and the communication interface 1702 may all be integrated on the fine-grained flexible optical data unit signal generating device 1701 based on FPGA, or the above-mentioned processor 1703, the memory 1704 and the communication interface 1702 may be respectively arranged on independent chips from each other, or may be at least partially or completely arranged on the same chip. Whether each device is independently arranged on different chips or integrated on one or more chips often depends on the needs of product design. This application does not limit the specific implementation form of the above-mentioned devices.

[0141] Fig.17 The communication device shown is merely exemplary. During implementation, the communication device may further include other components, which are not listed one by one in this article.

[0142] The embodiments disclosed in the present application also provide a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is executed on a computer, the computer executes the FPGA-based fine-grained flexible optical data unit signal generation method described in any of the above embodiments.

[0143] Although the preferred embodiments of the present application have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the application as disclosed in the accompanying claims.

Claims

1. A fine-grained flexible optical data unit signal generation device based on FPGA, characterized in that: The device comprises: A buffer module, used for buffering a received client signal; A reference rate generating module, comprising a first counter and a second counter, for triggering the second counter to accumulate count values ​​for each counting cycle of the first counter when the first counter reaches a maximum value, and generating a corresponding reference enable signal in response to each count value of the first counter, and resetting the second counter when the second counter is full, so as to obtain a plurality of reference enable signals, wherein each count value is defined as an identification number of the reference enable signal; a frame structure generating module, configured to determine at least one configured container identification number based on the client signal, the container identification number being bound to the same channel number, selecting a reference enable signal identical to the container identification number from the multiple reference enable signals, defining the selected reference enable signal as a channel enable signal corresponding to the channel number, performing byte counting in response to each channel enable signal, and generating an fgODUflex frame structure corresponding to the channel number; The signal mapping module is used to map the client signal into the fgODUflex frame structure to obtain the fgODUflex signal corresponding to the channel number.

2. The device according to claim 1, characterized in that The reference rate generation module is specifically used for: A first maximum value of the first counter in a first counting cycle and a second maximum value in a second counting cycle are set, and a third maximum value of the second counter in a third counting cycle is set, wherein the first maximum value, the second maximum value and the third maximum value are determined based on the system clock frequency and the data bus width of the FPGA, wherein: Whenever a clock signal of the system clock arrives, the first counter is triggered to perform counting; For each of the first counting cycles, in response to the count value of the first counter reaching a first maximum value, the count value of the second counter is increased by one, and the first counter is reset; In response to the count value of the second counter reaching a count threshold, the count period of the first counter is a second count period, and for each of the second count periods, in response to the count value of the first counter reaching a second maximum value, the count value of the second counter is increased by one, and the first counter is reset, and so on, until the count value of the second counter reaches a third maximum value, and the second counter is reset; In each first counting cycle and / or second counting cycle, a corresponding reference enable signal is generated in response to each count value of the first counter, and each count value indicates an identification number of the reference enable signal.

3. The device according to claim 1, characterized in that The frame structure generation module comprises: A first storage unit, used to use each count value generated by the first counter in any counting cycle as a storage address, and store the channel number and the channel valid identifier into a storage space corresponding to each storage address; A second storage unit, used to store a configuration table, wherein the configuration table is used to indicate a mapping relationship between a channel number and a payload type; a query unit, configured to determine at least one configured container identification number based on the client signal, use each of the container identification numbers as a read address of the first storage unit, read a channel number and a channel number valid identifier of a corresponding storage space, and query a corresponding payload type in the second storage unit according to the read channel number, wherein the container identification numbers correspond to the same channel number; an enable signal processing unit, configured to select, from the reference enable signals generated by the first counter in each counting cycle, a reference enable signal having the same identification number as the container, based on the identification number of each reference enable signal, define the selected reference enable signal as a channel enable signal corresponding to the channel number, obtain all channel enable signals in each counting cycle, and so on, obtain all channel enable signals in M ​​counting cycles, where M is the maximum value of the second counter; A frame structure counter is used to respond to each channel enable signal, perform byte cumulative counting based on a preset unit byte number, until the Nth channel enable signal stops counting, and obtain the fgODUflex frame structure corresponding to the channel number based on the acquired bytes, wherein N is determined according to the total number of bytes of the fgODUflex standard frame structure and the unit byte number.

4. The device according to claim 3, characterized in that The frame structure generation module also includes a payload enabling processing unit, wherein: The cache module is used to receive a client signal and store the client signal in a storage space corresponding to the channel number based on the channel number corresponding to the client signal; The payload enable processing unit is used to trigger a corresponding payload enable signal in response to each payload byte position according to the payload byte position of the payload area in the fgODUflex frame structure, thereby obtaining each payload enable signal in the fgODUflex frame structure; The signal mapping module is used to respond to each of the payload enable signals, obtain the client signal from the cache module, write the client signal into the corresponding payload position in the fgODUflex frame structure in sequence, and then obtain the fgODUflex signal corresponding to the channel number.

5. The device according to claim 4, characterized in that The signal mapping module includes a PRBS signal mapping unit, an Ethernet signal mapping unit and a CBR signal mapping unit, wherein: The payload enable processing unit is used to input the payload enable signal into the corresponding mapping unit in the signal mapping module according to the payload type corresponding to the channel number, wherein: If the payload type is a PRBS service, the payload enable processing unit inputs the payload enable signal to the PRBS signal mapping unit, and the PRBS signal mapping unit performs data mapping processing on the PRBS service; If the payload type is an Ethernet service, the payload enable processing unit inputs the payload enable signal to the Ethernet signal mapping unit, and the Ethernet signal mapping unit performs data and overhead mapping processing on the Ethernet service; If the payload type is CBR service, the payload enable processing unit inputs the payload enable signal to the CBR signal mapping unit, and the CBR signal mapping unit performs data and overhead mapping processing on the CBR service data, wherein the CBR service is at least one of the following: CBR service, VC service, E1 service.

6. The device according to claim 5, characterized in that The signal mapping module also includes a PRBS service generation unit, wherein: The PRBS service generating unit is used to generate a PRBS test signal; The PRBS signal mapping unit is used to write the PRBS test signal into the corresponding payload position in the fgODUflex frame structure in sequence in response to each payload enable signal, so as to obtain the fgODUflex signal carrying the PRBS test signal corresponding to the channel number.

7. The method according to claim 5, characterized in that: The Ethernet signal mapping unit comprises: An Ethernet counter is used to count the payload enable signal. In a first counting cycle of the Ethernet counter, in response to the count value 1-32, the corresponding 1st to 32nd Ethernet data enable signals are generated. The 33rd count value does not generate an enable signal, and the Ethernet counter is reset. The next count of the Ethernet counter starts from the 34th payload enable signal, and so on to obtain 32 Ethernet data enable signals in each count. an Ethernet encoding subunit, configured to read Ethernet service data from the corresponding storage space in the cache module in sequence according to the 1st to 32nd Ethernet data enable signals generated by the Ethernet counter, perform 64 / 66b encoding on the read Ethernet service data to obtain a 66-code block stream, and insert the 66-code block stream into the corresponding payload position in the fgODUflex frame structure under the triggering of the 1st to 33rd payload enable signals, and so on, insert each 66-code block stream obtained by encoding into the payload position in the fgODUflex frame structure to obtain a first fgODUflex signal that completes payload data mapping; The Ethernet FCS and overhead insertion subunit is used to perform CRC check based on the 66-code block stream to obtain check information, write the check information into the corresponding position of the first fgODUflex signal, obtain the second fgODUflex signal, and insert the pre-generated first overhead bytes into the corresponding overhead byte positions of the second fgODUflex signal in sequence to obtain the fgODUflex signal carrying Ethernet service corresponding to the channel number.

8. The device according to claim 5, characterized in that The CBR signal mapping unit comprises: The GMP algorithm subunit is used to obtain each valid payload position of the valid payload area in the fgODUflex frame structure based on the GMP algorithm, and obtain each valid payload enable signal based on each valid payload position and each payload enable signal; The overhead payload insertion subunit is used to obtain CBR service data from the cache module based on each valid payload enable signal, insert the CBR service data in sequence into the corresponding valid payload position in the fgODUflex frame structure, and insert the pre-generated second overhead byte into the corresponding overhead byte position in the fgODUflex frame structure, so as to obtain the fgODUflex signal carrying the CBR service data corresponding to the channel number.

9. A method for generating fine-grained flexible optical data unit signals based on FPGA, characterized in that: The method comprises: Buffering a received client signal; For each counting cycle of the first counter, when the first counter reaches a maximum value, the second counter is triggered to accumulate the count value, and a corresponding reference enable signal is generated in response to each count value of the first counter, and the second counter is reset when the second counter is full, so as to obtain a plurality of reference enable signals, wherein each count value is defined as an identification number of the reference enable signal; determining at least one configured container identification number based on the client signal, the container identification number being bound to the same channel number, selecting a reference enable signal identical to the container identification number from the multiple reference enable signals, defining the selected reference enable signal as a channel enable signal corresponding to the channel number, performing byte counting in response to each channel enable signal, and generating an fgODUflex frame structure corresponding to the channel number; The client signal is mapped into the fgODUflex frame structure to obtain the fgODUflex signal corresponding to the channel number.

10. A communication device, characterized in that: It comprises a fine-grained flexible optical data unit signal generating device based on FPGA as described in any one of claims 1-8.

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