A low quiescent current LDO with overshoot suppression

Abstract

The present invention proposes a low quiescent current LDO with overshoot suppression, comprising: a first part, a second part, a third part and a suppression network, wherein the first part comprises an error amplifier EA; the second part comprises: a MOS tube M5 and a MOS tube M4 connected in series; the third part comprises: a power tube M P and voltage divider feedback network; the suppression network includes: a second current source I REF2 , MOS tube M9, MOS tube M 10 、MOS tube M 11 , coupling capacitor C1. The present invention connects the upper plate of coupling capacitor C1 to the newly created voltage node V N When the load current suddenly decreases and overshoot occurs, V N The potential jumps rapidly from the ground potential to a certain potential and rises to V DD ,Since the upper plate voltage of C1 will have a larger voltage mutation, a larger discharge current can be obtained, thereby accelerating the overshoot recovery.

Description

Technical Field

[0001] The invention belongs to the technical field of linear voltage regulator circuits, and in particular relates to a low quiescent current LDO with overshoot suppression. Background Art

[0002] A sudden decrease in an LDO's load current causes a brief overshoot in the LDO's output voltage. It's generally desirable to minimize the overshoot voltage and minimize its duration (so that the overshoot recovers as quickly as possible). The duration of this overshoot is directly related to the discharge current on the LDO's output capacitor: the smaller the discharge current, the longer the overshoot duration. To maintain an extremely low quiescent current, the voltage divider feedback network in a low-quiescent-current LDO draws an extremely low quiescent current (tens or hundreds of nA). This results in a prolonged overshoot when the LDO switches from a heavy load current to near-zero load current.

[0003] At present, some engineers and scholars have proposed overshoot suppression circuits to address this situation. This circuit can detect the occurrence of overshoot and temporarily provide current to discharge the capacitor at the output of the LDO, thereby reducing the duration of overshoot without increasing static power consumption. However, these circuits require a capacitor to be connected to the power MOS tube (power tube M P ) gate to detect overshoot, which slows down the LDO’s response and negatively impacts key performance parameters such as PSR. Summary of the Invention

[0004] The present invention aims to provide a low quiescent current LDO with overshoot suppression, specifically an overshoot suppression circuit therein, which solves the problem of slow recovery of the LDO overshoot voltage when the load current jumps from heavy load to near zero load current. The technical solution adopted is as follows:

[0005] A low quiescent current LDO with overshoot suppression includes: a first part, a second part, a third part and a suppression network, one end of which is connected to a power supply voltage VDD and the other end is grounded;

[0006] The first part is used for the power tube M P Provides G-pole voltage bias, which includes an error amplifier EA; the second part includes: a MOS tube M5 and a MOS tube M4 connected in series; the third part includes: a power tube M P and voltage divider feedback network;

[0007] The error amplifier EA has its inverting input connected to the reference voltage V REF The non-inverting input terminal is connected to the feedback voltage signal V output by the voltage divider feedback network. FB Its output end is connected to the G pole of MOS tube M5 and the power tube M P The G pole;

[0008] The S pole of the MOS tube M5 and the power tube M P The S poles are connected to the power supply voltage VDD;

[0009] The D-pole of the MOS tube M5 is connected to the D-pole of the MOS tube M4, and the D-pole of M4 is connected to the G-pole of M4. The G-pole of the MOS tube M4 leads to the bias voltage signal V M The dynamic tail current source and suppression network to the error amplifier EA; the S pole of the MOS tube M4 is grounded;

[0010] The voltage divider feedback network has one end connected to the power tube M P The other end of the D pole is grounded, which leads to the feedback voltage signal V FB To the non-inverting input of the error amplifier EA;

[0011] Output voltage signal V OUT Self-power tube M P The D pole is connected to the load resistor R L The first end of the output capacitor C L The first end and MOS tube M 10 The D pole, load resistance R L The second end of the output capacitor C L The second end and MOS tube M 10 The S poles of the MOS tubes M are grounded; 10 It is an NMOS tube;

[0012] The suppression network includes: a second current source I REF2 、MOS tube M 11 , coupling capacitor C1 and MOS tube M9, the MOS tube M 10 ;

[0013] The second current source I REF2 One end is connected to MOS tube M 11 D pole, MOS tube M 11 The G pole receives the bias voltage signal V M , MOS tube M 11 The S pole is grounded, and the second current source I REF2 The other end is connected to the power supply voltage VDD;

[0014] Voltage signal V N From the second current source I REF2 and MOS tube M 11 The connection point N is led to the upper plate of the coupling capacitor C1, and the lower plate of the coupling capacitor C1 is connected to the MOS tube M 10 The G pole of the MOS tube M9 and the D pole of the MOS tube M9; the S pole of the MOS tube M9 is grounded, and the G pole of the MOS tube M9 is connected to its D pole.

[0015] Preferably, the width-to-length ratio of the MOS tube M5 is P 1 / K, K=40.

[0016] Preferably, the second current source I REF2 The limit is 100nA.

[0017] Preferably, the first part further includes: a first current source I REF1 , MOS tube M1 and MOS tube M2;

[0018] The MOS tube M2 is the static tail current source of the error amplifier EA;

[0019] The dynamic tail current source of the error amplifier EA is the MOS tube M3;

[0020] The S pole of the MOS tube M3 and the S pole of the MOS tube M2 are both grounded, the D pole of the MOS tube M3 is connected to the D pole of the MOS tube M2; the G pole of the MOS tube M3 is connected to the G pole of the MOS tube M4 to receive the bias voltage signal V M ;

[0021] One end of the error amplifier EA is connected to the D-pole of the MOS tube M3, and the other end is connected to the power supply voltage VDD;

[0022] The G pole of the MOS tube M1 is connected to its D pole, and its S pole is grounded. The G pole of the MOS tube M1 is connected to the G pole of the MOS tube M2; the D pole of the MOS tube M1 is connected to the first current source I REF1 ; The first current source I REF1 Connect the power supply voltage VDD.

[0023] Preferably, the first current source I REF1 The limit is 100nA.

[0024] Preferably, the voltage divider feedback network includes: MOS transistor M6, MOS transistor M7 and MOS transistor M8;

[0025] The G pole of the MOS tube M6 is connected to its D pole, the G pole of the MOS tube M7 is connected to its D pole, and the G pole of the MOS tube M8 is connected to its D pole;

[0026] The D pole of the MOS tube M6 is connected to the power tube M P The D pole of the MOS tube M7 is connected to the S pole of the MOS tube M6, the D pole of the MOS tube M8 is connected to the S pole of the MOS tube M7, and the S pole of the M8 is grounded;

[0027] Feedback voltage signal V FBIt is drawn out from the D-pole of the MOS tube M7 and connected to the non-inverting input terminal of the error amplifier EA.

[0028] Preferably, when a large load current is suddenly reduced to an extremely low load current and causes an overshoot, the voltage signal V N From ground potential to power supply voltage VDD, V N The change of the current is coupled to the MOS tube M through the capacitor C1. 10 G pole, rear MOS tube M 10 Turn on and discharge.

[0029] Preferably, the MOS tube M 10 It will automatically turn off after the set time.

[0030] Compared with the prior art, the advantages of the present invention are: the existing overshoot suppression circuit for low quiescent current LDO directly connects the upper plate of the coupling capacitor C1 to the gate of the power MOS tube, while the overshoot suppression circuit proposed by the present invention connects the upper plate of the coupling capacitor C1 to the newly created voltage node.

[0031] Therefore, the dynamic current bias structure of the low quiescent current LDO itself is utilized to avoid connecting the overshoot detection capacitor to the gate of the LDO power MOS tube, thereby avoiding its negative impact on the LDO speed, PSR, etc. Specifically:

[0032] 1. When overshoot occurs, V N The potential changes from ground to VDD, and the power MOS tube (power tube M P )'s gate jumps from the middle potential to close to VDD.

[0033] Compared with the prior art where the coupling capacitor C1 is connected to the gate of the power MOS tube, the present invention connects the coupling capacitor C1 to the V N Node, the upper plate voltage of C1 will have a more drastic change, which can make the discharge MOS tube (MOS tube M 10 ) better conduction.

[0034] Compared with the prior art, the same coupling capacitor C1 and the same diode-connected MOS - M9 and discharge MOS tube M 10 In this case, the technology proposed in the present invention can obtain a larger discharge current, thereby better accelerating the recovery of overshoot.

[0035] 2. Compared with the existing technology, the technology proposed in the present invention avoids the negative impact of the overshoot suppression circuit on the performance parameters of the LDO itself.

[0036] In the prior art, the capacitor C1 is connected to the power MOS tube (power tube M P) gate, so the capacitance that the error amplifier EA needs to drive when adjusting the gate voltage of the power MOS tube becomes larger, which will lead to problems such as poor PSR of the LDO.

[0037] The present invention avoids this situation. Simulation verification shows that adding the overshoot suppression circuit of the present invention has no negative impact on the original performance parameters of the LDO. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a structural diagram of a low quiescent current LDO with overshoot suppression according to the present invention;

[0039] Figure 2 The overshoot suppression of the same LDO by different overshoot suppression circuits is shown in Figure 2.

[0040] Figure 3 The effect of applying different overshoot suppression circuits on PSR. DETAILED DESCRIPTION

[0041] The following describes the overshoot suppression circuit for a low quiescent current LDO in more detail with reference to a schematic diagram, which illustrates a preferred embodiment of the present invention. It should be understood that those skilled in the art may modify the present invention described herein while still achieving the beneficial effects of the present invention. Therefore, the following description should be understood as a general guideline for those skilled in the art and not as a limitation of the present invention.

[0042] Low quiescent current LDOs are commonly used in low-power IoT devices. A large portion of these low quiescent current LDOs contain a dynamic current bias structure. This dynamic current bias structure detects the current of the power MOS tube in the LDO and makes the bias current of the LDO's error amplifier proportional to the current of the power MOS tube in the LDO. The low quiescent current LDOs described in this embodiment all refer to low quiescent current LDOs that use dynamic current bias.

[0043] When the IoT device is in standby mode, the LDO load current becomes very small. Due to the dynamic current bias, the quiescent current consumed by the LDO itself is extremely low at this time, which can further reduce the standby power consumption of the IoT device and increase the battery life.

[0044] To achieve extremely low quiescent power consumption, the current of the voltage divider network of advanced low quiescent current LDO is very small (usually tens or hundreds of nA). This will cause a long output voltage overshoot when the LDO switches from heavy load to near zero load.

[0045] The overshoot suppression circuit for a low quiescent current LDO in this embodiment does not change the original parameters of the LDO, such as PSR, and hardly increases the minimum quiescent power consumption of the LDO, while significantly reducing the duration of overshoot.

[0046] Among them, LDO - Low Dropout Regulator low voltage difference linear regulator;

[0047] PSR——Power Supply Rejection.

[0048] Figure 1 It can be divided into two parts: one is the schematic diagram of the low quiescent current LDO without overshoot suppression, and the other is the overshoot suppression circuit (suppression network) proposed by the present invention.

[0049] Figure 1 The solid line frame is a portion unique to the overshoot suppression circuit of the present invention; the dotted line frame is a portion common to the overshoot suppression circuit of the present invention and the low quiescent current LDO; and the other portions are portions unique to the low quiescent current LDO.

[0050] like Figure 1 The low quiescent current LDO with overshoot suppression shown in the figure includes: a first part, a second part, a third part and a suppression network, one end of which is connected to the power supply voltage VDD, and the other end is grounded.

[0051] The first part is used for the power tube M P Provides G-pole voltage bias, which includes error amplifier EA; the second part includes: MOS tube M5 and MOS tube M4 connected in series; the third part includes: power tube M P and voltage divider feedback network.

[0052] The error amplifier EA has its output connected to the G pole of MOS tube M5 and the power tube M P The G pole of the MOSFET is connected to the reference voltage signal V REF The non-inverting input terminal is connected to the feedback voltage V output by the voltage divider feedback network. FB .

[0053] The S pole of MOS tube M5 and the power tube M P The S poles are connected to the power supply voltage VDD.

[0054] The D-pole of MOS tube M5 is connected to the D-pole of MOS tube M4, and the D-pole of M4 is connected to the G-pole of M4. The G-pole of MOS tube M4 leads to the bias voltage signal V M To the dynamic tail current source (G pole of MOS tube M3) and suppression network of the error amplifier EA; the S pole of MOS tube M4 is grounded.

[0055] The voltage divider feedback network has one end connected to the power tube M P The other end of the D pole is grounded, which leads to the feedback voltage signal V FB To the non-inverting input of the error amplifier EA.

[0056] Output voltage signal V OUT Self-power tube M P The D pole is connected to the load resistor R L The first end of the output capacitor C L The first end and MOS tube M 10 The D pole, load resistance R L The second end of the output capacitor C L The second end and MOS tube M 10 The S poles of the MOS tubes are grounded; 10 It is an NMOS tube.

[0057] The suppression network includes: a second current source I REF2 , MOS tube M9, MOS tube M 10 、MOS tube M 11 , coupling capacitor C1.

[0058] The second current source I REF2 One end is connected to MOS tube M 11 D pole, MOS tube M 11 The G pole receives the bias voltage signal V M , MOS tube M 11 The S pole is grounded, and the second current source I REF2 The other end is connected to the power supply voltage VDD;

[0059] Voltage signal V N From the second current source I REF2 and MOS tube M 11 The connection point N is led to the upper plate of the coupling capacitor C1, and the lower plate of the coupling capacitor C1 is connected to the MOS tube M 10 The G pole of the MOS tube M9 and the D pole of the MOS tube M9; the S pole of the MOS tube M9 is grounded, and the G pole of the MOS tube M9 is connected to its D pole.

[0060] In this embodiment, the width-to-length ratio of the MOS tube M5 is M P 1 / K, K=40. The second current source I REF2 The first current source I REF1 The limit is 100nA.

[0061] When the load current jumps from heavy load to near zero load current and causes overshoot, the voltage signal V N From ground potential to power supply voltage VDD, V N The rise of is coupled to the MOS tube M through the capacitor C1 10 G pole, MOS tube M 10 Turn on and discharge. MOS tube M 10 It will automatically turn off after the set time, and its G pole voltage will return to the ground potential.

[0062] Furthermore, the first part also includes: a first current source I REF1 , MOS tube M1, MOS tube M2.

[0063] MOS tube M2 and MOS tube M3 are the static tail current source and dynamic tail current source of the error amplifier EA respectively;

[0064] The S pole of MOS tube M3 and the S pole of MOS tube M2 are both grounded, the D pole of MOS tube M3 is connected to the D pole of MOS tube M2; the G pole of MOS tube M3 is connected to the G pole of MOS tube M4 to receive the bias voltage signal V M ;

[0065] One end of the error amplifier EA is connected to the D-pole of the MOS tube M3, and the other end is connected to the power supply voltage VDD;

[0066] The G pole of the MOS tube M1 is connected to its D pole, and its S pole is grounded. The G pole of the MOS tube M1 is connected to the G pole of the MOS tube M2; the D pole of the MOS tube M1 is connected to the first current source I REF1 ; The first current source I REF1 Connect the power supply voltage VDD.

[0067] The voltage divider feedback network includes: MOS transistor M6, MOS transistor M7 and MOS transistor M8.

[0068] The G pole of the MOS tube M6 is connected to its D pole, the G pole of the MOS tube M7 is connected to its D pole, and the G pole of the MOS tube M8 is connected to its D pole;

[0069] The D pole of MOS tube M6 is connected to the power tube M P The D pole of the MOS tube M7 is connected to the S pole of the MOS tube M6, the D pole of the MOS tube M8 is connected to the S pole of the MOS tube M7, and the S pole of the MOS tube M8 is grounded;

[0070] Feedback voltage signal V FB It is drawn out from the D-pole of the MOS tube M7 and connected to the non-inverting input terminal of the error amplifier EA.

[0071] Among them, the conventional tail current source (static tail current source) of the error amplifier EA is the MOS tube M2, and the first current source I REF1 And MOS tube M1 is used to bias MOS tube M2.

[0072] The dynamic tail current source of EA is M3, and MOS tubes M4 and M5 generate the sensing voltage V M And bias the MOS tube M3.

[0073] G pole is V M Biased MOS tube M 11 With the second current source IREF2 creates a voltage node V N , which is connected to the upper plate of the coupling capacitor C1; C1 and the MOS tube M9 used as a resistor form a high-pass filter, thereby coupling the sudden change of the upper plate of the coupling capacitor C1 to the MOS tube M 10 of the gate.

[0074] MOS tube M 10 For the discharge MOS tube, the open MOS tube M 10 The output voltage signal V OUT The corresponding node discharges.

[0075] The MOS transistor M4 and the MOS transistor M5 are not only important components of the low quiescent current LDO itself, but also components of the overshoot suppression circuit proposed in the present invention.

[0076] Therefore, the present invention effectively utilizes the circuit characteristics of the low quiescent current LDO itself, thereby completing the overshoot suppression work by consuming only extremely small quiescent current and circuit area.

[0077] Working principle of the process suppression circuit:

[0078] MOS tube M5 and power MOS tube (power tube M P ) are connected together and are controlled by the output of the error amplifier EA, and the S poles of both are also connected to the power supply voltage VDD. P V GS Always be consistent.

[0079] The width-to-length ratio of MOS tube M5 is P 1 / K, so the current of M5 is about M P 1 / K of the current. Therefore, the power tube M can be detected by the MOS tube M5. P The current on.

[0080] MOS tube M4 and MOS tube M5 are connected in series, and MOS tube M3 and MOS tube M4 form a current mirror structure, so the current of MOS tube M3 is equal to the current of MOS tube M5, and its value is P 1 / K times the current.

[0081] Because the power tube M P The current is mainly determined by the load current, so the MOS tube M3 can provide corresponding dynamic current bias for EA according to the change of the load current.

[0082] Figure 1 The first current source I REF1 and the second current source I REF2It is a 100nA non-ideal current source mirrored by a reference current source. In actual design, it is usually a gate-biased PMOS tube or a biased cascode PMOS tube.

[0083] When the load resistance R L When the upper current is large:

[0084] The current on MOS tubes M6~M8 is 70nA, and K is 40.

[0085] MOS tube M 10 The gate voltage is zero voltage.

[0086] When the power tube M P When the current on M is 100μA, the current on M5 is 1 / K times of that, that is, 2.5μA.

[0087] The current of MOS tube M4 is also 2.5μA and generates a bias voltage V M .

[0088] According to the current mirror principle, the MOS tube M 11 The current should also be 2.5μA, because 2.5μA>100nA=I REF2 , V N is pulled down to near ground voltage, i.e. zero voltage.

[0089] But in fact, due to the 100nA second current source I REF2 Limit, the second current source I REF2 and MOS tube M 11 The actual current in this current branch is 100nA.

[0090] When the load resistance R L The upper current suddenly decreases to 0μA, then the power tube M P The current on the MOSFET will become 70nA. Specifically:

[0091] When the load resistance R L The upper current suddenly decreases to 0μA, V OUT Rising, overshoot trigger, V FB V OUT The rising voltage is fed back to the error amplifier EA, which raises the power tube M P and the gate of MOS tube M5, making it almost completely cut off. At this time, the power tube M P The upper current is 70nA, and the upper current of M5 is about 70nA / K=1.75nA.

[0092] At this time, due to I REF2 =100nA>1.75nA, V N is pulled high to close to V DD , and make IREF2 With MOS tube M 11 The DC current in this current branch is 1.75nA.

[0093] In summary, when the load current suddenly decreases and overshoot occurs, V N The potential jumps rapidly from the ground potential to a certain potential and rises to V DD .

[0094] V N The rapid rise of the 10 The gate of MOS tube M 10 The gate voltage will rise from 0 to its turn-on voltage V TH Above, turn on MOS tube M 10 V OUT discharge to speed up V OUT Overshoot recovery speed.

[0095] Due to the function of MOS tube M9, MOS tube M 10 It will not be turned on all the time. After a short period of time, the MOS tube M 10 The gate voltage will be lower than its turn-on voltage V TH ; and because of the subthreshold conductivity and leakage of M9, M 10 The gate voltage will eventually return to ground potential, ensuring that M 10 No static power consumption.

[0096] The existing overshoot suppression circuit or the overshoot suppression circuit of the present invention is added to a designed low quiescent current LDO, and the overshoot and PSR performances are simulated.

[0097] Figure 2 The output voltage response waveforms of the original low quiescent current LDO (without any overshoot suppression), the low quiescent current LDO using the existing overshoot suppression technology, and the low quiescent current LDO using the overshoot suppression technology of the present invention when the load current suddenly decreases.

[0098] Figure 3 The graphs show the PSR variation with frequency for the original low quiescent current LDO (without any overshoot suppression), the low quiescent current LDO using the existing overshoot suppression technology, and the low quiescent current LDO using the overshoot suppression technology of the present invention.

[0099] Figure 2 The results show that both the existing overshoot suppression technology and the overshoot suppression technology of the present invention can significantly reduce the overshoot duration of the LDO, but the overshoot suppression technology of the present invention has a stronger ability to suppress overshoot, and the overshoot duration and overshoot peak value are both shorter.

[0100] Figure 3The results show that the addition of the existing overshoot suppression circuit will destroy the original PSR performance of the LDO and reduce the ripple suppression capability of the LDO at the medium and high frequency ends. However, the PSR curve of the overshoot suppression circuit of the present invention is completely consistent with that of the original LDO and does not cause any negative impact.

[0101] Table 1 Simulation comparison of overshoot suppression technology

[0102]

[0103] Table 1 summarizes the performance comparison of the proposed overshoot suppression technology for low quiescent current LDOs, compared to a low quiescent current LDO without overshoot suppression and a low quiescent current LDO using existing overshoot suppression technology. Aside from a very slight increase in minimum quiescent current, the proposed technology offers advantages over existing technologies in all other respects.

[0104] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A low quiescent current LDO with overshoot suppression, characterized in that: include: One end of the first part, the second part, the third part and the suppression network are all connected to the power supply voltage VDD, and the other end are all grounded; The first part is used for the power tube M P Provides G-pole voltage bias, which includes an error amplifier EA; the second part includes: a MOS tube M5 and a MOS tube M4 connected in series; the third part includes: a power tube M P and voltage divider feedback network; The error amplifier EA has its inverting input connected to the reference voltage V REF The non-inverting input terminal is connected to the feedback voltage signal V output by the voltage divider feedback network. FB Its output end is connected to the G pole of MOS tube M5 and the power tube M P The G pole; The S pole of the MOS tube M5 and the power tube M P The S poles are connected to the power supply voltage VDD; The D-pole of the MOS tube M5 is connected to the D-pole of the MOS tube M4, and the D-pole of M4 is connected to the G-pole of M4. The G-pole of the MOS tube M4 leads to the bias voltage signal V M The dynamic tail current source and suppression network to the error amplifier EA; the S pole of the MOS tube M4 is grounded; The voltage divider feedback network has one end connected to the power tube M P The other end of the D pole is grounded, which leads to the feedback voltage signal V FB To the non-inverting input of the error amplifier EA; Output voltage signal V OUT Self-power tube M P The D pole is connected to the load resistor R L The first end of the output capacitor C L The first end and MOS tube M 10 The D pole, load resistance R L The second end of the output capacitor C L The second end and MOS tube M 10 The S poles of the MOS tubes M are grounded; 10 It is an NMOS tube; The suppression network includes: a second current source I REF2 、MOS tube M 11 , coupling capacitor C1 and MOS tube M9, the MOS tube M 10 ; The second current source I REF2 One end is connected to MOS tube M 11 D pole, MOS tube M 11 The G pole receives the bias voltage signal V M , MOS tube M 11 The S pole is grounded, and the second current source I REF2 The other end is connected to the power supply voltage VDD; Voltage signal V N From the second current source I REF2 and MOS tube M 11 The connection point N is led to the upper plate of the coupling capacitor C1, and the lower plate of the coupling capacitor C1 is connected to the MOS tube M 10 The G pole of the MOS tube M9 and the D pole of the MOS tube M9; the S pole of the MOS tube M9 is grounded, and the G pole of the MOS tube M9 is connected to its D pole.

2. The low quiescent current LDO with overshoot suppression according to claim 1, characterized in that: The width-to-length ratio of the MOS tube M5 is P 1 / K, K=40.

3. The low quiescent current LDO with overshoot suppression according to claim 1, characterized in that: The second current source I REF2 The limit is 100nA.

4. The low quiescent current LDO with overshoot suppression according to claim 1, characterized in that: The first part also includes: a first current source I REF1 , MOS tube M1 and MOS tube M2; The MOS tube M2 is the static tail current source of the error amplifier EA; The dynamic tail current source of the error amplifier EA is the MOS tube M3; The S pole of the MOS tube M3 and the S pole of the MOS tube M2 are both grounded, the D pole of the MOS tube M3 is connected to the D pole of the MOS tube M2; the G pole of the MOS tube M3 is connected to the G pole of the MOS tube M4 to receive the bias voltage signal V M ; One end of the error amplifier EA is connected to the D-pole of the MOS tube M3, and the other end is connected to the power supply voltage VDD; The G pole of the MOS tube M1 is connected to its D pole, and its S pole is grounded. The G pole of the MOS tube M1 is connected to the G pole of the MOS tube M2; the D pole of the MOS tube M1 is connected to the first current source I REF1 ; The first current source I REF1 Connect the power supply voltage VDD.

5. The low quiescent current LDO with overshoot suppression according to claim 4, characterized in that: The first current source I REF1 The limit is 100nA.

6. The low quiescent current LDO with overshoot suppression according to claim 1, characterized in that: The voltage divider feedback network includes: MOS transistor M6, MOS transistor M7 and MOS transistor M8; The G pole of the MOS tube M6 is connected to its D pole, the G pole of the MOS tube M7 is connected to its D pole, and the G pole of the MOS tube M8 is connected to its D pole; The D pole of the MOS tube M6 is connected to the power tube M P The D pole of the MOS tube M7 is connected to the S pole of the MOS tube M6, the D pole of the MOS tube M8 is connected to the S pole of the MOS tube M7, and the S pole of the M8 is grounded; Feedback voltage signal V FB It is drawn out from the D-pole of the MOS tube M7 and connected to the non-inverting input terminal of the error amplifier EA.

7. The low quiescent current LDO with overshoot suppression according to claim 1, characterized in that: During overshoot, the voltage signal V N From ground potential to power supply voltage VDD, V N The change of the current is coupled to the MOS tube M through the capacitor C1. 10 G pole, rear MOS tube M 10 Turn on and discharge.

8. The low quiescent current LDO with overshoot suppression according to any one of claims 1 to 7, characterized in that: The MOS tube M 10 It will automatically turn off after the set time.

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