Low-dropout linear regulators, chips, and electronic devices

Abstract

The embodiments of the present application relate to the field of power management technology, and more particularly to a low-voltage dropout linear regulator, chip, and electronic device, including a voltage adjustment circuit and an acceleration circuit, wherein the acceleration circuit is connected to the voltage adjustment circuit; the voltage adjustment circuit is used to adjust the output voltage of the low-voltage dropout linear regulator to a target voltage after the output voltage of the low-voltage dropout linear regulator overshoots or undershoots; and the acceleration circuit is used to accelerate the voltage adjustment circuit's adjustment of the low-voltage dropout linear regulator's output voltage when the output voltage of the low-voltage dropout linear regulator is outside a reference voltage range, and stop accelerating the voltage adjustment circuit's adjustment of the low-voltage dropout linear regulator's output voltage after a target duration, wherein the target voltage is within the reference voltage range and the output voltage of the low-voltage dropout linear regulator is outside the reference voltage range when overshooting or undershooting. Thus, this solution extends the service life of the low-voltage dropout linear regulator and simplifies the internal design of the low-voltage dropout linear regulator.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of power management technology, and in particular to a low voltage difference linear regulator, a chip, and an electronic device. Background Art

[0002] A low-dropout linear regulator (LDO) is a device that automatically maintains a relatively constant output voltage and is widely used in many fields such as medical, computer, industrial infrastructure equipment, and portable products.

[0003] During the operation of the low-voltage dropout linear regulator, the output voltage of the low-voltage dropout linear regulator basically maintains the target value. When the input voltage of the low-voltage dropout linear regulator changes or the load current undergoes a transient change, the output voltage of the low-voltage dropout linear regulator will have a relatively obvious undershoot (that is, the output voltage suddenly becomes significantly smaller) or overshoot (that is, the output voltage suddenly becomes significantly larger). In order to enable the low-voltage dropout linear regulator to adjust the output voltage as quickly as possible during undershoot and overshoot, a positively correlated inductive current is usually generated according to the load current. The larger the load current, the larger the inductive current. The inductive current is input to the voltage adjustment module included in the low-voltage dropout linear regulator to accelerate the voltage adjustment module to adjust the output voltage of the low-voltage dropout linear regulator. Therefore, when the output voltage of the low-voltage dropout linear regulator undershoots or overshoots, the output voltage of the low-voltage dropout linear regulator can be adjusted to the target value more quickly, thereby reducing the possibility that the subsequent circuit of the low-voltage dropout linear regulator cannot work normally or is even damaged.

[0004] However, the induced current received by the voltage adjustment module will cause the internal current of the low-voltage dropout linear regulator to be larger, and the larger the load current, the larger the induced current, and thus the larger the internal current of the low-voltage dropout linear regulator. Therefore, when the low-voltage dropout linear regulator is in a current-limiting state, the internal current of the low-voltage dropout linear regulator will always be large, so that the low-voltage dropout linear regulator basically operates in a high-current state, resulting in a short service life of the low-voltage dropout linear regulator. In addition, the internal current of the low-voltage dropout linear regulator changes with the load current, which also makes the internal design of the low-voltage dropout linear regulator more complicated. Summary of the Invention

[0005] In view of this, embodiments of the present application provide a low voltage dropout linear regulator to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present application, a low-voltage difference linear regulator is disclosed, comprising: a voltage adjustment circuit and an acceleration circuit, the acceleration circuit being connected to the voltage adjustment circuit; the voltage adjustment circuit being configured to adjust the output voltage of the low-voltage difference linear regulator to a target voltage after the output voltage of the low-voltage difference linear regulator overshoots or undershoots; the acceleration circuit being configured to accelerate the adjustment of the output voltage of the low-voltage difference linear regulator by the voltage adjustment circuit starting from when the output voltage of the low-voltage difference linear regulator is outside a reference voltage range, and to stop accelerating the adjustment of the output voltage of the low-voltage difference linear regulator by the voltage adjustment circuit after a target time has passed, wherein the target voltage is within the reference voltage range, and the output voltage of the low-voltage difference linear regulator is outside the reference voltage range when overshooting or undershooting.

[0007] In one possible implementation, the acceleration circuit includes a comparison module, a pulse generation module, and an acceleration module; the comparison module is configured to output a corresponding first pulse signal after the output voltage of the low-dropout linear regulator overshoots or undershoots, wherein the start time of the first pulse signal is the time when the corresponding overshoot or undershoot occurs, and the end time of the first pulse signal is the time when the output voltage of the low-dropout linear regulator first changes to within the reference voltage range after the corresponding overshoot or undershoot; the pulse generation module is connected to the comparison module, configured to generate a second pulse signal based on the first pulse signal and output the second pulse signal, wherein the start time of the second pulse signal is the same as the start time of the first pulse signal, the pulse width of the second pulse signal is equal to the target duration, and the pulse width of the second pulse signal is greater than the pulse width of the first pulse signal; the acceleration module is connected to the pulse generation module, configured to accelerate the voltage adjustment circuit's adjustment of the low-dropout linear regulator's output voltage during the process of receiving the second pulse signal, and stop accelerating the voltage adjustment circuit's adjustment of the low-dropout linear regulator's output voltage after receiving the second pulse signal.

[0008] In one possible implementation, the comparison module is further used to continuously output a first indication signal with a constant level value after the input voltage of the low-voltage difference linear regulator is less than the minimum voltage for normal operation of the low-voltage difference linear regulator and the output voltage of the low-voltage difference linear regulator is less than the minimum voltage of the reference voltage range; the pulse generation module is further used to generate a third pulse signal according to the first indication signal and output the third pulse signal, wherein the start time of the third pulse signal is the same as the start time of the first indication signal, and the pulse width of the third pulse signal is equal to the target duration; the acceleration module is further used to accelerate the adjustment of the output voltage of the low-voltage difference linear regulator by the voltage adjustment circuit during the process of receiving the third pulse signal, and stop accelerating the adjustment of the output voltage of the low-voltage difference linear regulator by the voltage adjustment circuit after completing the reception of the third pulse signal.

[0009] In one possible implementation, the pulse generating module includes a first pulse generating unit and a second pulse generating unit; the first pulse generating unit is connected to the comparison module, and is used to generate a fourth pulse signal based on the first pulse signal and output the fourth pulse signal, and is also used to generate a second indication signal with a constant level value based on the first indication signal, and output the second indication signal, wherein the pulse width of the fourth pulse signal is greater than the pulse width of the first pulse signal, and the start time of the second indication signal is the same as the start time of the first indication signal; the second pulse generating unit is connected to the first pulse generating unit, and is used to generate the second pulse signal based on the fourth pulse signal, and is also used to generate the third pulse signal based on the second indication signal, wherein the pulse width of the fourth pulse signal is greater than the pulse width of the second pulse signal.

[0010] In a possible implementation, the first pulse generating unit includes a first NOT gate, a first P-channel transistor, a first N-channel transistor, a first current source, a first capacitor, a second NOT gate, a third NOT gate, a first NOR gate, and a fourth NOT gate; the input end of the first NOT gate is connected to the output end of the comparison module, the output end of the first NOT gate is connected to the gate of the first P-channel transistor, and the output end of the first NOT gate is connected to the gate of the first N-channel transistor; the source of the first P-channel transistor is connected to the power supply, the drain of the first P-channel transistor is connected to the first end of the first capacitor; the source of the first N-channel transistor is connected to the output end of the comparison module, and the drain of the first P-channel transistor is connected to the first end of the first capacitor; the source of the first N-channel transistor is connected to the output end of the comparison module, and the drain of the first P-channel transistor is connected to the first end of the first capacitor; the drain of the first N-channel transistor is connected to the gate of the first P-channel transistor. The negative electrode of the first current source is connected, the drain of the first N-channel transistor is connected to the first end of the first capacitor; the positive electrode of the first current source is grounded; the second end of the first capacitor is grounded; the input end of the second NOT gate is connected to the first end of the first capacitor, the output end of the second NOT gate is connected to the input end of the third NOT gate; the output end of the third NOT gate is connected to the first input end of the first NOR gate; the second input end of the first NOR gate is connected to the output end of the comparison module, the output end of the first NOR gate is connected to the input end of the fourth NOT gate; the output end of the fourth NOT gate is connected to the second pulse generating unit.

[0011] In one possible implementation, the second pulse generating unit includes a fifth NOT gate, a sixth NOT gate, a second P-channel transistor, a second N-channel transistor, a second current source, a second capacitor, a seventh NOT gate, and an XNOR gate; an input of the fifth NOT gate is connected to the output of the fourth NOT gate, an output of the fifth NOT gate is connected to the input of the sixth NOT gate, an output of the sixth NOT gate is connected to the gate of the second P-channel transistor, and an output of the sixth NOT gate is connected to the gate of the second N-channel transistor; a source of the second P-channel transistor is connected to a power supply, and a drain of the second P-channel transistor is connected to the first end of the second capacitor; a source of the second N-channel transistor is connected to the negative electrode of the second current source, and a drain of the second N-channel transistor is connected to the first end of the second capacitor; a positive electrode of the second current source is grounded; a second end of the second capacitor is grounded; an input of the seventh NOT gate is connected to the first end of the second capacitor, an output of the seventh NOT gate is connected to the first input of the XNOR gate, a second input of the XNOR gate is connected to the output of the fifth NOT gate, and an output of the XNOR gate is connected to the acceleration module.

[0012] In one possible implementation, the comparison module includes a first comparator, a second comparator, a second NOR gate, and an eighth NOR gate; the non-inverting input of the first comparator is used to input a voltage to be compared, and the inverting input of the first comparator is used to input a first reference voltage, wherein the voltage to be compared is proportional to the output voltage of the low-dropout linear regulator, and the ratio of the voltage to be compared to the output voltage of the low-dropout linear regulator is a target ratio, and the first reference voltage is equal to the product of the maximum voltage of the reference voltage range and the target ratio; the non-inverting input of the second comparator is used to input a second reference voltage, and the inverting input of the second comparator is used to input the voltage to be compared, wherein the second reference voltage is equal to the product of the minimum voltage of the reference voltage range and the target ratio; the two inputs of the second NOR gate are respectively connected to the output of the first comparator and the output of the second comparator, and the output of the second NOR gate is connected to the input of the eighth NOR gate; the output of the eighth NOR gate is the output of the comparison module.

[0013] In one possible implementation, the acceleration module includes a third N-channel transistor and a fourth current source; the gate of the third N-channel transistor is connected to the output end of the XNOR gate, the source of the third N-channel transistor is connected to the negative electrode of the fourth current source, the drain of the third N-channel transistor is connected to the voltage adjustment circuit, and the positive electrode of the fourth current source is grounded.

[0014] In one possible implementation, the acceleration module further includes a fourth N-channel transistor and a fifth N-channel transistor. The voltage adjustment circuit includes a first large capacitance node and a second large capacitance node. The first large capacitance node is used to discharge when the voltage adjustment circuit adjusts the output voltage of the low-voltage dropout linear regulator to the target voltage, and the second large capacitance node is used to charge when the voltage adjustment circuit adjusts the output voltage of the low-voltage dropout linear regulator to the target voltage. The gate of the fourth N-channel transistor is connected to the output end of the XNOR gate, the source of the fourth N-channel transistor is grounded, and the drain of the fourth N-channel transistor is connected to the first large capacitance node. The gate of the fifth N-channel transistor is connected to the output end of the XNOR gate, the source of the fifth N-channel transistor is connected to the second large capacitance node, and the drain of the fifth N-channel transistor is connected to a power supply.

[0015] In one possible implementation, the voltage adjustment circuit includes a differential amplifier, a third current source, a target P-channel transistor, a first resistor, and a second resistor; the power input terminal of the differential amplifier is used to input the input voltage of the low-voltage difference linear regulator, the port of the differential amplifier for inputting the tail current is connected to the negative electrode of the third current source, the non-inverting input terminal of the differential amplifier is connected to the first end of the first resistor and to the first end of the second resistor, the inverting input terminal of the differential amplifier is used to input a reference voltage, and the output terminal of the differential amplifier is connected to the gate of the target P-channel transistor; the positive electrode of the third current source is grounded, and the negative electrode of the third current source is connected to the acceleration circuit; the source of the target P-channel transistor is used to input the input voltage of the low-voltage difference linear regulator, and the drain of the target P-channel transistor is connected to the second end of the second resistor; the second end of the first resistor is grounded; and the first end of the second resistor is connected to the output port of the low-voltage difference linear regulator.

[0016] According to a second aspect of an embodiment of the present application, a chip is disclosed, comprising the low voltage dropout linear regulator as described in the first aspect.

[0017] According to a third aspect of the embodiments of the present application, an electronic device is disclosed, comprising the low voltage dropout linear regulator as described in the first aspect.

[0018] According to the low-voltage difference linear regulator provided in the embodiment of the present application, by adopting a low-voltage difference linear regulator including a voltage adjustment circuit and an acceleration circuit, after the output voltage of the low-voltage difference linear regulator overshoots or undershoots, the voltage adjustment circuit can adjust the output voltage of the low-voltage difference linear regulator to a target voltage. At the same time, when the output voltage of the low-voltage difference linear regulator is outside the reference voltage range, the acceleration circuit starts to accelerate the voltage adjustment circuit's adjustment of the low-voltage difference linear regulator's output voltage, and stops accelerating the voltage adjustment circuit's adjustment of the low-voltage difference linear regulator's output voltage after a target time. Therefore, the acceleration circuit starts to accelerate the voltage adjustment circuit to adjust the output voltage of the low-voltage difference linear regulator when the output voltage of the low-voltage difference linear regulator overshoots or undershoots, and stops the acceleration after the target time. Therefore, after the output voltage of the low-voltage difference linear regulator overshoots or undershoots, the acceleration module only accelerates the adjustment of the output voltage of the low-voltage difference linear regulator in a short period of time. Compared with the voltage adjustment circuit that always receives the induction current for accelerating the adjustment of the output voltage of the low-voltage difference linear regulator during the operation of the low-voltage difference linear regulator, in the embodiment of the present application, the voltage adjustment circuit accelerates the adjustment of the output voltage of the low-voltage difference linear regulator during the operation of the low-voltage difference linear regulator. After the output voltage of the regulator overshoots or undershoots, the acceleration circuit responds quickly and exits quickly, so that the internal current of the low-voltage dropout linear regulator is low most of the time, and thus the low-voltage dropout linear regulator operates in a high-current state for a shorter time, thereby extending the service life of the low-voltage dropout linear regulator. In addition, the internal current of the low-voltage dropout linear regulator increases when the acceleration voltage adjustment circuit adjusts the output voltage of the low-voltage dropout linear regulator, and is low at other times. Therefore, the internal current of the low-voltage dropout linear regulator does not change with changes in the load current, which can simplify the internal design of the low-voltage dropout linear regulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0020] Figure 1 is a schematic block diagram of a low-dropout linear regulator according to an embodiment of the present application;

[0021] Figure 2 is a circuit diagram of a voltage regulation circuit according to an embodiment of the present application;

[0022] Figure 3 is a circuit diagram of a comparison module according to an embodiment of the present application;

[0023] Figure 4 is a circuit diagram of a pulse generating module according to an embodiment of the present application;

[0024] Figure 5 is a circuit diagram of an acceleration module according to an embodiment of the present application;

[0025] Figure 6 This is a schematic diagram of the changes in signals of various parts of a low-dropout linear regulator according to an embodiment of the present application;

[0026] Figure 7 This is a schematic diagram of the changes in signals of various parts in a low-dropout linear regulator according to another embodiment of the present application. DETAILED DESCRIPTION

[0027] Low Dropout Linear Regulator

[0028] An embodiment of the present application provides a low voltage dropout linear regulator, and the low voltage dropout linear regulator is described in detail below through multiple embodiments.

[0029] Figure 1 FIG. 1 is a schematic block diagram of a low voltage dropout linear regulator according to an embodiment of the present invention. Figure 1 As shown, the low-voltage difference linear regulator includes: a voltage adjustment circuit and an acceleration circuit, the acceleration circuit being connected to the voltage adjustment circuit; the voltage adjustment circuit being used to adjust the output voltage of the low-voltage difference linear regulator to a target voltage after the output voltage of the low-voltage difference linear regulator overshoots or undershoots; the acceleration circuit being used to accelerate the adjustment of the output voltage of the low-voltage difference linear regulator by the voltage adjustment circuit starting from when the output voltage of the low-voltage difference linear regulator is outside a reference voltage range, and to stop accelerating the adjustment of the output voltage of the low-voltage difference linear regulator by the voltage adjustment circuit after a target time has passed, wherein the target voltage is within the reference voltage range, and the output voltage of the low-voltage difference linear regulator is outside the reference voltage range when overshooting or undershooting.

[0030] In an embodiment of the present application, a low-voltage difference linear regulator including a voltage adjustment circuit and an acceleration circuit is adopted. After the output voltage of the low-voltage difference linear regulator overshoots or undershoots, the voltage adjustment circuit can adjust the output voltage of the low-voltage difference linear regulator to a target voltage. At the same time, when the output voltage of the low-voltage difference linear regulator is outside the reference voltage range, the acceleration circuit starts to accelerate the voltage adjustment circuit's adjustment of the output voltage of the low-voltage difference linear regulator, and stops accelerating the voltage adjustment circuit's adjustment of the output voltage of the low-voltage difference linear regulator after a target time. Therefore, the acceleration circuit starts to accelerate the voltage adjustment circuit to adjust the output voltage of the low-voltage difference linear regulator when the output voltage of the low-voltage difference linear regulator overshoots or undershoots, and stops the acceleration after the target time. Therefore, after the output voltage of the low-voltage difference linear regulator overshoots or undershoots, the acceleration module only accelerates the adjustment of the output voltage of the low-voltage difference linear regulator in a short period of time. Compared with the voltage adjustment circuit that always receives the induction current for accelerating the adjustment of the output voltage of the low-voltage difference linear regulator during the operation of the low-voltage difference linear regulator, in the embodiment of the present application, the voltage adjustment circuit accelerates the adjustment of the output voltage of the low-voltage difference linear regulator during the operation of the low-voltage difference linear regulator. After the output voltage of the regulator overshoots or undershoots, the acceleration circuit responds quickly and exits quickly, so that the internal current of the low-voltage dropout linear regulator is low most of the time, and thus the low-voltage dropout linear regulator operates in a high-current state for a shorter time, thereby extending the service life of the low-voltage dropout linear regulator. In addition, the internal current of the low-voltage dropout linear regulator increases when the acceleration voltage adjustment circuit adjusts the output voltage of the low-voltage dropout linear regulator, and is low at other times. Therefore, the internal current of the low-voltage dropout linear regulator does not change with changes in the load current, which can simplify the internal design of the low-voltage dropout linear regulator.

[0031] In one possible implementation, Figure 2As shown, the voltage adjustment circuit includes a differential amplifier EA, a third current source I3, a target P-channel transistor MPOWER, a first resistor RFB1 and a second resistor RFB2; the power input terminal of the differential amplifier EA is connected to the power supply VDD, and the output voltage of the power supply VDD is the input voltage of the low-voltage difference linear regulator, so that the power input terminal of the differential amplifier EA is used to input the input voltage of the low-voltage difference linear regulator, the port of the differential amplifier EA for inputting the tail current is connected to the negative electrode of the third current source I3, the non-inverting input terminal of the differential amplifier EA is connected to the first end of the first resistor RFB1, and is connected to the first end of the second resistor RFB2, and the differential amplifier The inverting input terminal of EA is used to input the reference voltage VREF, and the output terminal of the differential amplifier EA is connected to the gate of the target P-channel transistor MPOWER; the positive electrode of the third current source I3 is grounded, and the negative electrode of the third current source I3 is connected to the acceleration circuit; the source of the target P-channel transistor MPOWER is connected to the power supply VDD, so that the source of the target P-channel transistor MPOWER is used to input the input voltage of the low-voltage difference linear regulator, and the drain of the target P-channel transistor MPOWER is connected to the second end of the second resistor RFB2; the second end of the first resistor RFB1 is grounded; the first end of the second resistor RFB2 is connected to the output port of the low-voltage difference linear regulator.

[0032] After the output voltage of the low-voltage difference linear regulator overshoots or undershoots due to reasons such as excessive load, or after the input voltage of the low-voltage difference linear regulator is low, causing the output voltage of the low-voltage difference linear regulator to drop, the output voltage of the low-voltage difference linear regulator is not equal to the target voltage at this time, and a difference occurs between the input voltage of the non-inverting input terminal of the differential amplifier EA and the reference voltage. Then, the input voltage of the non-inverting input terminal of the differential amplifier EA can be adjusted to be equal to the reference voltage through the target P-channel transistor MPOWER, so that the output voltage of the low-voltage difference linear regulator is equal to the target voltage, wherein the target voltage is equal to VREF*(1+R2 / R1), R2 is the resistance value of the second resistor RFB2, and R1 is the resistance value of the first resistor RFB1.

[0033] It should be noted that when the output voltage of the low-dropout linear regulator drops significantly due to the input voltage of the low-dropout linear regulator being too low, the input voltage of the low-dropout linear regulator cannot maintain the normal operation of the low-dropout linear regulator. At this time, the low-dropout linear regulator can only increase the output voltage but cannot adjust the output voltage to the target voltage.

[0034] In an embodiment of the present application, by adopting a voltage adjustment circuit including a differential amplifier EA, a third current source I3, a target P-channel transistor MPOWER, a first resistor RFB1 and a second resistor RFB2, the structure of the voltage adjustment circuit can be simplified, the cost is low, and it is easy to implement.

[0035] In one possible implementation, the acceleration circuit includes a comparison module, a pulse generation module and an acceleration module; the comparison module is used to output a corresponding first pulse signal after the output voltage of the low-voltage difference linear regulator overshoots or undershoots, wherein the start time of the first pulse signal is the time when the corresponding overshoot or undershoot occurs, and the end time of the first pulse signal is the time when the output voltage of the low-voltage difference linear regulator first changes to within the reference voltage range after the corresponding overshoot or undershoot; the pulse generation module is connected to the comparison module, and is used to generate a second pulse signal according to the first pulse signal and output the second pulse signal, wherein the start time of the second pulse signal is the same as the start time of the first pulse signal, the pulse width of the second pulse signal is equal to the target duration, and the pulse width of the second pulse signal is greater than the pulse width of the first pulse signal; the acceleration module is connected to the pulse generation module, and is used to accelerate the voltage adjustment circuit to adjust the output voltage of the low-voltage difference linear regulator during the process of receiving the second pulse signal, and stop accelerating the voltage adjustment circuit to adjust the output voltage of the low-voltage difference linear regulator after receiving the second pulse signal.

[0036] Among them, the first pulse signal and the second pulse signal are both single pulse signals, the pulse width of the first pulse signal is smaller than the pulse width of the second pulse signal, and the specific boundary value of the reference voltage range can be set according to actual needs, and the embodiment of the present application does not limit this.

[0037] In an embodiment of the present application, a comparison module outputs a first pulse signal after the output voltage of the low-dropout linear regulator overshoots or undershoots. The pulse generation module generates and outputs a second pulse signal based on the first pulse generation signal, having the same start time as the first pulse signal and a pulse width of a target duration. The acceleration module is configured to accelerate the voltage adjustment circuit's adjustment of the low-dropout linear regulator's output voltage during the process of receiving the first pulse signal, and to stop the acceleration after receiving the second pulse signal. Thus, starting from the overshoot or undershoot of the low-dropout linear regulator's output voltage, the voltage adjustment circuit's adjustment of the low-dropout linear regulator's output voltage is accelerated within the target duration, and the acceleration is stopped after the target duration has elapsed, thereby reducing power consumption.

[0038] In one possible implementation, the comparison module is also used to: when the input voltage of the low-voltage difference linear regulator is less than the minimum voltage for normal operation of the low-voltage difference linear regulator, and the output voltage of the low-voltage difference linear regulator is less than the minimum voltage of the reference voltage range, the input voltage of the low-voltage difference linear regulator is too low, and the low-voltage difference linear regulator cannot adjust the output voltage of the low-voltage difference linear regulator to the target voltage. At this time, the comparison module continues to output the first indication signal with an unchanged level value; the pulse generation module is also used to generate a third pulse signal according to the first indication signal, and output the third pulse signal, wherein the third pulse signal is a single pulse signal, the start time of the third pulse signal is the same as the start time of the first indication signal, and the pulse width of the third pulse signal is equal to the target duration; the acceleration module is also used to accelerate the voltage adjustment circuit to adjust the output voltage of the low-voltage difference linear regulator during the process of receiving the third pulse signal, and stop accelerating the voltage adjustment circuit to adjust the output voltage of the low-voltage difference linear regulator after receiving the third pulse signal.

[0039] Among them, the signal output by the comparison module is a digital signal, that is, its level value is a low level or a high level. The level value of the signal output by the comparison module when the output voltage of the low-voltage difference linear regulator is equal to the target voltage is opposite to the level value of the first indication signal. The minimum voltage for the normal operation of the low-voltage difference linear regulator refers to the minimum input voltage at which the low-voltage difference linear regulator can adjust the output voltage to the target voltage.

[0040] In an embodiment of the present application, the comparison module continuously outputs a first indication signal with a constant level value after the input voltage of the low-dropout linear regulator is less than the minimum voltage for normal operation of the low-dropout linear regulator and the output voltage of the low-dropout linear regulator is less than the minimum voltage of the reference voltage range. The pulse generation module generates and outputs a third pulse signal having a start time identical to that of the first indication signal and a pulse width equal to a target duration based on the first indication signal. The acceleration module is configured to accelerate the voltage adjustment circuit's adjustment of the low-dropout linear regulator's output voltage during the process of receiving the third pulse signal and to stop the acceleration after receiving the third pulse signal. Thus, starting from the time when the input voltage of the low-dropout linear regulator is less than the minimum voltage for normal operation of the low-dropout linear regulator and the output voltage of the low-dropout linear regulator is less than the minimum voltage of the reference voltage range, the voltage adjustment circuit's adjustment of the low-dropout linear regulator's output voltage is accelerated for a target duration and then stopped after the target duration has elapsed, thereby reducing power consumption.

[0041] Furthermore, the acceleration module can not only accelerate the voltage adjustment circuit's adjustment of the output voltage of the low-voltage difference linear regulator after the output voltage overshoots or undershoots, but also accelerate the voltage adjustment circuit's adjustment of the output voltage of the low-voltage difference linear regulator after the input voltage of the low-voltage difference linear regulator is too low, resulting in the output voltage being too low. Even if the input voltage of the low-voltage difference linear regulator is too low, resulting in the output voltage of the low-voltage difference linear regulator being unable to recover to the target voltage, the acceleration module will stop accelerating the voltage adjustment circuit's adjustment of the output voltage of the low-voltage difference linear regulator after the target time has passed, thereby further reducing power consumption.

[0042] In one possible implementation, Figure 3 As shown, the comparison module includes a first comparator HS_COMP1, a second comparator HS_COMP2, a second NOR gate NOR2 and an eighth NOR gate INV8, wherein the first comparator HS_COMP1 and the second comparator HS_COMP2 are both high-speed comparators; a non-inverting input terminal of the first comparator HS_COMP1 is connected to the non-inverting input terminal of the differential amplifier EA for inputting a voltage to be compared, and an inverting input terminal of the first comparator HS_COMP1 is used for inputting a first reference voltage, wherein the voltage to be compared is proportional to the output voltage of the low-dropout linear regulator, and a ratio of the voltage to be compared to the output voltage of the low-dropout linear regulator is a target ratio, which is equal to R1 / (R2+R1). The first reference voltage is equal to the product of the maximum voltage in the reference voltage range and the target ratio; the positive input terminal of the second comparator HS_COMP2 is used to input the second reference voltage, and the inverting input terminal of the second comparator HS_COMP2 is connected to the positive input terminal of the differential amplifier EA, for inputting the voltage to be compared, wherein the second reference voltage is equal to the product of the minimum voltage in the reference voltage range and the target ratio; the two input terminals of the second NOR gate NOR2 are respectively connected to the output terminal of the first comparator HS_COMP1 and the output terminal of the second comparator HS_COMP2, and the output terminal of the second NOR gate NOR2 is connected to the input terminal of the eighth NOR gate INV8; the output terminal of the eighth NOR gate INV8 is the output terminal of the comparison module.

[0043] When the output voltage of the low-dropout linear regulator is the target voltage, the voltage to be compared is greater than the second reference voltage and less than the first reference voltage, so that the first comparator HS_COMP1 and the second comparator HS_COMP2 both output a low level, and then the second NOR gate NOR2 outputs a high level, and the eighth NOT gate INV8 outputs a low level.

[0044] After the output voltage of the low-voltage difference linear regulator undershoots, the voltage to be compared is less than the second reference voltage and less than the first reference voltage, so that the level values ​​output by the first comparator HS_COMP1 and the second comparator HS_COMP2 are different, and then the second NOR gate NOR2 outputs a low level and the eighth NOR gate INV8 outputs a high level; after the output voltage of the low-voltage difference linear regulator overshoots, the voltage to be compared is greater than the second reference voltage and greater than the first reference voltage, so that the level values ​​output by the first comparator HS_COMP1 and the second comparator HS_COMP2 are different, and then the second NOR gate NOR2 outputs a low level and the eighth NOR gate INV8 outputs a high level; after the output voltage of the low-voltage difference linear regulator undershoots or overshoots, the output voltage of the low-voltage difference linear regulator is readjusted to the target voltage so that the eighth NOR gate INV8 starts to output a low level.

[0045] Therefore, after the output voltage of the low-dropout linear regulator overshoots or undershoots, the comparison module outputs a corresponding first pulse signal, and the first pulse signal is a high-level pulse signal.

[0046] After the input voltage of the low-voltage difference linear regulator is less than the minimum voltage for normal operation of the low-voltage difference linear regulator, and the output voltage of the low-voltage difference linear regulator is less than the minimum voltage of the reference voltage range, the voltage to be compared is less than the second reference voltage and less than the first reference voltage, so that the level values ​​output by the first comparator HS_COMP1 and the second comparator HS_COMP2 are different, and then the second OR gate NOR2 outputs a low level, and the eighth NOT gate INV8 outputs a high level; after the input voltage of the low-voltage difference linear regulator is less than the minimum voltage for normal operation of the low-voltage difference linear regulator, and the output voltage of the low-voltage difference linear regulator is less than the minimum voltage of the reference voltage range, since the input voltage of the low-voltage difference linear regulator is not sufficient to adjust the output voltage of the low-voltage difference linear regulator to the target voltage, the eighth NOT gate INV8 continues to output a high level.

[0047] Therefore, the comparison module outputs a first indication signal with a high level value after the input voltage of the low-voltage difference linear regulator is lower than the minimum voltage for normal operation of the low-voltage difference linear regulator and the output voltage of the low-voltage difference linear regulator is lower than the minimum voltage of the reference voltage range.

[0048] In an embodiment of the present application, by adopting a comparison module including a first comparator HS_COMP1, a second comparator HS_COMP2, a second NOR gate NOR2 and an eighth NOR gate INV8, it is possible to output a corresponding first pulse signal after the output voltage of the low-voltage difference linear regulator overshoots or undershoots, and continuously output a first indication signal with a constant level value after the input voltage of the low-voltage difference linear regulator is less than the minimum voltage for normal operation of the low-voltage difference linear regulator and the output voltage of the low-voltage difference linear regulator is less than the minimum voltage of the reference voltage range. The structure of the comparison module can also be made simple, the cost is low, and it is easy to implement.

[0049] Since the pulse generating module needs to generate the third pulse signal according to the first indication signal with unchanged level value, it is easy to cause the pulse width of the second pulse signal generated by the pulse generating module according to the first pulse signal to be narrower than the pulse width of the first pulse signal. To solve this problem:

[0050] In one possible implementation, the pulse generating module includes a first pulse generating unit and a second pulse generating unit; the first pulse generating unit is connected to the output end of the eighth NOT gate INV8 in the comparison module, and is used to generate a fourth pulse signal according to the first pulse signal, and output the fourth pulse signal, and is also used to generate a second indication signal with a constant level value according to the first indication signal, and output the second indication signal, wherein the fourth pulse signal is a single pulse signal, the pulse width of the fourth pulse signal is greater than the pulse width of the first pulse signal, and the start time of the second indication signal is the same as the start time of the first indication signal; the second pulse generating unit is connected to the first pulse generating unit, and is used to generate a second pulse signal according to the fourth pulse signal, and is also used to generate a third pulse signal according to the second indication signal, wherein the pulse width of the fourth pulse signal is greater than the pulse width of the second pulse signal.

[0051] In an embodiment of the present application, the first pulse generating unit generates a fourth pulse signal based on the first pulse signal, the second pulse generating unit generates a second pulse signal based on the fourth pulse signal, and the first pulse generating unit generates a second indication signal based on the first indication signal, and the second pulse generating unit generates a third pulse signal based on the second indication signal, wherein the pulse width of the fourth pulse signal is greater than the pulse width of the second pulse signal. Therefore, compared to directly using the first pulse signal as the second pulse signal, in the embodiment of the present application, a fourth pulse signal with a wider pulse width is first generated based on the first pulse signal, and then a second pulse signal is generated based on the fourth pulse signal, so that the pulse width of the second pulse signal is as wide as possible, and thus the acceleration module can fully accelerate the voltage adjustment circuit to adjust the output voltage of the low-voltage difference linear regulator, thereby improving the efficiency of the voltage adjustment circuit in adjusting the output voltage of the low-voltage difference linear regulator.

[0052] In one possible implementation, Figure 4As shown, the first pulse generating unit includes a first NOT gate INV1, a first P-channel transistor MP1, a first N-channel transistor MN1, a first current source I1, a first capacitor C1, a second NOT gate INV2, a third NOT gate INV3, a first NOR gate NOR1 and a fourth NOT gate INV4; the input end of the first NOT gate INV1 is connected to the output end of the eighth NOT gate INV8 in the comparison module to achieve connection with the output end of the comparison module, the output end of the first NOT gate INV1 is connected to the gate of the first P-channel transistor MP1, and the output end of the first NOT gate INV1 is connected to the gate of the first N-channel transistor MN1; the source of the first P-channel transistor MP1 is connected to the power supply VDD, and the drain of the first P-channel transistor MP1 is connected to the gate of the first capacitor C1. The first end is connected; the source of the first N-channel transistor MN1 is connected to the negative electrode of the first current source I1, and the drain of the first N-channel transistor MN1 is connected to the first end of the first capacitor C1; the positive electrode of the first current source I1 is grounded; the second end of the first capacitor C1 is grounded; the input end of the second NOT gate INV2 is connected to the first end of the first capacitor C1, and the output end of the second NOT gate INV2 is connected to the input end of the third NOT gate INV3; the output end of the third NOT gate INV3 is connected to the first input end of the first NOR gate NOR1; the second input end of the first NOR gate NOR1 is connected to the output end of the comparison module, and the output end of the first NOR gate NOR1 is connected to the input end of the fourth NOT gate INV4; the output end of the fourth NOT gate INV4 is connected to the second pulse generating unit.

[0053] When the output voltage of the low-dropout linear regulator reaches the target voltage, the eighth inverter INV8 of the comparison module outputs a low level. Based on this, the first inverter INV1 outputs a high level, the first P-channel transistor MP1 turns off, the first N-channel transistor MN1 turns on, and the first capacitor C1 slowly discharges under the action of the first current source I1 until the voltage at the first end of the first capacitor C1 is sufficiently low. At this time, the second inverter INV2 outputs a high level, the third inverter INV3 outputs a low level, the first NOR gate NOR1 outputs a high level, and the fourth inverter INV4 outputs a low level.

[0054] After the output voltage of the low-voltage difference linear regulator overshoots or undershoots, the eighth inverter INV8 of the comparison module outputs a first pulse signal, which is a high-level pulse signal, that is, the first pulse signal suddenly changes from a low level to a high level at its start time and suddenly changes from a high level to a low level at its end time. Based on this, when the output of the eighth NOT gate INV8 suddenly changes from a low level to a high level, the first NOT gate INV1 outputs a low level, the first P-channel transistor MP1 is turned on, the first N-channel transistor MN1 is turned off, and the first capacitor C1 is quickly charged until the voltage at the first end of the first capacitor C1 is high enough. At this time, the second NOT gate INV2 outputs a low level, the third NOT gate INV3 outputs a high level, the first NOR gate NOR1 outputs a low level, and the fourth NOT gate INV4 outputs a high level; when the output of the eighth NOT gate INV8 suddenly changes from a high level to a low level, the first NOT gate INV1 outputs a high level, the first P-channel transistor MP1 is turned off, the first N-channel transistor MN1 is turned on, and the first capacitor C1 is slowly discharged until the voltage at the first end of the first capacitor C1 is low enough. At this time, the second NOT gate INV2 outputs a high level, the third NOT gate INV3 outputs a low level, the first NOR gate NOR1 outputs a high level, and the fourth NOT gate INV4 outputs a low level. Therefore, in the process of the eighth NOT gate INV8 of the comparison module outputting the first pulse signal, the fourth NOT gate INV4 in the first pulse generating unit can output the fourth pulse signal, which is a high-level pulse signal, and the pulse width of the fourth pulse signal is greater than the pulse width of the first pulse signal.

[0055] After the input voltage of the low-voltage difference linear regulator is less than the minimum voltage for normal operation of the low-voltage difference linear regulator, and the output voltage of the low-voltage difference linear regulator is less than the minimum voltage of the reference voltage range, the eighth NOT gate INV8 of the comparison module outputs a first indication signal with a high level value. Based on this, the first NOT gate INV1 outputs a low level, the first P-channel transistor MP1 is turned on, the first N-channel transistor MN1 is turned off, and the first capacitor C1 is quickly charged until the voltage at the first end of the first capacitor C1 is high enough. At this time, the second NOT gate INV2 outputs a low level, the third NOT gate INV3 outputs a high level, the first NOR gate NOR1 outputs a low level, and the fourth NOT gate INV4 outputs a high level. Therefore, during the process of the eighth NOT gate INV8 of the comparison module outputting the first indication signal, the fourth NOT gate INV4 in the first pulse generating unit can output a second indication signal with a high level value.

[0056] In an embodiment of the present application, by adopting a first pulse generating unit including a first NOT gate INV1, a first P-channel transistor MP1, a first N-channel transistor MN1, a first current source I1, a first capacitor C1, a second NOT gate INV2, a third NOT gate INV3, a first NOR gate NOR1 and a fourth NOT gate INV4, it is possible to generate a fourth pulse signal with a wider pulse width according to the first pulse signal, and it is also possible to generate a second indication signal with a constant level value according to the first indication signal.

[0057] In one possible implementation, Figure 4 As shown, the second pulse generating unit includes a fifth NOT gate INV5, a sixth NOT gate INV6, a second P-channel transistor MP2, a second N-channel transistor MN2, a second current source I2, a second capacitor C2, a seventh NOT gate INV7 and an exclusive OR gate XNOR1; the input end of the fifth NOT gate INV5 is connected to the output end of the fourth NOT gate INV4, the output end of the fifth NOT gate INV5 is connected to the input end of the sixth NOT gate INV6, the output end of the sixth NOT gate INV6 is connected to the gate of the second P-channel transistor MP2, and the output end of the sixth NOT gate INV6 is connected to the gate of the second N-channel transistor MN2; the source of the second P-channel transistor MP2 is connected to the gate of the capacitor C2. The first circuit 1 is connected to the power supply VDD, the second P-channel transistor MP2 is connected to the first end of the second capacitor C2; the source of the second N-channel transistor MN2 is connected to the negative electrode of the second current source I2, and the drain of the second N-channel transistor MN2 is connected to the first end of the second capacitor C2; the positive electrode of the second current source I2 is grounded; the second end of the second capacitor C2 is grounded; the input end of the seventh NOT gate INV7 is connected to the first end of the second capacitor C2, the output end of the seventh NOT gate INV7 is connected to the first input end of the EXCLUSIVE-OR gate XNOR1, the second input end of the EXCLUSIVE-OR gate XNOR1 is connected to the output end of the fifth NOT gate INV5, and the output end of the EXCLUSIVE-OR gate XNOR1 is connected to the acceleration module.

[0058] When the output voltage of the low-voltage difference linear regulator is the target voltage, the fourth NOT gate INV4 in the first pulse generating unit outputs a low level. Based on this, the fifth NOT gate INV5 outputs a high level, the sixth NOT gate INV6 outputs a low level, the second N-channel transistor MN2 is turned off, the second P-channel transistor MP2 is turned on, and the second capacitor C2 is quickly charged until the voltage at the first end of the second capacitor C2 is large enough, the seventh NOT gate INV7 outputs a low level, and the XNOR gate XNOR1 outputs a low level.

[0059] After the output voltage of the low-voltage difference linear regulator overshoots or undershoots, the fourth inverter INV4 in the first pulse generating unit outputs a fourth pulse signal. The fourth pulse signal is a high-level pulse signal, that is, the fourth pulse signal suddenly changes from a low level to a high level at its start time and suddenly changes from a high level to a low level at its end time. Based on this, when the output of the fourth NOT gate INV4 suddenly changes from a low level to a high level, the fifth NOT gate INV5 outputs a low level, the sixth NOT gate INV6 outputs a high level, the second N-channel transistor MN2 is turned on, the second P-channel transistor MP2 is turned off, and the second capacitor C2 is slowly discharged under the action of the second current source I2. At the beginning of discharge, the voltage at the first end of the second capacitor C2 is large, the seventh NOT gate INV7 outputs a low level, and the EXOR gate XNOR1 outputs a high level. After a period of discharge, the voltage at the first end of the second capacitor C2 is small enough, the seventh NOT gate INV7 outputs a high level, and the EXOR gate XNOR1 outputs a low level; when the output of the fourth NOT gate INV4 suddenly changes from a high level to a low level, the fifth NOT gate INV5 outputs a high level, the sixth NOT gate INV6 outputs a low level, the second N-channel transistor MN2 is turned off, the second P-channel transistor MP2 is turned on, and the second capacitor C2 is quickly charged until the voltage at the first end of the second capacitor C2 is large enough, the seventh NOT gate INV7 outputs a low level, and the EXOR gate XNOR1 outputs a low level. Therefore, in the process of the fourth NOT gate INV4 in the first pulse generating unit outputting the fourth pulse signal, the XNOR gate XNOR1 in the second pulse generating unit can output the second pulse signal, which is a high-level pulse signal, and the pulse width of the second pulse signal is smaller than the pulse width of the fourth pulse signal.

[0060] After the input voltage of the low-voltage dropout linear regulator is less than the minimum voltage for normal operation of the low-voltage dropout linear regulator, and the output voltage of the low-voltage dropout linear regulator is less than the minimum voltage of the reference voltage range, the fourth NOT gate INV4 in the first pulse generating unit outputs a second indication signal with a high level. Based on this, after the output of the fourth NOT gate INV4 starts to output the second indication signal, the fifth NOT gate INV5 outputs a low level, the sixth NOT gate INV6 outputs a high level, the second N-channel transistor MN2 is turned on, the second P-channel transistor MP2 is turned off, and the second capacitor C2 slowly discharges under the action of the second current source I2. At the beginning of discharge, the voltage at the first end of the second capacitor C2 is relatively large, the seventh NOT gate INV7 outputs a low level, and the XNOR gate XNOR1 outputs a high level. After a period of discharge, the voltage at the first end of the second capacitor C2 is sufficiently small, the seventh NOT gate INV7 outputs a high level, and the XNOR gate XNOR1 outputs a low level. Therefore, in the process of the fourth NOT gate INV4 in the first pulse generating unit outputting the second indication signal, the XNOR gate XNOR1 in the second pulse generating unit can output the third pulse signal and maintain a low level subsequently. The pulse width of the third pulse signal is generally the same as the pulse width of the second pulse signal.

[0061] In an embodiment of the present application, by adopting a second pulse generating unit including a fifth NOT gate INV5, a sixth NOT gate INV6, a second P-channel transistor MP2, a second N-channel transistor MN2, a second current source I2, a second capacitor C2, a seventh NOT gate INV7 and an XNOR gate XNOR1, it is possible to generate a second pulse signal according to the fourth pulse signal, and it is also possible to generate a third pulse signal according to a second indication signal whose level value remains unchanged.

[0062] In one possible implementation, Figure 5 As shown, the acceleration module includes a third N-channel transistor MN3 and a fourth current source; the gate of the third N-channel transistor MN3 is connected to the output end of the XNOR gate XNOR1, the source of the third N-channel transistor MN3 is connected to the negative electrode of the fourth current source, and the drain of the third N-channel transistor MN3 is connected to the negative electrode of the third current source I3 in the voltage regulation circuit to achieve connection with the voltage regulation circuit. Therefore, the acceleration module has a simple structure, low cost, and is easy to implement.

[0063] The specific way of connecting the drain of the third N-channel transistor MN3 to the negative electrode of the third current source I3 in the voltage adjustment circuit can be as follows: Figure 2 and Figure 5 As shown, the drain of the third N-channel transistor MN3 is connected to the differential amplifier EA in the voltage adjustment circuit through the port a, and the port a is connected to the negative electrode of the third current source I3 in the differential amplifier EA.

[0064] In one possible implementation, the acceleration module further includes a fourth N-channel transistor MN4 and a fifth N-channel transistor MN5. The voltage adjustment circuit includes a first large capacitance node C01 and a second large capacitance node C02. The first large capacitance node C01 is used to discharge when the voltage adjustment circuit adjusts the output voltage of the low-voltage difference linear regulator to a target voltage, and the second large capacitance node C02 is used to charge when the voltage adjustment circuit adjusts the output voltage of the low-voltage difference linear regulator to the target voltage; the gate of the fourth N-channel transistor MN4 is connected to the output end of the XNOR gate XNOR1, the source of the fourth N-channel transistor MN4 is grounded, and the drain of the fourth N-channel transistor MN4 is connected to the first large capacitance node; the gate of the fifth N-channel transistor MN5 is connected to the output end of the XNOR gate, the source of the fifth N-channel transistor MN5 is connected to the second large capacitance node, and the drain of the fifth N-channel transistor MN5 is connected to the power supply VDD.

[0065] The specific manner of connecting the drain of the fourth N-channel transistor MN4 to the first large capacitor node may be as follows: Figure 2 and Figure 5As shown, the drain of the fourth N-channel transistor MN4 is connected to the first large capacitance node through the port b; the source of the fifth N-channel transistor MN5 is connected to the second large capacitance node in the following specific manner: Figure 2 and Figure 5 As shown, the source of the fifth N-channel transistor MN5 is connected to the second large capacitance node through the port c.

[0066] In addition, the first large capacitance node C01 and the second large capacitance node C02 are both large capacitance nodes, which can be set as follows: Figure 2 The nodes in the loop formed by EA, MPOWER and RFB2 shown, for example, the large capacitor node can be a compensation capacitor node in the loop, or a node connected to the gate of the power tube.

[0067] Thus, the first large capacitance node C01 and the fourth N-channel transistor MN4 form a pull-down path, and the second large capacitance node C02 and the fifth N-channel transistor MN5 form a pull-up path. When the output terminal of the XNOR gate XNOR1 outputs the second signal pulse or the third signal pulse, the fourth N-channel transistor MN4 and the fifth N-channel transistor MN5 are turned on, and both the pull-up path and the pull-down path are opened, which can increase the slew rate of the voltage regulation circuit and accelerate the voltage regulation circuit's adjustment of the output voltage of the low-dropout linear regulator.

[0068] Based on this:

[0069] After the output voltage of the low-dropout linear regulator overshoots or undershoots, the changes in the signals of each part of the low-dropout linear regulator are as follows: Figure 6 As shown; when the input voltage of the low-voltage dropout linear regulator is less than the minimum voltage for normal operation of the low-voltage dropout linear regulator, and the output voltage of the low-voltage dropout linear regulator is less than the minimum voltage of the reference voltage range, the changes of the signals of each part of the low-voltage dropout linear regulator are as shown in Figure 7 shown.

[0070] exist Figure 6 and Figure 7In the figure, VOUT is the output voltage of the low-dropout linear regulator, VREFH is the first reference voltage, VFB is the voltage to be compared, VREFL is the second reference voltage, VUPovershoot is the signal output by the first comparator HS_COMP1, VUPundershoot is the signal output by the second comparator HS_COMP2, VA is the signal output by the eighth inverter, VB is the signal output by the first inverter, VC is the voltage at the first end of the first capacitor C1, VD is the signal output by the third inverter, VPULSE1 is the signal output by the fourth inverter, VE is the signal output by the fifth inverter, VF is the signal output by the sixth inverter, VG is the voltage at the first end of the second capacitor C2, VH is the signal output by the seventh inverter, VPULSE is the signal output by the exclusive-OR gate XNOR1, and VIN is the voltage output by the power supply VDD.

[0071] pass Figure 6 and Figure 7 It can be seen that the pulse width of the fourth pulse signal is Tpulse1, the pulse widths of the second pulse signal and the third pulse signal are both Tpulse, and Tpulse1>Tpulse.

[0072] chip

[0073] An embodiment of the present application provides a chip, which includes the above-mentioned low-dropout linear regulator.

[0074] It should be noted that the chip of this embodiment includes the low voltage dropout linear regulator in the aforementioned embodiment and has corresponding beneficial effects, which will not be described in detail in this embodiment.

[0075] electronic devices

[0076] An embodiment of the present application provides an electronic device, which includes the above-mentioned low-dropout linear regulator.

[0077] It should be noted that the electronic device of this embodiment includes the low voltage dropout linear regulator in the aforementioned embodiment and has corresponding beneficial effects, which will not be described in detail in this embodiment.

[0078] It should be noted that, in this application, the N-channel transistor is usually NMOS, and the P-channel transistor is usually PMOS.

[0079] It should be noted that, in this article, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical factors in the process, method, article or device comprising the elements.

[0080] Not all steps and modules in the above processes and system structure diagrams are required, and certain steps or modules can be omitted according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The system structure described in the above embodiments can be a physical structure or a logical structure. That is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or may be implemented by certain components in multiple independent devices.

[0081] In the above embodiments, the hardware module can be implemented mechanically or electrically. For example, a hardware module can include a permanent dedicated circuit or logic (such as a dedicated processor, FPGA or ASIC) to complete the corresponding operation. The hardware module can also include programmable logic or circuits (such as a general-purpose processor or other programmable processors), which can be temporarily set by software to complete the corresponding operation. The specific implementation method (mechanical method, or dedicated permanent circuit, or temporarily set circuit) can be determined based on cost and time considerations.

[0082] The present application has been presented and described in detail above through the accompanying drawings and preferred embodiments. However, the present application is not limited to these disclosed embodiments. Based on the above multiple embodiments, those skilled in the art can know that the code review methods in the above different embodiments can be combined to obtain more embodiments of the present application, and these embodiments are also within the scope of protection of the present application.

Claims

1. A low voltage dropout linear regulator, characterized in that: include: a voltage regulating circuit and an acceleration circuit, wherein the acceleration circuit is connected to the voltage regulating circuit; The voltage adjustment circuit is configured to adjust the output voltage of the low-voltage-dropout linear regulator to a target voltage after the output voltage of the low-voltage-dropout linear regulator overshoots or undershoots; The acceleration circuit is configured to accelerate the adjustment of the output voltage of the low-voltage dropout linear regulator by the voltage adjustment circuit starting from when the output voltage of the low-voltage dropout linear regulator is outside a reference voltage range, and stop accelerating the adjustment of the output voltage of the low-voltage dropout linear regulator by the voltage adjustment circuit after a target duration, wherein the target voltage is within the reference voltage range, and the output voltage of the low-voltage dropout linear regulator is outside the reference voltage range when overshooting and undershooting; The acceleration circuit includes a comparison module, a pulse generation module and an acceleration module; The comparison module is configured to output a corresponding first pulse signal after the output voltage of the low-dropout linear regulator overshoots or undershoots, wherein the start time of the first pulse signal is the time when the corresponding overshoot or undershoot occurs, and the end time of the first pulse signal is the time when the output voltage of the low-dropout linear regulator first changes to within the reference voltage range after the corresponding overshoot or undershoot; The pulse generating module is connected to the comparing module, and is used to generate a second pulse signal according to the first pulse signal, and output the second pulse signal, wherein the start time of the second pulse signal is the same as the start time of the first pulse signal, the pulse width of the second pulse signal is equal to the target duration, and the pulse width of the second pulse signal is greater than the pulse width of the first pulse signal; The acceleration module is connected to the pulse generating module and is used to accelerate the adjustment of the output voltage of the low-voltage difference linear regulator by the voltage adjustment circuit during the process of receiving the second pulse signal, and stop accelerating the adjustment of the output voltage of the low-voltage difference linear regulator by the voltage adjustment circuit after completing the reception of the second pulse signal.

2. The low-dropout linear regulator according to claim 1, wherein: The comparison module is further configured to continuously output a first indication signal having a constant level value after the input voltage of the low-dropout linear regulator is less than a minimum voltage for normal operation of the low-dropout linear regulator and the output voltage of the low-dropout linear regulator is less than a minimum voltage of the reference voltage range; The pulse generating module is further configured to generate a third pulse signal according to the first indication signal and output the third pulse signal, wherein a start time of the third pulse signal is the same as a start time of the first indication signal, and a pulse width of the third pulse signal is equal to the target duration; The acceleration module is also used to accelerate the adjustment of the output voltage of the low-voltage difference linear regulator by the voltage adjustment circuit during the process of receiving the third pulse signal, and stop accelerating the adjustment of the output voltage of the low-voltage difference linear regulator by the voltage adjustment circuit after completing the reception of the third pulse signal.

3. The low-dropout linear regulator according to claim 2, wherein: The pulse generating module includes a first pulse generating unit and a second pulse generating unit; The first pulse generating unit is connected to the comparing module, and is configured to generate a fourth pulse signal according to the first pulse signal and output the fourth pulse signal, and is further configured to generate a second indication signal having a constant level value according to the first indication signal and output the second indication signal, wherein the pulse width of the fourth pulse signal is greater than the pulse width of the first pulse signal, and the start time of the second indication signal is the same as the start time of the first indication signal; The second pulse generating unit is connected to the first pulse generating unit, and is used to generate the second pulse signal according to the fourth pulse signal, and is also used to generate the third pulse signal according to the second indication signal, wherein the pulse width of the fourth pulse signal is greater than the pulse width of the second pulse signal.

4. The low-dropout linear regulator according to claim 3, wherein: The first pulse generating unit includes a first NOT gate, a first P-channel transistor, a first N-channel transistor, a first current source, a first capacitor, a second NOT gate, a third NOT gate, a first NOR gate, and a fourth NOT gate; The input end of the first NOT gate is connected to the output end of the comparison module, the output end of the first NOT gate is connected to the gate of the first P-channel transistor, and the output end of the first NOT gate is connected to the gate of the first N-channel transistor; the source of the first P-channel transistor is connected to a power supply, and the drain of the first P-channel transistor is connected to the first end of the first capacitor; the source of the first N-channel transistor is connected to the negative electrode of the first current source, and the drain of the first N-channel transistor is connected to the first end of the first capacitor; the positive electrode of the first current source is grounded; the second end of the first capacitor is grounded; the input end of the second NOT gate is connected to the first end of the first capacitor, and the output end of the second NOT gate is connected to the input end of the third NOT gate; the output end of the third NOT gate is connected to the first input end of the first NOR gate; the second input end of the first NOR gate is connected to the output end of the comparison module, and the output end of the first NOR gate is connected to the input end of the fourth NOR gate; the output end of the fourth NOR gate is connected to the second pulse generating unit.

5. The low-dropout linear regulator according to claim 4, wherein: The second pulse generating unit includes a fifth NOT gate, a sixth NOT gate, a second P-channel transistor, a second N-channel transistor, a second current source, a second capacitor, a seventh NOT gate and an XNOR gate; The input end of the fifth NOT gate is connected to the output end of the fourth NOT gate, the output end of the fifth NOT gate is connected to the input end of the sixth NOT gate, the output end of the sixth NOT gate is connected to the gate of the second P-channel transistor, and the output end of the sixth NOT gate is connected to the gate of the second N-channel transistor; the source of the second P-channel transistor is connected to a power supply, and the drain of the second P-channel transistor is connected to the first end of the second capacitor; the source of the second N-channel transistor is connected to the negative electrode of the second current source, and the drain of the second N-channel transistor is connected to the first end of the second capacitor; the positive electrode of the second current source is grounded; the second end of the second capacitor is grounded; the input end of the seventh NOT gate is connected to the first end of the second capacitor, the output end of the seventh NOT gate is connected to the first input end of the XNOR gate, the second input end of the XNOR gate is connected to the output end of the fifth NOT gate, and the output end of the XNOR gate is connected to the acceleration module.

6. The low-dropout linear regulator according to any one of claims 1 to 5, characterized in that: The comparison module includes a first comparator, a second comparator, a second NOR gate and an eighth NOR gate; The non-inverting input terminal of the first comparator is used to input a voltage to be compared, and the inverting input terminal of the first comparator is used to input a first reference voltage, wherein the voltage to be compared is proportional to the output voltage of the low-dropout linear regulator, and the ratio of the voltage to be compared to the output voltage of the low-dropout linear regulator is a target ratio, and the first reference voltage is equal to the product of the maximum voltage of the reference voltage range and the target ratio; The non-inverting input terminal of the second comparator is used to input a second reference voltage, and the inverting input terminal of the second comparator is used to input the voltage to be compared, wherein the second reference voltage is equal to the product of the minimum voltage of the reference voltage range and the target ratio; Two input terminals of the second NOR gate are connected to the output terminal of the first comparator and the output terminal of the second comparator respectively, and the output terminal of the second NOR gate is connected to the input terminal of the eighth NOT gate; The output end of the eighth NOT gate is the output end of the comparison module.

7. The low-dropout linear regulator according to claim 5, wherein: The acceleration module includes a third N-channel transistor and a fourth current source; The gate of the third N-channel transistor is connected to the output end of the XNOR gate, the source of the third N-channel transistor is connected to the negative electrode of the fourth current source, the drain of the third N-channel transistor is connected to the voltage adjustment circuit, and the positive electrode of the fourth current source is grounded.

8. The low-dropout linear regulator according to claim 7, wherein: The acceleration module further includes a fourth N-channel transistor and a fifth N-channel transistor, and the voltage adjustment circuit includes a first large capacitance node and a second large capacitance node, the first large capacitance node being configured to discharge when the voltage adjustment circuit adjusts the output voltage of the low-dropout linear regulator to the target voltage, and the second large capacitance node being configured to charge when the voltage adjustment circuit adjusts the output voltage of the low-dropout linear regulator to the target voltage; The gate of the fourth N-channel transistor is connected to the output terminal of the XNOR gate, the source of the fourth N-channel transistor is grounded, and the drain of the fourth N-channel transistor is connected to the first large capacitor node; The gate of the fifth N-channel transistor is connected to the output end of the XNOR gate, the source of the fifth N-channel transistor is connected to the second large capacitor node, and the drain of the fifth N-channel transistor is connected to a power supply.

9. The low-dropout linear regulator according to claim 1, wherein: The voltage adjustment circuit includes a differential amplifier, a third current source, a target P-channel transistor, a first resistor and a second resistor; The power input terminal of the differential amplifier is used to input the input voltage of the low-dropout linear regulator, the port of the differential amplifier for inputting the tail current is connected to the negative electrode of the third current source, the non-inverting input terminal of the differential amplifier is connected to the first end of the first resistor and the first end of the second resistor, the inverting input terminal of the differential amplifier is used to input a reference voltage, and the output terminal of the differential amplifier is connected to the gate of the target P-channel transistor; The positive electrode of the third current source is grounded, and the negative electrode of the third current source is connected to the acceleration circuit; The source of the target P-channel transistor is used to input the input voltage of the low-dropout linear regulator, and the drain of the target P-channel transistor is connected to the second end of the second resistor; The second end of the first resistor is grounded; The first end of the second resistor is connected to the output port of the low voltage dropout linear regulator.

10. A chip, characterized in that: The invention comprises the low voltage drop linear regulator according to any one of claims 1 to 9.

11. An electronic device, characterized in that: The invention comprises the low voltage drop linear regulator according to any one of claims 1 to 9.

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