Low Dropout Linear Regulator and Voltage Stabilization Method

Abstract

An embodiment of the present invention relates to a low-voltage-dropout linear regulator, comprising: a clamping circuit having a first branch for clamping a system input voltage so that the voltage of the first branch is maintained within a preset voltage range; an output voltage sensing circuit for increasing the output voltage when the system output voltage is greater than a preset voltage threshold; and decreasing the output voltage when the system output voltage is less than the preset voltage threshold; a conversion circuit for increasing the current of the conversion circuit when the voltage of the output voltage sensing circuit increases, and decreasing the current when the voltage of the output voltage sensing circuit decreases; and an output stage circuit for decreasing the system output voltage when the current of the conversion circuit increases, and increasing the system output voltage when the current of the conversion circuit decreases.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a low voltage difference linear regulator and a voltage stabilization method. Background Art

[0002] With the advancement of integrated circuit technology, systems-on-chip (SoCs) are gradually moving towards low voltage and ultra-low power consumption. Traditional capless low-dropout linear regulators (LDOs) utilize a P-type metal-oxide-semiconductor (PMOS) power output structure with an error amplifier loop. These devices require a large implementation area, have suboptimal power consumption, and suffer from significant output pole offsets under varying operating conditions, making compensation difficult.

[0003] Currently, there are several main ways to implement on-chip LDO: (1) Using NMOS of the error amplifier as the output stage. Although the influence of the output pole on the loop stability can be solved, low voltage difference output cannot be achieved without designing a charge pump as the gate drive of the N-type metal-oxide-semiconductor (NMOS), and the power consumption is not optimized. (2) Using an off-chip Anycap structure, by moving the main pole of the loop to the output pole, the loop compensation problem is solved and the power supply noise is reduced. However, this design method requires the addition of an off-chip PIN interface, which is not optimized for chips with many pins and many voltage domains. (3) Improving the inverted voltage follower (FVF) type LDO, by connecting the source of two MOS in series to achieve a follow-up output of a specified voltage bias. This design method can realize a pure on-chip power supply, can achieve heavy-load output, and reasonably select the device size to achieve single-pole stability. However, the need to provide relatively accurate voltage and current bias during the chip startup phase is not optimal from a design cost perspective. Therefore, implementing an on-chip LDO has become an urgent problem to be solved. Summary of the Invention

[0004] The purpose of the present invention is to provide a low voltage dropout linear regulator to solve the problems existing in the prior art.

[0005] To achieve the above objectives, the present invention provides a low-dropout linear regulator in a first aspect, comprising:

[0006] a clamping circuit, the clamping circuit having a first branch, an input end of the clamping circuit being connected to a system voltage input end, and being configured to clamp the system input voltage so that the voltage of the first branch remains within a preset voltage range;

[0007] an output voltage sensing circuit, wherein a first terminal of the output voltage sensing circuit is connected to the clamping circuit and then to ground, and a second terminal of the output voltage sensing circuit is connected to the system output voltage terminal, and is used to detect the system output voltage, and when the system output voltage is greater than a preset voltage threshold, control the output voltage to increase; when the system output voltage is less than the preset voltage threshold, control the output voltage to decrease;

[0008] a conversion circuit, wherein a first end of the conversion circuit is connected to the input end of the clamping circuit, and a second end of the conversion circuit is connected to the output voltage sensing circuit, and is configured to increase a current of the conversion circuit when the voltage of the output voltage sensing circuit increases, and decrease the current when the voltage of the output voltage sensing circuit decreases;

[0009] An output stage circuit, wherein a first end of the output stage circuit is connected to a third end of the conversion circuit, and a second end of the output stage circuit is connected to a system output voltage end, and is used to control the system output voltage to decrease when the current of the conversion circuit increases, and to control the system output voltage to increase when the current of the conversion circuit decreases.

[0010] In a possible implementation, the clamping circuit includes a clamping diode, a first resistor, and a first MOS transistor;

[0011] The first end of the clamping diode is connected to the system voltage input end, the second end of the clamping diode is connected to the first end of the first resistor and the gate of the first MOS transistor; the second end of the first resistor is connected to the drain of the first MOS transistor and the ground end respectively.

[0012] In a possible implementation, the preset voltage range includes a first level and a second level, a branch between the gate of the first MOS transistor and the first end of the first resistor is a first branch; the first branch has a first branch voltage;

[0013] When the system input voltage is less than the clamping level, the first branch voltage is pulled down to a preset first level;

[0014] When the system input voltage is greater than the clamping level, the first branch voltage is raised to a preset second level.

[0015] In a possible implementation, the conversion circuit includes: a second MOS transistor, a third MOS transistor, and a fourth MOS transistor;

[0016] The source of the second MOS transistor is respectively connected to the first end of the clamping diode and the system voltage input end, the gate of the second MOS transistor is respectively connected to the drain of the second MOS transistor and the drain of the third MOS transistor, the gate of the third MOS transistor is connected to the system voltage output end, the source of the third MOS transistor is connected to the drain of the fourth MOS transistor, and the source of the fourth MOS transistor is respectively connected to the second end of the first resistor and the ground end.

[0017] In a possible implementation, a second branch is provided between the third MOS transistor and the fourth MOS transistor, and the second branch has a second branch voltage.

[0018] In a possible implementation, the output voltage sensing circuit includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, and a second resistor;

[0019] The source of the fifth MOS transistor is respectively connected to the source of the seventh MOS transistor and the system output end; the gate of the fifth MOS transistor is respectively connected to the gate of the seventh MOS transistor, the drain of the seventh MOS transistor, and the source of the eighth MOS transistor; the drain of the fifth MOS transistor is respectively connected to the drain of the sixth MOS transistor and the gate of the fourth MOS transistor; the gate of the eighth MOS transistor is respectively connected to the drain of the eighth MOS transistor and the source of the ninth MOS transistor; the gate of the ninth MOS transistor is respectively connected to the drain of the ninth MOS transistor and the first end of the second resistor; and the second end of the second resistor is respectively connected to the source of the sixth MOS transistor, the drain of the first MOS transistor, the source of the fourth MOS transistor, the second end of the first resistor, and the ground end.

[0020] In a possible implementation, the output stage circuit includes a tenth MOS transistor, an eleventh MOS transistor, and a third resistor;

[0021] The source of the tenth MOS transistor is respectively connected to the source of the eleventh MOS transistor, the source of the second MOS transistor, and the system power input terminal; the gate of the tenth MOS transistor is connected to the gate of the second MOS transistor; the drain of the tenth MOS transistor is connected to the first end of the third resistor; the second end of the third resistor is connected to the source of the first MOS transistor; and the drain of the eleventh MOS transistor is respectively connected to the source of the fifth MOS transistor, the source of the seventh MOS transistor, and the system voltage output terminal.

[0022] A second aspect of the present invention provides a voltage stabilization method based on a low voltage dropout linear regulator, the method comprising:

[0023] The clamping circuit has a first branch, and the clamping circuit clamps the system input voltage so that the voltage of the first branch is maintained within a preset voltage range;

[0024] The output voltage sensing circuit increases the output voltage when the system output voltage is greater than the preset voltage threshold; and decreases the output voltage when the system output voltage is less than the preset voltage threshold.

[0025] The conversion circuit increases the current of the conversion circuit when the voltage of the output voltage sensing circuit increases, and decreases the current when the voltage of the output voltage sensing circuit decreases;

[0026] The output stage circuit controls the system output voltage to decrease when the current of the conversion circuit increases, and controls the system output voltage to increase when the current of the conversion circuit decreases.

[0027] In a possible implementation, the preset voltage range includes a first level and a second level, and the first branch has a first branch voltage;

[0028] When the system input voltage is less than the clamping level, the first branch voltage is pulled down to a preset first level;

[0029] When the system input voltage is greater than the clamping level, the first branch voltage is raised to a preset second level.

[0030] By applying the low-voltage difference linear regulator provided by the embodiment of the present invention, when the system input voltage rises, if the system output voltage is higher than the preset voltage threshold, the low-voltage difference linear regulator controls the output voltage to decrease to complete the negative feedback loop. When the system output voltage is lower than the preset voltage threshold, the control system output voltage rises to be equal to the system input voltage, thereby realizing low-voltage difference linear voltage regulation. The system input voltage of this application is generally high. Through the low-voltage difference linear regulator, the system input voltage can be maintained at a lower voltage, and the power consumption is low, the circuit structure is simple, and the voltage stabilization effect is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A structural diagram of a low-dropout linear regulator provided by an embodiment of the present invention;

[0032] Figure 2 for Figure 1 A specific embodiment of

[0033] Figure 3 for Figure 2 A magnified view of the clamping circuit in FIG.

[0034] Figure 4 for Figure 2 Method diagram of the conversion circuit in;

[0035] Figure 5 for Figure 2 A magnified view of the output voltage sensing circuit in FIG;

[0036] Figure 6 for Figure 2 An enlarged view of the output stage circuit in FIG;

[0037] Figure 7 This is a flow chart of a voltage stabilization method based on a low-dropout linear regulator provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only some, not all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0039] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments.

[0040] Figure 1 A schematic diagram of a low-dropout linear regulator flow diagram provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the low voltage dropout linear regulator includes: a clamping circuit 10 , a conversion circuit 20 , an output stage circuit 30 and an output voltage sensing circuit 40 .

[0041] The clamping circuit 10 has a first branch, and the input end of the clamping circuit 10 is connected to the system voltage input end, and is used to clamp the system input voltage so that the voltage of the first branch is maintained within a preset voltage range;

[0042] The first end of the output voltage sensing circuit 40 is connected to the clamping circuit 10 and then to the ground, and the second end of the output voltage sensing circuit 40 is connected to the system output voltage end, so as to increase the output voltage when the system output voltage is greater than a preset voltage threshold; and decrease the output voltage when the system output voltage is less than the preset voltage threshold, thereby stabilizing the system input voltage within a set range.

[0043] A first terminal of the conversion circuit 20 is connected to the input terminal of the clamp circuit 10, and a second terminal of the conversion circuit 20 is connected to the output voltage sensing circuit 40, so that when the voltage of the output voltage sensing circuit 40 increases, the current of the conversion circuit 20 increases, and when the voltage of the output voltage sensing circuit 40 decreases, the current decreases;

[0044] The first end of the output stage circuit 30 is connected to the third end of the conversion circuit 20, and the second end of the output stage circuit 30 is connected to the system output voltage end, which is used to control the system output voltage to decrease when the current of the conversion circuit 20 increases, and to control the system output voltage to increase when the current of the conversion circuit 20 decreases.

[0045] Figure 2 for Figure 1 A specific embodiment of Figure 3 This is an enlarged view of the clamping circuit, combined with Figure 1-Figure 3 The clamping circuit 10 includes a clamping diode Z1, a first resistor R1, and a first MOS transistor M1; a first end of the clamping diode Z1 is connected to a system voltage input terminal, a second end of the clamping diode Z1 is connected to a first end of the first resistor R1 and a gate of the first MOS transistor M1; a second end of the first resistor R1 is connected to a drain of the first MOS transistor M1 and a ground terminal, respectively.

[0046] The preset voltage range includes a first level and a second level. The branch between the gate of the first MOS transistor M1 and the first end of the first resistor R1 is the first branch. The first branch has a first branch voltage. When the system input voltage is less than the clamping level, the first branch voltage is pulled down to the preset first level. When the system input voltage is greater than the clamping level, the first branch voltage is raised to the preset second level.

[0047] Among them, see Figure 2 The first branch voltage is Node A, with a first level of 0V and a second level of VIN-5V. Clamping diode Z1 and R1 are connected in series between the system input voltage terminal VIN and ground terminal GND. The clamping level of clamping diode Z1 is determined by the process and is typically around 5V. When the system input voltage VIN is lower than the clamping level, Node A is pulled down to approximately zero level by first resistor R1. At this time, the source level of first MOS transistor M1, due to the source follower effect of the source, will be approximately 1V higher than zero level under current injection conditions, a gate-source level. This level has an upper limit of approximately 4V. When the system input voltage VIN is higher than the clamping level of clamping diode Z1, Node A will be approximately 5V lower than the system input voltage VIN due to the clamping effect of clamping diode Z1. The source level of first MOS transistor M1 raises the Node A level to approximately 4V below VIN.

[0048] See also Figure 2 and Figure 4The conversion circuit 20 is a low-to-high (L2H) conversion circuit, including: a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4; the source of the second MOS transistor M2 is respectively connected to the first end of the clamping diode Z1 and the system voltage input end, the gate of the second MOS transistor M2 is respectively connected to the drain of the second MOS transistor M2 and the drain of the third MOS transistor M3, the gate of the third MOS transistor M3 is connected to the system voltage output end, the source of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4, and the source of the fourth MOS transistor M4 is respectively connected to the second end of the first resistor R1 and the ground end.

[0049] When the system output voltage OUT is clamped to a low voltage level, the source follower function of the third MOS transistor M3 can limit the second branch voltage Node B to approximately 1V lower than the system output voltage OUT. The current drain-gate level of the fourth MOS transistor M4 is determined by the structure of the output voltage sensing circuit 40, which can achieve power consumption control of the conversion circuit 20 and simultaneously transmit output level information to the second MOS transistor M2.

[0050] See also Figure 2 and Figure 5 The output voltage sensing circuit 40 includes a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, and a second resistor R2. The source of the fifth MOS transistor M5 is respectively connected to the source of the seventh MOS transistor M7 and the system output terminal. The gate of the fifth MOS transistor M5 is respectively connected to the gate of the seventh MOS transistor M7, the drain of the seventh MOS transistor M7, and the source of the eighth MOS transistor M8. The drain of the fifth MOS transistor M5 is respectively connected to the drain of the sixth MOS transistor M6 and the gate of the fourth MOS transistor M4. The gate of the eighth MOS transistor M8 is respectively connected to the drain of the eighth MOS transistor M8 and the source of the ninth MOS transistor M9. The gate of the ninth MOS transistor M9 is respectively connected to the drain of the ninth MOS transistor M9 and the first end of the second resistor R2. The second end of the second resistor R2 is respectively connected to the source of the sixth MOS transistor M6, the drain of the first MOS transistor M1, the source of the fourth MOS transistor M4, the second end of the first resistor R1, and the ground terminal.

[0051] When the system output voltage OUT is lower than the threshold voltage of the triad of the seventh MOS transistor M7 through the ninth MOS transistor M9, the associated path becomes high-impedance. When the system output voltage OUT is higher than the threshold voltage of the triad of the seventh MOS transistor M7 through the ninth MOS transistor M9, the current in the associated path gradually increases with the increase in the system output voltage OUT, with the two being directly proportional. The fifth MOS transistor M5 replicates the current flowing through the seventh MOS transistor M7 and transfers the branch current to the sixth MOS transistor M6. The gate of the sixth MOS transistor M6 connects the gate level of the feedback output level information to the current of the fourth MOS transistor M4 in the conversion circuit 20, completing the output voltage sensing.

[0052] See also Figure 2 and Figure 6 The output stage circuit 30 includes a tenth MOS transistor M10, an eleventh MOS transistor M11, and a third resistor R3; the source of the tenth MOS transistor M10 is respectively connected to the source of the eleventh MOS transistor M11, the source of the second MOS transistor M2, and the system power input terminal; the gate of the tenth MOS transistor M10 is connected to the gate of the second MOS transistor M2; the drain of the tenth MOS transistor M10 is connected to the first end of the third resistor R3; the second end of the third resistor R3 is connected to the source of the first MOS transistor M1; the drain of the eleventh MOS transistor M11 is respectively connected to the source of the fifth MOS transistor M5, the source of the seventh MOS transistor M7, and the system voltage output terminal.

[0053] The gate level of the tenth MOS transistor M10 is connected to the conversion circuit 20, and output-stage current drive is achieved by replicating the current information of the conversion circuit 20. The first end of the third resistor R3 injects the current of the tenth MOS transistor M10, and the second end of the third resistor R3 is connected to the source of the clamping circuit 10 to achieve gate clamping and voltage drive of the eleventh MOS transistor M11.

[0054] Among them, the first MOS tube M1 is a high-voltage DPMOS, the second MOS tube M2 is a high-voltage well PMOS MOS Diode, the third MOS tube M3 is a high-voltage DNMOS, the fourth MOS tube M4 is a low-voltage well NMOS, the fifth MOS tube M5 is a low-voltage well PMOS, the sixth MOS tube M6 is a low-voltage well NMOS MOS Diode, the seventh MOS tube M7 to the ninth MOS tube M9 are low-voltage well PMOS MOS Diode M7, the tenth MOS tube M10 is a high-voltage well PMOS current source, and the eleventh MOS tube M11 is a DPMOS.

[0055] The working process of the low-dropout linear regulator is described in detail below:

[0056] In the actual circuit of the present invention, the clamping circuit 10, the conversion circuit 20, the output voltage sensing circuit 40, and the output stage circuit 30 jointly realize the function of a high-voltage input on-chip low-voltage ultra-low-power LDO.

[0057] When the system is powered on, the system output voltage OUT is at zero. At the initial power-on moment, all components in the output voltage sensing circuit 40 are in the cutoff region and do not participate in output voltage OUT control. Because the third MOS transistor M3 of the conversion circuit 20 is in the cutoff region, the second branch Node B in which it resides does not participate in output voltage OUT control. Only the clamping circuit 10 and the output stage circuit 30 complete the system startup logic. Because the second MOS transistor M2 is in the cutoff region, the replicated current of the tenth MOS transistor M10 is zero. The clamping action of the clamping diode Z1 on the first MOS transistor M1 remains below the system input voltage VIN. Therefore, the gate voltage of the eleventh MOS transistor M11 is pulled down by the third resistor R3 and the first MOS transistor M1, turning on the eleventh MOS transistor M11 and increasing the system output voltage OUT.

[0058] In the actual circuit of the present invention, the system starts operating when the system input voltage VIN is powered on from zero level. When the stable DC level of the system input voltage VIN is higher than the predetermined output value of the system output voltage OUT, the feedback loop operates. When the stable DC level of the system input voltage VIN is lower than the predetermined output value of the system output voltage OUT, the feedback loop does not operate.

[0059] The following describes the circuit logic for ensuring that the stable DC level of the system input voltage VIN is higher than the predetermined output value of the system output voltage OUT.

[0060] After the system completes startup, the clamping circuit 10 maintains the voltage of the first branch within a preset range. As the system input voltage V1N continues to rise, the system output voltage OUT tends to increase. A voltage threshold VTAR is preset. When the system output voltage OUT exceeds the preset voltage threshold VTAR, the current flowing through the branch where the seventh MOS transistor M7 resides increases. The output current replicated by the fifth MOS transistor M5 and transmitted to the sixth MOS transistor M6 also increases. The gate voltage of the sixth MOS transistor M6 in the output voltage sensing circuit 40 controls the gate voltage of the fourth MOS transistor M4 in the conversion circuit 20 to increase. This increases the current flowing through the drain of the fourth MOS transistor M4 and the current transmitted to the second MOS transistor M2. The tenth MOS transistor M10 replicates the current of the second MOS transistor M2, increasing the current flowing through the third resistor R3. The gate voltage of the eleventh MOS transistor M11 increases, and the system output voltage OUT decreases, completing the negative feedback loop.

[0061] The following describes the circuit logic for maintaining the stable DC level of the system input voltage VIN lower than the predetermined output value of the system output voltage OUT.

[0062] After the system is started up, as the system input voltage VIN continues to rise, the system output voltage OUT tends to increase. When the system output voltage OUT is lower than the voltage threshold VTAR, the current flowing through the branch where the seventh MOS transistor M7 is located is relatively small. The output current copied by the fifth MOS transistor M5 and transmitted to the sixth MOS transistor M6 is relatively small. The gate voltage of the sixth MOS transistor M6 in the output voltage sensing circuit controls the gate voltage of the fourth MOS transistor M4 in the conversion circuit 20. The current flowing through the fourth MOS transistor M4 is relatively small, and the current transmitted to the second MOS transistor M2 is relatively small. The current copied by the tenth MOS transistor M10 from the second MOS transistor M2 is relatively small, and the current flowing through the third resistor R3 is relatively small. The gate voltage of the eleventh MOS transistor M11 is relatively low, and the eleventh MOS transistor M11 is close to a fully conductive state. At this time, the system output voltage OUT is close to the system input voltage VIN.

[0063] It is understandable that the present application can replace the clamping diode Z1 in the clamping circuit 10 with a MOS diode.

[0064] By applying the low-voltage difference linear regulator provided by the embodiment of the present invention, when the system input voltage rises, if the system output voltage is higher than the preset voltage threshold, the low-voltage difference linear regulator controls the output voltage to decrease to complete the negative feedback loop. When the system output voltage is lower than the preset voltage threshold, the control system output voltage rises to be equal to the system input voltage, thereby realizing low-voltage difference linear voltage regulation. The system input voltage of this application is generally high. Through the low-voltage difference linear regulator, the system input voltage can be maintained at a lower voltage, and the power consumption is low, the circuit structure is simple, and the voltage stabilization effect is good.

[0065] Figure 7 The flow chart of the voltage stabilization method based on the low voltage difference linear regulator provided by the embodiment of the present invention is as follows: Figure 7 As shown, the method includes the following steps:

[0066] Step 710: The clamping circuit has a first branch, and clamps the system input voltage so that the voltage of the first branch remains within a preset voltage range;

[0067] Step 720: When the system output voltage is greater than a preset voltage threshold, the output voltage of the output voltage sensing circuit increases; when the system output voltage is less than the preset voltage threshold, the output voltage decreases;

[0068] Step 730 , when the voltage of the output voltage sensing circuit increases, the current of the conversion circuit increases, and when the voltage of the output voltage sensing circuit decreases, the current decreases;

[0069] In step 740 , the output stage circuit controls the output voltage of the control system to decrease when the current of the conversion circuit increases, and controls the output voltage of the control system to increase when the current of the conversion circuit decreases.

[0070] Furthermore, the preset voltage range includes a first level and a second level, and the first branch has a first branch voltage; when the system input voltage is less than the clamping level, the first branch voltage is pulled down to the preset first level; when the system input voltage is greater than the clamping level, the first branch voltage is raised to the preset second level.

[0071] Professionals should also be further aware that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0072] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0073] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A low voltage dropout linear regulator, characterized in that: The low-dropout linear regulator comprises: a clamping circuit having a first branch, configured to clamp a system input voltage so that the voltage of the first branch remains within a preset voltage range; The output voltage sensing circuit is used to detect the system output voltage. When the system output voltage is greater than a preset voltage threshold, the output voltage is controlled to increase; when the system output voltage is less than the preset voltage threshold, the output voltage is controlled to decrease. a conversion circuit, configured to increase a current of the conversion circuit when the voltage of the output voltage sensing circuit increases, and decrease the current when the voltage of the output voltage sensing circuit decreases; an output stage circuit, configured to control the system output voltage to decrease when the current of the conversion circuit increases, and to control the system output voltage to increase when the current of the conversion circuit decreases; The clamping circuit includes a clamping diode, a first resistor and a first MOS tube; The first end of the clamping diode is connected to the system voltage input terminal, the second end of the clamping diode is connected to the first end of the first resistor and the gate of the first MOS transistor; the second end of the first resistor is connected to the drain of the first MOS transistor and the ground terminal respectively; The conversion circuit includes: a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; The source of the second MOS transistor is connected to the first end of the clamping diode and the system voltage input end respectively, the gate of the second MOS transistor is connected to the drain of the second MOS transistor and the drain of the third MOS transistor respectively, the gate of the third MOS transistor is connected to the system voltage output end, the source of the third MOS transistor is connected to the drain of the fourth MOS transistor, and the source of the fourth MOS transistor is connected to the second end of the first resistor and the ground end respectively; The output voltage sensing circuit includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a second resistor; The source of the fifth MOS transistor is respectively connected to the source of the seventh MOS transistor and the system output voltage terminal; the gate of the fifth MOS transistor is respectively connected to the gate of the seventh MOS transistor, the drain of the seventh MOS transistor, and the source of the eighth MOS transistor; the drain of the fifth MOS transistor is respectively connected to the drain of the sixth MOS transistor and the gate of the fourth MOS transistor; the gate of the eighth MOS transistor is respectively connected to the drain of the eighth MOS transistor and the source of the ninth MOS transistor; the gate of the ninth MOS transistor is respectively connected to the drain of the ninth MOS transistor and the first end of the second resistor; the second end of the second resistor is respectively connected to the source of the sixth MOS transistor, the drain of the first MOS transistor, the source of the fourth MOS transistor, the second end of the first resistor, and the ground terminal; The output stage circuit includes a tenth MOS transistor, an eleventh MOS transistor and a third resistor; The source of the tenth MOS transistor is respectively connected to the source of the eleventh MOS transistor, the source of the second MOS transistor, and the system power input terminal; the gate of the tenth MOS transistor is connected to the gate of the second MOS transistor; the drain of the tenth MOS transistor is connected to the first end of the third resistor; the second end of the third resistor is connected to the source of the first MOS transistor; the drain of the eleventh MOS transistor is respectively connected to the source of the fifth MOS transistor, the source of the seventh MOS transistor, and the system output voltage terminal; and the gate of the eleventh MOS transistor is connected to the first end of the third resistor.

2. The low-dropout linear regulator according to claim 1, wherein: The preset voltage range includes a first level and a second level, and a branch between the gate of the first MOS transistor and the first end of the first resistor is a first branch; the first branch has a first branch voltage; When the system input voltage is less than the clamping level, the first branch voltage is pulled down to a preset first level; When the system input voltage is greater than the clamping level, the first branch voltage is raised to a preset second level.

3. The low-dropout linear regulator according to claim 1, wherein: A second branch is formed between the third MOS transistor and the fourth MOS transistor, and the second branch has a second branch voltage.

4. A voltage stabilization method based on the low voltage dropout linear regulator according to any one of claims 1 to 3, characterized in that: The method comprises: The clamping circuit has a first branch, and the clamping circuit clamps the system input voltage so that the voltage of the first branch is maintained within a preset voltage range; The output voltage sensing circuit increases the output voltage when the system output voltage is greater than the preset voltage threshold; and decreases the output voltage when the system output voltage is less than the preset voltage threshold. The conversion circuit increases the current of the conversion circuit when the voltage of the output voltage sensing circuit increases, and decreases the current when the voltage of the output voltage sensing circuit decreases; The output stage circuit controls the system output voltage to decrease when the current of the conversion circuit increases, and controls the system output voltage to increase when the current of the conversion circuit decreases.

5. The method according to claim 4, characterized in that The preset voltage range includes a first level and a second level, and the first branch has a first branch voltage; When the system input voltage is less than the clamping level, the first branch voltage is pulled down to a preset first level; When the system input voltage is greater than the clamping level, the first branch voltage is raised to a preset second level.

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