Control method, device and equipment of flash memory, and storage medium

Abstract

The application relates to the technical field of Internet of Things, and discloses a FLASH memory control method and device, equipment and a storage medium, which comprise the following steps: after receiving an erasing and writing command transmitted by a first processor, stopping processing of a new task command transmitted by a second processor, and instructing the FLASH memory to perform an erasing and writing operation; judging whether a suspension condition is reached, instructing the FLASH memory to pause the erasing and writing operation and to resume processing of the new task command transmitted by the second processor when the suspension condition is reached; instructing the FLASH memory to perform an operation corresponding to the task command; judging whether a recovery condition is reached, instructing the FLASH memory to stop performing the operation corresponding to the task command, to re-perform the erasing and writing operation, and to stop processing of the new task command transmitted by the second processor, so that the interaction between the processors is avoided, the cost of software overhead and the communication coupling degree between dual-core processors are reduced, and the operation efficiency of the system is improved.

Description

Technical Field

[0001] This application relates to the field of Internet of Things (IoT) technology and discloses a control method, apparatus, device, and storage medium for FLASH memory. Background Technology

[0002] In IoT communication systems, there is usually a dual-core SOC (System on Chip) architecture. Due to cost considerations, there is usually only one shared flash memory available for the dual-core system. The dual-core processors will have the need to access the external flash memory at the same time, requiring frequent interaction between the two cores.

[0003] Therefore, it suffers from problems such as long processing time, slow CP response, high cost, and high system power consumption. Summary of the Invention

[0004] The purpose of this invention is to solve the above-mentioned problems and provide a control method, device, equipment and storage medium for FLASH memory, which avoids the interaction between two processors, reduces the cost of software overhead and the communication coupling between dual-core processors, and improves the operating efficiency of the system.

[0005] To address the aforementioned problems, embodiments of this application provide a control method for a FLASH memory, comprising: upon receiving an erase / write command transmitted by a first processor, stopping processing a new task command transmitted by a second processor and instructing the FLASH memory to perform an erase / write operation; determining whether a suspension condition has been met, and if the suspension condition has been met, instructing the FLASH memory to pause the erase / write operation and resume processing the new task command transmitted by the second processor; instructing the FLASH memory to execute the operation corresponding to the task command; determining whether a recovery condition has been met, and if the recovery condition has been met, instructing the FLASH memory to stop executing the operation corresponding to the task command and re-execute the erase / write operation, and stopping processing the new task command transmitted by the second processor.

[0006] To address the aforementioned problems, embodiments of this application provide a control device for a FLASH memory, comprising: a processing module, configured to, upon receiving an erase / write command transmitted by a first processor, stop processing a new task command transmitted by a second processor and instruct the FLASH memory to perform an erase / write operation; a first determining module, configured to determine whether a suspension condition has been met, and if the suspension condition has been met, instruct the FLASH memory to pause the erase / write operation and resume processing the new task command transmitted by the second processor; an instructing module, configured to instruct the FLASH memory to execute the operation corresponding to the task command; and a second determining module, configured to determine whether a recovery condition has been met, and if the recovery condition has been met, instruct the FLASH memory to stop executing the operation corresponding to the task command and re-execute the erase / write operation, while stopping processing the new task command transmitted by the second processor.

[0007] To address the aforementioned problems, embodiments of this application also provide an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to execute the aforementioned FLASH memory control method.

[0008] To address the aforementioned issues, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the aforementioned control method for the FLASH memory.

[0009] The FLASH memory control method proposed in this application automatically detects erase / write commands and other task commands sent by the processor. When the FLASH memory is performing an erase / write operation and other processors need to perform task operations, it can automatically send suspend and resume commands to control the external FLASH memory. While ensuring normal operation of the FLASH memory, it avoids interaction between dual-core processors, significantly reduces software overhead, and greatly shortens task response time, thereby improving the overall system efficiency.

[0010] In some embodiments, after receiving the erase / write command transmitted by the first processor, the method further includes: timing the execution time of the erase / write operation, and instructing the FLASH memory to pause the erase / write operation when the execution time of the erase / write operation reaches a preset suspension threshold.

[0011] In some embodiments, upon receiving a task command transmitted by a second processor, the FLASH memory is instructed to pause erase / write operations.

[0012] In some embodiments, after instructing the FLASH memory to pause the erase / write operation, the method further includes: timing the pause time of the erase / write operation; when the pause time of the erase / write operation reaches a preset recovery threshold, instructing the FLASH memory to stop executing the operation corresponding to the task command and re-execute the erase / write operation.

[0013] In some embodiments, if the FLASH memory completes the operation corresponding to the task command of the second processor, the FLASH memory is instructed to re-execute the erase / write operation.

[0014] In some embodiments, the internal state of the FLASH memory is detected according to a preset query interval; if the FLASH memory has completed the erase / write operation, the processing of new task commands transmitted by the second processor is resumed, and the timing of the execution time and pause time of the erase / write operation is stopped. Attached Figure Description

[0015] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0016] Figure 1 This is a flowchart of a control method for a FLASH memory provided in an embodiment of this application;

[0017] Figure 2 This is a schematic diagram of the structure of a control device for a FLASH memory provided in an embodiment of this application;

[0018] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0020] One embodiment of this application relates to a control method for a FLASH memory, comprising: upon receiving an erase / write command transmitted by a first processor, stopping processing a new task command transmitted by a second processor and instructing the FLASH memory to perform an erase / write operation; determining whether a suspension condition has been met; if the suspension condition has been met, instructing the FLASH memory to pause the erase / write operation and resume processing the new task command transmitted by the second processor; instructing the FLASH memory to execute the operation corresponding to the task command; determining whether a recovery condition has been met; if the recovery condition has been met, instructing the FLASH memory to stop executing the operation corresponding to the task command and re-execute the erase / write operation, and stopping processing the new task command transmitted by the second processor. This avoids interaction between the two processors, reduces software overhead costs and communication coupling between dual-core processors, and improves system operating efficiency.

[0021] The implementation details of the method in this embodiment are described below. The following content is only for understanding the implementation details of this solution and is not essential for implementing this solution. The specific process is as follows: Figure 1 As shown, the steps may include the following:

[0022] In step 101, after receiving the erase / write command transmitted by the first processor, the processing of new task commands transmitted by the second processor is stopped, and the FLASH memory is instructed to perform the erase / write operation.

[0023] In this embodiment, the first processor is one of the dual-core processors, and the second processor is the other dual-core processor. The specific types of the first and second processors are not limited in this application, nor are the task commands transmitted by the second processor limited.

[0024] In one example, the first processor is a coprocessor, and the second processor is an application processor.

[0025] In one example, the Flash controller receives commands transmitted by the CP (Central Processor). If the command is detected to be Erase or Write, the Flash controller stops processing new task commands transmitted by the AP (Application Processor) and converts the Erase and Write commands transmitted by the CP into Erase and Write timing commands that the Flash memory can recognize, so that the Flash memory can perform erase and write operations according to the Erase and Write timing commands.

[0026] In step 102, it is determined whether the suspension condition has been met. If the suspension condition has been met, the FLASH memory is instructed to pause the erase and write operation and resume processing the new task command transmitted by the second processor.

[0027] In one example, after the FLASH memory performs an erase / write operation, it is determined whether the suspension condition has been met. If the suspension condition is met, the FLASH memory sends a Suspend timing command to the FLASH memory, which then suspends the erase / write operation of the first processor and resumes processing the new task command transmitted by the second processor.

[0028] In one example, the conditions (suspend conditions) for the Flash controller to send the Suspend timing command to the Flash memory include: the Flash controller receiving a task command from the second processor while the Flash memory is performing an erase / write task by the first processor; or, the time to send the suspend timing command is reached while the Flash memory is performing an erase / write task.

[0029] In this embodiment of the application, after receiving the erase / write command transmitted by the first processor, the method further includes timing the execution time of the erase / write operation, and instructing the FLASH memory to pause the erase / write operation when the execution time of the erase / write operation reaches a preset suspension threshold.

[0030] In one example, after receiving the Erase and Write commands from the CP, the Flash controller simultaneously starts timing the execution time of the erase and write operations. When the time to send the Suspend timing command is reached, the Flash controller sends the Suspend timing command to the Flash memory, so that the Flash memory can perform a suspend operation according to the Suspend timing command, that is, instruct the Flash memory to pause the erase and write operations and no longer stop receiving and processing new task commands transmitted by the AP.

[0031] In this embodiment of the application, upon receiving a task command transmitted by the second processor, the FLASH memory is instructed to pause the erase and write operations.

[0032] In one example, when the Flash memory is performing a CP erase / write operation, after receiving the Read command transmitted by the AP, the Flash controller sends a Suspend timing command to the Flash memory, so that the Flash memory can perform a suspend operation according to the Suspend timing command and no longer stop processing new task commands transmitted by the AP.

[0033] In step 103, the FLASH memory is instructed to perform the operation corresponding to the task command.

[0034] In one example, the FLASH controller sends a Read timing command to the Flash memory, which then performs a read operation according to the Read timing command.

[0035] In step 104, it is determined whether the recovery condition has been met. If the recovery condition has been met, the FLASH memory is instructed to stop executing the operation corresponding to the task command and re-execute the erase / write operation, and stop processing the new task command transmitted by the second processor.

[0036] In one example, after the FLASH memory suspends the erase / write operation, it is determined whether the recovery condition has been met. If the recovery condition is met, the FLASH memory sends a Resume timing command to the FLASH memory, so that the FLASH memory stops executing the operation corresponding to the second processor's task command according to the Resume timing command, and re-executes the erase / write operation of the first processor, while stopping the processing of newly transmitted task commands from the second processor.

[0037] In one example, the conditions (recovery conditions) for Flash memory to send a Resume timing command to Flash memory include: when the Flash memory pauses the erase / write operation for a preset time; or when the Flash memory completes the operation corresponding to the command task of another processor.

[0038] In this embodiment of the application, after instructing the FLASH memory to pause the erase / write operation, the method further includes: timing the pause time of the erase / write operation; when the pause time of the erase / write operation reaches a preset recovery threshold, instructing the FLASH memory to stop executing the operation corresponding to the task command and re-execute the erase / write operation.

[0039] In one example, the Flash controller receives a Read command transmitted by the AP, sends a Read timing command to the Flash memory, obtains the data that the AP needs to read from the Flash memory, and stops receiving new Read commands when the Flash memory suspends the erase / write operation for a preset time. At the same time, the Flash controller sends a Resume timing command to the Flash memory so that the Flash memory can continue to perform the erase / write operation according to the Resume timing command.

[0040] In this embodiment of the application, when the FLASH memory completes the operation corresponding to the task command of the second processor, the FLASH memory is instructed to re-execute the erase / write operation.

[0041] In one example, the Flash controller receives a Read command transmitted by the AP, sends a Read timing command to the Flash memory, obtains the data that the AP needs to read from the Flash memory, and stops receiving new Read commands when the Flash memory has completed the current read operation. At the same time, the Flash controller sends a Resume timing command to the Flash memory so that the Flash memory can continue to perform erase and write operations according to the Resume timing command.

[0042] In this embodiment of the application, when the FLASH memory is performing an erase / write operation, the internal state of the FLASH memory is detected according to a preset query interval; when the FLASH memory is detected to have completed the erase / write operation, the processing of new task commands transmitted by the second processor is resumed, and the timing of the execution time and pause time of the erase / write operation is stopped.

[0043] In one example, based on the interval of the status query, the Flash controller detects the internal state of the Flash memory during the erase and write operation. If it detects that the Flash memory has completed the current erase and write operation, the Flash controller will no longer block the processing of new task commands. At the same time, the timing of the Ssuspend and Resume commands will end, and data transmission will proceed normally.

[0044] The FLASH memory control method provided in this application embodiment controls the external FLASH memory through a hardware FLASH controller. When the FLASH memory performs an erase / write operation, the FLASH controller automatically detects whether the suspension condition has been met according to a preset setting, and then automatically sends a suspension command to control the external FLASH memory to pause the erase / write operation. When the FLASH memory pauses the erase / write operation, it automatically detects whether the recovery condition has been met according to a preset setting, and then sends a recovery command to control the FLASH memory to resume the erase / write operation. This greatly ensures the accuracy of FLASH memory operation. At the same time, the FLASH memory control method proposed in this application embodiment avoids the interaction between dual-core processors, significantly reduces software overhead, and greatly shortens the task response time, thereby improving the overall system operating efficiency.

[0045] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0046] This application also provides a control device for a FLASH memory, such as... Figure 2 As shown, it includes: a processing module 201, a first judgment module 202, an indication module 203, and a second judgment module 204.

[0047] Specifically, the processing module 201 is used to stop processing new task commands transmitted by the second processor after receiving the erase / write command transmitted by the first processor, and instruct the FLASH memory to perform the erase / write operation; the first judgment module 202 is used to determine whether the suspension condition has been met, and if the suspension condition has been met, instruct the FLASH memory to pause the erase / write operation and resume processing new task commands transmitted by the second processor; the instruction module 203 is used to instruct the FLASH memory to perform the operation corresponding to the task command; the second judgment module 204 is used to determine whether the recovery condition has been met, and if the recovery condition has been met, instruct the FLASH memory to stop executing the operation corresponding to the task command and re-execute the erase / write operation, and stop processing new task commands transmitted by the second processor.

[0048] In one example, the processing module 201 receives commands transmitted by the first processor (coprocessor). If the command is detected to be Erase or Write, the Flash controller stops processing new task commands transmitted by the second processor (application processor) and converts the Erase and Write commands transmitted by the first processor (coprocessor) into Erase and Write timing commands that the Flash memory can recognize, so that the Flash memory can perform erase and write operations according to the Erase and Write timing commands.

[0049] In one example, after the first judgment module 202 performs an erase / write operation on the FLASH memory, it determines whether the suspension condition has been met. If the suspension condition is met, the FLASH memory sends a Suspend timing command to the FLASH memory, so that the FLASH memory can suspend the erase / write operation of the first processor according to the Suspend timing command, and at the same time resume processing the new task command transmitted by the second processor.

[0050] In one example, instruction module 203 sends a Read timing command to the Flash memory, so that the Flash memory can perform a read operation according to the Read timing command.

[0051] In one example, after the FLASH memory suspends the erase / write operation, the second judgment module 204 determines whether the recovery condition has been met. If the recovery condition is met, the Flash memory sends a Resume timing command to the Flash memory, so that the Flash memory stops executing the operation corresponding to the second processor task command according to the Resume timing command and re-executes the erase / write operation of the first processor, while stopping the processing of newly transmitted task commands from the second processor.

[0052] The FLASH memory control device provided in this application embodiment controls the external FLASH memory. When the FLASH memory performs an erase / write operation, the FLASH controller automatically detects whether the suspension condition has been met according to a preset setting, and then automatically sends a suspension command to control the external FLASH memory to pause the erase / write operation. When the FLASH memory pauses the erase / write operation, it automatically detects whether the recovery condition has been met according to a preset setting, and then sends a recovery command to control the FLASH memory to resume the erase / write operation. This greatly ensures the accuracy of FLASH memory operation. At the same time, the FLASH memory control device proposed in this application embodiment avoids the interaction between dual-core processors, significantly reduces software overhead, and greatly shortens the task response time, thereby improving the overall system operating efficiency.

[0053] It is not difficult to see that this embodiment is a device embodiment corresponding to the above-described FLASH memory control method embodiment, and this embodiment can be implemented in conjunction with the above-described FLASH memory control method embodiment. The relevant technical details mentioned in the above-described FLASH memory control method embodiment are still valid in this embodiment, and will not be repeated here to avoid repetition. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above-described FLASH memory control method embodiment.

[0054] It is worth mentioning that all modules involved in the above embodiments of this application are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problem proposed in this application; however, this does not mean that other units are absent from this embodiment.

[0055] Embodiments of this application also provide an electronic device, such as... Figure 3As shown, it includes at least two processors 301 and processor 302; and a memory 303 communicatively connected to the at least two processors 301 and processor 302; wherein the memory 303 stores instructions that can be executed by the at least two processors 301 and processor 302, and the instructions are executed by the at least two processors 301 and processor 302 to enable the at least one processor to execute the above-described FLASH memory control method.

[0056] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0057] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0058] The above-mentioned products can perform the methods provided in the embodiments of this application, and have the corresponding functional modules and beneficial effects of performing the methods. For technical details not described in detail in this embodiment, please refer to the methods provided in the embodiments of this application.

[0059] Embodiments of this application also provide a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the above-described method embodiments.

[0060] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. The program is stored in a storage medium and includes several instructions to cause multiple processors to execute all or part of the steps of the methods described in the various embodiments of this application.

[0061] The above embodiments are provided for those skilled in the art to implement and use this application. Those skilled in the art can make various modifications or changes to the above embodiments without departing from the inventive concept of this application. Therefore, the protection scope of this application is not limited to the above embodiments, but should conform to the maximum scope of the innovative features mentioned in the claims.

Claims

1. A control method for a FLASH memory, applied to a FLASH controller, characterized in that, include: Upon receiving the erase / write command from the first processor, it stops processing new task commands transmitted by the second processor and instructs the FLASH memory to perform the erase / write operation. The execution time of the erase / write operation is timed; The FLASH controller automatically determines whether the suspension condition has been met. If the suspension condition is met, it instructs the FLASH memory to pause the erase / write operation and resume processing new task commands transmitted by the second processor. The suspension condition includes: the execution time of the erase / write operation reaches a preset suspension threshold. Instruct the FLASH memory to execute the operation corresponding to the task command; The pause time of the erase / write operation is timed; The FLASH controller automatically determines whether the recovery condition has been met. If the recovery condition is met, it instructs the FLASH memory to stop executing the operation corresponding to the task command and re-execute the erase / write operation, and stops processing new task commands transmitted by the second processor. The recovery condition includes: the pause time of the erase / write operation reaches a preset recovery threshold.

2. The control method for FLASH memory according to claim 1, characterized in that, The step of instructing the FLASH memory to pause the erase / write operation when the suspension condition is met includes: Upon receiving a task command transmitted by the second processor, the FLASH memory is instructed to suspend the erase / write operation.

3. The control method for FLASH memory according to claim 1, characterized in that, The step of instructing the FLASH memory to re-execute the erase / write operation when the recovery conditions are met includes: When the FLASH memory completes the operation corresponding to the task command of the second processor, the FLASH memory is instructed to re-execute the erase / write operation.

4. The control method for a FLASH memory according to any one of claims 1 to 3, characterized in that, When performing an erase / write operation on the FLASH memory, the following are included: The internal state of the FLASH memory is detected according to a preset query interval; Upon detecting that the FLASH memory has completed the erase / write operation, processing of new task commands transmitted by the second processor resumes, and the timing of the execution time and pause time of the erase / write operation is stopped. The timing of the execution time of the erase / write operation includes timing the execution time of the erase / write operation after receiving the erase / write command transmitted by the first processor. The timing of the pause time of the erase / write operation includes timing the pause time of the erase / write operation after instructing the FLASH memory to pause the erase / write operation.

5. A controller for a FLASH memory, characterized in that, include: The processing module is used to stop processing new task commands transmitted by the second processor after receiving an erase / write command transmitted by the first processor, and to instruct the FLASH memory to perform an erase / write operation. The execution time of the erase / write operation is timed; The first judgment module is used to automatically determine whether the suspension condition has been met by the FLASH controller. If the suspension condition is met, the module instructs the FLASH memory to pause the erase / write operation and resume processing the new task command transmitted by the second processor. The suspension condition includes: the execution time of the erase / write operation reaches a preset suspension threshold. An instruction module is used to instruct the FLASH memory to execute the operation corresponding to the task command; and to time the pause time of the erase / write operation; The second judgment module is used to automatically determine whether the recovery condition has been met by the FLASH controller. If the recovery condition is met, the module instructs the FLASH memory to stop executing the operation corresponding to the task command and re-execute the erase / write operation, and stops processing new task commands transmitted by the second processor. The recovery condition includes: the pause time of the erase / write operation reaches a preset recovery threshold.

6. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the control method of the FLASH memory as described in any one of claims 1 to 4.

7. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the control method of the FLASH memory as described in any one of claims 1 to 4.

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