A circuit board testing method and system based on visual recognition

Abstract

The invention relates to the technical field of circuit board detection, and is a circuit board testing method and system based on visual recognition. The specific method comprises: acquiring surface image data of the circuit board, extracting welding defect feature data of each solder joint of the circuit board; calculating the welding defect value of each solder joint in the circuit board; importing temperature data and welding defect value into a heat dissipation defect value calculation strategy to calculate the heat dissipation defect value of each solder joint area in the circuit board; importing signal transmission data into a signal distortion defect value calculation strategy to calculate the signal transmission distortion defect value in the circuit board; determining the performance threat value of the circuit board caused by the welding defects of each solder joint area in an adjacent electronic component test group; the invention can well solve the problem in the prior art that defects in circuit board welding will lead to uneven temperature distribution in each working area of ​​the circuit board under working state and signal transmission distortion.

Description

Technical Field

[0001] The invention relates to the technical field of circuit board detection, and relates to a circuit board testing method and system based on visual recognition. Background Art

[0002] Circuit board testing refers to a comprehensive inspection and evaluation of the circuit boards in electronic equipment to ensure their normal operation and stable performance. Its significance is to improve the reliability and safety of electronic equipment, prevent potential failures and accidents, extend the service life of the equipment, and ensure that the equipment can normally transmit signals, dissipate heat, and weld connections when working. During the manufacturing and transportation of circuit boards, careless operation by operators or damage from the external environment can cause scratches on the welding area of ​​the circuit board. Scratches can cause loose welding connections, increase resistance, affect signal transmission and heat dissipation, and even distort the signal transmission of the circuit board, thereby affecting the normal operation and stable performance of the circuit board.

[0003] In the existing disclosed invention technology, for example, the patent with application publication number CN114298996A discloses a circuit board scratch detection method and system based on image processing, which obtains a circuit board surface image; grayscales and filters the image to obtain a grayscale image; performs Gaussian filtering and denoising on the grayscale image, and then performs Gaussian smoothing; uses circuit components to make a background template, matches the template with the image, and locates the position of the circuit components in the image; removes the circuit components in the image, and obtains an image of shielded circuit components through area filling; and extracts scratches from the image without circuit components.

[0004] The background template used in the above patent to match the position of circuit components may have errors, especially when there are many components on the circuit board or the layout is complex, the matching accuracy may be affected. Summary of the invention

[0005] The technical problem to be solved by the present invention is that in the prior art, defects in circuit board welding will lead to uneven temperature distribution in various working areas of the circuit board and distorted signal transmission when the circuit board is in working state, and a circuit board testing method and system based on visual recognition are proposed.

[0006] In order to achieve the above object, the technical solution of a circuit board testing method based on visual recognition of the present invention comprises the following steps:

[0007] S1: Use a high-resolution camera to shoot the circuit board to obtain surface image data of the circuit board; pre-process the acquired image data, and extract welding defect feature data of each solder joint of the circuit board from the pre-processed image;

[0008] S2: Importing welding feature data into welding defect assessment strategy to calculate welding defect value of each welding point in the circuit board;

[0009] S3: collecting the working temperature data of the solder joint area of ​​the circuit board through the temperature sensor, and importing the temperature data and the welding defect value into the heat dissipation defect value calculation strategy to calculate the heat dissipation defect value of each solder joint area in the circuit board;

[0010] S4: collecting signal transmission data between different electronic components in the trial operation state of the circuit board, and importing the signal transmission data into the signal distortion defect value calculation strategy to calculate the signal transmission distortion defect value in the circuit board;

[0011] S5: determining the performance threat value of the circuit board caused by the welding defects of each solder joint area in the adjacent electronic component test group according to the signal transmission distortion defect value and the heat dissipation defect value of each solder joint area;

[0012] S6: Arrange the performance threat values ​​of each solder joint area in descending order, and upload the arranged threat value data to the circuit board maintenance department, and give priority to repairing the solder joints with high performance threat values.

[0013] Specifically, S1 includes the following specific steps:

[0014] S11: extracting the surface image data of the circuit board in S1;

[0015] S12: preprocessing the collected surface image data of the circuit board, wherein the preprocessing includes denoising, adjusting image brightness and contrast, graying the preprocessed surface image data, and performing threshold segmentation processing on the surface grayscale image of the circuit board to segment and extract the solder joint area from the entire image;

[0016] S13: Establish a machine learning model, input the solder joint area into the machine learning model, identify the scratch area in the solder joint area and extract welding defect feature data, wherein the welding defect feature data includes solder joint: pixel value of each pixel point in the scratch area, aspect ratio of the scratch in the scratch area and scratch depth.

[0017] The welding feature data also includes: the geometric shape and color of the welding spot.

[0018] Specifically, the welding defect assessment strategy described in S2 includes:

[0019] S21: Extracting the scratch depth of scratched areas in a single circuit board And the solder joint height data of a single solder joint , evaluate and calculate the effective thickness ratio of a single weld ;

[0020] S22: Extract the number of scratch areas in a single circuit board , the total number of pixels in the scratch area , the aspect ratio of the scratch area And welding effective thickness ratio , evaluate and calculate the invalid welding value of each scratch area, and the calculation strategy of the invalid welding value is as follows:

[0021] ;

[0022] in, The pixel baseline set during the board testing process, The scratch baseline set during the circuit board testing process, The thickness ratio baseline set during the circuit board test process, where The i in is a subscript, indicating the welding defect characteristic data corresponding to the i-th scratch area; The sum of pixels in each scratch area is , aspect ratio And welding effective thickness ratio The influence ratio of causing invalid welding.

[0023] Specifically, S3 includes the following specific steps:

[0024] S31: Debug the circuit board to the working state, collect the working temperature data of different solder joint areas through the temperature sensor, and form a working temperature data set: ; Synchronously extract the invalid welding value data of each scratch area in S3 to form an invalid welding value data set ;

[0025] S32: Import the data set described in S31 into the heat dissipation defect value calculation strategy. The calculation strategy of the heat dissipation defect value of the i-th solder joint area is:

[0026] ;

[0027] in, is the operating temperature data of the ith solder joint area, is the invalid welding value of the i-th welding spot area, The closest operating temperature data among all solder joint areas of the circuit board The value of The closest value in the invalid solder value data set of all solder joint areas on the circuit board The value of .

[0028] Specifically, S4 includes the following specific steps:

[0029] S41: Extract the total number of electronic components in the circuit board as N, and the length of the signal transmission line between each group of adjacent electronic components ,in, ;

[0030] S42: Collect the peak-to-peak data of the signal during the transmission process between each group of adjacent electronic components on the circuit board , delay data and signal-to-noise ratio data ;

[0031] S43: Importing the data collected in S42 into the signal distortion defect value calculation strategy to calculate the signal transmission distortion defect value of the circuit board, the signal distortion defect value calculation strategy is:

[0032] ;

[0033] in, They are the contribution coefficients of signal distortion defects of signal peak-to-peak data, time delay data and signal-to-noise ratio data respectively;

[0034] The closest peak-to-peak value of the signal in all adjacent electronic component test groups on the circuit board The value of The closest delay data among all adjacent electronic component test groups in the circuit board The value of The closest signal-to-noise ratio data among all adjacent electronic component test groups in the circuit board The value of

[0035] Where n is a subscript, indicating the signal distortion defect value, signal peak-to-peak value data, delay data and signal-to-noise ratio data in the nth group of adjacent electronic component test groups.

[0036] Specifically, determining the performance threat value of the circuit board caused by the welding defects in each solder point area according to the signal transmission distortion defect value and the heat dissipation defect value of each solder point area in S5 includes:

[0037] S51: Extract the length of the signal transmission line between each group of adjacent electronic components in each adjacent electronic component test group. ;

[0038] Synchronous extraction, the number of solder joint areas on the signal transmission line And the heat dissipation defect value of each solder joint area ;

[0039] S52: Calculate the performance threat value of the circuit board caused by the welding defects of each solder joint area in each adjacent electronic component test group; the performance threat value The calculation strategy is as follows:

[0040] .

[0041] In addition, the circuit board testing system based on visual recognition of the present invention includes the following modules:

[0042] Circuit board image acquisition module, welding defect value calculation module, heat dissipation defect value calculation module, signal transmission distortion defect value calculation module, solder joint performance threat value assessment module, and visualization module;

[0043] The circuit board image acquisition module is used to photograph the circuit board to obtain surface image data of the circuit board; preprocess the acquired image data, and extract welding defect feature data of each solder joint of the circuit board from the preprocessed image;

[0044] The welding defect value calculation module is used to import welding feature data into the welding defect assessment strategy to calculate the welding defect value of each welding point in the circuit board;

[0045] The heat dissipation defect value calculation module collects the operating temperature data of the solder joint area of ​​the circuit board through the temperature sensor, and imports the temperature data and the welding defect value into the heat dissipation defect value calculation strategy to calculate the heat dissipation defect value of each solder joint area in the circuit board;

[0046] The signal transmission distortion defect value calculation module is used to collect signal transmission data between different electronic components in the trial operation state of the circuit board, and import the signal transmission data into the signal distortion defect value calculation strategy to calculate the signal transmission distortion defect value in the circuit board;

[0047] The solder joint performance threat value assessment module determines the performance threat value of the circuit board caused by the soldering defects of each solder joint area in the adjacent electronic component test group according to the signal transmission distortion defect value and the heat dissipation defect value of each solder joint area;

[0048] The visualization module is used to arrange the performance threat values ​​of each solder joint area in descending order, and upload the arranged threat value data to the circuit board maintenance department, so as to give priority to the maintenance of solder joints with high performance threat values.

[0049] A storage medium stores instructions, and when a computer reads the instructions, the computer executes the circuit board testing method based on visual recognition.

[0050] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned circuit board testing method based on visual recognition when executing the computer program.

[0051] Compared with the prior art, the technical effects of the present invention are as follows:

[0052] 1. The present invention conducts comprehensive inspection and evaluation of the circuit board through the scratch depth, average solder joint height and number of scratches during the circuit board welding process, covering multiple aspects such as welding defects, heat dissipation defects and signal transmission distortion, and integrates multi-faceted data indicator evaluation to improve the accuracy and practicality of the working status and performance detection of the circuit board.

[0053] 2. The present invention takes into account the scratch defects that may appear in the welding area of ​​the circuit board during the manufacturing and transportation of the circuit board. By calculating the signal transmission distortion defect value and the heat dissipation defect value of each solder joint area, the present invention quantifies the impact of the increased resistance of the circuit board due to welding defects on the signal transmission and heat dissipation effects of the circuit board, thereby improving the normal working stability of the circuit board.

[0054] 3. The present invention arranges the performance threat values ​​of each solder joint area in descending order, and uploads the arranged threat value data to the circuit board maintenance department, so as to give priority to repairing the solder joints with high performance threat values, thereby facilitating the maintenance department to better formulate maintenance plans and repair welding defects in a targeted manner, saving circuit board manufacturers the waste of manpower, material and financial resources in the quality inspection process, and improving the quality inspection efficiency of circuit boards. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0056] Figure 1 A schematic diagram of a circuit board testing method based on visual recognition according to the present invention;

[0057] Figure 2 The figure is a schematic diagram of the structure of a circuit board testing system based on visual recognition of the present invention. DETAILED DESCRIPTION

[0058] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0059] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0060] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0061] Embodiment 1:

[0062] like Figure 1 As shown, a circuit board testing method based on visual recognition according to an embodiment of the present invention is as follows: Figure 1 As shown, the specific steps are as follows:

[0063] S1: Use a high-resolution camera to shoot the circuit board to obtain surface image data of the circuit board; pre-process the acquired image data, and extract welding defect feature data of each solder joint of the circuit board from the pre-processed image;

[0064] S1 includes the following specific steps:

[0065] S11: extracting the surface image data of the circuit board in S1;

[0066] S12: preprocessing the collected surface image data of the circuit board, wherein the preprocessing includes denoising, adjusting image brightness and contrast, graying the preprocessed surface image data, and performing threshold segmentation processing on the surface grayscale image of the circuit board to segment and extract the solder joint area from the entire image;

[0067] S13: Establish a machine learning model, input the solder joint area into the machine learning model, identify the scratch area in the solder joint area and extract welding defect feature data, wherein the welding defect feature data includes solder joint: pixel value of each pixel point in the scratch area, aspect ratio of the scratch in the scratch area and scratch depth.

[0068] The welding feature data also includes: the geometric shape and color of the welding spot.

[0069] S2: Importing welding feature data into welding defect assessment strategy to calculate welding defect value of each welding point in the circuit board;

[0070] The welding defect assessment strategy described in S2 includes:

[0071] S21: Extracting the scratch depth of scratched areas in a single circuit board And the solder joint height data of a single solder joint , evaluate and calculate the effective thickness ratio of a single weld ;

[0072] S22: Extract the number of scratch areas in a single circuit board , the total number of pixels in the scratch area , the aspect ratio of the scratch area And welding effective thickness ratio , evaluate and calculate the invalid welding value of each scratch area, and the calculation strategy of the invalid welding value is as follows:

[0073] ;

[0074] in, The pixel baseline set during the board testing process, The scratch baseline set during the circuit board testing process, The thickness ratio baseline set during the circuit board test process, where The i in is a subscript, indicating the welding defect characteristic data corresponding to the i-th scratch area; The sum of pixels in each scratch area is , aspect ratio And welding effective thickness ratio The influence ratio of causing invalid welding.

[0075] S3: collecting the working temperature data of the solder joint area of ​​the circuit board through the temperature sensor, and importing the temperature data and the welding defect value into the heat dissipation defect value calculation strategy to calculate the heat dissipation defect value of each solder joint area in the circuit board;

[0076] S3 includes the following specific steps:

[0077] S31: Debug the circuit board to the working state, collect the working temperature data of different solder joint areas through the temperature sensor, and form a working temperature data set: ; Synchronously extract the invalid welding value data of each scratch area in S3 to form an invalid welding value data set ;

[0078] S32: Import the data set described in S31 into the heat dissipation defect value calculation strategy. The calculation strategy of the heat dissipation defect value of the i-th solder joint area is:

[0079] ;

[0080] in, is the operating temperature data of the ith solder joint area, is the invalid welding value of the i-th welding spot area, The closest operating temperature data among all solder joint areas of the circuit board The value of The closest value in the invalid solder value data set of all solder joint areas on the circuit board The value of .

[0081] S4: collecting signal transmission data between different electronic components in the trial operation state of the circuit board, and importing the signal transmission data into the signal distortion defect value calculation strategy to calculate the signal transmission distortion defect value in the circuit board;

[0082] S4 includes the following specific steps:

[0083] S41: Extract the total number of electronic components in the circuit board as N, and the length of the signal transmission line between each group of adjacent electronic components ,in ,;

[0084] S42: Collect the peak-to-peak data of the signal during the transmission process between each group of adjacent electronic components on the circuit board , delay data and signal-to-noise ratio data ;

[0085] S43: Importing the data collected in S42 into the signal distortion defect value calculation strategy to calculate the signal transmission distortion defect value of the circuit board, the signal distortion defect value calculation strategy is:

[0086] ;

[0087] in, They are the contribution coefficients of signal distortion defects of signal peak-to-peak data, time delay data and signal-to-noise ratio data respectively;

[0088] The closest peak-to-peak value of the signal in all adjacent electronic component test groups on the circuit board The value of The closest delay data among all adjacent electronic component test groups in the circuit board The value of The closest signal-to-noise ratio data among all adjacent electronic component test groups in the circuit board The value of

[0089] Where n is a subscript, indicating the signal distortion defect value, signal peak-to-peak value data, delay data and signal-to-noise ratio data in the nth group of adjacent electronic component test groups.

[0090] S5: determining the performance threat value of the circuit board caused by the welding defects of each solder joint area in the adjacent electronic component test group according to the signal transmission distortion defect value and the heat dissipation defect value of each solder joint area;

[0091] Determining the performance threat value of the circuit board caused by the welding defects in each solder point area according to the signal transmission distortion defect value and the heat dissipation defect value of each solder point area in S5 includes:

[0092] S51: Extract the length of the signal transmission line between each group of adjacent electronic components in each adjacent electronic component test group. ;

[0093] Synchronous extraction, the number of solder joint areas on the signal transmission line And the heat dissipation defect value of each solder joint area ;

[0094] S52: Calculate the performance threat value of the circuit board caused by the welding defects of each solder joint area in each adjacent electronic component test group; the performance threat value The calculation strategy is as follows:

[0095] .

[0096] S6: Arrange the performance threat values ​​of each solder joint area in descending order, and upload the arranged threat value data to the circuit board maintenance department, and give priority to repairing the solder joints with high performance threat values.

[0097] Embodiment 2:

[0098] like Figure 2 As shown, a circuit board testing system based on visual recognition according to an embodiment of the present invention is as follows: Figure 2 As shown, it includes the following modules:

[0099] Circuit board image acquisition module, welding defect value calculation module, heat dissipation defect value calculation module, signal transmission distortion defect value calculation module, solder joint performance threat value assessment module, and visualization module;

[0100] The circuit board image acquisition module is used to photograph the circuit board to obtain surface image data of the circuit board; preprocess the acquired image data, and extract welding defect feature data of each solder joint of the circuit board from the preprocessed image;

[0101] The welding defect value calculation module is used to import welding feature data into the welding defect assessment strategy to calculate the welding defect value of each welding point in the circuit board;

[0102] The heat dissipation defect value calculation module collects the operating temperature data of the solder joint area of ​​the circuit board through the temperature sensor, and imports the temperature data and the welding defect value into the heat dissipation defect value calculation strategy to calculate the heat dissipation defect value of each solder joint area in the circuit board;

[0103] The signal transmission distortion defect value calculation module is used to collect signal transmission data between different electronic components in the trial operation state of the circuit board, and import the signal transmission data into the signal distortion defect value calculation strategy to calculate the signal transmission distortion defect value in the circuit board;

[0104] The solder joint performance threat value assessment module determines the performance threat value of the circuit board caused by the soldering defects of each solder joint area in the adjacent electronic component test group according to the signal transmission distortion defect value and the heat dissipation defect value of each solder joint area;

[0105] The visualization module is used to arrange the performance threat values ​​of each solder joint area in descending order, and upload the arranged threat value data to the circuit board maintenance department, so as to give priority to the maintenance of solder joints with high performance threat values.

[0106] Embodiment three:

[0107] This embodiment provides an electronic device, including: a processor and a memory, wherein the memory stores a computer program that can be called by the processor;

[0108] The processor executes the above-mentioned circuit board testing method based on visual recognition by calling the computer program stored in the memory.

[0109] The electronic device may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) and one or more memories, wherein the memory stores at least one computer program, which is loaded and executed by the processor to implement a circuit board testing method based on visual recognition provided by the above method embodiment. The electronic device may also include other components for realizing the functions of the device, for example, the electronic device may also have components such as a wired or wireless network interface and an input and output interface to input and output data. This embodiment will not be described in detail here.

[0110] Embodiment 4:

[0111] This embodiment provides a computer-readable storage medium having a rewritable computer program stored thereon;

[0112] When the computer program runs on a computer device, the computer device is enabled to execute the above-mentioned circuit board testing method based on visual recognition.

[0113] For example, the computer readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0114] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0115] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0116] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When a computer instruction or computer program is loaded or executed on a computer, a process or function according to an embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center through a wired network or / and a wireless network. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0117] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0118] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0119] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only one, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0120] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0121] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0122] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0123] In summary, compared with the prior art, the technical effects of the present invention are as follows:

[0124] 1. The present invention conducts comprehensive inspection and evaluation of the circuit board through the scratch depth, average solder joint height and number of scratches during the circuit board welding process, covering multiple aspects such as welding defects, heat dissipation defects and signal transmission distortion, and integrates multi-faceted data indicator evaluation to improve the accuracy and practicality of the working status and performance detection of the circuit board.

[0125] 2. The present invention takes into account the scratch defects that may appear in the welding area of ​​the circuit board during the manufacturing and transportation of the circuit board. By calculating the signal transmission distortion defect value and the heat dissipation defect value of each solder joint area, the present invention quantifies the impact of the increased resistance of the circuit board due to welding defects on the signal transmission and heat dissipation effects of the circuit board, thereby improving the normal working stability of the circuit board.

[0126] 3. The present invention arranges the performance threat values ​​of each solder joint area in descending order, and uploads the arranged threat value data to the circuit board maintenance department, so as to give priority to the maintenance of solder joints with high performance threat values, so as to facilitate the maintenance department to better formulate maintenance plans and repair welding defects in a targeted manner, thereby saving the waste of manpower, material and financial resources of circuit board manufacturers in the quality inspection link, and improving the quality inspection efficiency of circuit boards. The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only to illustrate the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the invention to be protected. The scope of protection claimed by the present invention is defined by the attached claims and their equivalents.

Claims

1. A circuit board testing method based on visual recognition, characterized in that: The method comprises the following specific steps: S1: Use a high-resolution camera to shoot the circuit board to obtain surface image data of the circuit board; pre-process the acquired image data, and extract welding defect feature data of each solder joint of the circuit board from the pre-processed image; S2: Importing welding feature data into welding defect assessment strategy to calculate welding defect value of each welding point in the circuit board; S3: collecting the working temperature data of the solder joint area of ​​the circuit board through the temperature sensor, and importing the temperature data and the welding defect value into the heat dissipation defect value calculation strategy to calculate the heat dissipation defect value of each solder joint area in the circuit board; S4: collecting signal transmission data between different electronic components in the trial operation state of the circuit board, and importing the signal transmission data into the signal distortion defect value calculation strategy to calculate the signal transmission distortion defect value in the circuit board; S5: determining the performance threat value of the circuit board caused by the welding defects of each solder joint area in the adjacent electronic component test group according to the signal transmission distortion defect value and the heat dissipation defect value of each solder joint area; S6: Arrange the performance threat values ​​of each solder joint area in descending order, and upload the arranged threat value data to the circuit board maintenance department, and give priority to repairing the solder joints with high performance threat values.

2. A circuit board testing method based on visual recognition according to claim 1, characterized in that: S1 includes the following specific steps: S11: extracting the surface image data of the circuit board in S1; S12: preprocessing the collected surface image data of the circuit board, wherein the preprocessing includes denoising, adjusting image brightness and contrast, graying the preprocessed surface image data, and performing threshold segmentation processing on the surface grayscale image of the circuit board to segment and extract the solder joint area from the entire image; S13: Establish a machine learning model, input the solder joint area into the machine learning model, identify the scratch area in the solder joint area and extract welding defect feature data, wherein the welding defect feature data includes solder joint: pixel value of each pixel point in the scratch area, aspect ratio of the scratch in the scratch area and scratch depth.

3. A circuit board testing method based on visual recognition according to claim 2, characterized in that: The welding defect assessment strategy described in S2 includes: S21: Extracting the scratch depth of scratched areas in a single circuit board And the solder joint height data of a single solder joint , evaluate and calculate the effective thickness ratio of a single weld ; S22: Extract the number of scratch areas in a single circuit board , the total number of pixels in the scratch area , the aspect ratio of the scratch area And welding effective thickness ratio , evaluate and calculate the invalid welding value of each scratch area, and the calculation strategy of the invalid welding value is as follows: ； in, The pixel baseline set during the board testing process, The scratch baseline set during the circuit board testing process, The thickness ratio baseline set during the circuit board test process, where The i in is a subscript, indicating the welding defect characteristic data corresponding to the i-th scratch area; is the sum of pixels in each scratch area , aspect ratio And welding effective thickness ratio The influence ratio of causing invalid welding.

4. A circuit board testing method based on visual recognition according to claim 3, characterized in that: The machine learning model in S23 includes: input layer, convolution layer, sampling layer, pooling layer, fully connected layer and output layer, where each convolution layer is set to 10 The convolution kernel.

5. A circuit board testing method based on visual recognition according to claim 4, characterized in that: S3 includes the following specific steps: S31: Debug the circuit board to the working state, collect the working temperature data of different solder joint areas through the temperature sensor, and form a working temperature data set: ; Synchronously extract the invalid welding value data of each scratch area in S3 to form an invalid welding value data set ; S32: Import the data set described in S31 into the heat dissipation defect value calculation strategy. The calculation strategy of the heat dissipation defect value of the i-th solder joint area is: ； in, is the operating temperature data of the i-th solder joint area, is the invalid welding value of the ith welding spot area, The closest operating temperature data among all solder joint areas of the circuit board The value of The closest value in the invalid solder value data set of all solder joint areas on the circuit board The value of .

6. A circuit board testing method based on visual recognition according to claim 5, characterized in that: S4 includes the following specific steps: S41: Extract the total number of electronic components in the circuit board as N, and the length of the signal transmission line between each group of adjacent electronic components ,in, ; S42: Collect the peak-to-peak data of the signal during the transmission process between each group of adjacent electronic components on the circuit board , delay data and signal-to-noise ratio data ; S43: Importing the data collected in S42 into the signal distortion defect value calculation strategy to calculate the signal transmission distortion defect value of the circuit board, the signal distortion defect value calculation strategy is: ； in, They are the contribution coefficients of signal distortion defects of signal peak-to-peak data, time delay data and signal-to-noise ratio data respectively; The closest peak-to-peak value of the signal in all adjacent electronic component test groups on the circuit board The value of The closest delay data among all adjacent electronic component test groups in the circuit board The value of The closest signal-to-noise ratio data among all adjacent electronic component test groups in the circuit board The value of Where n is a subscript, indicating the signal distortion defect value, signal peak-to-peak value data, delay data and signal-to-noise ratio data in the nth group of adjacent electronic component test groups.

7. A circuit board testing method based on visual recognition according to claim 6, characterized in that: Determining the performance threat value of the circuit board caused by the welding defects in each solder point area according to the signal transmission distortion defect value and the heat dissipation defect value of each solder point area in S5 includes: S51: Extract the length of the signal transmission line between each group of adjacent electronic components in each adjacent electronic component test group. ; Synchronous extraction, the number of solder joint areas on the signal transmission line And the heat dissipation defect value of each solder joint area ; S52: Calculate the performance threat value of the circuit board caused by the welding defects of each solder joint area in each adjacent electronic component test group; the performance threat value The calculation strategy is as follows: 。 8. A circuit board testing system based on visual recognition, which is implemented based on a circuit board testing method based on visual recognition as claimed in any one of claims 1 to 7, characterized in that: The system includes the following modules: Circuit board image acquisition module, welding defect value calculation module, heat dissipation defect value calculation module, signal transmission distortion defect value calculation module, solder joint performance threat value assessment module, and visualization module; The circuit board image acquisition module is used to photograph the circuit board to obtain surface image data of the circuit board; preprocess the acquired image data, and extract welding defect feature data of each solder joint of the circuit board from the preprocessed image; The welding defect value calculation module is used to import welding feature data into the welding defect assessment strategy to calculate the welding defect value of each welding point in the circuit board; The heat dissipation defect value calculation module collects the operating temperature data of the solder joint area of ​​the circuit board through the temperature sensor, and imports the temperature data and the welding defect value into the heat dissipation defect value calculation strategy to calculate the heat dissipation defect value of each solder joint area in the circuit board; The signal transmission distortion defect value calculation module is used to collect signal transmission data between different electronic components in the trial operation state of the circuit board, and import the signal transmission data into the signal distortion defect value calculation strategy to calculate the signal transmission distortion defect value in the circuit board; The solder joint performance threat value assessment module determines the performance threat value of the circuit board caused by the soldering defects of each solder joint area in the adjacent electronic component test group according to the signal transmission distortion defect value and the heat dissipation defect value of each solder joint area; The visualization module is used to arrange the performance threat values ​​of each solder joint area in descending order, and upload the arranged threat value data to the circuit board maintenance department, so as to give priority to the maintenance of solder joints with high performance threat values.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, a circuit board testing method based on visual recognition as described in any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: A memory for storing instructions; A processor is used to execute the instruction so that the device performs the operation of implementing a circuit board testing method based on visual recognition as described in any one of claims 1-7.

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