Perovskite / crystalline silicon tandem cell and method for manufacturing the same

Abstract

This invention discloses a perovskite / crystalline silicon tandem solar cell and its fabrication method, belonging to the field of perovskite / crystalline silicon tandem solar cells. It includes a bottom cell and a top cell. The bottom cell uses a crystalline silicon wafer as a substrate, with an interface passivation layer, a first doped silicon layer, a first transparent conductive oxide film layer, and a metal conductive film layer sequentially disposed on its back side. An interface passivation layer, a second doped silicon layer, and an intermediate composite layer are sequentially disposed on its front side. The top cell uses a perovskite light-absorbing layer as the light-absorbing layer, with a first carrier transport layer disposed on its back side. A second carrier transport layer, a second transparent conductive oxide film layer, and a metal grid electrode are sequentially disposed on its front side. An amorphous germanium layer is disposed between the second doped silicon layer and the intermediate composite layer, enhancing the tunneling conductivity between them, reducing the interface contact resistance, and improving the cell's flyback effect (FF) and conversion efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of perovskite / crystalline silicon tandem, in particular to a perovskite / crystalline silicon tandem cell and a preparation method thereof. BACKGROUND

[0002] The highest laboratory conversion efficiency of single-crystal silicon cells has reached 27.09%, close to the theoretical limit of 29.4%, and the future efficiency improvement space is small. In order to break through the efficiency ceiling, perovskite / crystalline silicon tandem cells have become one of the new directions of photovoltaic technology revolution. The perovskite / crystalline silicon tandem cell formed by stacking crystalline silicon cells and perovskite cells has a theoretical conversion efficiency of 43%, and the highest laboratory conversion efficiency has reached 33.9%. The perovskite / crystalline silicon tandem cell has a significantly higher theoretical efficiency and laboratory efficiency than the single-crystal silicon cell.

[0003] The tandem cell needs to use an intermediate series layer to exchange carriers between the top and bottom cells, so the photoelectric performance will directly affect the photoelectric conversion efficiency of the tandem cell.

[0004] The intermediate series layer usually uses a transparent conductive oxide film layer or an n / p type silicon-based tunneling junction. Using an n / p type silicon-based tunneling junction as an intermediate series layer, due to the process conditions, the n / p type silicon-based tunneling junction has a high tunneling barrier, which makes the carrier tunneling probability low, the density of defect states at the interface is low, and the carrier exchange rate is low, increasing the recombination loss of photo-generated carriers, thereby causing high electrical loss at the tunneling junction in the solar cell. Using a TCO composite junction as an intermediate series layer, there is a Schottky barrier between the TCO film layer and the doped silicon layer, and the barrier height is greatly affected by the effective doping concentration and the band gap of the doped silicon layer, which easily leads to a too high interface contact resistance, causing an increase in the series resistance of the cell and a decrease in the fill factor. In addition, too high a barrier height will cause the depletion layer thickness in the doped silicon layer to be too large, affecting the open-circuit voltage of the cell, and ultimately reducing the conversion efficiency of the cell.

[0005] In view of this, the present inventors have carried out in-depth research on this demand, and thus the present application is produced. SUMMARY

[0006] In view of the series of problems existing in the prior art that the perovskite / crystalline silicon tandem cell uses a transparent conductive oxide film layer or an n / p type silicon-based tunneling composite junction as an intermediate series layer, the present application provides a perovskite / crystalline silicon tandem cell, which comprises a bottom cell and a top cell,

[0007] The bottom cell takes a crystalline silicon wafer as a substrate, and the back surface is sequentially provided with an interface passivation layer, a first doped silicon layer, a first transparent conductive oxide film layer and a metal conductive film layer, and the front surface is sequentially provided with an interface passivation layer, a second doped silicon layer and an intermediate composite layer;

[0008] The top cell has a perovskite light-absorbing layer as a light-absorbing layer, a first carrier transport layer is arranged on the back surface, and a second carrier transport layer, a second transparent conductive oxide film layer and a metal grid electrode are sequentially arranged on the front surface; an amorphous germanium layer is arranged between the second doped silicon layer and the intermediate composite layer.

[0009] Preferably, the amorphous germanium layer is amorphous, nanocrystalline or microcrystalline and is undoped, p-type doped or n-type doped.

[0010] Preferably, the amorphous germanium layer comprises at least one of hydrogenated amorphous germanium, hydrogenated amorphous germanium silicon or hydrogenated amorphous germanium carbon thin film, and has a thickness of 0.5-5.0 nm.

[0011] Preferably, the crystalline silicon wafer can be a Czochralski single crystal silicon wafer, a cast ingot single crystal silicon wafer or a polycrystalline silicon wafer, can be N-type doped or P-type doped, has a resistivity of 0.1-10.0 Ωcm and a thickness of 50-500 um.

[0012] Preferably, the intermediate composite layer is one of a transparent conductive oxide layer, n-type doped silicon or p-type doped silicon, and has a thickness of 10-30 nm.

[0013] Preferably, the first doped silicon layer is a low-temperature amorphous silicon film layer or a high-temperature polycrystalline silicon film layer, and is n-type doped or p-type doped, has a doping concentration of 10 17 -10 20 cm -3 ;

[0014] The second doped silicon layer is a low-temperature amorphous silicon film layer or a high-temperature polycrystalline silicon film layer, and is n-type doped or p-type doped, has a doping concentration of 10 17 -10 20 cm -3 , and the second doped silicon layer has a conductive type opposite to that of the first doped silicon layer.

[0015] The low-temperature amorphous silicon film layer is formed at a temperature of 100-300℃, and the high-temperature polycrystalline silicon film layer is formed at a temperature of 600-1000℃.

[0016] Preferably, the low-temperature amorphous silicon film layer comprises at least one of a-Si:H, a-SiOx:H, a-SiCx:H, uc-Si:H, uc-SiOx:H, uc-SiCx:H, and has a thickness of 5-20 nm.

[0017] The high-temperature polycrystalline silicon film layer comprises at least one of poly-Si, poly-SiOx, poly-SiNx, poly-SiCx, and has a thickness of 5-50 nm.

[0018] Preferably, the first transparent conductive oxide film layer comprises at least one of doped indium oxide, tin oxide and zinc oxide-based thin film, and has a thickness of 60-150 nm.

[0019] The second transparent conductive oxide film layer comprises at least one of doped indium oxide, tin oxide, and zinc oxide-based thin film, and has a thickness of 60-150 nm;

[0020] The metal conductive film layer comprises at least one of Ag, Al, Ni, Cu, and Fe, and has a thickness of 100-1000 nm.

[0021] Preferably, the interface passivation layer comprises at least one of an intrinsic amorphous silicon film layer or a tunneling dielectric film layer;

[0022] The intrinsic amorphous silicon film layer comprises at least one of a-Si:H, a-SiOx:H, and a-SiCx:H, and has a thickness of 4-8 nm; the tunneling dielectric film layer comprises at least one of SiOx, SiNx, and SiCx, and has a thickness of 1-3 nm.

[0023] Preferably, the perovskite light-absorbing layer has a general formula of ABX3, wherein A is a monovalent cation, and the A comprises but is not limited to any one of lithium, sodium, potassium, cesium, amine group, or amidine group; B is a divalent cation, and the B comprises but is not limited to any one of lead and tin; X is a monovalent anion, and the X comprises but is not limited to any one of iodine, bromine, and chlorine; the perovskite light-absorbing layer has a thickness of 500-1500 nm.

[0024] Preferably, the first carrier transport layer comprises a first inorganic carrier transport layer and a first organic carrier transport layer stacked together; the first carrier transport layer is a hole transport layer or an electron transport layer; the first carrier transport layer has the same conductivity type as the first doped silicon layer;

[0025] The second carrier transport layer comprises a second inorganic carrier transport layer and a second organic carrier transport layer stacked together; the second carrier transport layer is a hole transport layer or an electron transport layer; the second carrier transport layer has a conductivity type opposite to that of the first carrier transport layer and the same as that of the second doped silicon layer.

[0026] Preferably, the first inorganic carrier transport layer comprises an inorganic hole transport layer or an inorganic electron transport layer; the second inorganic carrier transport layer comprises an inorganic hole transport layer or an inorganic electron transport layer, and the first inorganic carrier transport layer has a conductivity type opposite to that of the second inorganic carrier transport layer;

[0027] The inorganic hole transport layer comprises at least one of NiOx, V2O5, MoOx, WOx, and Cu2O, and has a thickness of 0.5-50.0 nm; the inorganic electron transport layer preferably comprises at least one of SnO2, TiO2, ZnO, Nb2O5, ZrO2, TiSnOx, SnZnOx, LiF, and MgFx, and has a thickness of 0.5-50.0 nm;

[0028] The first organic carrier transport layer comprises an organic hole transport layer or an organic electron transport layer, the second organic carrier transport layer comprises an organic hole transport layer or an organic electron transport layer, and the first organic carrier transport layer and the second organic carrier transport layer are opposite in conductive type;

[0029] The organic hole transport layer preferably comprises at least one of 2PACz, Me-4PACz, MeO-2PACz, PTAA, P3HT, Poly-TPD, PEDOT:PSS, Spiro-OMeTAD, m-MTDATA, Spiro-TTB, F4-TCNQ, F6-TCNNQ, and TAPC, and has a thickness of 0.5-50.0 nm.

[0030] The organic electron transport layer preferably comprises at least one of fullerene C60, fullerene C70, and fullerene derivative PCBM, and has a thickness of 0.5-50.0 nm.

[0031] Preferably, the metal gate line electrode is at least one of Ag, Al, Ni, Cu, and Fe, has a thickness of 0.1-20.0 um, and has a pitch of 0.5-5.0 mm.

[0032] The application also provides a preparation method of the perovskite / crystalline silicon stacked cell, which is simple in process and easy to implement, and specifically comprises the following steps:

[0033] S1, etching and cleaning the surface of the crystalline silicon wafer;

[0034] S2, sequentially arranging a first interface passivation layer and a first doped silicon layer on the back surface of the crystalline silicon wafer, and sequentially arranging a second interface passivation layer, a second doped silicon layer, an amorphous germanium layer, and an intermediate composite layer on the front surface of the crystalline silicon wafer;

[0035] S3, arranging a first transparent conductive oxide film layer and a metal conductive film layer on the surface of the first doped silicon layer on the back surface, and arranging a first carrier transport layer on the surface of the first doped silicon layer on the front surface;

[0036] S4, depositing a perovskite light-absorbing layer on the surface of the first carrier transport layer;

[0037] S5, depositing a second carrier transport layer on the surface of the perovskite light-absorbing layer;

[0038] S6, depositing a second transparent conductive oxide film layer on the surface of the second carrier transport layer;

[0039] S7, arranging a metal gate line electrode on the surface of the second transparent conductive oxide film layer.

[0040] The beneficial effects of the technical scheme of the present application are as follows: the ultra-thin amorphous germanium layer is arranged between the second doped silicon layer and the intermediate composite layer, the tunneling conduction capability between the second doped silicon layer and the intermediate composite layer is enhanced, the interface contact resistance is reduced, and the FF and conversion efficiency of the battery are improved. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical scheme of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced as follows, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of the drawings.

[0042] Figure 1 is a layer structure schematic diagram of a perovskite / crystalline silicon stacked battery in the present application;

[0043] Figure 2 is a preparation process flow chart of a perovskite / crystalline silicon stacked battery in the present application;

[0044] Figure 3 is a layer structure schematic diagram of a perovskite / crystalline silicon stacked battery in Example 1 of the present application;

[0045] Figure 4 is a layer structure schematic diagram of a perovskite / crystalline silicon stacked battery in Example 2 of the present application;

[0046] Figure 5 is a layer structure schematic diagram of a perovskite / crystalline silicon stacked battery in Comparative Example 1 of the present application.

[0047] In the drawings:

[0048] 1, bottom cell; 11, crystalline silicon wafer; 12, interface passivation layer; 13, first doped silicon layer; 14, first transparent conductive oxide film layer; 15, metal conductive film layer; 16, second doped silicon layer; 17, intermediate composite layer; 2, top cell; 21, perovskite light-absorbing layer; 22, first carrier transport layer; 23, second carrier transport layer; 24, second transparent conductive oxide film layer; 25, metal grid electrode. DETAILED DESCRIPTION

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0050] like Figure 1 As shown, a perovskite / crystalline silicon tandem solar cell includes a bottom cell 1 and a top cell 2.

[0051] The bottom cell 1 uses a crystalline silicon wafer 11 as a substrate. On its back side, an interface passivation layer 12, a first doped silicon layer 13, a first transparent conductive oxide film layer 14 and a metal conductive film layer 15 are sequentially disposed. On its front side, an interface passivation layer 12, a second doped silicon layer 16 and an intermediate composite layer 17 are sequentially disposed.

[0052] The top cell 2 uses a perovskite light-absorbing layer 21 as the light-absorbing layer, a first carrier transport layer 22 is provided on the back side, and a second carrier transport layer 23, a second transparent conductive oxide film layer 24 and a metal grid electrode 25 are sequentially provided on the front side; an amorphous germanium layer 3 is provided between the second doped silicon layer 16 and the intermediate composite layer 17.

[0053] In a preferred embodiment, the amorphous germanium layer 3 is an undoped, p-type doped, or n-type doped amorphous, nanocrystalline, or microcrystalline material.

[0054] In a preferred embodiment, the amorphous germanium layer 3 includes at least one of hydrogenated amorphous germanium, hydrogenated amorphous germanium silicon, or hydrogenated amorphous germanium carbon film, and its thickness is 0.5-5.0 nm.

[0055] In a preferred embodiment, the crystalline silicon wafer 11 may be a Czochralski single-crystal silicon wafer, a cast single-crystal silicon wafer, or a polycrystalline silicon wafer, and may be N-type doped or P-type doped, with a resistivity of 0.1-10.0 Ωcm and a thickness of 50-500 μm.

[0056] In a preferred embodiment, the intermediate composite layer 18 is one of a transparent conductive oxide layer, an n-type doped silicon layer, or a p-type doped silicon layer, and its thickness is 10-30 nm.

[0057] In a preferred embodiment, the first doped silicon layer 13 is a low-temperature amorphous silicon film or a high-temperature polycrystalline silicon film, and is n-type doped or p-type doped with a doping concentration of 10. 17 -10 20 cm-3 ;

[0058] The second doped silicon layer 17 is a low-temperature amorphous silicon film layer or a high-temperature polysilicon film layer, and is n-type doped or p-type doped, with a doping concentration of 10 17 -10 20 cm -3 , and the second doped silicon layer is opposite in conductive type to the first doped silicon layer.

[0059] The low-temperature amorphous silicon film layer is formed at a temperature of 100-300℃, and the high-temperature polysilicon film layer is formed at a temperature of 600-1000℃.

[0060] As a preferred embodiment, the low-temperature amorphous silicon film layer includes at least one of a-Si:H, a-SiOx:H, a-SiCx:H, uc-Si:H, uc-SiOx:H, uc-SiCx:H, with a thickness of 5-20nm.

[0061] The high-temperature polysilicon film layer includes at least one of poly-Si, poly-SiOx, poly-SiNx, poly-SiCx, with a thickness of 5-50nm.

[0062] As a preferred embodiment, the first transparent conductive oxide film layer 14 includes at least one of doped indium oxide, tin oxide, zinc oxide-based thin film, with a thickness of 60-150nm.

[0063] The second transparent conductive oxide film layer 24 includes at least one of doped indium oxide, tin oxide, zinc oxide-based thin film, with a thickness of 60-150nm.

[0064] The metal conductive film layer 15 includes at least one of Ag, Al, Ni, Cu, Fe, with a thickness of 100-1000nm.

[0065] As a preferred embodiment, the interface passivation layer 16 includes at least one of an intrinsic amorphous silicon film layer or a tunneling dielectric film layer.

[0066] The intrinsic amorphous silicon film layer includes at least one of a-Si:H, a-SiOx:H, a-SiCx:H, with a thickness of 4-8nm; and the tunneling dielectric film layer includes at least one of SiOx, SiNx, SiCx, with a thickness of 1-3nm.

[0067] As a preferred embodiment, the perovskite light-absorbing layer 21 has a general formula of ABX3, wherein A is a monovalent cation, including but not limited to any one of lithium, sodium, potassium, cesium, amine group or amidine group; B is a divalent cation, including but not limited to any one of lead or tin; X is a monovalent anion, including but not limited to any one of iodine, bromine or chlorine; the perovskite light-absorbing layer has a thickness of 500-1500 nm.

[0068] As a preferred embodiment, the first carrier transport layer 22 includes a first inorganic carrier transport layer and a first organic carrier transport layer stacked together; the first carrier transport layer is a hole transport layer or an electron transport layer; the first carrier transport layer has the same conductivity type as the first doped silicon layer;

[0069] The second carrier transport layer 23 includes a second inorganic carrier transport layer and a second organic carrier transport layer stacked together; the second carrier transport layer is a hole transport layer or an electron transport layer; the second carrier transport layer has a conductivity type opposite to that of the first carrier transport layer and the same conductivity type as the second doped silicon layer.

[0070] As a preferred embodiment, the first inorganic carrier transport layer includes an inorganic hole transport layer or an inorganic electron transport layer; the second inorganic carrier transport layer includes an inorganic hole transport layer or an inorganic electron transport layer, and the first inorganic carrier transport layer has a conductivity type opposite to that of the second inorganic carrier transport layer;

[0071] The inorganic hole transport layer includes at least one of NiOx, V2O5, MoOx, WOx, Cu2O, and has a thickness of 0.5-50.0 nm; the inorganic electron transport layer preferably includes at least one of SnO2, TiO2, ZnO, Nb2O5, ZrO2, TiSnOx, SnZnOx, LiF, MgFx, and has a thickness of 0.5-50.0 nm;

[0072] The first organic carrier transport layer includes an organic hole transport layer or an organic electron transport layer; the second organic carrier transport layer includes an organic hole transport layer or an organic electron transport layer, and the first organic carrier transport layer has a conductivity type opposite to that of the second organic carrier transport layer;

[0073] The organic hole transport layer preferably includes at least one of 2PACz, Me-4PACz, MeO-2PACz, PTAA, P3HT, Poly-TPD, PEDOT:PSS, Spiro-OMeTAD, m-MTDATA, Spiro-TTB, F4-TCNQ, F6-TCNNQ, TAPC, and has a thickness of 0.5-50.0 nm;

[0074] The organic electron transport layer preferably comprises at least one of fullerene C60, fullerene C70, fullerene derivative PCBM, and has a thickness of 0.5-50.0 nm.

[0075] As a preferred embodiment, the metal grid electrode 25 is at least one of Ag, Al, Ni, Cu, and Fe, has a thickness of 0.1-20.0 um, and has a pitch of 0.5-5.0 mm.

[0076] As shown in Figure 2 The embodiment further provides a preparation method of the perovskite / crystalline silicon stacked cell, which is simple in process and easy to implement, and specifically comprises the following steps:

[0077] S1, etching and cleaning the surface of the crystalline silicon wafer;

[0078] S2, sequentially arranging a first interface passivation layer and a first doped silicon layer on the back surface of the crystalline silicon wafer, and sequentially arranging a second interface passivation layer, a second doped silicon layer, an amorphous germanium layer, and an intermediate composite layer on the front surface of the crystalline silicon wafer;

[0079] S3, arranging a first transparent conductive oxide film layer and a metal conductive film layer on the surface of the first doped silicon layer on the back surface, and arranging a first carrier transport layer on the surface of the first doped silicon layer on the front surface;

[0080] S4, depositing a perovskite light-absorbing layer on the surface of the first carrier transport layer;

[0081] S5, depositing a second carrier transport layer on the surface of the perovskite light-absorbing layer;

[0082] S6, depositing a second transparent conductive oxide film layer on the surface of the second carrier transport layer;

[0083] S7, arranging a metal grid electrode on the surface of the second transparent conductive oxide film layer.

[0084] The beneficial effects of the perovskite / crystalline silicon stacked cell and the preparation process thereof in the embodiment are further commented on through several groups of examples.

[0085] Example 1:

[0086] As shown in Figure 3 The perovskite / crystalline silicon stacked cell in the embodiment comprises, from the back surface to the front surface, an Ag conductive film layer, an ITO layer, a p-a-Si:H layer, an i-a-Si:H layer, an n-CZ Si layer, an i-a-Si:H layer, an n-a-Si:H layer, an a-GeCx:H layer, a p-uc-SiOx:H layer, a NiOx layer, a 2PACz layer, a PVK layer, a LiF layer, a C60 layer, a SnO2 layer, an IZO layer, and an Ag grid line.

[0087] The preparation method of the perovskite / crystalline silicon stacked cell in the embodiment comprises the following steps:

[0088] S1, a wet process is used to perform texturing cleaning on the surface of the N-type silicon wafer; organic contamination and metal impurities on the surface of the silicon wafer are eliminated by using acid and alkali chemicals, a surface pyramid texture is formed on the surface of the monocrystalline silicon wafer to increase the absorption of sunlight and reduce reflection; the monocrystalline silicon wafer is a phosphorus-doped N-type monocrystalline silicon wafer with a resistivity of 1 Ωcm and a thickness of 150 um.

[0089] S2, an i / p-type amorphous silicon layer is deposited on the back surface of the silicon wafer by using a PECVD method, and an i / n-type amorphous silicon layer is deposited on the front surface of the silicon wafer; the thickness of the i layer on the back surface is 4-8 nm, the thickness of the p layer is 5-10 nm, and the boron doping concentration is 0.5%; the thickness of the i layer on the front surface is 4-8 nm, the thickness of the n layer is 5-10 nm, and the phosphorus doping concentration is 1%; the deposition temperature is 200℃.

[0090] S3, an n-type doped amorphous germanium layer with a thickness of 0.5-1 nm is deposited on the surface of the front n-type amorphous silicon layer by using a PECVD process, the reaction gas is PH3, GeH4 and H2, the flow ratio of PH3 and GeH4 is 0.01, the flow ratio of H2 and GeH4 is 5, the power density of the PECVD equipment is 15 mW / cm 2 , the pressure is 50 Pa, and the substrate temperature is 200℃; then a p-type doped microcrystalline silicon oxide layer p-uc-SiOx:H is deposited on the surface of the amorphous germanium layer, the deposition temperature is 180℃, the thickness is 15 nm, SiH4, CO2, H2 and B2H6 are used as the reaction gas, the CO2 / SiH4 gas flow ratio is 0.5, the H2 / SiH4 flow ratio is 200:1, and the B2H6 / SiH4 gas flow ratio is 0.5%.

[0091] S4, ITO / Ag is deposited on the surface of the back p-type amorphous silicon layer by using a PVD method, the ITO target material is 90wt% In2O3+10wt% SnO, the sputtering atmosphere is 0.2% O2 / Ar, the ITO thickness is 100 nm, the Ag target material has a purity of 99.99wt%, and the Ag thickness is 500 nm; then NiOx is deposited on the surface of the front p-type doped microcrystalline silicon oxide layer by using an RF sputtering process, the target material is a NiO target material with a purity of 99.99%, the sputtering atmosphere is pure Ar, and the thickness is 20 nm.

[0092] S5, 2PACz and PVK layers are deposited on the surface of the NiOx by using a spin coating+drying method. First, 1 mg / mL 2PACz ethanol solution is used to spin coat at a speed of 4000 r / min for 30 s, and then drying is performed at 100℃ for 10 min; 1.7 mol / L Cs 0.05 FA 0.8 MA 0.15Pb(I 0.755 Br 0.255 A perovskite precursor solution was prepared by mixing DMF and DMSO (volume ratio 4:1) at 3500 rpm for 40 s, and then dried at 100 °C / N2 for 30 min. The resulting perovskite had a band gap of 1.69 eV.

[0093] S6 uses a vapor deposition method to deposit LiF / C60 on the surface of the PVK layer. 1 nm of LiF is thermally evaporated on the PVK surface, and 18 nm of C60 is thermally evaporated and deposited on the LiF surface.

[0094] S7 uses the ALD process to deposit SnO2 on a C60 surface. TDMASn and H2O are used as reactant gases, N2 is used as carrier gas, the deposition temperature is 80℃, and the SnO2 deposition thickness is 20nm.

[0095] S8 uses PVD to deposit IZO on the SnO2 surface. The IZO target composition is 90wt% In2O3 + 10wt% ZnO, the sputtering atmosphere is 0.2% O2 / Ar, the IZO thickness is 100nm, the Ag target purity is 99.99wt%, and the Ag thickness is 500nm.

[0096] S9 uses a printing and curing process to form low-temperature Ag paste grid line electrodes on the IZO surface. The grid line width is 30µm, the spacing is 2mm, and the curing temperature is 120℃ for 10min.

[0097] Example 2:

[0098] like Figure 4 As shown, the perovskite / crystalline silicon tandem solar cell in this embodiment includes, from the back side to the front side, an Ag conductive film layer, an ITO layer, a p-poly-Si layer, a SiO2 layer, an n-CZ Si layer, a SiO2 layer, an n-poly-Si layer, an a-GeCx:H layer, a p-uc-SiOx:H layer, a NiOx layer, a 2PACz layer, a PVK layer, a LiF layer, a C60 layer, a SnO2 layer, an IZO layer, and an Ag gate line.

[0099] The fabrication method of the perovskite / crystalline silicon tandem solar cell in this embodiment includes the following steps:

[0100] S1. A wet process is used to texturize and clean the surface of the N-type silicon wafer. Acidic and alkaline chemicals are used to remove organic contaminants and metallic impurities from the silicon wafer surface, forming a surface pyramid texture on the monocrystalline silicon wafer to increase sunlight absorption and reduce reflection. The monocrystalline silicon wafer is a phosphorus-doped N-type monocrystalline silicon wafer with a resistivity of 1 Ωcm and a thickness of 150 μm.

[0101] S2, depositing ultra-thin SiO2 film layer and p-type amorphous silicon film layer on the back surface of the silicon wafer by PECVD; depositing ultra-thin SiO2 film layer and n-type amorphous silicon film layer on the front surface of the silicon wafer. The ultra-thin SiO2 film layer is formed by plasma discharge oxidation with N2O as the reaction gas, the deposition temperature is 250°C, and the thickness is 2nm; the n-type amorphous silicon film layer is deposited at a temperature of 250°C and a thickness of 20nm, with SiH4, H2 and PH3 as the reaction gases, and the PH3 / SiH4 gas flow ratio being 1.5%; the p-type amorphous silicon film layer is deposited at a temperature of 250°C and a thickness of 20nm, with SiH4, H2 and B2H6 as the reaction gases, and the B2H6 / SiH4 gas flow ratio being 1%.

[0102] S3, activating the p-type and n-type amorphous silicon film layers by high-temperature annealing in a furnace tube, the annealing temperature being 850°C, the time being 30min, and the annealing atmosphere being N2; after the annealing treatment, the p-type and n-type amorphous silicon film layers are converted into p-type and n-type polycrystalline silicon film layers, the doping concentration being 1E20-1E21cm -3 .

[0103] S4, removing the parasitic oxide layer on the surface of the p-type and n-type polycrystalline silicon film layers after the annealing by using HF solution, the HF concentration being 1wt%, the temperature being 20-30°C, and the time being 1-3min.

[0104] S5, depositing n-type doped amorphous germanium carbon layer with a thickness of 0.5-1.0nm on the front n-type polycrystalline silicon film layer by PECVD process, the reaction gases being PH3, GeH4, CH4 and H2, the flow ratio of PH3 and GeH4 being 0.01, the flow ratio of CH4 / GeH4 being 4, and the flow ratio of H2 and GeH4 being 5, the power density of the PECVD equipment being 75mW / cm 2 , the pressure being 50Pa, and the substrate temperature being 180°C; then depositing p-type doped microcrystalline silicon oxide layer p-uc-SiOx:H on the surface of the amorphous germanium carbon layer, the deposition temperature being 180°C, the thickness being 15nm, and the reaction gases being SiH4, CO2, H2 and B2H6, the CO2 / SiH4 gas flow ratio being 0.5, the H2 / SiH4 flow ratio being 200:1, and the B2H6 / SiH4 gas flow ratio being 0.5%.

[0105] S6, depositing ITO / Ag on the surface of the back p-type amorphous silicon layer by PVD, the ITO target material being 90wt% In2O3+10wt% SnO, the sputtering atmosphere being 0.2% O2 / Ar, the ITO thickness being 100nm, the Ag target material being pure with a purity of 99.99wt%, and the Ag thickness being 500nm; depositing NiOx on the surface of the front p-type doped microcrystalline silicon oxide layer, the sputtering target material being pure NiO with a purity of 99.99%, the sputtering atmosphere being pure Ar, and the thickness being 20nm;

[0106] S7, using a spin-coating and drying method, deposited 2PACz and PVK layers on the NiOx surface. First, a 1 mg / mL 2PACz ethanol solution was used for spin-coating at 4000 rpm for 30 seconds, followed by drying at 100°C for 10 minutes; the resulting deposition composition was 1.7 mol / L. 0.05 FA 0.8 MA 0.15 Pb(I 0.755 Br 0.255 A perovskite precursor solution was prepared by mixing DMF and DMSO (volume ratio 4:1) at 3500 rpm for 40 s, and then dried at 100 °C / N2 for 30 min. The resulting perovskite had a band gap of 1.69 eV.

[0107] S8 uses a vapor deposition method to deposit LiF / C60 on the surface of the PVK layer. 1 nm of LiF is thermally evaporated on the PVK surface, and 18 nm of C60 is thermally evaporated and deposited on the LiF surface.

[0108] S9 uses the ALD process to deposit SnO2 on a C60 surface. TDMASn and H2O are used as reactant gases, N2 is used as carrier gas, the deposition temperature is 80℃, and the SnO2 deposition thickness is 20nm.

[0109] S10 uses PVD to deposit IZO on the SnO2 surface. The IZO target composition is 90wt% In2O3 + 10wt% ZnO, the sputtering atmosphere is 0.2% O2 / Ar, the IZO thickness is 100nm, the Ag target purity is 99.99wt%, and the Ag thickness is 500nm.

[0110] S11 uses a printing and curing method to form low-temperature Ag paste grid line electrodes on the IZO surface. The grid line width is 30µm and the spacing is 2mm; the curing temperature is 120℃ and the time is 10min.

[0111] Comparative Example 1:

[0112] like Figure 5 As shown, the perovskite / crystalline silicon tandem solar cell in this comparative example includes, from the back to the front, an Ag conductive film layer, an ITO layer, a pa-Si:H layer, an ia-Si:H layer, an n-CZ Si layer, an ia-Si:H layer, a na-Si:H layer, a p-uc-SiOx:H layer, a NiOx layer, a 2PACz layer, a PVK layer, a LiF layer, a C60 layer, a SnO2 layer, an IZO layer, and an Ag gate line.

[0113] The fabrication method of the perovskite / crystalline silicon tandem solar cell in this comparative example includes the following steps:

[0114] S1, using wet process, the surface of N-type silicon wafer is etched and cleaned. Using acid and alkali chemicals, the organic contamination and metal impurities on the surface of the silicon wafer are eliminated, the surface pyramid texture is formed on the surface of the monocrystalline silicon wafer, the absorption of sunlight is increased and the reflection is reduced; the monocrystalline silicon wafer is a phosphorus-doped N-type monocrystalline silicon wafer with a resistivity of 1Ωcm and a thickness of 150um.

[0115] S2, using PECVD method, i / p type amorphous silicon layer is deposited on the back surface of the silicon wafer, and i / n type amorphous silicon layer is deposited on the front surface of the silicon wafer. The thickness of the back i layer is 4-8nm, the thickness of the p layer is 5-10nm, the boron doping concentration is 0.5%; the thickness of the front i layer is 4-8nmn, the thickness of the n layer is 5-10nm, the phosphorus doping concentration is 1%; the deposition temperature is 200℃.

[0116] S3, using PECVD process, p-type doped microcrystalline silicon oxide layer p-uc-SiOx:H is deposited on the surface of the front n-type polysilicon film layer, the deposition temperature is 180℃, the thickness is 15nm, SiH4, CO2, H2 and B2H6 are used as reaction gas, the CO2 / SiH4 gas flow ratio is 0.5, the H2 / SiH4 flow ratio is 200:1,

[0117] B2H6 / SiH4 gas flow ratio is 0.5%.

[0118] S4, using PVD method, ITO / Ag is deposited on the surface of the back p amorphous silicon layer, ITO target material is 90wt% In2O3+10wt% SnO, sputtering atmosphere is 0.2% O2 / Ar, ITO thickness is 100nm, Ag target material is pure 99.99wt%, Ag thickness is 500nm; NiOx is deposited on the front p-type doped microcrystalline silicon oxide layer, NiOx uses RF sputtering process, the purity of NiOx target material is 99.99%, the sputtering atmosphere is pure Ar, the thickness of NiOx is 20nm.

[0119] S5, using spin coating + drying method, 2PACz and PVK layers are deposited on the surface of NiOx. First, 1mg / mL 2PACz ethanol solution is used, the rotation speed is 4000r / min, and the spin coating time is 30s, then it is dried at 100℃ for 10min; 1.7mol / L Cs 0.05 FA 0.8 MA 0.15 Pb(I 0.755 Br 0.255 )3 DMF and DMSO mixed solution (volume ratio 4:1) perovskite precursor solution, rotation speed 3500rpm, time 40s, then dried at 100℃ / N2 for 30min, the obtained perovskite band gap is 1.69eV.

[0120] S6, LiF / C60 is deposited on the surface of the PVK layer by evaporation. 1 nm of LiF is evaporated on the surface of the PVK, and 20 nm of C60 is evaporated on the surface of the LiF.

[0121] S7, SnO2 is deposited on the surface of the C60 by ALD. TDMASn and H2O are used as the reaction gas, N2 is used as the carrier gas, the deposition temperature is 80 DEG C, and the thickness of the deposited SnO2 is 20 nm.

[0122] S8, IZO is deposited on the surface of the SnO2 by PVD. The target material of the IZO is composed of 90 wt% In2O3+10 wt% ZnO, the sputtering atmosphere is 0.2% O2 / Ar, the thickness of the IZO is 100 nm, the target material of the Ag is pure, the sputtering atmosphere is pure Ar, and the thickness of the Ag is 500 nm.

[0123] S9, a low-temperature Ag paste gate line electrode is formed on the surface of the IZO by printing and curing. The width of the gate line is 30 um, the pitch is 2 mm, the curing temperature is 120 DEG C, and the curing time is 10 min.

[0124] The solar cells obtained in the above two groups of examples and one group of comparative examples are subjected to performance testing, IV tester is used to determine the parameters of the solar cell, and the results are shown in Table 1.

[0125] Table 1 shows the performance test results of the solar cells in the examples.

[0126]

[0127] As shown in Table 1, in the perovskite / silicon tandem solar cell of Comparative Example 1, the n / p type silicon-based tunnel junction is used as the intermediate series layer, and the tunneling barrier of the n / p type silicon-based tunnel junction is relatively high due to the limitation of the process conditions, which makes the carrier tunneling probability low, the density of the defect state at the interface low, and the carrier exchange rate low, resulting in the increase of the recombination loss of the photo-generated carriers, and thus the electrical loss at the tunnel junction in the solar cell is high, and the FF and the efficiency of the tandem solar cell are low.

[0128] In Example 1, an ultra-thin amorphous germanium layer a-Ge:H is arranged between the bottom cell n-a-Si:H and the intermediate composite layer p-uc-SiOx:H, which enhances the tunneling conductivity between the n-a-Si:H and the p-uc-SiOx:H, reduces the interface tunneling barrier, and improves the FF and the conversion efficiency of the solar cell.

[0129] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A perovskite / crystalline silicon tandem cell, characterized by, The bottom cell and the top cell are included, The bottom cell takes a crystalline silicon wafer as a substrate, and a back surface of the crystalline silicon wafer is sequentially provided with an interface passivation layer, a first doped silicon layer, a first transparent conductive oxide film layer and a metal conductive film layer, and a front surface of the crystalline silicon wafer is sequentially provided with an interface passivation layer, a second doped silicon layer and an intermediate composite layer; The top cell takes a perovskite light-absorbing layer as a light-absorbing layer, and a back surface of the top cell is provided with a first carrier transport layer, and a front surface of the top cell is sequentially provided with a second carrier transport layer, a second transparent conductive oxide film layer and a metal grid electrode; an amorphous germanium layer is arranged between the second doped silicon layer and the intermediate composite layer; The amorphous germanium layer includes at least one of hydrogenated amorphous germanium, hydrogenated amorphous germanium silicon or hydrogenated amorphous germanium carbon thin film, and a thickness of the amorphous germanium layer is 0.5-5.0 nm; The intermediate composite layer is one of n-type doped silicon or p-type doped silicon.

2. The perovskite / crystalline silicon tandem cell of claim 1, wherein A thickness of the intermediate composite layer is 10-30 nm.

3. The perovskite / crystalline silicon tandem cell of claim 1, wherein The first doped silicon layer is a low-temperature amorphous silicon film layer or a high-temperature polysilicon film layer, and is n-type doped or p-type doped, with a doping concentration of 10 17 -10 20 cm -3 ; The second doped silicon layer is a low-temperature amorphous silicon film layer or a high-temperature polysilicon film layer, and is n-type doped or p-type doped, with a doping concentration of 10 17 -10 20 cm -3 , and the second doped silicon layer is opposite to the first doped silicon layer in the conductive type. A forming temperature of the low-temperature amorphous silicon film layer is 100-300 ℃, and a forming temperature of the high-temperature polycrystalline silicon film layer is 600-1000 ℃.

4. The perovskite / crystalline silicon tandem cell of claim 3, wherein The low-temperature amorphous silicon film layer includes at least one of a-Si:H, a-SiOx:H, a-SiCx:H, uc-Si:H, uc-SiOx:H, uc-SiCx:H, and a thickness of the low-temperature amorphous silicon film layer is 5-20 nm; The high-temperature polycrystalline silicon film layer includes at least one of poly-Si, poly-SiOx, poly-SiNx, poly-SiCx, and a thickness of the high-temperature polycrystalline silicon film layer is 5-50 nm.

5. The perovskite / crystalline silicon stacked cell according to claim 1, wherein The interface passivation layer includes at least one of an intrinsic amorphous silicon film layer or a tunneling dielectric film layer; The intrinsic amorphous silicon film layer includes at least one of a-Si:H, a-SiOx:H, a-SiCx:H, and a thickness of the intrinsic amorphous silicon film layer is 4-8 nm; the tunneling dielectric film layer includes at least one of SiOx, SiNx, SiCx, and a thickness of the tunneling dielectric film layer is 1-3 nm.

6. The perovskite / crystalline silicon stacked cell according to claim 1, wherein The first carrier transport layer includes a first inorganic carrier transport layer and a first organic carrier transport layer which are stacked; the first carrier transport layer is a hole transport layer or an electron transport layer; and the first carrier transport layer and the first doped silicon layer are of the same conductive type; The second carrier transport layer includes a second inorganic carrier transport layer and a second organic carrier transport layer which are stacked; the second carrier transport layer is a hole transport layer or an electron transport layer; the second carrier transport layer and the first carrier transport layer are of opposite conductive types, and the second carrier transport layer and the second doped silicon layer are of the same conductive type.

7. The perovskite / crystalline silicon stacked cell according to claim 6, wherein The first inorganic carrier transport layer includes an inorganic hole transport layer or an inorganic electron transport layer; the second inorganic carrier transport layer includes an inorganic hole transport layer or an inorganic electron transport layer, and the first inorganic carrier transport layer and the second inorganic carrier transport layer are of opposite conductive types. The inorganic hole transport layer comprises at least one of NiOx, V2O5, MoOx, WOx, Cu2O, and has a thickness of 0.5-50.0 nm; the inorganic electron transport layer comprises at least one of SnO2, TiO2, ZnO, Nb2O5, ZrO2, TiSnOx, SnZnOx, LiF, MgFx, and has a thickness of 0.5-50.0 nm; The first organic carrier transport layer comprises an organic hole transport layer or an organic electron transport layer, the second organic carrier transport layer comprises an organic hole transport layer or an organic electron transport layer, and the first organic carrier transport layer and the second organic carrier transport layer are opposite in conductive type; The organic hole transport layer comprises at least one of 2PACz, Me-4PACz, MeO-2PACz, PTAA, P3HT, Poly-TPD, PEDOT:PSS, Spiro-OMeTAD, m-MTDATA, Spiro-TTB, F4-TCNQ, F6-TCNNQ, and TAPC, and has a thickness of 0.5-50.0 nm; The organic electron transport layer comprises at least one of fullerene C60, fullerene C70, and fullerene derivative PCBM, and has a thickness of 0.5-50.0 nm.

8. A method for producing a perovskite / crystalline silicon tandem cell as claimed in any one of claims 1 to 7, characterized in that, The method comprises the following steps: S1, etching and cleaning the surface of a crystalline silicon wafer; S2, sequentially arranging a first interface passivation layer and a first doped silicon layer on the back surface of the crystalline silicon wafer, and sequentially arranging a second interface passivation layer, a second doped silicon layer, an amorphous germanium layer, and an intermediate composite layer on the front surface of the crystalline silicon wafer; S3, arranging a first transparent conductive oxide film layer and a metal conductive film layer on the surface of the first doped silicon layer on the back surface, and arranging a first carrier transport layer on the surface of the first doped silicon layer on the front surface; S4, depositing a perovskite light-absorbing layer on the surface of the first carrier transport layer; S5, depositing a second carrier transport layer on the surface of the perovskite light-absorbing layer; S6, depositing a second transparent conductive oxide film layer on the surface of the second carrier transport layer; S7, arranging a metal grid electrode on the surface of the second transparent conductive oxide film layer.

Images