Power management for peripheral component interconnect

Abstract

Aspects relate to power management of peripheral component interconnect. Transmit traffic activity can be monitored for a peripheral component interconnect express (PCIe) link (1102). Receive traffic activity can also be monitored for the link (1104). A first power of transmit lines of the link is managed as a transmit group according to the transmit traffic activity (1106). A second power of receive lines of the link is managed as a receive group according to the receive traffic activity (1108). The first power of the transmit lines is managed independently of the second power of the receive lines.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to pending U.S. nonprovisional application No. 17 / 715,792, filed April 7, 2022, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Background Technology

[0003] This disclosure relates generally to peripheral component rapid interconnect (PCIe) devices, and more specifically to managing link power for PCIe devices. High-speed interfaces are frequently used between circuits and components in mobile wireless devices and other complex systems. For example, some devices may include processing, communication, storage, and / or display devices that interact with each other via one or more high-speed interfaces. Some of these devices (including synchronous dynamic random access memory (SDRAM)) may be able to provide or use data and control information at the processor clock rate. Other devices (e.g., display controllers) may use variable amounts of data at relatively low video refresh rates.

[0004] The Peripheral Component Rapid Interconnect (PCIe) standard is a popular high-speed interface that supports high-speed links capable of sending data at gigabits per second. This interface also features multiple standby modes for when the link is inactive. Compared to parallel buses, PCIe offers lower latency and higher data transfer rates. PCIe is specified for communication between a wide variety of different devices. Typically, a device (e.g., a processor or hub) acts as a host, communicating with multiple devices (called endpoints) via PCIe links. Peripheral devices or components can include graphics adapters, network interface cards (NICs), storage accelerator devices, mass storage devices, input / output interfaces, and other high-performance peripherals.

[0005] The connection between any two PCIe devices is called a link. A PCIe link is established around a full-duplex, serial (1-bit), differential, point-to-point connection called a channel. Using PCIe, data is transmitted via two pairs of signals: two lines (wires, board traces, etc.) for transmitting and two lines for receiving. The transmit and receive pairs are separate differential pairs used for a total of four data lines per channel. The link comprises a set of channels, and each channel is capable of simultaneously transmitting and receiving data packets between the host and the endpoints.

[0006] As currently defined, a PCIe link can scale from one lane to 32 individual lanes. Typical deployments have 1, 2, 4, 8, 12, 16, or 32 lanes, which can be labeled as xl, x2, x4, x8, x12, x16, or x32, respectively, where the number is literally the number of lanes. In one example, a PCIe xl implementation has four lines to connect one pair of wires per direction for one lane, while a PCIe x16 implementation has 16 times that number, 16 lanes, or 64 lines. SUMMARY

[0007] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0008] In one example, an apparatus for a Peripheral Component Interconnect Express (PCIe) link having an interface circuit and a controller is disclosed. The apparatus includes an interface circuit and a controller configured to provide an interface to a Peripheral Component Interconnect Express (PCIe) link. The controller is configured to monitor transmit traffic activity of the link, monitor receive traffic activity of the link, manage a first power of transmit lanes of the link as a transmit group according to the transmit traffic activity, and manage a second power of receive lanes of the link as a receive group according to the receive traffic activity independent of the power of the transmit lanes.

[0009] Another example provides a method that includes monitoring transmit traffic activity of a Peripheral Component Interconnect Express (PCIe) link, monitoring receive traffic activity of the link, managing a first power of transmit lanes of the link as a transmit group according to the transmit traffic activity, and managing a second power of receive lanes of the link as a receive group according to the receive traffic activity independent of the power of the transmit lanes.

[0010] Another example provides a non-transitory computer readable medium having stored therein instructions for causing a processor of an interconnect link to perform operations comprising monitoring transmit traffic activity of a Peripheral Component Interconnect Express (PCIe) link, monitoring receive traffic activity of the link, managing a first power of transmit lanes of the link as a transmit group according to the transmit traffic activity, and managing a second power of receive lanes of the link as a receive group according to the receive traffic activity independent of the power of the transmit lanes.

[0011] To the accomplishment of the foregoing and related ends, one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the appended drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations can be employed and the described implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block diagram of a computing architecture with a PCIe interface suitable for aspects of the present disclosure.

[0013] Figure 2 is a block diagram of a system including a host system and an endpoint device system according to aspects of the present disclosure.

[0014] Figure 3 is a diagram of lanes in a link and corresponding drivers according to aspects of the present disclosure.

[0015] Figure 4 is a state diagram illustrating operation of a power management state machine according to aspects of the present disclosure.

[0016] Figure 5 is a block diagram of duplex traffic lanes of a link between a host and an endpoint according to aspects of the present disclosure.

[0017] Figure 6 is a block diagram of duplex traffic lanes of a link grouped into transmit and receive groups according to aspects of the present disclosure.

[0018] Figure 7 is an example of a lookup table mapping traffic activity to a number of active lanes according to certain aspects of the present disclosure.

[0019] Figure 8 is a table of link activity conditions in an x4 link according to aspects of the present disclosure.

[0020] Figure 9 is a state diagram illustrating a portion of a power management protocol for transmit and receive states of an x4 link according to aspects of the present disclosure.

[0021] Figure 10 is a block diagram of PCIe link interface processing circuitry according to aspects of the present disclosure.

[0022] Figure 11 is a flow diagram of an exemplary method for bandwidth-based power management according to aspects of the present disclosure. DETAILED DESCRIPTION

[0023] The detailed description set forth below, in connection with the appended drawings and embodiments described theriin, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0024] One aspect relates to a system for managing power across a wired peripheral component interconnect link (e.g., PCIe). A first power of transmit lanes is managed as a transmit group according to transmit traffic activity, and a second power of receive lanes is managed as a receive group according to receive traffic activity. The power of the receive lanes of the link is managed independently of the power of the transmit lanes of the link. Power can be managed by controlling the number of active lanes in each direction, among other communication parameters. In some aspects, each lane is placed in an active or standby state. In some aspects, each group is placed in an active or one of a plurality of standby states depending on the number of lanes in an active state.

[0025] Aspects of the disclosure provide bandwidth-based PCIe power management for each direction of a link. Independent active lane scaling can be used in each direction. Aspects of the disclosure are discussed below using the example of an x4 link in PCIe Generation 5. However, the disclosure is not limited to these examples. The disclosure can be used to provide power management for future implementations of the PCIe standard (e.g., GEN 6 and beyond). Moreover, while the disclosure is discussed with respect to PCIe links, the underlying principles of the disclosed systems and methods can be implemented in other types of peripheral component interconnect (PCI) links or even other physical serial interconnects between a host and a client device.

[0026] Aspects of the present disclosure relate to dynamically changing the power state of a Peripheral Component Interconnect Express (PCIe) link to optimally conserve device power. The PCIe specification allows for an active state (e.g., L0) and one or more standby states (e.g., LI, L2, L3) and sub-states (e.g., LI.1, LI.2). In an example, each lane of a link can have a different active state. As one example, an x4 link with 4 lanes can operate with zero, one, two, three, or all four lanes active, giving five possible active states but sixteen possible active implementations depending on which lanes are active. As one example, a state with one active lane can be implemented in four different ways by making any one of the four lanes the active lane. Each active state also allows for different link speeds, also referred to as data rates, which depend on the specified speed capability of the link. PCIe GEN1 allows for 2.5 gigatransfers per second (GT / s), PCIe GEN2 allows for 5 GT / s, PCIe GEN3 allows for 8 GT / s, PCIe GEN4 allows for 16 GT / s, PCIe GEN5 allows for 32 GT / s, and subsequent versions can provide higher data rates for each lane of the link.

[0027] Power management and bandwidth negotiation as defined in current standards are performed at link initialization, but can be repeated at a later time. During negotiation, each link partner can advertise the number of lanes supported (e.g., link width) and the bandwidth desired to run. For example, the link partners can agree to run at the highest bandwidth supported by both partners. The link partners negotiate a number of lanes of the link to be in an active state, and can change the number of lanes to a lower rate for reasons of link stability. In one example, the link width can be changed autonomously by the hardware. As the number of lanes increases, the power to run the link also increases. Thus, in some cases, an x16 link can be run as an xl link at a lower power. This reduces the power consumed by the supporting hardware during periods of low activity.

[0028] Power management and bandwidth negotiation are done for the entire link as defined in current standards. Transmit and receive data are handled in the same way. For example, if the negotiated receive bandwidth is large, the power allocated to the transmit bandwidth will also be large. However, in some cases, the transmit and receive usage or requirements are different. As one example, traffic flow can be largely unidirectional with no reverse traffic. This can occur, for example, if the link is used for data storage and there are a large number of write operations to the data store. In another example, the receive bandwidth usage can be large while the transmit usage can be very low. This can occur, for example, if the link is used to download video files over a wireless network link in which only a small number of acknowledgement packets are transmitted in the transmit direction. There are many other scenarios in which there is asymmetric bandwidth usage. Additional power savings can be achieved by handling power management and bandwidth negotiation independently in one direction from the other.

[0029] In some examples, the transmit lines of all lanes in a PCIe link are managed as a transmit group, and the receive lines of all lanes in a PCIe link are managed as a receive group. Separate power management and bandwidth negotiation are performed for transmit and receive, and the results are set in transmit and receive registers maintained at the host and endpoint. This allows the transmit group to run at low power, for example two or four active lines with the rest in standby, even if the receive group has more active lines and runs at high power, for example eight or sixteen receive lines, and vice versa.

[0030] Figure 1 is a block diagram of an example computing architecture that uses a PCIe interface. The computing architecture 100 operates using multiple high-speed PCIe interface serial links. A PCIe interface can be characterized as a device that includes a point-to-point topology, with individual serial links connecting each device to a host, which is referred to as a root complex 104. In the computing architecture 100, the root complex 104 couples a processor 102 to a memory device (e.g., a memory subsystem 108) and a PCIe switch fabric 106. In some instances, the PCIe switch fabric 106 includes cascaded switch devices. One or more PCIe endpoint devices 110 can be coupled directly to the root complex 104, while other PCIe endpoint devices 112-1, 112-2,..., 112-N can be coupled to the root complex 104 through the PCIe switch fabric 106. The root complex 104 can be coupled to the processor 102 using a proprietary local bus interface or a standard defined local bus interface. The root complex 104 can control configuration and data transactions over the PCIe interface and can generate transaction requests for the processor 102. In some examples, the root complex 104 is implemented in the same integrated circuit (IC) device as the processor 102. The root complex 104 supports multiple PCIe ports.

[0031] Root complex 104 can control communications between processor 102 and memory subsystem 108, which is one example of an endpoint. Root complex 104 also controls communications between processor 102 and other PCIe endpoint devices 110, 112-1, 112-2,..., 112-N. A PCIe interface can support full-duplex communication between any two endpoints without fixed limitations on concurrent access across multiple endpoints. Data packets can carry information over any PCIe link. In a multi-lane PCIe link, packet data can be striped across multiple lanes. The number of lanes in a multi-lane link can be negotiated during device initialization and can be different for different endpoints.

[0032] When one or both traffic directions of a lane of a PCIe link are not fully utilized by low-bandwidth applications, which can be adequately served by fewer lanes, the root complex 104 and the endpoints can run the link with more or fewer transmit and receive lanes in one or both directions. In some embodiments, the lanes of the link can be placed in one or more standby states in which some or all of the lanes are running in a low-power or no-power mode. Changing the number of active lanes for low-bandwidth applications reduces the power to run the link. Providing less power reduces current leakage, heat, and power consumption.

[0033] Figure 2 is a block diagram of an example PCIe system in which aspects of the present disclosure can be implemented. System 205 includes a host system 210 and an endpoint device system 250. Host system 210 can be integrated on a first chip (e.g., a system on a chip or SoC), and endpoint device system 250 can be integrated on a second chip. Alternatively, the host system and / or the endpoint device system can be integrated in a first package and a second package (e.g., a SiP), a first system board and a second system board having multiple chips, or in other hardware or any combination. In this example, host system 210 and endpoint device system 250 are coupled through a PCIe link 285.

[0034] Host system 210 includes one or more host clients 214. Each of the one or more host clients 214 can be implemented on a processor that executes software that performs the functions of the host client 214 discussed herein. For examples of more than one host client, the host clients can be implemented on the same processor or different processors. Host system 210 also includes a host controller 212, which can perform root complex functions. Host controller 212 can be implemented on a processor that executes software that performs the functions of the host controller 212 discussed herein.

[0035] The host system 210 includes a PCIe interface circuit 216, a system bus interface 215, and a host system memory 240. The system bus interface 215 can interface one or more host clients 214 with the host controller 212, and each of the one or more host clients 214 and the host controller 212 with the PCIe interface circuit 216 and the host system memory 240. The PCIe interface circuit 216 provides an interface to the PCIe link 285 for the host system 210. In this regard, the PCIe interface circuit 216 is configured to send data (e.g., from the host clients 214) to the endpoint device system 250 via the PCIe link 285 and receive data from the endpoint device system 250 via the PCIe link 285. The PCIe interface circuit 216 includes a PCIe controller 218, a physical interface 220 for a Peripheral Component Interconnect Express (PIPE) interface, a physical (PHY) transmit (TX) block 222, a clock generator 224, and a PHY receive (RX) block 226. The PIPE interface 220 provides a parallel interface between the PCIe controller 218 and the PHY TX block 222 and the PHY RX block 226. The PCIe controller 218, which can be implemented in hardware, can be configured to perform transaction layer, data link layer, and control flow functions specified in the PCIe specification, as discussed further below.

[0036] The host system 210 also includes an oscillator (e.g., a crystal oscillator or “XO”) 230 configured to generate a reference clock signal 232. In one example, the reference clock signal 232 can have a frequency of 19.2 MHz, but is not limited to this frequency. The reference clock signal 232 is input to the clock generator 224, which generates a plurality of clock signals based on the reference clock signal 232. In this regard, the clock generator 224 can include one or more phase-locked loops (PLLs), where each PLL generates a respective one of the plurality of clock signals by multiplying the frequency of the reference clock signal 232.

[0037] The endpoint device system 250 includes one or more device clients 254. Each device client 254 can be implemented on a processor that executes software that performs the functions of the device client 254 discussed herein. For examples with more than one device client 254, the device clients 254 can be implemented on the same processor or different processors. The endpoint device system 250 also includes a device controller 252. The device controller 252 can be configured to receive a bandwidth request from one or more device clients and determine whether to change the number of transmit lanes or the number of receive lanes based on the bandwidth request. The device controller 252 can be implemented on a processor that executes software that performs the functions of the device controller.

[0038] The endpoint device system 250 includes PCIe interface circuitry 260, system bus interface 256, and endpoint system memory 274. The system bus interface 256 can interface one or more device clients 254 with the device controller 252, and each of the one or more device clients 254 and the device controller 252 with the PCIe interface circuitry 260 and the endpoint system memory 274. The PCIe interface circuitry 260 provides an interface to the PCIe link 285 for the endpoint device system 250. In this regard, the PCIe interface circuitry 260 is configured to transmit data (e.g., from the device clients 254) to the host system 210 (also referred to as a host device) over the PCIe link 285 and receive data from the host system 210 via the PCIe link 285. The PCIe interface circuitry 260 includes a PCIe controller 262, a PIPE interface 264, a PHY TX block 266, a PHY RX block 270, and a clock generator 268. The PIPE interface 264 provides a parallel interface between the PCIe controller 262 and the PHY TX block 266 and the PHY RX block 270. The PCIe controller 262 (which can be implemented in hardware) can be configured to perform transaction layer, data link layer, and control flow functions.

[0039] The host system memory 240 and the endpoint system memory 274 at the endpoint can be configured to contain registers for the state of each transmit and receive lane of the PCIe link 285. The transmit lanes can be configured as differential transmit lane pairs, and the receive lanes can be configured as differential receive lane pairs. These registers include group control registers and group status registers. In an example, both the host system memory 240 and the endpoint system memory 274 have transmit group control registers, transmit group status registers, and transmit group capability registers, etc. for a transmit group. Both the host system memory 240 and the endpoint system memory 274 also have receive group control registers, receive group status registers, and receive group capability registers, etc. for a receive group.

[0040] The endpoint device system 250 also includes an oscillator (e.g., a crystal oscillator) 272 configured to generate a stable reference clock signal 273 for the endpoint system memory 274. In an example, the clock generator 268 is configured to generate a clock signal 271 for the PCIe interface circuitry 260 based on the stable reference clock signal 273. Figure 2In the example of FIG. 2, clock generator 224 at host system 210 is configured to generate a stable reference clock signal 273 that is forwarded by PHY RX block 226 to endpoint device system 250 via differential clock line 288. At endpoint device system 250, PHY RX block 270 receives the EP reference clock signal on differential clock line 288 and forwards the EP reference clock signal to clock generator 268. The EP reference clock signal can have a frequency of 100 MHz, but is not limited to this frequency. Clock generator 268 is configured to generate a plurality of clock signals based on the EP reference clock signal from differential clock line 288, as discussed further below. In this regard, clock generator 268 can include a plurality of PLLs, with each PLL generating a respective one of the plurality of clock signals by multiplying the frequency of the EP reference clock signal.

[0041] System 205 also includes a power management integrated circuit (PMIC) 290 coupled to a power source 292 (e.g., a mains voltage, a battery, or other power source). PMIC 290 is configured to convert a voltage of power source 292 into a plurality of supply voltages (e.g., using switching regulators, linear voltage regulators, or any combination thereof). In this example, PMIC 290 generates voltage 242 for oscillator 230, voltage 244 for PCIe controller 218, and voltage 246 for PHY TX block 222, PHY RX block 226, and clock generator 224. Voltages 242, 244, and 246 can be programmable, with PMIC 290 configured to set voltage levels (angles) of voltages 242, 244, and 246 according to instructions (e.g., from host controller 212).

[0042] PMIC 290 also generates voltage 280 for oscillator 272, voltage 278 for PCIe controller 262, and voltage 276 for PHY TX block 266, PHY RX block 270, and clock generator 268. Voltages 280, 278, and 276 can be programmable, with PMIC 290 configured to set voltage levels (angles) of voltages 280, 278, and 276 according to instructions (e.g., from device controller 252). PMIC 290 can be implemented on one or more chips. Although PMIC 290 is shown as one PMIC in FIG. 2, it should be understood that PMIC 290 can be implemented by two or more PMICs. For example, PMIC 290 can include a first PMIC to generate voltages 242, 244, and 246 and a second PMIC to generate voltages 280, 278, and 276. In this example, both the first PMIC and the second PMIC can be coupled to the same power source 292 or different power sources. Figure 2

[0043] ​In operation, the PCIe interface circuit 216 on the host system 210 can send data from one or more host clients 214 to the endpoint device system 250 via the PCIe link 285. When the host controller negotiates bandwidth for the link, data from the one or more host clients 214 can be directed to the PCIe interface circuit 216 according to PCIe mappings established by the host controller 212 during initial configuration, sometimes referred to as link initialization. In an example, the host controller negotiates a first bandwidth for the transmit group of the link and a second bandwidth for the receive group of the link. At the PCIe interface circuit 216, the PCIe controller 218 can perform transaction layer and data link layer functions on the data, such as packetizing the data, generating error correction codes to be sent with the data, etc.

[0044] The PCIe controller 218 outputs the processed data to the PHY TX block 222 via the PIPE interface 220. The processed data includes data from the one or more host clients 214 as well as overhead data (e.g., packet headers, error correction codes, etc.). In one example, the clock generator 224 can generate a clock 234 for the appropriate data rate or transmission rate based on the reference clock signal 232 and input the clock 234 to the PCIe controller 218 to clock operations of the PCIe controller 218. In this example, the PIPE interface 220 can include a 22-bit parallel bus that transfers 22 bits of data in parallel to the PHY TX block for each cycle of the clock 234. At a frequency of 250 MHz, the transmission rate is approximately 8 GT / s.

[0045] The PHY TX block 222 serializes the parallel data from the PCIe controller 218 and drives the PCIe link 285 with the serialized data. In this regard, the PHY TX block 222 can include one or more serializers and one or more drivers. The clock generator 224 can generate a high frequency clock for the one or more serializers based on the reference clock signal 232.

[0046] At the endpoint device system 250, the PHY RX block 270 receives the serialized data via the PCIe link 285 and de-serializes the received data into parallel data. In this regard, the PHY RX block 270 can include one or more receivers and one or more de-serializers. The clock generator 268 can generate a high frequency clock for the one or more de-serializers based on the EP reference clock signal. The PHY RX block 270 transmits the de-serialized data to the PCIe controller 262 via the PIPE interface 264. The PCIe controller 262 can recover the data from the one or more host clients 214 from the de-serialized data and forward the recovered data to the one or more device clients 254.

[0047] On the endpoint device system 250, the PCIe interface circuit 260 can send data from one or more device clients 254 to the host system memory 240 via the PCIe link 285. In this regard, the PCIe controller 262 at the PCIe interface circuit 260 can perform transaction layer and data link layer functions on the data, such as packetizing the data, generating error correction codes to be sent with the data, etc. The PCIe controller 262 outputs the processed data to the PHY TX block 266 via the PIPE interface 264. The processed data includes data from the one or more device clients 254 as well as overhead data (e.g., packet headers, error correction codes, etc.). In one example, the clock generator 268 can generate a clock based on the EP reference clock over a differential clock line 288 and input the clock to the PCIe controller 262 to clock operations of the PCIe controller 262.

[0048] The PHY TX block 266 serializes the parallel data from the PCIe controller 262 and drives the PCIe link 285 with the serialized data. In this regard, the PHY TX block 266 can include one or more serializers and one or more drivers. The clock generator 268 can generate a high frequency clock for the one or more serializers based on the EP reference clock signal.

[0049] At the host system 210, the PHY RX block 226 receives the serialized data via the PCIe link 285 and de-serializes the received data into parallel data. In this regard, the PHY RX block 226 can include one or more receivers and one or more de-serializers. The clock generator 224 can generate a high frequency clock for the one or more de-serializers based on the reference clock signal 232. The PHY RX block 226 transmits the de-serialized data to the PCIe controller 218 via the PIPE interface 220. The PCIe controller 218 can recover the data from the one or more device clients 254 from the de-serialized data and forward the recovered data to the one or more host clients 214.

[0050] Figure 3 is available at Figure 1 and Figure 2a diagram of lanes in a link 385 (e.g., PCIe link 285) used in the system of FIG. 1. In this example, the link 385 includes a plurality of lanes 310-1 through 310-n, where each lane includes a respective first differential pair of lines 312-1 through 312-n for transmitting data from the host system 210 to the endpoint device system 250, and a respective second differential pair of lines 315-1 through 315-n for transmitting data from the endpoint device system to the host system 210. From the perspective of the host system, the first lane 310-1 is double simplex, with the first differential pair of lines 312-1 as a transmit line and the second differential pair of lines 315-1 as a receive line. From the perspective of the endpoint device system, the first lane 310-1 has a receive line and a transmit line. The first differential pair of lines 312-1 through 312-n and the second differential pair of lines 315-1 through 315-n can be implemented with metal traces on a substrate (e.g., a printed circuit board), where the host system can be integrated on a first chip mounted on the substrate, and the endpoint device integrated on a second chip mounted on the substrate. Alternatively, the link can be implemented through an adapter card slot, a cable, or a combination of different media. The link can also include an optical portion in which PCIe packets are encapsulated within different systems. In this example, when transmitting data from the host system to the endpoint device system across multiple lanes, the PHY TX block 222 can include logic for dividing data among the lanes. Similarly, when transmitting data from the endpoint device system to the host system 210 across multiple lanes, the PHY TX block 266 can include logic for dividing data among the lanes.

[0051] Figure 2 The PHY TX block 222 of the host system 210 shown in FIG. 1 can be implemented to include transmit drivers 320-1 through 320-n for driving each first differential pair of lines 312-1 through 312-n to transmit data, and Figure 2 The PHY RX block 270 of the host shown in FIG. 1 can be implemented to include receivers 340-1 through 340-n (e.g., amplifiers) for driving each second differential pair of lines 312-1 through 312-n to receive data. Each transmit driver 320-1 through 320-n is configured to drive the respective differential pair of lines 312-1 through 312-n with data, and each receiver 340-1 through 340-n is configured to receive data from the respective first differential pair of lines 312-1 through 312-n. Further, in Figure 2In particular embodiments, the PHY TX block 266 of the endpoint device system 250 can include a transmit driver 345-1 to 345-n for each second differential line pair 315-1 to 315-n, and the PHY RX block 226 of the host system 210 can include a receiver 325-1 to 325-n (e.g., an amplifier) for each second differential line pair 315-1 to 315-n. Each transmit driver 345-1 to 345-n is configured to drive the corresponding second differential line pair 315-1 to 315-n with data, and each receiver 325-1 to 325-n is configured to receive data from the corresponding second differential line pair 315-1 to 315-n.

[0052] In certain aspects, the width of the scalable link 385 is scaled to match the capabilities of the host system and endpoint. The link can use one lane 310-1 for xl links, two lanes 310-1, 310-2 for x2 links, or multiple lanes up to n lanes from 310-1 to 310-n for wider links. Current links are defined as 1, 2, 4, 8, 16, and 32 lanes, but different numbers of lanes can be used to accommodate particular implementations.

[0053] In one example, the host system 210 can include a power switch circuit 350 configured to individually control power to the transmit drivers 320-1 to 320-n and receivers 325-1 to 325-n from the PMIC 290. Thus, in this example, the number of powered drivers and receivers is proportional to the width of the link 385. Similarly, as Figure 2 The endpoint device system 250, as shown in FIG. 3B, can include a power switch circuit 360 configured to individually control power to the transmit drivers 345-1 to 345-n and receivers 340-1 to 340-n from the PMIC 290. In this way, the host system sets the number of drivers that will be selectively powered by the power switch circuit to change the number of active transmit or receive lines based on the number of lines that are powered. With differential signaling, the lines will be set in pairs to either an active or standby state.

[0054] Figure 4is a state diagram 400 illustrating the operation of a power management state machine in accordance with certain aspects disclosed herein. The active state power management (ASPM) protocol is a state machine approach to reducing power based on detected link activity on a PCIe link between a root complex and an endpoint PCIe device. The state diagram is consistent with the link training and state state machine (LTSSM) defined for PCIe. However, other approaches can alternatively be used. In this approach, the link operates in an L0 power state (i.e., link running state) when data is being transferred over the PCIe link. In this example, an L0 state 404 and an LI state 406 are shown. The ASPM protocol can also support additional active and standby states and sub-states, such as LI.1 and LI.2 sub-states, etc. As shown, the LI state 406 is only accessible through a connection to the L0 state 404. ASPM state changes can be initiated when conditions on the link indicate or suggest that a transition between states is needed or appropriate. Both communication partners on the link can initiate a power state change request when conditions are normal.

[0055] When the link is idle (e.g., for short intervals of time between data bursts), the link can enter a standby state L0s 402 from the L0 state 404, which is only accessible through a connection to the L0 state 404. In this example, the L0s 402 is a low power standby state of the L0 404. The LI state 406 is a standby state with lower latency than the L0s state 402. The L0s state 402 is used as a standby state and also as an initialization state after power-up, system reset, or after detecting an error condition. In the L0s 402, device discovery and bus configuration procedures can be implemented before the link transitions 422 to the L0 404. In the L0 404, the PCIe device can be active and responsive to PCIe transactions and / or can request or initiate PCIe transactions. The LI state 406 is the primary standby state and allows for a fast return to the L0 state 404. When the PCIe device determines that there are no outstanding PCIe requests or pending transactions, the transition 424 to the LI state 406 can be made. Power consumption can be reduced by disabling or idling transceivers in the PCIe bus interface, disabling, gating, or slowing down clocks used by the PCI device, and disabling PLL circuits used to generate clocks for receiving data. The transition 424 to the LI state 406 can be made by operation of a hardware controller or some combination of an operating system and hardware control circuitry.

[0056] When the PCIe link is inactive for longer periods of time, the link can enter L2 state 416 or L3 state 418 through L2 / L3 ready state 412 to achieve even lower power consumption. L2 / L3 ready state 412 is a pseudo state that prepares the link components for loss of power and loss of reference clock. L2 state 416 and L3 state 418 are further reduced in power and have longer latencies than LI state 406. Additional lower power states can be provided to accommodate other implementations.

[0057] When the PCIe link becomes active while the device is running in L2 state 412 or L3 state L3 418, a return to L0 state 404 is initiated for the device. A direct transition to L0 state 404 can not be available. The PCIe link can transition 416 to a resume state, LDn state 420, in which the transceivers in the PCIe bus interface, clocks used by the PCI device, and / or PLL circuitry are enabled. When it is determined that the transceivers and other circuitry are functional, a transition 422 from LDn state 420 to L0 state 404 can be initiated. LDn state 420 can also be entered through a reset or link disable operation.

[0058] In some examples, the ASPM protocol determines whether a transition 424 to LI state 406 should be initiated based on a finite time interval or threshold defined as an LI entry latency. Similar thresholds can be defined for L2 state 416, L3 state 418, and other states. LI state 406 is a link power state in which no data transfers are allowed over the PCIe link. Whenever the PCIe link is inactive for a given LI entry latency duration, the PCIe controller can request that the link partner enter a low power link state in order to conserve power. In some instances, the LI entry latency duration is selected based on overall system parameters, activity, and / or pending operations. In some modes of operation, the ASPM protocol can be configured to conserve power by reducing the transmit time that the PCIe link is active and consuming power. During high bandwidth bursts, some modes can be configured to avoid link transitions to low power states, which would otherwise extend the transmit time. The ASPM can initiate a transition to a low power state transition after an observed link inactivity time. The particular entry latency duration can be adjusted to accommodate different system architectures and device characteristics. In some implementations, the packet latency between read / write requests in the PCIe interface can vary between, for example, 1 and 40 μβ.

[0059] By reducing the link width during low-throughput data traffic scenarios, the subsystem of the PCIe link can scale down the voltage levels (e.g., to lower operating levels that meet the current throughput on the PCIe link). The scaled down voltage level(s) reduce power consumption (e.g., reduce leakage current during periods of sustained low-throughput traffic or idle usage). The number of lanes also affects power consumption. In fact, there is an L0, LI transition state diagram for each lane.

[0060] Figure 5 is a diagram of a PCIe link that is a duplex traffic lane between link 504, such as host 502 and endpoint 506. The duplex traffic lane can have the same physical structure as Figure 3 but is generalized to show how lanes are grouped in a typical configuration. Link 504 includes four lanes 511, 512, 513, 514, but more or fewer lanes can be used. Each lane includes two transmit lines as differential pair lines and two receive lines as differential pair lines, four lines per lane, and sixteen lines for an x4 link. Based on the example in Figure 3 the PHY TX block 222 shown in Figure 2 may be implemented to include a transmit driver for each differential pair of two transmit lines, and Figure 2 the PHY RX block 270 shown in

[0061] In certain aspects, the width of link 504 can be scalable by controlling the number of lanes 511, 512, 513, 514 that are in an active state. Host 502 or endpoint 506 can configure the link width by configuring the number of traffic lanes that are powered to transmit and receive data over link 504. In the case of high transmit or receive traffic, all traffic lanes are activated. If both transmit and receive traffic are low or if there is traffic inactivity, one or more duplex traffic lanes can be placed in a low power state, such as an LI state.

[0062] Figure 6 is a diagram of duplex traffic lanes of link 604 between host 602 and endpoint 606 that are grouped into transmit groups 610 and receive groups 620. The link can be a PCIe link that can have the same physical structure as Figure 3The same physical structure as in FIG. 6B, but where the lanes have been logically grouped into a group for host transmit 610 and a group for host receive 620. The host transmit group (B0) is also the endpoint receive group, and the host receive group (B1) is also the endpoint transmit group. In this example, the link 604 includes four lanes, but more or fewer lanes can be used. The transmit group 610 includes four transmit differential line pairs 611, 612, 613, 614, one for each of the four lanes, which are logically grouped into the host transmit group 610 for communicating data from the host 602 to the endpoint 606. The receive group 620 includes four receive differential line pairs 621, 622, 623, 624, which are logically grouped into the host receive group 620 for receiving data at the host 602 from the endpoint 606. Using the grouping shown in FIG. 6B, the PHY TX block 222 can include logic for dividing data among the transmit lines of the transmit group 610, and the PHY RX block 226 can include logic for dividing data among the receive lines of the receive group 620 independent of the transmit group. Similarly, when communicating data from the endpoint 606 to the host 602 across multiple lines, the PHY TX block 266 can include logic for dividing data among the transmit lines of the transmit group independent of the receive lines of the receive group. Figure 6

[0063] As described above, each differential line pair includes a driver and a receiver, so if any one of the differential line pairs in either direction is placed in a low power or standby state, power is reduced. In this example, for the transmit group 610 within the link 604, the number of active transmit lines is scalable independent of the power of the receive lines of the receive group 620. Similarly, the number of active receive lines within the receive group 620 is scalable independent of the power of the transmit lines of the transmit group 610.

[0064] As described above, the host system 210 can include a power switch circuit 350 configured to individually control power from the PMIC 290 to the transmit drivers 320-1 through 320-n and the receivers 325-1 through 325-n. In this regard, the power switch circuit 350 can couple the transmit drivers and receivers of active lines to the voltage 246 and decouple the transmit drivers and receivers of inactive lines from the voltage 246. Thus, the number of powered transmit drivers and receivers is proportional to the number of active lines in the transmit group and the number of active lines in the receive group. The endpoint can also include a power switch circuit 360 for individually controlling power to the transmit and receive drivers. For ease of illustration, Figure 6 The individual connections or couplings between the power switch circuits, drivers, and receivers are not shown in FIG. 6B.

[0065] ​In some examples, a threshold procedure can be used to determine whether to transition to or from a standby state for any particular transmit or receive line or for a transmit or receive group as a whole. As one example, a procedure can be to monitor transmit traffic activity of a link, compare the transmit traffic activity of the link to a threshold, and manage a first power of transmit lines of the link as a transmit group according to the transmit traffic activity. The procedure can manage the first power by placing one or more transmit lines or one or more differential line pairs of the transmit lines in a standby substate in response to the transmit traffic activity being less than the threshold. The standby substate is a lower power state than the standby state. Alternatively, traffic inactivity can be compared to a threshold. Receive traffic at an endpoint corresponds to transmit traffic at a host, so either procedure or both procedures can be used to determine appropriate power management of a link.

[0066] The procedure can be represented as Thread 0 shown below. LINK STATE B0 refers to the link state of transmit group B0, which has an active state L0 B0, an inactive state L1 B0, and an inactive substate L1SS B0, although there can be multiple substates with different numbers of inactive transmit lines. EP refers to an endpoint, RX_traffic_inactivity_at_EP refers to a monitored amount of receive traffic activity at the endpoint, which corresponds to transmit traffic inactivity at the receiver. changeLinkState refers to a command from the procedure to a link controller. In the example of the Thread 0 procedure, the procedure can be applied when the link state of transmit group B0 is in the L1 standby state or the L1SS standby substate. The procedure compares the receive traffic inactivity at the endpoint to a threshold for the L1SS substate. If the receive traffic inactivity is greater than the threshold, the link state is set to the standby substate L1SS, and if not, the link state is set to the standby state L1.

[0067]

[0068] A similar procedure can be performed for receive traffic at a host by comparing activity or inactivity to a threshold. In one example, a procedure is to monitor receive traffic activity of a link, compare the receive traffic activity of the link to a threshold, and manage a second power of receive lines of the link as a receive group according to the receive traffic activity. The procedure can manage the second power by placing receive traffic lines of the link in a standby state or a standby substate (e.g., L1 or L1SS) in response to the receive traffic activity being less than the threshold.

[0069] The process can be represented as thread 1 below. In the example of the thread 1 process, the process can be applied when the link state for group B1 of links is in the LI standby state or the LI SS standby substate. The process compares the received traffic inactivity at the host or receiver to a threshold for the LI SS substate. If the received traffic inactivity is greater than the threshold, the link state is set to the standby substate LI SS, and if not, the link state is set to the standby state LI.

[0070]

[0071] Additional threshold processes can be established for each link width transition in each direction. Figure 7 is an example of table 700, such as a lookup table for mapping monitored traffic activity usage or settings to a number of active differential line pairs. At the transmitting side, the monitored transmit traffic activity is applied to one or more thresholds in the first column 710. For the case of multiple clients, the monitored traffic activity can be the aggregate bandwidth. The traffic can be measured as data rate (e.g., Mbps or another format), spacing between packets, or in other units. Traffic inactivity can be used instead, and can be measured in time units, data rate, or other units. The transmit traffic activity is converted through the lookup table using the thresholds in the first column 710 to a number of active differential line pairs in the second column 720. The second column 720 has a corresponding number of active differential line pairs (labeled “1” through “32”), and the first column provides thresholds that trigger a transition from one number of active differential line pairs to another number of active differential line pairs for each range of traffic activity that lies between the thresholds. The x4 link can support 1, 2, 3, or 4 active differential line pairs, depending on the traffic or traffic inactivity. While the second column provides a number of active differential line pairs, it does not provide which of the available differential line pairs are selected for the active state.

[0072] The third column 730 provides thresholds for comparing monitored receive traffic activity. These receive traffic activity thresholds are also mapped in the same way to a number of active differential line pairs in the fourth column 740. There can be different tables for transmission and reception, or the same table can be used to solve for both the number of active differential line pairs for transmission and reception. The thresholds can be the same or different. For transmit traffic activity, the controller places the determined number of active transmit differential line pairs in the active state and the remaining transmit differential line pairs in the standby substate according to the response threshold. For receive traffic activity, the controller places the determined number of active receive differential line pairs in the active state and the remaining transmit differential line pairs in the standby substate according to the response threshold.

[0073] Table 700 can be pre-stored in memory of a bandwidth solver coupled to PCIe controller 218, 262. As the bandwidth solver monitors transmit traffic activity and receive traffic activity from one or more clients. The bandwidth solver can convert the monitored traffic activity into a number of active transmit differential line pairs and active receive differential line pairs by applying one of these thresholds. Table 700 can be generated based on computer simulation of the system and / or power measurements of the system for various traffic activity and active line scenarios. In this example, based on simulation results and / or power measurements, the number of active lines that result in the lowest power for a particular bandwidth can be mapped to the appropriate traffic activity threshold in table 700.

[0074] Figure 8 Table 800 is a table of power modes suitable for transmit groups (designated here as B0) or receive groups (designated here as B1). In this example, there are four differential line pairs, however, more or fewer differential line pairs can be used. The differential line pairs are designated as L1, L2, L3, and L4 in table 800. Each differential line pair can be in an inactive state (indicated as “1”) or an active state (indicated as “0”). Referring to table 800, there is one unique state, indicated as 0x0, in which all lines are in the active state. In this state, no lines are configured to a low power state, such as L1. This can be used as a default state for fast response. There is one unique state, indicated as 0x9, in which all lines are in the inactive state. All lines can be in a low power state, such as L1. This state can be entered after monitoring traffic and comparing traffic activity or inactivity to a threshold (such as Figure 7 thresholds) of table 700. Other states correspond to one inactive differential line pair (two lines) indicated as 0x1, two inactive differential line pairs (four lines) indicated as 0x3, and three inactive differential line pairs (6 lines) indicated as 0x7. Other codes can be used for PCIe links configured as xl, x2, x8, x16, or x32, etc. to accommodate more or fewer states. The codes are stored in registers with the host or endpoint controller for controlling the state of transmit and receive lines. Figure 8 shows that for each number of differential line pairs from Figure 7 there can be a variety of possible configurations of a set of differential line pairs. Values such as 0x7 correspond to numbers such as “1” from threshold table 700. The sequence or order of placing lines in active or standby state can be adjusted to accommodate particular configurations and implementations.

[0075] Figure 9This is a state diagram illustrating a portion of the power management protocol, specifically five inactive sub-states within the L1 state. These states and sub-states can be applied independently to both the transmit and receive groups. On the transmit side, for logical transmit packet B0, there exists an active L0 B0 state 902, which is related to... Figure 4 The L0 state 404 is the same as or similar to the L0 state 404, but is only used for sending packets. The transition between L0B0 state 902 and the inactive or standby L1B0 state 904 is also similar to... Figure 4 The L1 state 406 is the same as or similar to the L1 state 406, but is only used for transmitting packets. Standby state L0 B0 904 has four sub-states. These four sub-states correspond to, for example, using... Figure 8 The codes 0x0, 0x1, 0x3, 0x7, and 0x9 indicate the number of active differential line pairs sent, such as when using a threshold (e.g., Figure 7 The threshold value is determined by the bandwidth. The controller (e.g., a PCIe controller) places at least one transmit differential line pair in a standby state in response to the negotiated bandwidth or the selected bandwidth. The selected at least one transmit differential line pair can be any one of the transmit differential line pairs in the transmit group.

[0076] The first standby substate L1-1 B0 911 for 0x9 is the state of four standby differential line pairs in the transmit group. There are no active lines in the transmit group. This state corresponds to the standard standby state L1 B0 904 and can be replaced by this state. The second standby substate L1-2 B0 911 is the 0x7 state for three standby differential line pairs and one active differential line pair in the transmit group. The third standby substate L1-3 B0 913 for 0x3 is the state for two standby differential line pairs and two active differential line pairs. The fourth standby substate L1-4 B0 914 is the 0x1 state for one standby differential line pair and four active differential line pairs. The fifth state 0x0, where all lines are active, corresponds to L0 B0 902. In this example, there are four substates for the x4 link. More or fewer substates may exist to accommodate different numbers of lines and different implementations. In some examples, not every combination is used. As an example, the x16 link can support 17 different numbers of standby line combinations; however, for simplicity, the system can be configured to use only 8 or less of another number of line combinations.

[0077] On the receiving side, for logical receive packet B1, there exists an active L0 B1 state 922 in which all four receive differential line pairs are active, which is related to... Figure 4The L0 state 404 is the same as or similar to the L0 state 404, but is only used for receiving packets. The transition between L0 B1 state 922 and the inactive or standby L1 B1 state 924 is also similar to... Figure 4 The L1 state 406 is the same as or similar to this state, but is used only for receiving packets. The controller (e.g., a PCIe controller) then uses thresholding and traffic activity to place at least one selected receive differential line pair in a standby state. This at least one transmit differential line pair can be selected based on channel sequence negotiation or otherwise. The L1 B1 state is used for 0x9, where all lines are inactive or can be used as a transitional state to enter a substate. Standby state L1 B1 924 has four substates. These four substates correspond to, for example, using... Figure 8 The codes 0x0, 0x1, 0x3, 0x7, and 0x9 indicate the number of active receive service lines, such as when using a threshold (e.g., Figure 7 The threshold is determined by the following. The first standby substate L1-1 B1 931 for 0x9 is the state of four standby differential line pairs in the receiver group. There are no active lines in the receiver group. This state corresponds to the standard standby state L1 B1 924 and can be replaced by this state. The second standby substate L1-2 B1 931 is the 0x7 state for three standby differential line pairs and one active differential line pair in the receiver group. The third standby substate L1-3 B1 933 for 0x3 is the state for two standby differential line pairs and two active differential line pairs. The fourth standby substate L1-4 B1 934 is the 0x1 state for one standby differential line pair and three active differential line pairs. There may be more or fewer than four substates to accommodate different numbers of lines and different specific implementations, and not every combination is used in every example. Although these sub-states are shown as sub-states corresponding to standby states 904 and 924, these sub-states are a mixture of standby and active states, and can alternatively be sub-states of active states 902 and 922.

[0078] Figure 10 This is a block diagram of the link interface processing circuitry. Processing circuitry 1004 is a device that can be part of a host or endpoint. This processing circuitry is coupled to a link 1002 with multiple duplex channels, such as a PCIe link. Link 1002 is coupled at its opposite end to another PCIe device, such as an endpoint or host. Data and control information transmitted as packets through link 1002 are coupled to link 1020, which provides a PHY-level interface to link 1002 and converts baseband signals into packets. Data and control packets are transmitted via link 1020 through bus 1010 to other components of processing circuitry 1004. Link 1020 has a direct connection to interface configuration block 1018 for configuring and controlling the operation of link 1020.

[0079] The processing circuit 1004 includes blocks and memory. A timer module / circuit block 1012 is coupled to the bus 1010 for timing latencies, inactivity, acknowledgements, and driving the standby state. The timer module / circuit block 1012 accesses the computer-readable storage medium 1008 to access code 1032 for managing timers. In aspects, the storage medium is a non-transitory computer-readable medium. The timer module / circuit block 1012 can also access registers in the storage medium 1008 to measure durations within the PCIe link, which registers contain a receive traffic timing threshold 1034 and a transmit traffic timing threshold 1034, such as the L1 B0_THRESHOLD or L1 B1_THRESHOLD discussed above or other thresholds as in Figure 7 .

[0080] Also within the processing circuit 1004, a power management block 1014 manages power to each lane and to other components of the PCIe system. The power management block 1014 accesses, through the bus 1010, code 1040 for managing PCIe power and transmit lane status registers 1042 and receive lane status registers 1044. These registers can be used to store the status of each transmit lane and each receive lane, each transmit group and each receive group, or the transmit side and the receive side of the link. This status can be determined using the code 1032 for managing timers, the code 1040 for managing PCIe power, or in another manner.

[0081] A TX / RX link traffic monitoring block 1016 within the processing circuit 1004 can access the bus 1010 to monitor transmit traffic activity on the link 1002 and to monitor receive traffic activity on the link 1002. Traffic activity and traffic inactivity can be monitored. The TX / RX link traffic monitoring block 1016 can access code in the storage medium 1008 for monitoring TX / RX link traffic 1050 and can also access registers to store results and to obtain traffic activity thresholds. Transmit traffic activity thresholds 1052 and receive traffic activity thresholds 1054 (e.g., the thresholds of the first column 710 of Figure 7 . The transmit traffic activity thresholds 1052 and the receive traffic activity thresholds 1054 can be used to compare traffic activity to thresholds for both transmit traffic activity and receive traffic activity, respectively. The power management block 1014 can manage power of transmit lanes and power of receive lanes according to the transmit traffic activity and the receive traffic activity. The interface configuration block 1018 can modify configurations in response to the power management block 1014.

[0082] The interface configuration block 1018 is coupled to the bus like the TX / RX link traffic monitoring block 1016, the power management block 1014, and the timer module / circuit block 1012, so each of these blocks can communicate with each other, with the storage medium 1008, and with the processor 1006. The processor 1006 controls the operation of the other blocks and initiates an instance of each block according to the operation of the processing circuit 1004. The interface configuration block 1018 can also access code for configuring the PCIe interface 1060. In executing this code, the interface configuration block 1018 reads from and writes to various configuration registers. These registers include transmit control, status, and capability registers 1062 and receive control, status, and capability registers. These registers can be accessed and read at the beginning of link initialization and then updated with the results of the initialization. The registers can also be modified in response to power management and bandwidth negotiation or changing the state of one or more transmit or receive lanes of the link 1002.

[0083] The processing circuit 1004 can initialize the link 1002, manage power, and change the number of active lanes of the link 1002. In operation, bandwidth requests can also be received from the host or endpoint. The bandwidth requests can cause bandwidth negotiation, which subsequently changes the values set to the control, status, and capability registers. The number of active lanes can then be changed in response to transmit traffic activity and receive traffic activity. The TX / RX link traffic monitoring block 1016 also monitors transmit traffic activity of the transmit lanes of the link 1002 and receive traffic activity of the receive lanes of the link 1002. The transmit traffic activity and the receive traffic activity are evaluated to determine a change in the number of active lanes. The power management block 1014 can place one or more transmit or receive lanes into a standby state. The state changes can then be recorded in the transmit lane status registers 1042 and the receive lane status registers 1044. This evaluation can be done in different ways. In some examples, at the TX / RX link traffic monitoring block 1016, the transmit traffic activity is compared to one or more thresholds in the transmit traffic threshold registers 1052 and the receive traffic activity is compared to one or more thresholds in the receive traffic threshold registers 1054. A message can then be communicated over the link 1002 to the connected device, host, or endpoint.

[0084] After changing the number of active lanes, the power management block 1014 can change the voltage level of one or more of the voltages 276, 278, and 280 by instructing the PMIC 290 to set the voltage level of one or more of the voltages provided by the PMIC 290, as Figure 2The power management block 1014 can also connect or disconnect power to the drivers and receivers of the affected lanes according to the new number of active lanes, as shown in FIG. 10. As one example, if the number of active lanes decreases, the power management block 1014 can power down the drivers in the PHY TX block 222 and / or the receivers in the PHY RX block 226 that correspond to the lanes in the link 1002 that are deactivated as a result of the change. The power management block 1014 can power down the selected drivers and / or receivers by transmitting instructions to the power switch circuit to turn off the selected drivers and / or receivers. Thus, power according to the negotiated bandwidth is managed by providing one or more voltages to the interface circuit of the link and by setting the level of the one or more voltages.

[0085] Figure 11 A flow diagram of a method 1100 for traffic-based power management for a link (e.g., a PCIe link) in accordance with aspects of the present disclosure is illustrated. In certain aspects, the method 1100 implements scaling of the number of active lanes, e.g., reducing the number of powered transmit lanes and powered receive lanes (e.g., selectively powering on or off the drivers 320 or 345).

[0086] The method 1100 includes monitoring transmit traffic activity of a link at block 1102. As described, the link is a PCIe link, however, the method can be adapted to accommodate other links having transmit lanes and receive lanes. The method 1100 includes monitoring receive traffic activity of the link at block 1104. The method 1100 includes managing a first power of transmit lanes of the link as a transmit group according to the transmit traffic activity at block 1106. The method 1100 includes managing a second power of receive lanes of the link as a receive group according to the receive traffic activity, independent of the power of the transmit lanes, at block 1108.

[0087] An overview of examples of the present disclosure is provided below.

[0088] Example 1 : An apparatus comprising: an interface circuit configured to provide an interface to a Peripheral Component Interconnect Express (PCIe) link; and a controller configured to: monitor transmit traffic activity of the link; monitor receive traffic activity of the link; manage a first power of transmit lanes of the link as a transmit group according to the transmit traffic activity; and manage a second power of receive lanes of the link as a receive group according to the receive traffic activity, independent of the power of the transmit lanes.

[0089] Embodiment 2: The apparatus of embodiment 1, wherein the controller is configured to set a transmit group link control register to store a number of active transmit lines in accordance with the transmit traffic activity, and to set a receive group link control register to store a number of active receive lines in accordance with the receive traffic activity.

[0090] Embodiment 3: The apparatus of embodiment 1 or 2, wherein the controller is configured to set a transmit group capability register to store capabilities of the transmit lines in accordance with the transmit traffic activity, and to set a receive group capability register to store capabilities of the receive lines in accordance with the receive traffic activity.

[0091] Embodiment 4: The apparatus of any one or more of the above embodiments, wherein the controller is configured to manage the first power including placing a selected at least one transmit line of the transmit group in a standby state.

[0092] Embodiment 5: The apparatus of embodiment 4, wherein the controller is configured to: compare the transmit traffic activity of the link to a threshold; and in response to the transmit traffic activity being less than the threshold, place the transmit line in a standby substate, wherein the standby substate is a lower power state than the standby state.

[0093] Embodiment 6: The apparatus of any one or more of the above embodiments, wherein the controller is configured to manage the second power by placing a selected at least one receive line of the receive group in a standby state.

[0094] Embodiment 7: The apparatus of embodiment 6, wherein the controller is further configured to: compare the receive traffic activity of the link to a threshold; and in response to the receive traffic activity being less than the threshold, place the receive line in a standby substate, wherein the standby substate is a lower power state than the standby state.

[0095] Embodiment 8: The apparatus of any one or more of the above embodiments 1, wherein managing the first power includes managing a number of active transmit lines of the transmit group of the link.

[0096] Embodiment 9: The apparatus of any one or more of the above embodiments, wherein the controller is configured to manage the first power by: providing one or more voltages or clocks to interface circuitry configured to provide an interface to the link; and providing a level of the one or more voltages to the interface circuitry based on the first power setting.

[0097] Example 10: A method comprising: monitoring transmit traffic activity of a Peripheral Component Interconnect Express (PCIe) link; monitoring receive traffic activity of the link; managing a first power of transmit lanes of the link as a transmit group according to the transmit traffic activity; and independent of the power of the transmit lanes, managing a second power of receive lanes of the link as a receive group according to the receive traffic activity.

[0098] Example 11 : The method of example 10, further comprising: setting a transmit group link control register according to the transmit traffic activity, and setting a receive group link control register according to the receive traffic activity.

[0099] Example 12: The method of example 10 or 11, further comprising: setting a transmit group link status register according to the transmit traffic activity, and setting a receive group link status register according to the receive traffic activity.

[0100] Example 13: The method of any one or more of examples 10-12, wherein managing the first power comprises placing a selected at least one transmit lane of the transmit group into a standby state.

[0101] Example 14: The method of example 13, further comprising: comparing the transmit traffic activity of the link to a threshold; and responsive to the transmit traffic activity being less than the threshold, placing the transmit lane into a standby substate, wherein the standby substate is a lower power state than the standby state.

[0102] Example 15: The method of any one or more of the above examples, wherein managing the second power comprises placing a selected at least one receive lane of the receive group into a standby state.

[0103] Example 16: The method of example 15, further comprising: comparing the receive traffic activity of the link to a threshold; and responsive to the receive traffic activity being less than the threshold, placing the receive lane into a standby substate, wherein the standby substate is a lower power state than the standby state.

[0104] Example 17: The method of any one or more of the above examples, wherein managing the second power comprises managing a number of active receive lanes of the receive group of the link.

[0105] Embodiment 18: The method of any one or more of the above embodiments, wherein managing the second power comprises providing one or more voltages or clocks to an interface circuit configured to provide an interface to the link and setting a level of the one or more voltages provided to the interface circuit based on the second power setting.

[0106] Embodiment 19: A non-transitory computer-readable medium having stored therein instructions for causing a processor of an interconnect link to perform operations comprising: monitoring transmit traffic activity of a Peripheral Component Interconnect Express (PCIe) link; monitoring receive traffic activity of the link; managing a first power of transmit lanes of the link as a transmit group according to the transmit traffic activity; and independently of the power of the transmit lanes, managing a second power of receive lanes of the link as a receive group according to the receive traffic activity.

[0107] Embodiment 20: The computer-readable medium of embodiment 19, further comprising: comparing the transmit traffic activity of the link to a threshold; and responsive to the transmit traffic activity being less than the threshold, placing a selected at least one transmit lane of the transmit group in a standby state, wherein the standby state is a low power state.

[0108] It should be understood that the present disclosure is not limited to the exemplary terminology used above to describe aspects of the present disclosure. For example, bandwidth can also be referred to as throughput, data rate, or another term.

[0109] While aspects of the present disclosure are discussed above using the example of the PCIe standard, it should be understood that the present disclosure is not limited to this example and can be used with other standards.

[0110] Each of the host client 214, host controller 212, device controller 252, and device client 254 discussed above can be implemented with a controller or processor configured to perform the functions described herein by executing software including code for performing the functions. The software can be stored on a non-transitory computer-readable storage medium, such as RAM, ROM, EEPROM, optical disk, and / or magnetic disk, shown as host system memory 240, endpoint system memory 274, or another memory.

[0111] Any reference to an element herein using a designation such as "first," "second," and so forth does not limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

[0112] Within the disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to express either a direct or indirect electrical coupling or other communicative coupling between two structures. Further, the term "about" means within ten percent of the stated value.

[0113] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Modifications to various implementations of the disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: an interface circuit configured to provide an interface to a Peripheral Component Interconnect Express (PCIe) link; and a controller configured to: monitor transmit traffic activity of the link; monitor receive traffic activity of the link; manage a first power of transmit lanes of the link as a transmit group according to the transmit traffic activity by converting the transmit traffic activity to a number of active differential lane pairs of the transmit group using a plurality of thresholds and transitioning the link from an active state to a standby sub-state corresponding to the number of active differential lane pairs of the transmit lanes of the transmit group according to the transmit traffic activity; and independent of the first power of the transmit lanes, manage a second power of receive lanes of the link as a receive group according to the receive traffic activity by converting the receive traffic activity to a number of active differential lane pairs of the receive group using a plurality of thresholds and transitioning the link from an active state to a standby sub-state corresponding to the number of active differential lane pairs of the receive lanes of the receive group according to the receive traffic activity.

2. The apparatus of claim 1, wherein the controller is configured to set a transmit group link control register to store the number of active transmit lanes according to the transmit traffic activity and set a receive group link control register to store the number of active receive lanes according to the receive traffic activity.

3. The apparatus of claim 1, wherein the controller is configured to set a transmit group capability register to store capabilities of the transmit lanes according to the transmit traffic activity and set a receive group capability register to store capabilities of the receive lanes according to the receive traffic activity.

4. The apparatus of claim 1, wherein the controller is configured to: compare the transmit traffic activity of the link to a threshold; and in response to the transmit traffic activity being less than the threshold, place the transmit lanes in the standby sub-state, wherein the standby sub-state is a lower power state than the active state.

5. The apparatus of claim 1, wherein the controller is further configured to: compare the receive traffic activity of the link to a threshold; and in response to the receive traffic activity being less than the threshold, place the receive lanes in the standby sub-state, wherein the standby sub-state is a lower power state than the active state.

6. The apparatus of claim 1, wherein managing the first power comprises managing a number of active transmit lanes of the transmit group of the link.

7. The apparatus of claim 1, wherein the controller is configured to manage the first power by: providing one or more voltages or clocks to an interface circuit configured to provide an interface to the link; and setting a level of the one or more voltages provided to the interface circuit based on the first power.

8. A method comprising: monitoring transmit traffic activity of a Peripheral Component Interconnect Express (PCIe) link; monitoring a receive traffic activity of the link; managing a first power of a transmit line of the link as a transmit group according to the transmit traffic activity by converting the transmit traffic activity to a number of active differential line pairs of the transmit group using a plurality of thresholds and transitioning the link from an active state to a standby sub-state corresponding to the number of active differential line pairs of the transmit line of the transmit group; and managing a second power of a receive line of the link as a receive group according to the receive traffic activity independently of the first power of the transmit line by converting the receive traffic activity to a number of active differential line pairs of the receive group using a plurality of thresholds and transitioning the link from an active state to a standby sub-state corresponding to the number of active differential line pairs of the receive line of the receive group.

9. The method of claim 8, further comprising: setting a transmit group link control register according to the transmit traffic activity and a receive group link control register according to the receive traffic activity.

10. The method of claim 8, further comprising: setting a transmit group link state register according to the transmit traffic activity and a receive group link state register according to the receive traffic activity.

11. The method of claim 8, further comprising: comparing the transmit traffic activity of the link to a threshold; and in response to the transmit traffic activity being less than the threshold, placing the transmit line in the standby sub-state, wherein the standby sub-state is a lower power state than the active state.

12. The method of claim 8, further comprising: comparing the receive traffic activity of the link to a threshold; and in response to the receive traffic activity being less than the threshold, placing the receive line in the standby sub-state, wherein the standby sub-state is a lower power state than the active state.

13. The method of claim 8, wherein managing the second power comprises managing a number of active receive lines of the receive group of the link.

14. The method of claim 8, wherein managing the second power comprises: providing one or more voltages or clocks to an interface circuit configured to provide an interface to the link; and setting a level of the one or more voltages provided to the interface circuit based on the second power.

15. A non-transitory computer readable medium having stored therein instructions for causing a processor of an interconnect link to perform operations comprising: monitoring a transmit traffic activity of a Peripheral Component Interconnect Express (PCIe) link; monitoring a receive traffic activity of the link; managing a first power of a transmit line of the link as a transmit group according to the transmit traffic activity by converting the transmit traffic activity to a number of active differential line pairs of the transmit group using a plurality of thresholds and transitioning the link from an active state to a standby sub-state corresponding to the number of active differential line pairs of the transmit line of the transmit group; and managing a second power of a receive line of the link as a receive group according to the receive traffic activity independently of the first power of the transmit line by converting the receive traffic activity to a number of active differential line pairs of the receive group using a plurality of thresholds and transitioning the link from an active state to a standby sub-state corresponding to the number of active differential line pairs of the receive line of the receive group. independent of the first power of the transmit line, managing a second power of a receive line of the link as a receive group according to the receive traffic activity by: using a plurality of thresholds to convert the receive traffic activity to a number of active differential line pairs of the receive group, and transitioning the link from an active state to a standby substate corresponding to the number of active differential line pairs of the receive line of the receive group.

16. The non-transitory computer-readable medium of claim 15, further comprising instructions for causing the processor of the interconnect link to perform operations comprising: comparing the transmit traffic activity of the link to a threshold; and in response to the transmit traffic activity being less than the threshold, placing the selected at least one transmit line of the transmit group in the standby substate, wherein the standby substate is a low power state.

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