An FPGA-based IP core module debugging method

Abstract

The present application discloses an IP core module debugging method based on FPGA, which relates to the technical field of digital integrated circuits and includes: obtaining data streams generated under different abnormal conditions of the IP core module as analog test cases; using a support vector machine (SVM) model set on the FPGA chip to obtain feature patterns in the data streams as abnormal patterns; setting fault trigger conditions for obtaining corresponding abnormal patterns according to the obtained abnormal patterns; setting state trigger conditions under different states according to the state changes of the finite state machine (FSM) inside the IP core module; debugging the IP core module according to the set trigger conditions and state trigger conditions; performing static analysis on the code of the IP core module by using a program control flow graph parsing algorithm set on the FPGA chip; and debugging the IP core module through correlation analysis according to the debugging results and static analysis results. Aiming at the problem of low debugging efficiency of IP core modules in the prior art, the present application improves the debugging efficiency.

Description

Technical Field

[0001] This application relates to the field of digital integrated circuit technology, and particularly to a debugging method for IP core modules based on FPGA. Background Art

[0002] In recent years, with the continuous progress of semiconductor technology and the increasing complexity of chip design, System on Chip (SoC) has become the mainstream trend in integrated circuit design. By integrating multiple functional modules such as processors, memories, and peripheral interfaces into a single chip, SoC can significantly improve system performance, reduce power consumption, and cut costs. However, SoC design also faces many challenges, among which the debugging and verification of IP core (Intellectual Property Core) modules are one of the most critical and time-consuming processes.

[0003] IP cores are the basic building blocks of SoC, providing standardized functional interfaces and reusable design modules, which can greatly shorten the design cycle of SoC. However, errors and defects in the IP core itself may also lead to abnormal functions and performance degradation of the entire SoC. Traditional IP core debugging methods mainly rely on manually designed test cases and target board debugging, suffering from problems such as insufficient test coverage, difficult positioning, and low efficiency. With the increasing complexity of IP core functions and the continuous growth of parameter scales, traditional methods are no longer able to meet the requirements of rapid iterative development.

[0004] Hardware-assisted verification based on FPGA (Field Programmable Gate Array) has become an important means for IP core debugging. By mapping the IP core to the FPGA platform, a higher operating speed and a more realistic execution environment can be obtained compared to software simulation, which helps to accelerate error excitation and shorten the debugging time. However, existing FPGA debugging methods mainly focus on data path comparison and timing analysis, lacking effective observation means for the internal state and control flow of the IP core, and it is difficult to locate the root cause of complex anomalies.

[0005] In addition, the debugging process of IP cores usually requires manually constructing a test environment and monitoring logic, lacking sufficient automation means and exception handling mechanisms, which are prone to introducing additional workload and debugging blind spots. At the same time, for hidden errors and extreme conditions in IP core code, existing methods are difficult to establish the correlation between data anomalies and code errors, resulting in insufficient pertinence and effectiveness of debugging. Summary of the Invention

[0006] Aiming at the problem of low debugging efficiency of IP core modules in the existing technology, this application provides an FPGA-based debugging method for IP core modules, which uses a support vector machine model to extract and classify abnormal features of data streams, obtains the control flow and data flow information of the IP core module through a static analysis program, and combines data-driven fault triggering conditions and state triggering conditions, etc., to improve the real-time performance and accuracy of abnormal location, thereby improving the debugging efficiency.

[0007] The purpose of this application is achieved through the following technical solutions.

[0008] This embodiment of the specification provides an FPGA-based debugging method for IP core modules, which is characterized by including the following steps: obtaining the data streams generated under different abnormal conditions of the IP core module as simulation test cases, and inputting the data streams into the support vector machine (SVM) model set on the FPGA chip through the data interface circuit set on the FPGA chip. The data interface circuit is used to realize the conversion and synchronization of external data and internal data of the FPGA chip; using the support vector machine (SVM) model to extract features from the input data streams, and based on wavelet transform and Fourier transform through the feature extraction circuit set on the FPGA chip, extracting the time domain, frequency domain, and time-frequency domain features of the data streams, and forming the extracted features into feature vectors; inputting the feature vectors into the support vector machine (SVM) model for classification, obtaining the feature patterns in the data streams as abnormal patterns, and the abnormal patterns represent the types of abnormalities in the data streams; according to the obtained abnormal patterns, through the trigger condition generation circuit set on the FPGA chip, setting and obtaining the corresponding fault trigger conditions. The trigger conditions include the threshold conditions of abnormal features and the abnormal duration conditions, and storing the trigger conditions in the storage unit of the FPGA chip through the storage interface circuit set on the FPGA chip.

[0009] Obtaining the state change information of the finite state machine (FSM) inside the IP core module, and according to the state change information, setting the state trigger conditions in different states through the state trigger condition generation circuit set on the FPGA chip. The state trigger conditions include state transition conditions and state duration conditions, and storing the state trigger conditions in the storage unit of the FPGA chip through the storage interface circuit; according to the trigger conditions and state trigger conditions stored in the storage unit of the FPGA chip, monitoring the input data and output data of the IP core module in real time, and through the data monitoring circuit set on the FPGA chip, collecting the input data and output data of the IP core module in real time, extracting their features and comparing them with the trigger conditions and state trigger conditions; when it is detected that the trigger conditions or state trigger conditions are triggered, automatically executing a preset debugging operation through the debugging logic circuit set on the FPGA chip, obtaining the internal data and state information of the IP core module during the abnormality, and generating a debugging result report.

[0010] The program control flow graph parsing algorithm set on the FPGA chip is used to perform static analysis on the code of the IP core module. Through the code parsing circuit set on the FPGA chip, syntax and semantic analysis are carried out on the RTL-level or gate-level description code of the IP core module, control flow and data flow information are extracted, a program control flow graph model is constructed, and static analysis results are obtained. According to the debugging results and static analysis results, through the correlation analysis algorithm, and through the correlation analysis circuit set on the FPGA chip, the data and status at the time of anomaly occurrence in the debugging results are correlated with the control flow graph in the static analysis results, the code segments related to the anomaly in the IP core module are found, correction suggestions are automatically generated, and the correction suggestions are displayed on the display unit of the FPGA chip to assist the user in marking and modifying the anomaly code segments, thus completing the debugging of the IP core module.

[0011] Among them, the IP core module refers to a reusable design unit implemented on the FPGA chip, which encapsulates specific functions and can be integrated into a larger system design like the core component of a large-scale integrated circuit IC. Anomaly situations refer to situations that cause errors in the operation of the IP core module, including core algorithm errors, data out-of-bounds, infinite loops, etc., which result in incorrect outputs or the module stopping running. Simulation test cases are input data sequences used to verify the correctness of the design. Here, it specifically refers to inputting simulation data under different anomaly situations of the IP core module and obtaining the data flow of its output to obtain test cases containing anomaly information.

[0012] Among them, the data flow refers to a series of digital signal sequences generated in chronological order when the IP core module processes the data of the simulation test cases. It reflects the operating status and output results of the IP core module under different anomaly situations. The FPGA chip is a field-programmable gate array chip that can implement custom logic circuits inside the chip. The support vector machine is a supervised learning model used for classification and regression analysis. The feature pattern refers to the eigenvalue distribution or combination in the data flow that reflects a specific anomaly situation and can uniquely identify a certain type of anomaly.

[0013] Specifically, a Support Vector Machine (SVM) model is set on the FPGA chip, and the hardware description of the SVM model is designed using HLS tools to convert the model algorithm description into Verilog code at the Register Transfer Level (RTL). The main modules include: Input module: Receives the data stream and caches the input features. Kernel module: Implements the calculation of the SVM kernel function. Decision module: Judges the classification result according to the output of the kernel function. The Verilog code is synthesized using the FPGA development tool to generate a configurable gate-level netlist for the FPGA. The netlist of the SVM model is loaded onto the specified programmable logic block on the FPGA chip through the JTAG or other configuration interfaces. The top-level design of the SVM model is instantiated on the FPGA and connected to the data stream interface. The input module receives the data stream and pushes it to the kernel module. The kernel module calculates the kernel function value. The decision module judges the classification result of the abnormal mode according to the output of the kernel function. The classification result is output to the result analysis module to complete the abnormal mode detection. The correctness of the model on the FPGA is ensured through co-design and simulation verification.

[0014] Among them, the trigger condition refers to a set of rules or criteria used to detect the occurrence of an abnormal mode. When the trigger condition is met, it indicates that the abnormal mode has occurred. In this application, according to the abnormal mode extracted from the data stream, the corresponding fault trigger condition is set. The trigger condition can include threshold criteria for abnormal data, data feature relationship criteria, etc. When the real-time data stream meets the set trigger condition, it can be considered that the corresponding abnormal mode has occurred. By judging the trigger condition, the abnormal situation of the IP core module can be detected immediately for module status monitoring.

[0015] Among them, the Finite State Machine (FSM) is a mathematical model used to model a finite number of states and the transitions and actions between these states, etc. State change means that the FSM transfers from one state to the next state. The state trigger condition refers to the condition criterion that causes the state change of the FSM. When this condition is met, the state switch is triggered. In this application, it refers to establishing the FSM model of the internal algorithm logic of the IP core module. For different possible state change situations in the FSM of the IP core module, the corresponding state trigger conditions are set. The state trigger condition can include the values of internal Signals in the module, the values of status registers, etc. The state trigger condition is set according to the state change law of the FSM.

[0016] Specifically, according to the set trigger conditions and status trigger conditions, the IP core module is debugged. After obtaining the abnormal mode, the corresponding fault trigger conditions are set, such as the criterion for data out-of-bounds. Analyze the state machine of the IP core module and set the status trigger conditions for the transition between states, such as the value of the status register. Integrate a logic analyzer on the FPGA to monitor the real-time running signals of the IP core module. When it is detected that the set trigger conditions are met, information such as the trigger time and module status is recorded. Locate the corresponding code, check the variable values and register status at that moment, and analyze the cause of the abnormality. If the trigger conditions are inconsistent with the status changes, the state machine logic also needs to be checked. Repeat the debugging multiple times to collect the trigger condition information under various abnormal situations. According to the information obtained from the debugging, locate the root cause of the abnormality, make modifications and verifications, and improve the design of the IP core module. Until all types of abnormal situations can be correctly detected by the trigger conditions and the running logic of the IP core module is correct. Finally, a complete debugging report is formed.

[0017] Among them, the program control flow graph parsing algorithm is an algorithm for structurally analyzing the program source code, which can construct the control flow relationship in the source code, that is, the execution order and conditional relationship between the basic blocks of the program. Static analysis is the non-execution analysis of computer software, which checks the code before the program runs to find problem points or verify correctness. In this application, this algorithm is implemented on the FPGA chip to improve the analysis efficiency; through lexical and syntactic analysis, the basic blocks of the IP core module code are obtained; a program control flow graph is constructed to represent the execution transfer relationship between the basic blocks; the code is statically analyzed without execution to analyze the core running logic and find the critical path.

[0018] Specifically, set the program control flow graph parsing algorithm on the FPGA chip, and use Verilog or VHDL language on the FPGA chip to design the hardware description of the program control flow graph parsing algorithm. The main modules include: Lexical analysis module: perform lexical tokenization and identifier parsing of the source code; Syntactic analysis module: construct the abstract syntax tree (AST) of the code and check the syntax; Control flow analysis module: extract the basic blocks from the AST and construct the control flow relationship; Data flow analysis module: analyze the variable definitions and uses in the code and establish the data flow relationship. Use the development tools of the FPGA to synthesize the designed Verilog or VHDL code into a gate-level netlist configurable by the FPGA. Use the corresponding configuration interface on the FPGA development board to load and configure the generated netlist data onto the corresponding programmable logic blocks of the FPGA chip. Instantiate the top-level module of the parsing algorithm on the FPGA chip and establish a data path between this module and the IP core interface. The source code of the IP core module is transmitted through the set interface to the parsing algorithm module for processing. The parsing algorithm module outputs the parsing results and sends them to the result analysis module to complete the static analysis of the IP core code.

[0019] Among them, correlation analysis refers to a technical means of comprehensively considering the correlation between two or more analysis results and conducting overall analysis to find the root cause of problems. In this application, this solution includes two technical means: dynamic debugging and static analysis. Dynamic debugging can find the actual location where an exception occurs. Static analysis can directly locate logical errors in the code. Specifically, according to the debugging results and static analysis results, correlation analysis is carried out, and the exception information obtained from dynamic debugging and static analysis is collected respectively, including the trigger location, exception data, key variables, key code paths, etc. Mark the exception location obtained from dynamic debugging on the program control flow graph. Compare the results of dynamic debugging and static analysis to find the related exception points. By correlating these related exception points, the cause of the exception can be located, such as algorithm errors, variable out-of-bounds, etc. Debug according to the correlation analysis results, and for each determined cause of the exception, make corrections in the source code, such as adding boundary checks, modifying algorithm logic, etc.

[0020] Further, the steps of using the support vector machine SVM model to extract features from the input data stream and obtain the feature pattern in the data stream as the abnormal pattern include: inputting the input data stream into the dual-wavelet transform denoising circuit set on the FPGA chip, and the dual-wavelet transform denoising circuit performs forward and inverse transforms on the input data stream using wavelet transform, removes the noise components in the data stream by threshold processing of the wavelet coefficients, obtains the denoised data stream, and outputs the denoised data stream to the feature extraction circuit;

[0021] The denoised data stream is input into a feature extraction circuit arranged on an FPGA chip, and the feature extraction circuit includes a time domain feature extraction unit, a frequency domain feature extraction unit and a time-frequency feature extraction unit; wherein the time domain feature extraction unit divides the data stream by a sliding window method, calculates the statistical characteristics of the data in each window, including the mean, variance, skewness and kurtosis, and obtains the time domain characteristics of the data stream; the frequency domain feature extraction unit performs spectrum analysis on the data stream by using a fast Fourier transform FFT, calculates the power spectrum and spectrum entropy of the data stream, and obtains the frequency domain characteristics of the data stream; the time-frequency feature extraction unit performs time-frequency analysis on the data stream by using a wavelet packet transform, calculates the energy distribution of the data stream at different scales and time positions, and obtains The method comprises the following steps: extracting time-domain features, frequency-domain features and time-frequency features to form a high-dimensional feature vector, and outputting the high-dimensional feature vector to a dimensionality reduction processing circuit; inputting the high-dimensional feature vector to a dimensionality reduction processing circuit arranged on an FPGA chip, and the dimensionality reduction processing circuit performs dimensionality reduction processing on the high-dimensional feature vector by adopting a local preservation projection (LPP) algorithm, constructing a neighbor graph of the high-dimensional feature vector, calculating the distance between the vertices on the graph, constructing a Laplace matrix according to the distance, solving the eigenvector corresponding to the minimum eigenvalue of the Laplace matrix as the projection direction, mapping the high-dimensional feature vector to a low-dimensional space, obtaining a low-dimensional feature vector after dimensionality reduction, and outputting the low-dimensional feature vector to a SVM training circuit.

[0022] Taking the low-dimensional feature vector as the input, a support vector machine (SVM) model is established. The SVM model is trained using the low-dimensional feature vector as the training sample. The dual problem of the SVM model is solved by the sequential minimal optimization (SMO) algorithm to obtain the optimal hyperplane parameters of the SVM model, including: extracting the critical path in the operation logic as the feature path according to the operation logic structure of the IP core module and the abnormal pattern association relationship table; where the critical path refers to the path segment covering the critical nodes of the abnormal pattern; performing data flow analysis on each feature path, extracting the variable definition-use chain on the feature path, and constructing a path data flow graph; the nodes of the path data flow graph represent variables and operation operations, and the directed edges represent the data dependency relationships from variables to operations and from operations to variables. Preferably, when constructing the path data flow graph, a data flow-sensitive cut-point is introduced to improve the sparsity of the graph structure and reduce the computational complexity of subsequent graph embedding; using the graph convolutional neural network algorithm, mapping the path data flow graph to a low-dimensional real number space to generate a low-dimensional real-valued feature vector of the path; each dimension of the low-dimensional real-valued feature vector represents the weight coefficient of the path in the corresponding feature dimension; the graph convolutional neural network learns the local and global structural features of the nodes by iteratively aggregating the neighborhood information of the nodes to obtain a path embedding representation with high discriminability; based on the low-dimensional real-valued feature vector, a support vector machine (SVM) model is constructed; the input of the SVM model is the low-dimensional real-valued feature vector of the feature path, and the output is the abnormal determination result of the feature path; a kernel function is introduced to map the low-dimensional real-valued feature vector to a high-dimensional space to improve the non-linear classification ability of the SVM model; using the sequential minimal optimization (SMO) algorithm to solve the dual problem of the SVM model to obtain the support vectors, threshold, and classification weight parameters of the SVM model; the SMO algorithm heuristically selects the violated pair and optimizes and updates it to iteratively solve the optimal hyperplane parameters; introducing a sample confusion degree index to adaptively adjust the iterative termination condition of the SMO algorithm to balance the training accuracy and efficiency; during debugging and running, for the IP core module to be analyzed, dynamically extract the critical path in its operation logic, and generate a low-dimensional real-valued feature vector of the critical path through path data flow analysis and the graph convolutional neural network; adopting an incremental calculation method to reuse the feature vectors of the previous critical path to reduce duplicate calculations; inputting the low-dimensional real-valued feature vector of the critical path into the trained SVM model to obtain the abnormal determination result and abnormal type of the path; adopting a path combination strategy to comprehensively consider the determination results of multiple critical paths to improve the overall diagnosis accuracy and coverage.

[0023] Furthermore, the dual-wavelet transform denoising circuit includes a coiflet wavelet filter and a bior wavelet filter connected in series; the input data stream is input into the coiflet wavelet filter, and the coiflet wavelet filter performs multi-level wavelet decomposition on the input data stream using the coiflet wavelet basis. By performing high-pass and low-pass filtering on the data stream, the low-frequency approximation coefficients and high-frequency detail coefficients of the data stream at different scales are extracted; the extracted high-frequency detail coefficients are input into the threshold processing unit provided in the coiflet wavelet filter, and the threshold processing unit performs hard threshold processing on the high-frequency detail coefficients using a preset threshold, setting the high-frequency detail coefficients smaller than the threshold to zero to remove high-frequency noise; among them, the high-frequency coefficients represent the high-frequency components in the data stream, reflecting the detail information and fast-changing parts of the data. In wavelet transform, the high-frequency coefficients of the data stream are extracted through a high-pass filter. High-frequency coefficients usually contain high-frequency interferences such as noise and spike pulses, but may also contain some important transient features. In denoising applications, by performing threshold processing or weighted processing on the high-frequency coefficients, the noise components in the data can be effectively suppressed while retaining the key detail information. The low-frequency coefficients represent the low-frequency components in the data stream, reflecting the trend information and slow-changing parts of the data. In wavelet transform, the low-frequency coefficients of the data stream are extracted through a low-pass filter. Low-frequency coefficients usually contain the main energy and basic features of the data, representing the general trend and average level of the data. In denoising applications, the low-frequency coefficients are usually retained as the basis for data reconstruction to ensure that the denoised data still maintains the original trend characteristics.

[0024] The high-frequency detail coefficients after threshold processing and the low-frequency approximation coefficients are input together into the wavelet reconstruction unit set in the coiflet wavelet filter. The wavelet reconstruction unit uses the coiflet wavelet basis to perform multi-level wavelet reconstruction on the high-frequency detail coefficients and low-frequency approximation coefficients after threshold processing. By upsampling and convolving the wavelet coefficients at different scales, the data stream after forward transformation is obtained, and the data stream after forward transformation is output to the bior wavelet filter; the data stream after forward transformation is input to the bior wavelet filter. The bior wavelet filter uses the bior wavelet basis to perform multi-level wavelet decomposition on the data stream after forward transformation. By performing high-pass and low-pass filtering on the data stream, the low-frequency approximation coefficients and high-frequency detail coefficients of the data stream after forward transformation at different scales are extracted; the extracted high-frequency detail coefficients are input to the anti-threshold processing unit set in the bior wavelet filter. The anti-threshold processing unit performs soft threshold processing on the high-frequency detail coefficients using a preset threshold, subtracting the threshold from the high-frequency detail coefficients greater than the threshold to remove the high-frequency pseudo-details introduced in the forward transformation; the high-frequency detail coefficients after anti-threshold processing and the low-frequency approximation coefficients are input together into the wavelet reconstruction unit set in the bior wavelet filter. The wavelet reconstruction unit uses the bior wavelet basis to perform multi-level wavelet reconstruction on the high-frequency detail coefficients and low-frequency approximation coefficients after anti-threshold processing. By upsampling and convolving the wavelet coefficients at different scales, the denoised data stream is obtained, and the denoised data stream is output to the subsequent feature extraction circuit.

[0025] Further, in the feature extraction circuit, first, the denoised data stream is input to the Bayesian estimation circuit. The Bayesian estimation circuit uses the Bayesian estimation algorithm to estimate the statistical characteristics of the data stream. Specifically, by constructing a probability model of the data stream, taking the sliding window width as the parameter to be estimated and introducing it into the posterior probability distribution, and then by maximizing the log posterior probability, using a numerical optimization algorithm to solve the optimal sliding window width, and outputting the optimal sliding window width to the time-domain statistical feature extraction circuit. The time-domain statistical feature extraction circuit receives the denoised data stream and the optimal sliding window width, and uses the moving average method to perform windowing processing on the data stream. Specifically, by setting a sliding window with a length equal to the optimal width, uniformly windowing the data stream, and sliding the window in turn to intercept the data. For the sampling points in each data window, calculate their mean value, variance, and kurtosis coefficient. The mean value reflects the average amplitude of the signal within the window, the variance reflects the degree of signal fluctuation, and the kurtosis coefficient reflects the sharpness of the signal peaks. The mean value, variance, and kurtosis coefficient calculated in each window are output as the time-domain statistical features of the data stream.

[0026] The denoised data stream is simultaneously input into the frequency-domain feature extraction circuit. The frequency-domain feature extraction circuit uses the fast Fourier transform (FFT) algorithm based on the Pino sequence to perform spectral analysis on the data stream. The traditional FFT algorithm needs to store and access the spectral coefficients according to the bit-reversal permutation, resulting in a large number of memory accesses. The FFT algorithm based on the Pino sequence utilizes the pseudo-randomness of the Pino sequence to rearrange the input data and operation coefficients of the FFT, reducing the bit-reversal operation, thereby reducing the number of memory accesses and improving the operation speed. The spectral coefficients are obtained through the FFT transformation of the data stream, and the power spectral density and spectral entropy of the data stream are calculated. Among them, the power spectral density reflects the power distribution of the signal at different frequencies, and the spectral entropy reflects the degree of chaos of the spectrum. The calculated power spectral density and spectral entropy are output as the frequency-domain features of the data stream.

[0027] The denoised data stream is simultaneously input into the time-frequency feature extraction circuit. The time-frequency feature extraction circuit uses the orthogonal matching pursuit algorithm to perform adaptive wavelet packet decomposition on the data stream, and adaptively selects the best-matched wavelet packet basis. Specifically, by constructing wavelet packet bases with different scales and different frequency bands, the projection coefficients of the data stream on each wavelet packet basis are calculated. The magnitude of the projection coefficient reflects the matching degree between the data stream and the wavelet packet basis. The wavelet packet basis with the largest projection coefficient is selected as the best-matched basis, and the corresponding wavelet packet node is output as the optimal wavelet packet node.

[0028] The optimal wavelet packet node is input into the sparse wavelet transform circuit. The sparse wavelet transform circuit performs sparse representation of the wavelet coefficients of the optimal wavelet packet node. Specifically, by taking the absolute value of the wavelet coefficients and setting a sparsity threshold, the wavelet coefficients smaller than the threshold are set to zero, while the wavelet coefficients larger than the threshold are retained, thereby realizing the sparsification of the wavelet coefficients. The optimal wavelet packet node is reconstructed using the sparsified wavelet coefficients, and the energy distribution of the reconstructed nodes at different scales is calculated as the wavelet packet energy spectrum; the correlation between adjacent wavelet packet nodes at different scales is calculated as the inter-packet coherence. The wavelet packet energy spectrum and the inter-packet coherence are output as the time-frequency features of the data stream. Finally, the mean, variance, and kurtosis coefficient output by the time-domain statistical feature extraction circuit, the power spectral density and spectral entropy output by the frequency-domain feature extraction circuit, and the wavelet packet energy spectrum and the inter-packet coherence output by the time-frequency feature extraction circuit are combined into a high-dimensional feature vector and output to the dimensionality reduction processing circuit for subsequent feature dimensionality reduction.

[0029] Further, the dimensionality reduction processing circuit performs dimensionality reduction processing on the high-dimensional feature vector to obtain a low-dimensional feature vector, and the steps include: inputting the high-dimensional feature vector output by the feature extraction circuit into the distance matrix calculation module, where the distance matrix calculation module calculates the Euclidean distance between any two high-dimensional feature vectors, constructs the distance matrix of the high-dimensional feature vectors, and outputs the distance matrix to the K-nearest neighbor graph construction module; inputting the distance matrix into the K-nearest neighbor graph construction module, where the K-nearest neighbor graph construction module searches for its K nearest neighbor vectors for each high-dimensional feature vector based on the distance matrix, constructs the K-nearest neighbor structure of the high-dimensional feature vectors, and outputs the K-nearest neighbor structure to the Laplacian matrix construction module; where K is a preset positive integer; inputting the K-nearest neighbor structure into the Laplacian matrix construction module, where the Laplacian matrix construction module traverses the K-nearest neighbor structure of each high-dimensional feature vector, and if two high-dimensional feature vectors are K-nearest neighbors, fills 1 in the corresponding element of the Laplacian matrix, otherwise fills 0, constructs the Laplacian matrix of the high-dimensional feature vectors, and outputs the Laplacian matrix to the generalized eigenvalue solving module.

[0030] Input the Laplacian matrix into the generalized eigenvalue solving module. The generalized eigenvalue solving module uses the Rayleigh quotient iteration algorithm to solve the generalized eigenvalue problem of the Laplacian matrix, obtains the generalized eigenvector corresponding to the smallest non-zero generalized eigenvalue equal to the number of dimensions of the preset dimensionality reduction target, uses the obtained generalized eigenvector as the projection vector of the locally linear embedding algorithm to form a projection matrix, and outputs the projection matrix to the low-dimensional feature mapping module; input the high-dimensional feature vector and the projection matrix into the low-dimensional feature mapping module. The low-dimensional feature mapping module linearly transforms the high-dimensional feature vector using the projection matrix, maps the high-dimensional feature vector to the low-dimensional feature space, obtains the dimensionality-reduced low-dimensional feature vector, and outputs the low-dimensional feature vector to the fault diagnosis circuit.

[0031] Specifically, to calculate the distance matrix between high-dimensional feature vectors, collect the extracted high-dimensional feature vectors. Suppose there are m vectors, and each vector has a length of n. Define an mxm distance matrix D. Traverse all pairs of feature vectors to calculate the distance: for i = 1 to m: for j = 1 to m: if i == j: D[i, j] = 0; otherwise: D[i, j] = calculate the distance between vector i and vector j. There are various distance calculation methods, and commonly used ones include: Euclidean distance: the square root of the sum of the squares of the differences of the corresponding components of two vectors, Manhattan distance: the sum of the absolute values of the differences of the corresponding components of two vectors, cosine distance: the cosine value of the angle between two vectors. Select an appropriate distance calculation method according to the feature type and purpose. After the above steps, an mxm distance matrix D is obtained, which reflects the distance relationship between each feature vector. The distance matrix can be used in subsequent clustering, dimensionality reduction and other algorithms.

[0032] Among them, the K-nearest neighbor structure: For each sample point, find the set of K other sample points that are closest to it. These K nearest sample points constitute the K-nearest neighbor structure of this sample point. In this application, the K-nearest neighbor structure is constructed according to the distance matrix. The distance matrix D of the sample set is calculated, and D[i, j] represents the distance between sample i and j. For each sample i, find the K other samples that are closest to it: Sort D[i, :], and take out the sample indices corresponding to the smallest K distance values. These K sample indices are the K-nearest neighbor structure of sample i. Repeat the above process to traverse the sample set and obtain the K-nearest neighbor structure of each sample. Integrate the K-nearest neighbor structures of all samples, which is the K-nearest neighbor structure of the entire sample set. The value of K is generally taken as a small integer, and common values include 5, 10, etc.

[0033] Among them, the Laplacian matrix: A matrix that reflects the connection relationship between sample points, and its elements are the weighted values of the similarity or distance between sample points. In this application, the Laplacian matrix is constructed according to the K-nearest neighbor structure. The K-nearest neighbor structure of each sample point is constructed to obtain the nearest neighbor sample indices. Initialize an N*N Laplacian matrix L, where N is the total number of samples. For each pair of nearest neighbor sample points i and j, update the Laplacian matrix: d is the distance between i and j, σ is the Gaussian kernel width, L[i, j] = L[j, i], and the diagonal element L[i, i] = -sum(L[i, :]). The Laplacian matrix L is obtained, which encodes the local similarity relationship between samples. L can be used for dimensionality reduction and can also reflect the global structure of the sample set.

[0034] Among them, the Rayleigh quotient: An objective function used to optimize the projection vector, defined as the ratio of the vector after the projection vector is multiplied by the Laplacian matrix. In this application, the Laplacian matrix L is constructed according to the K-nearest neighbor structure of the samples. Initialize a random projection vector v. Calculate the Rayleigh quotient: v T represents the transpose of v, L is the Laplacian matrix, v is the projection vector, iteratively optimize v to maximize the Rayleigh quotient R(v). When the Rayleigh quotient converges, the optimal projection vector v is obtained. v is orthogonal to the low-dimensional manifold structure of the data samples. Map the samples onto v to obtain the dimensionality reduction result. Repeat the process to find multiple projection vectors to complete dimensionality reduction.

[0035] Specifically, repeatedly solve the projection vectors and construct the projection matrix. Initialization: Set the target dimensionality reduction dimension n, that is, n projection vectors are required. Solve the first projection vector v1: Construct the Laplacian matrix L of the samples, randomly initialize v1, and maximize the Rayleigh quotient R(v1) to obtain the optimal v1. Solve the second projection vector v2: According to v1, construct the constrained Laplacian matrix L' excluding the direction of v1, randomly initialize v2, and maximize the Rayleigh quotient R(v2) to obtain the optimal v2. Solve the i-th projection vector v i , with dimension n: According to [v1, v2,......, v n , construct the constrained Laplacian matrix, randomly initialize v i , and optimize to obtain the optimal v i . Obtain n orthogonal projection vectors [v1, v2,......, v n . Construct the projection matrix P = [v1, v2,......, v n . Multiply the sample data by the P matrix to complete dimensionality reduction.

[0036] Specifically, reduce the dimensionality of the high-dimensional feature vectors using the constructed projection matrix, collect the extracted high-dimensional feature vectors to form the sample matrix X, where each row is a sample. Through iterative optimization, n projection vectors [v1, v2,......, v n are obtained. Construct the projection matrix P = [v1, v2,......, v n . The size of the projection matrix P is n×m, where n is the target dimensionality reduction number and m is the original high-dimensional number. Left-multiply the sample matrix X by the projection matrix P to achieve projection transformation: Y = PX, where Y is the dimensionality-reduced sample matrix with size n×number of samples. Sample each row vector: y = Px, and the dimensionality reduction result y corresponding to the high-dimensional sample x can be obtained. Perform the above operations on all high-dimensional samples in sequence. Finally, obtain the dimensionality-reduced sample set Y, whose dimension is reduced from m to n. The dimensionality-reduced sample set retains the local manifold structure of the original data.

[0037] Further, the Laplacian matrix adopts a positive definite matrix; the projection matrix adopts an orthogonal matrix. The Laplacian matrix output by the Laplacian matrix construction module is input into the positive definite matrix conversion module. The positive definite matrix conversion module performs diagonalization correction on the Laplacian matrix, converts the Laplacian matrix into a positive definite matrix, and outputs the positive definite Laplacian matrix to the generalized eigenvalue solving module; wherein, the method of positive definite matrix conversion is: adding a positive number greater than the absolute value of its minimum eigenvalue to each element of the Laplacian matrix to obtain the positive definite Laplacian matrix; the projection vector matrix output by the generalized eigenvalue solving module is input into the orthogonalization processing module. The orthogonalization processing module uses the Schmidt orthogonalization method to orthogonalize the projection vectors to obtain the orthogonalized projection matrix, and outputs the orthogonal projection matrix to the low-dimensional feature mapping module; wherein, the steps of Schmidt orthogonalization are: taking the first column vector of the projection matrix as the first vector of the orthogonal basis; for each subsequent column vector of the projection matrix, using the Gram-Schmidt orthogonalization formula, subtracting its projection on the already obtained orthogonal basis vectors to obtain a new orthogonal vector; repeating until all column vectors of the projection matrix are orthogonalized to generate the orthogonal projection matrix.

[0038] Further, the support vector machine SVM model adopts the C-SVM model; the kernel function of the C-SVM model adopts the Gaussian kernel function; the expression of the Gaussian kernel function is as follows: where x and x i are the sample feature vectors input into the kernel function, representing the test sample and the support vector in the support vector machine respectively; ||x - x i || represents the Euclidean distance between the test sample x and the support vector x i ; σ(x, x i ) represents the variable kernel width based on x and x i . where σ0 is the initial kernel width of the Gaussian kernel function, and its value is predetermined before training; α is the kernel width adjustment parameter, controlling the amplitude of the kernel width change, and its value range is positive real numbers; β is the kernel width adjustment parameter, controlling the rate of the kernel width change, and its value range is positive real numbers.

[0039] Among them, the C-SVM model is an improved support vector machine model, and a regularization parameter C is introduced into the optimization objective. In this application, the C-SVM adds a regularization term to the loss function, which can balance the model complexity and the training set error. By adjusting the value of the parameter C, the sensitivity of the model to outliers can be controlled. When C approaches infinity, the C-SVM degenerates into the original SVM model. Selecting an appropriate value of C can improve the generalization ability of the model and avoid overfitting. In this solution, the optimal C is selected through cross-validation to obtain a C-SVM model with strong generalization ability. Then the optimized C-SVM model is used for fault detection and classification.

[0040] Among them, the Gaussian kernel function: a popular SVM kernel function, which measures similarity by calculating the Gaussian function value of the distance between samples. In this application, the expression of the Gaussian kernel function is as follows: A variable kernel width σ(x, x i ) based on samples x and x i is introduced, rather than a fixed σ. σ(x, x i ) can vary according to the density of x and xilocal. Using the variable kernel width σ(x, x i ) in the kernel function instead of a fixed global kernel width makes the kernel function more sensitive to sample points of different patterns. It adapts to the density changes of sample distributions in different regions, improves the flexibility of the kernel function mapping space, and enhances the SVM's modeling ability for samples with complex distributions. The variable kernel width reduces the risk of overfitting. By introducing a variable kernel width, the improved Gaussian kernel function enhances the adaptability of the SVM to complex sample distributions and improves the classification performance of the model. x is the test sample, and x i is the support vector, which is input into the kernel function K for kernel mapping. ||x - x i || calculates the Euclidean distance between the two samples. σ(x, x i ) is the variable kernel width calculated according to x and x i . The expression of the kernel function is: The variable kernel width σ(x, x i ) is used in the denominator instead of a fixed σ. When the distance between x and x i is farther, σ(x, x i ) will increase according to the formula. The farther the distance, the faster the exponential term decreases and the smaller the kernel function value. This realizes that the support vectors closer to the test sample x contribute more, thereby improving the sensitivity of the kernel mapping to the local sample distribution. Finally, the kernel matrix is input into the SVM to improve the ability to model complex samples.

[0041] Specifically, the variable kernel width of σ(x, x i ) σ0 is the initial kernel width, and a global constant value is preset. α is the parameter for kernel width adjustment, controlling the variation range, and takes positive real numbers. The larger α is, the greater the change in kernel width. β is the rate parameter for kernel width change, and takes positive real numbers. The larger β is, the faster the kernel width changes with distance. ||x - x i || is the Euclidean distance between the test sample x and the support vector xi. The calculation formula for the kernel width σ(x, x i ) is as follows: When the distance between x and xi is farther, the numerator term increases, and the kernel width σ(x, x i ) will be larger. This achieves the effect of automatically adjusting the kernel width according to the sample distance. By selecting an appropriate α, β can control the degree of change in the kernel width.

[0042] Furthermore, in the fault diagnosis circuit, the program control flow graph parsing algorithm is used to perform static analysis on the code of the IP core module, obtain the running logic of the IP core module and the code corresponding to the abnormal mode, and provide support for source code-level fault diagnosis. The static code analysis includes: First, the source code of the IP core module is input into the lexical and syntactic analysis module. The lexical and syntactic analysis module uses lexical analysis and syntactic analysis techniques to traverse the character stream of the source code, and according to the predefined lexical rules and syntactic rules, converts the source code into the form of a token sequence and an Abstract Syntax Tree (AST). On this basis, the basic blocks in the source code are extracted, and each basic block represents a continuous instruction sequence with a single entry and a single exit. The division of basic blocks is based on the control flow of the program. There are no jump instructions inside a basic block, and the boundaries of basic blocks are determined by jump instructions (such as conditional branches, loops, etc.). The lexical and syntactic analysis module outputs the extracted basic blocks as the input for constructing the control flow graph.

[0043] Then, the basic blocks are input into the control flow graph construction module. The control flow graph construction module uses the control flow analysis algorithm to construct the control flow graph (Control Flow Graph, CFG) of the IP core module according to the jump relationship and conditional judgment statements between the basic blocks. The control flow graph is a directed graph used to represent the control flow structure of a program, where nodes represent basic blocks and directed edges represent the execution order and conditional judgment relationship between basic blocks. By analyzing the jump target and conditional judgment statements of basic blocks, the successor blocks of basic blocks can be determined, and directed edges are added between the corresponding nodes. The control flow graph construction module outputs the constructed control flow graph, which reflects the static execution process of the IP core module.

[0044] Next, input the control flow graph into the loop recognition module. The loop recognition module traverses the control flow graph using the Tarjan algorithm to identify the loop structures in the program. Preferably, use the Tarjan loop recognition algorithm to traverse the control flow graph, identify the strongly connected components with the same start node and end node, label the node set corresponding to the strongly connected component as a loop, obtain the location information of the loop in the source code, and generate an annotated control flow graph with loop information, including: set the starting node of the loop recognition algorithm as the entry node of the control flow graph, start from the starting node, and traverse all nodes and edges of the control flow graph using the depth-first search strategy; during the traversal process, record the access timestamp and backtracking value of the current node; where the access timestamp represents the time when the node is first accessed, and the backtracking value represents the node with the earliest access timestamp that the current node can trace back to; if a child node of the current node has been accessed, compare the backtracking value of the current node with the access timestamp of the child node, if the timestamp of the child node is less than the backtracking value of the current node, then update the backtracking value of the current node to the timestamp of the child node; if all child nodes of the current node have been accessed, and the access timestamp and backtracking value of the current node are equal, then generate a strongly connected component with the current node as the root node, and push the strongly connected component onto the loop stack; after identifying all strongly connected components, traverse each strongly connected component in the loop stack, extract the node set included in each strongly connected component, use the starting line number and ending line number of the basic block corresponding to the node set in the source code as the location information of the loop, and construct a loop information table; according to the loop information table, annotate each node in the control flow graph, if the node belongs to a certain loop, then add a loop attribute mark to the node, and the mark content includes the loop number and location information to which it belongs, and generate an annotated control flow graph with loop information.

[0045] Input the annotated control flow graph into the data flow analysis module. The data flow analysis module uses the Reaching Definition data flow analysis algorithm to solve the data flow on the control flow graph and obtain the variable definitions and usage situations at different positions in the program. Preferably, perform a topological sort on the annotated control flow graph to obtain the linear execution order of all basic blocks; according to the linear execution order, starting from the entry node of the control flow graph, use symbolic execution technology to traverse each path of the control flow graph; during the symbolic execution process, perform semantic analysis on each instruction in the basic block, extract the instruction opcode, source operands, and destination operands, and update the program state according to the instruction semantics; where the program state includes the symbolic values of variables, path conditions, and instruction pointers; when the symbolic execution passes through a branch node in the control flow graph, perform constraint solving on the path conditions according to the branch conditions to determine the reachable paths, and continue the symbolic execution on the reachable paths; when the symbolic execution reaches the exit node of the control flow graph, generate a complete symbolic execution path, and construct a data flow fact table according to the instruction sequence and program state updates on the path; the data flow fact table records the definitions and usage situations of each variable at different program points; traverse each item in the data flow fact table, and construct a data dependency graph of variables according to the definition-use chain; the nodes of the data dependency graph represent variables, the directed edges represent the data dependency relationships between variables, and the direction of the edges is the direction of data transfer; perform a topological sort on the data dependency graph to generate the calculation order of variables; combine the instruction sequence and the calculation order of variables to generate the running logic structure of the IP core module; the running logic structure is represented in the form of a directed acyclic graph, where the nodes in the graph represent instructions, and the directed edges represent the execution order and data dependency relationships between instructions.

[0046] Finally, input the operation logic of the IP core module and the code corresponding to the exception mode into the correlation analysis module. The correlation analysis module uses a pattern matching algorithm to search for code fragments in the operation logic that match the exception mode and establish an association relationship between the two. Exception modes usually represent some specific code structures or data flow patterns, such as null pointer references, buffer overflows, deadlocks, etc. By matching these exception modes in the operation logic, potential fault locations and causes are identified, and a mapping relationship is established between the matching results and the source code locations. The results of the correlation analysis connect the source code and the fault behavior, providing direct support for fault diagnosis. Preferably, the operation logic of the IP core module is transformed into the Static Single Assignment form (SSA) to generate the SSA intermediate representation; the SSA intermediate representation includes the definition and usage of each variable, as well as the data flow relationship between instructions; according to the type of the exception mode, a corresponding matching template is constructed; the matching template is in the form of a regular expression, describing the characteristic structure of the exception mode in the SSA intermediate representation; an Abstract Syntax Tree matching algorithm is used to search for subtree structures in the SSA intermediate representation that match the matching template; for the successfully matched subtree structures, extract the key nodes in the subtree, and the key nodes include variable definition nodes, control flow decision nodes, and exception trigger nodes; according to the mapping relationship from the SSA intermediate representation to the source code, map the key nodes back to the source code to obtain the key statements corresponding to the exception mode, and the key statements include variable definition statements, branch judgment statements, and exception trigger statements; construct an association relationship table between the operation logic and the code corresponding to the exception mode, and each item of the association relationship table consists of an exception mode number, a set of key nodes, and a set of key statements; during source code-level fault diagnosis, query the association relationship table according to the exception mode number, locate the key statements corresponding to the exception mode, and infer the fault cause based on the actual values of the key statements when the system behavior is abnormal, and generate a fault diagnosis report.

[0047] Furthermore, in the fault diagnosis circuit, according to the exception mode obtained from the correlation analysis module, set the corresponding fault trigger conditions for real-time capturing of fault signals during the operation of the IP core module. The trigger condition setting includes: First, the correlation analysis module transmits the extracted exception mode to the trigger condition generation module through the data bus. The exception mode data is organized in a structured form, including multiple fields such as exception type, exception parameters, threshold conditions, etc. The trigger condition generation module reads the exception mode data from the input interface and stores it in the internal buffer for subsequent processing.

[0048] The trigger condition generation module parses and classifies the abnormal pattern data in the buffer one by one. It extracts classification information from the abnormal type field of each abnormal pattern data, and according to the predefined classification rules, classifies the anomalies into two types: eigenvalue overrun anomaly and signal deviation overrun anomaly. The classification rule for the eigenvalue overrun anomaly is that the abnormal type field is marked as "eigenvalue overrun", and the abnormal parameter field contains the feature parameter name and the threshold condition. This kind of anomaly indicates that a certain performance parameter or statistical parameter value of the IP core module exceeds the preset safety range, such as too low throughput, too high latency, excessive error rate, etc. The classification rule for the signal deviation overrun anomaly is that the abnormal type field is marked as "signal deviation overrun", and the abnormal parameter field contains the signal name, the nominal value, and the deviation upper limit. This kind of anomaly indicates that the amplitude of the input / output signal or the internal node signal of the IP core module deviates too much from the nominal value, exceeding the maximum allowable error, such as level drift, interference noise, distortion, etc.

[0049] After completing the classification of the abnormal patterns, the trigger condition generation module further semantically parses the two types of abnormal pattern data. For the eigenvalue overrun anomaly, it extracts the feature parameter name and the threshold condition from the abnormal parameter field, and constructs a judgment expression in the form of "feature parameter value < lower threshold" or "feature parameter value > upper threshold" as the fault trigger condition. For the signal deviation overrun anomaly, it extracts the signal name, the nominal value, and the deviation upper limit from the abnormal parameter field, and constructs a judgment expression in the form of "|actual signal value - nominal value| > maximum deviation" as the fault trigger condition.

[0050] Finally, the trigger condition generation module summarizes the fault trigger conditions generated by the two types of abnormal patterns, combines them through logical OR operation, and forms a complete trigger condition judgment logic. When the IP core module is running, the real-time collected feature parameter values and signal amplitudes are sent into the trigger condition judgment logic for real-time evaluation. Once any trigger condition is met, a fault trigger signal is output to start the collection and recording of the fault signal.

[0051] Generation of the fault trigger condition for the eigenvalue overrun anomaly, feature extraction: First, according to the functional characteristics and performance requirements of the IP core module, determine the key feature parameters reflecting its operating state, such as throughput, latency, resource utilization, etc. At the design stage of the IP core module, insert a feature extraction module on the key data path to statistically calculate these feature parameter values in real time. The feature extraction module can be constructed based on circuit units such as hardware counters and shift registers, and through operations such as accumulation, comparison, and shifting, obtain the instantaneous value or average value of the feature parameters online.

[0052] Threshold Setting: For each characteristic parameter, set the upper and lower limits of its safety threshold according to the design specifications and application scenarios of the IP core module. The setting of the safety threshold needs to comprehensively consider factors such as the performance margin of the IP core module and environmental disturbances. It is necessary to avoid overly loose settings that may lead to missed detection of abnormalities and overly strict settings that may lead to misdiagnosis. The threshold can be configured statically or adjusted dynamically according to the operating history and trends of the IP core module. Comparison and Judgment: Compare the real-time characteristic parameter value obtained by the feature extraction module with the preset threshold to determine whether it exceeds the limit. The specific judgment logic is as follows: If the characteristic parameter value is higher than the upper threshold or lower than the lower threshold, it is considered that a characteristic value overrun abnormality has occurred, and an abnormality detection signal is output; otherwise, it is considered that the characteristic parameter is normal, and no abnormality detection signal is output. The abnormality detection signal can be a single-bit Boolean value, representing the abnormal state of the characteristic parameter. Abnormality Reporting: When any characteristic parameter has an overrun abnormality, report the abnormality detection signal to the trigger condition generation module of the fault diagnosis circuit. The trigger condition generation module summarizes the abnormal states of each characteristic parameter and comprehensively judges whether to trigger the acquisition of the fault signal. For example, when multiple characteristic parameters exceed the limit simultaneously, or a single characteristic parameter exceeds the limit continuously for multiple times, these can all be used as conditions for triggering the acquisition of the fault signal.

[0053] Fault Trigger Condition Generation for Signal Deviation Overrun Abnormality, Baseline Modeling: First, perform statistical modeling on the signals of the input, output, and internal key nodes of the IP core module to obtain the amplitude distribution characteristics under its nominal operating state. The modeling can be based on simulation data or chip sample test data. Through methods such as histograms and normal distribution fitting, statistical characteristics such as the mean, variance, maximum value, and minimum value of the signal are extracted as the reference baseline for fault diagnosis. Deviation Calculation: During the operation of the IP core module, collect the amplitude data of the input, output, and internal signals in real time, and calculate the deviation relative to the nominal value. The deviation can be measured by the relative error, that is, |(actual signal value - nominal value) / nominal value|. To reduce the computational overhead, simplified deviation metrics such as absolute error and mean square error can also be used. The deviation calculation can be implemented using a digital signal processing unit or an embedded soft core. Deviation Judgment: Compare the calculated signal deviation value with the preset maximum allowable deviation threshold to determine whether it exceeds the limit. The specific judgment logic is as follows: If the absolute value of the signal deviation is greater than the maximum allowable deviation, it is considered that a signal deviation overrun abnormality has occurred, and an abnormality detection signal is output; otherwise, it is considered that the signal deviation is normal, and no abnormality detection signal is output. The abnormality detection signal can be a single-bit Boolean value, representing the abnormal state of the signal.

[0054] Abnormal reporting: Similar to the abnormal situation of eigenvalue exceeding the limit, when any signal has a deviation exceeding the limit, the abnormal detection signal is reported to the trigger condition generation module. The trigger condition generation module summarizes the abnormal states of each signal and determines whether to trigger the acquisition of fault signals. For example, when multiple signals deviate beyond the limit simultaneously, or a key signal deviates beyond the limit for a certain period of time, these can all be used as conditions for triggering the acquisition of fault signals. Finally, the trigger condition generation module logically combines the constructed eigenvalue exceeding the limit trigger condition and the signal deviation exceeding the limit trigger condition to form the final fault trigger condition. The logical combination uses an "OR" relationship, that is, as long as any one of the trigger conditions is satisfied, a fault trigger signal is output. The fault trigger signal is used as the input of the fault signal acquisition module to start the acquisition and recording of the fault signals of the IP core module until the fault disappears, completing a diagnostic and acquisition process from the abnormal mode to the fault signal.

[0055] Furthermore, the state trigger condition includes a signal fluctuation trigger condition and an error code trigger condition. Specifically, the abnormal mode output by the correlation analysis module is input to the trigger condition generation module. According to the state type information in the abnormal mode, the type of the state trigger condition is determined to be a signal fluctuation trigger condition or an error code trigger condition; for the signal fluctuation trigger condition, the name of the key signal causing the abnormality, the length of the sampling time window, and the fluctuation threshold range are extracted from the abnormal mode to construct the signal fluctuation trigger condition, that is, when the amplitude fluctuation range of a certain key signal within the specified sampling time window exceeds the fluctuation threshold range, the acquisition of fault signals is triggered; the length of the sampling time window is determined according to the control clock cycle and the fault response time of the IP core module, and the fluctuation threshold range is determined according to the normal waveform characteristics of the key signal; for the error code trigger condition, the error code type and the error code value causing the abnormality are extracted from the abnormal mode to construct the error code trigger condition, that is, when the status register or flag bit of the IP core module appears an error code of the specified type and value, the acquisition of fault signals is triggered; the error code type and the error code value are determined according to the design specifications of the IP core module and the abnormal status code table.

[0056] The signal fluctuation trigger condition and the error code trigger condition are summarized into the fault trigger logic circuit and combined through an "OR" logical relationship to form the state trigger condition; the state trigger condition is combined with the eigenvalue exceeding the limit trigger condition and the signal deviation exceeding the limit trigger condition through an "AND" logical relationship to form a complete fault trigger condition; the trigger condition generation module outputs the fault trigger condition to the fault signal acquisition module to realize the mapping from the abnormal mode to the fault acquisition trigger; the fault signal acquisition module, according to the fault trigger condition, monitors the data flow and status information of the IP core module in real time. When the fault trigger condition is satisfied, it starts the recording and saving of the fault site data until the fault disappears, completing a debugging process from abnormal location to fault recording.

[0057] Compared with the prior art, the advantages of this application are:

[0058] By implementing a support vector machine model on an FPGA and using data stream feature extraction and classification, abnormal patterns of IP core modules can be automatically identified, enabling rapid detection and location of faults. Combining the control flow and data flow information obtained from static program analysis can accurately locate the code positions where anomalies occur, improving the pertinence and effectiveness of debugging.

[0059] Introducing optimization algorithms such as dual wavelet transform denoising, locally preserving projection dimensionality reduction, and Bayesian estimation can effectively remove noise interference in the data stream, extract key feature dimensions, reduce the computational overhead of data processing, and ensure the real-time response ability of fault diagnosis. Using an improved Gaussian kernel function and SMO optimization algorithm can improve the classification generalization ability and convergence speed of the SVM model, reducing the false alarm rate and missed alarm rate.

[0060] Through loop recognition algorithms and data stream analysis algorithms, the program structure and execution logic of IP core modules are extracted, and the mapping relationship between source code and control flow graphs is constructed. Combining the correlation analysis of abnormal patterns and code segments, a two-way tracking mechanism for data-level anomalies and code-level errors is established, which can support both black-box testing and white-box testing, achieving comprehensive coverage and multi-angle diagnosis of IP core modules.

[0061] Implementing computationally intensive tasks such as data processing, feature extraction, and anomaly classification in the form of hardware circuits, and utilizing the parallel processing ability of the FPGA, significantly improves the efficiency and throughput of fault diagnosis. Implementing control-intensive tasks such as state machines, trigger conditions, and loop analysis in the form of reconfigurable logic enhances the adaptability and scalability of diagnostic strategies.

[0062] Combining data-driven abnormal feature extraction with code-driven static program analysis forms a multi-dimensional diagnostic method that integrates data flow and control flow. Through hardware-software co-design, the reusability, tailoring, and portability of diagnostic function modules are realized, supporting flexible debugging of different types and scales of IP cores, and improving the adaptability, generality, and scalability of the diagnostic framework. Brief Description of the Drawings

[0063] This specification will be further described in the form of exemplary embodiments, and these exemplary embodiments will be described in detail through the drawings. These embodiments are not restrictive, and in these embodiments, the same numbers represent the same structures, where:

[0064] Figure 1 is an exemplary flowchart of a method for debugging an IP core module based on an FPGA according to some embodiments of this specification;

[0065] Figure 2An exemplary flowchart for obtaining an abnormal pattern as shown in some embodiments of this specification;

[0066] Figure 3 An exemplary flowchart for obtaining high-dimensional features as shown in some embodiments of this specification;

[0067] Figure 4 An exemplary flowchart for dimensionality reduction processing as shown in some embodiments of this specification;

[0068] Figure 5 An exemplary flowchart for static analysis as shown in some embodiments of this specification. Detailed implementation manners

[0069] The methods and systems provided in the embodiments of this specification will be described in detail below with reference to the accompanying drawings.

[0070] Figure 1 An exemplary flowchart of a method for debugging an IP core module based on FPGA as shown in some embodiments of this specification. A method for debugging an IP core module based on FPGA includes: obtaining data streams generated under different abnormal conditions of the IP core module as simulation test cases; using a support vector machine (SVM) model to obtain the feature patterns in the data streams as abnormal patterns, where the abnormal patterns represent the types of abnormalities in the data streams; setting fault trigger conditions for obtaining the corresponding abnormal patterns according to the obtained abnormal patterns; setting state trigger conditions for different states according to the state changes of the finite state machine (FSM) inside the IP core module; debugging the IP core module according to the set trigger conditions and state trigger conditions; performing static analysis on the code of the IP core module using a program control flow graph parsing algorithm; and debugging the IP core module through correlation analysis according to the debugging results and static analysis results.

[0071] A data acquisition module obtains analog data streams generated under different abnormal conditions of the IP core module as the input data of the technical solution. A software module is directly connected to the FPGA simulation platform to collect the data streams output by the IP core. On the FPGA platform, different signals can be injected to simulate the abnormalities of the IP core, such as setting an adder overflow to simulate an algorithm abnormality, and randomly perturbing signals to simulate signal interference. The data acquisition module can obtain the corresponding analog data streams at the output end of the IP core for different abnormal patterns, such as: pattern 1, normal data stream; pattern 2, data stream with overflow error; pattern 3, data stream with noise. The collected multi-pattern data stream samples are provided as input data to the technical solution for anomaly detection.

[0072] Figure 2It is an exemplary flowchart for obtaining an abnormal pattern according to some embodiments of this specification. The input analog data stream contains noise, and a simulated signal with a length of 1000 samples is generated, which is a sine wave containing two frequency components. Gaussian white noise is added to this signal, and the noise power is 30% of the signal power. A sample of the analog data stream with noise is obtained. Five-layer coiflet wavelet decomposition is performed. In the first layer, a low-frequency approximation coefficient cA1 and a detail coefficient cD1 with a length of 500 are generated. In the second layer, cA1 is decomposed into cA2 and cD2 with lengths of 250 respectively, and so on. In the fifth layer, cA5 and cD5 are obtained. Threshold processing of the high-frequency detail signals. Since the noise is mainly in the high frequency, a hard threshold of 15 is set to filter cD1 to cD5 of the five layers, and the detail coefficients with absolute values lower than 15 are set to 0. The low-frequency approximation signal is retained, and the low-frequency approximation coefficient cA5 of the fifth layer is retained, which contains the denoised main signal. Wavelet inverse transform reconstruction is performed on the coefficients after threshold processing to obtain the denoised signal. The signal that has been denoised using the coiflet wavelet forward transform has a length of 1000. Using the bior1.5 wavelet, the denoised signal is decomposed into five layers to obtain a low-frequency approximation coefficient cA and high-frequency detail coefficients cD. The low-frequency approximation coefficient cA is retained unchanged, which contains the main energy. All the high-frequency detail coefficients cD are set to zero. The inverse transform of the bior1.5 wavelet is performed on the coefficients after the zeroing process. The reconstructed signal after the inverse transform is obtained, and the noise and error are further reduced through the bior wavelet reconstruction, and the denoised and cleaned data is output. Compared with the original signal, the signal-to-noise ratio is increased by 2 dB, ensuring the quality of the reconstructed data.

[0073] Figure 3 It is an exemplary flowchart for obtaining high-dimensional features according to some embodiments of this specification. Denoised signal: an analog signal sequence x[n] with a length of 1000. Select the sliding window length: First, take L = 50, 100, 150, 200 for partitioning, calculate the signal-to-noise ratio (SNR) under each window length, and use Bayesian estimation to determine that the SNR is the highest when L = 200. Time-domain feature extraction: The signal x[n] is partitioned into sliding windows with a length of 200. For example, the first window signal is x1[n], where n = 1,......, 200. Calculate the statistical features of x1[n]: mean u1 = 0.51, variance σ1 = 0.23, kurtosis coefficient γ1 = 1.38. Sliding window sampling is performed, and the signal is sequentially slid and segmented to extract the time-domain features of each window.

[0074] The sliding window signal has segmented the signal x[n] into sliding window signals of length 200. For example, the first window signal is x1[n], where n = 1,......, 200. FFT transformation: Perform a 512-point FFT on x1[n], and use the PN sequence for oversampling to obtain its spectrum X1[k], where k = 1,......, 512. Frequency domain feature extraction: Calculate the power spectrum: P1[k] = |X1[k] 2 , calculate the power spectral density: Calculate the average value of P1[k] in different frequency bands respectively, and calculate the spectral entropy:

[0075] H1 = -∑P1[k]×logP1[k]. Sliding calculation: Repeat the FFT and frequency domain feature extraction for each window signal. Frequency domain feature matrix: Finally, form a matrix containing the frequency domain features of all windows. Sliding window signal, wavelet packet decomposition: Use the orthogonal matching pursuit algorithm, select db5 as the wavelet packet, and perform 3-layer wavelet packet decomposition on x1[n] to obtain multiple packet signals. Feature extraction: Calculate the energy E of each packet signal i . Packet energy ratio: R i = E i / ∑(E i ). Reconstruct the features: According to the decomposition structure, reconstruct each packet ratio R i to obtain the time-frequency features. Sliding calculation: Repeat the time-frequency feature extraction for each window signal. Time-frequency feature matrix: Finally, form the time-frequency feature matrix of all windows.

[0076] Extract time-domain statistical features from the denoised data: A simulated signal sequence of length 1000, which is the result after wavelet denoising. Time-domain statistical feature extraction: Calculate the mean of the signal: 0.51, calculate the variance of the signal: 0.23, calculate the skewness of the signal: -0.03 (close to symmetric distribution), calculate the peak value of the signal: 1.38, calculate the root mean square value of the signal: 0.72. Construct a feature vector: Combine the above statistics into a 5D vector as the time-domain statistical features of the signal sequence: [0.51, 0.23, -0.03, 1.38, 0.72]. Extract frequency-domain features from the denoised data: A simulated signal sequence of length 1000, which has been wavelet denoised. Perform a 1024-point fast Fourier transform (FFT) on the signal. Calculate the main frequency components and their amplitudes of the signal, such as f1 = 10Hz, A1 = 1.5, calculate the absolute mean of the spectrum: 0.32, calculate the standard deviation of the spectrum: 0.11, calculate the skewness of the spectrum: -1.02. Construct a frequency-domain feature vector: [f1, A1, 0.32, 0.11, -1.02]. Extract time-frequency features: A simulated signal sequence of length 1000, which has been wavelet denoised. Use the db5 wavelet basis to perform 3-layer wavelet decomposition on the signal. Calculate the energy ratios of the wavelet coefficients at each layer to reflect time-frequency information. Energy ratio of the first layer: 0.7, energy ratio of the second layer: 0.2, energy ratio of the third layer: 0.1. Construct a time-frequency feature vector: [0.7, 0.2, 0.1]. Construct a high-dimensional feature vector, feature extraction results: Time-domain statistical features: [0.51, 0.23, -0.03, 1.38, 0.72], frequency-domain features: [f1, A1, 0.32, 0.11, -1.02], time-frequency features: [0.7, 0.2, 0.1]. Construct a high-dimensional feature vector: Simply arrange and combine the above three types of features to form a 13D feature vector: [0.51, 0.23, -0.03, 1.38, 0.72, f1, A1, 0.32, 0.11, -1.02, 0.7, 0.2, 0.1]. The high-dimensional vector contains the time-domain, frequency-domain, and time-frequency information of the signal and can comprehensively reflect the characteristics of the signal.

[0077] Figure 4 is an exemplary flowchart of dimensionality reduction processing shown according to some embodiments of this specification. X contains 500 samples, and each sample is a 20D feature vector. The size of X is 500×20. Calculate the distance matrix D: Take two samples x i and x j , both of which are 20D vectors. Their Euclidean distance is: Traverse and calculate the Euclidean distances between pairs of samples in X to form a 500×500 symmetric distance matrix D. x i = [1.1, 2.3, 1.7,......,], xj = [0.5, 3.1, 2.2,......, ], Euclidean distance d ij = 1.23, calculate successively between all samples to obtain the distance matrix D. The Euclidean distance matrix D between pairwise samples has been calculated, with a size of 500×500. Determine the number of K nearest neighbors for each sample. Here, set K = 5. For sample x i : Find the indices of the 5 samples closest to x i in the i-th row of D. These 5 samples are the 5 nearest neighbors of x i . Repeat the above steps to search for the 5 nearest neighbors of each sample. Record the indices of the K nearest neighbors of all samples together to form the K nearest neighbor structure. Index information of 5 nearest neighbors for each sample. K nearest neighbor structure, the index information of 5 nearest neighbors of each high-dimensional sample has been obtained. Laplacian matrix L, L is a 500×500 symmetric matrix. Assignment method: If i and j are connected in the K nearest neighbor structure, then: Lij = 1 / distance d ij (obtained from the distance matrix D), otherwise L ij = 0. Sample 2 and sample 5 are connected in the K nearest neighbor structure, and the distance d_25 = 3.2, then L_25 = 1 / 3.2, L_52 = 1 / 3.2, symmetric matrix, assign values successively to construct the symmetric Laplacian matrix L. Given the Laplacian matrix L, with a size of 500×500, and the distance matrix D, with a size of 500×500. Find the first projection vector y1: The objective function is y1 represents a vector, represents the transpose of the vector, L and D represent matrices, the objective function represents the correlation size between the vector y1 and the matrix, reflecting the representativeness degree of the information contained in the matrix L to the vector y1, and is the energy size of the vector y1 under the subspace defined by the matrix L. The subspace refers to the space composed of the eigenvectors corresponding to the matrix L. Use an optimization algorithm to solve to obtain y1, whose dimension is 500. Repeat the solution: Solve y2, y3...... in the same way until 20 500-dimensional projection vectors are solved. Form the projection matrix: Combine the 20 projection vectors to form the projection matrix M, with a size of 500×20, M is an orthogonal matrix: Normalize y to satisfy M'M = I, output the projection matrix M for subsequent dimensionality reduction calculation. Original high-dimensional matrix: X is a 500×20 high-dimensional feature matrix, projection matrix: The previously constructed LPP projection matrix M, is a 500×5 orthogonal matrix. Dimensionality reduction calculation: Z = M T ×X, here: M T is a 5×500 matrix, X is a 500×13 matrix, so it can be calculated that Z is a 5×20 low-dimensional matrix. Matrix properties: L is a 500×500 positive definite symmetric matrix, M is a 500×5 orthogonal matrix (M T×M = I), Result: Z is the new feature matrix after dimensionality reduction to 5 dimensions, with a size of 5×13.

[0078] Use the Locality Preserved Projections (LPP) algorithm to perform dimensionality reduction on high-dimensional features. High-dimensional features: A 13-dimensional feature matrix containing 500 samples, with each sample being a 13-dimensional vector. The 500 samples, each a 13-dimensional vector, form a 500×13 feature matrix X. Calculate the Euclidean distance between each sample vector in X to construct a similarity graph W of the samples. Construct the LPP transformation matrix M based on graph W, with the matrix size being 13×3. Original feature matrix X: 500 13-dimensional samples, X is 500×13. Similarity graph W: W is a 500×500 symmetric matrix, and W ij represents the similarity between samples i and j. Construct the LPP matrix: Calculate the graph Laplacian matrix L = D - W, where D is a diagonal matrix. Generate a random 13×3 matrix U. Calculate M = argmin_M||X T M|| 2 , with the constraint M T ×L×M = I. By optimizing to solve for M, the dimension is 13×3. Dimensionality reduction calculation: Y = M T ×X, Parameter settings: Neighbor size 5, Heat kernel parameter 1.

[0079] Use the constructed projection matrix for dimensionality reduction. Original feature matrix X: X is a 500×13 matrix containing 500 13-dimensional feature vectors. LPP matrix M: M is obtained through graph construction optimization, with a size of 13×3. Dimensionality reduction calculation: Y = M T ×X, where X is a 500×13 matrix and M T is a 3×13 matrix, so Y = 500×3. The first sample vector in X is: [1.2, 3.4, 5.7,......, ], 13-dimensional, and the first row vector of M T is:

[0080] [0.2, 0.3, 0.1,......, ], 3-dimensional. Then the first sample vector in Y is the inner product of the two, resulting in a 3-dimensional [2.1, 1.5, 0.8]. Result: Obtain a 500×3 feature matrix Y after dimensionality reduction, with each sample reduced from 13 dimensions to 3 dimensions.

[0081] Train an SVM model, using C-SVM, set the penalty parameter C = 1. Gaussian kernel function, set the initial kernel width σ0 = 0.5, adjustment parameters α = 0.8, β = 0.5. For sample x and support vector x i , the kernel function expression is: The low-dimensional feature subset is input into the kernel SVM, and through iterative optimization and solution, an svm model is obtained. The LPP algorithm is used to reduce the dimensionality of the 13-dimensional features of 500 samples to 3 dimensions, resulting in a feature matrix X of 500x3. The SVM package of scikit-learn is used, and the kernel function is set to the RBF kernel. The main parameters include: kernel='rbf', C = 1.0, gamma = 0.1. Using the 3-dimensional feature matrix X as the input, the SVM model is trained. The SVM package internally uses the SMO algorithm for optimization training to solve for the optimal hyperplane parameters. The SVC module will automatically call the SMO sequential minimal optimization algorithm when fitting, and accelerate the solution of the SVM dual problem through iteration. SMO will solve for w and b in the decision function and define the optimal separation hyperplane. After training is completed, the optimized SVC model clf is output, which contains the solved parameters. After training is completed, the optimized SVM classification model is output. The trained SVM model is used to detect abnormal patterns in the test data stream, generating a simulated test signal with a length of 2000, including normal patterns and introduced abnormal patterns. A SVM model with an RBF kernel has been trained with the dimensionality-reduced data before. The test signal sequence is input point by point, and the SVM model is used to determine whether it belongs to the normal pattern or the abnormal pattern. anomalies = [], for i in range(len(test_data)): if svm_predict(test_data[i]) == -1: anomalies.append(i). The anomalies list records the indices of the detected abnormal points.

[0082] The trained RBF kernel SVM model contains information such as support vectors and decision functions. A time series signal of length 2000 is generated as the test stream input. Each sample x[i] in X is detected using the SVM model: x[i] is substituted into the SVM decision function to calculate the classification output y[i]. If y[i] = -1, it is detected as an outlier. The points with subscripts [113, 115, 201, 256] in X are detected as outliers, and their indices are recorded in a list. Finally, an outlier index list is obtained, representing the detection result. Two abnormal patterns in the data stream are detected: [100, 350] and [800, 880]. [100, 350] corresponds to the signal deviation exceeding the limit, and [800, 880] corresponds to the eigenvalue exceeding the limit. If the absolute value of the deviation of the signal from the normal range is greater than 0.2, it is determined as abnormal. If the eigenvalue is greater than 0.8, it is determined as abnormal. If a significant increase in signal fluctuation or an error code is detected, it is also determined as abnormal. The above three types of trigger conditions are combined to form the final comprehensive trigger condition, and the corresponding trigger condition is set according to the abnormal pattern result. Existing trigger conditions: A: The absolute value of the signal deviation is greater than 0.2, B: The eigenvalue is greater than 0.8, C: Signal fluctuation or error code is detected. Logical combination: The trigger conditions are combined using the logical "or" relationship: Trigger condition = A or B or C. Decision rule: If any one of the conditions A, B, or C is satisfied, it is determined as abnormal and an alarm is triggered. The individual trigger conditions are combined through the logical "or" relationship to form the final comprehensive trigger condition.

[0083] The IP core debugging module performs abnormal capture and dynamic debugging on the IP core module according to the generated trigger conditions. The generated trigger condition expression contains three parts: signal deviation, eigenvalue, and status. The already implemented IP core function code is used for signal processing. The trigger condition expression is as follows: if (A or B or C): Trigger an exception, where: A: Signal deviation > 0.2, B: Eigenvalue > 0.8, C: Fluctuation or error is detected. Main functional modules of the IP core code: def signal filtering(): def feature extraction():......, def pattern recognition():...... The code format is written in Python language. Signal filtering, feature extraction, and pattern recognition. Abnormal capture: Insert in the signal filtering function: if signal deviation > 0.2: print("Capture signal deviation abnormality"). Dynamic debugging: Insert in the feature extraction function: print("Current eigenvalue:", calculate eigenvalue), output_status(). Simulation verification: Construct a test input signal with noise or distortion. Run the code and observe whether the printed output meets the expectations. Debugging and optimization: For example, format the printed output to make the log clearer. Add code comments, etc. Output: Obtain the IP core code with debugging statements inserted.

[0084] Figure 5 It is an exemplary flowchart of static analysis shown in some embodiments of this specification. The IP core source code is a Python code for signal filtering and feature extraction, which contains multiple functions. Traverse the code to obtain basic syntax elements such as keywords, variable names, operators, etc. Scan the code to obtain basic syntax elements such as keywords (import, def, return, etc.), variable names (x, y, feat), operators (=), etc. Construct a syntax tree based on the lexical elements and analyze the syntactic relationships. For example, the function bodies of filter and feature_extract are basic blocks. Based on the previous lexical analysis, construct the syntax tree of the code: the function definition is the root node of the tree, the statements in the function body are the child nodes, and the execution logic relationship between the statements is represented as the branches of the tree. While constructing the syntax tree, check the correctness of the syntax. The basic blocks can be directly obtained from the syntax tree: two statements in the filter function body form a basic block, and three statements in the feature_extract function body form a basic block. Each basic block has only one entry and one exit. The statements in the basic block are executed continuously in order. The code contains basic blocks A, B, and C. After A is executed, a judgment condition is made, and according to the judgment result, B or C is executed. Nodes: basic blocks A, B, and C; Edges: A is connected to B, A is connected to C; Condition: the edges connecting A to B / C are marked with the judgment conditions. Nodes: basic blocks A, B, and C; Edges: A is connected to B, A is connected to C; Condition: the edges connecting A to B / C are marked with the judgment conditions. It contains basic blocks A, B, and C, where A is connected to B and C after judgment, and C is then connected back to A to form a loop. Scan the nodes and edges of the control flow graph to find the loop paths with the same start and end points. Use a highlighted or bold style to represent the loop, and add a text annotation next to the loop path to indicate the loop structure. Handle more complex multi-layer nested loop loops. Data flow analysis: basic block A defines variable x, and basic block B uses variable x for operations. Mark the data dependency of x flowing from A to B. In basic block B, if x meets a certain condition, it is determined to be an exception. Correlate the code logic using x in basic block B with the exception pattern. Control flow graph: mark the basic blocks and the execution flow; Data flow graph: mark the data flow between variable definitions and uses; Text report: explain the correspondence between the exception pattern and the code logic. Based on the analysis, give suggestions for code optimization.

Claims

1. A method for debugging an IP core module based on FPGA, comprising: Obtain the data streams generated by different abnormal situations of the IP core module as simulation test cases, and input the data streams into the support vector machine (SVM) model set on the FPGA chip; Using the support vector machine (SVM) model, feature extraction is performed on the input data stream to obtain the feature pattern in the data stream as the abnormal pattern; wherein the abnormal pattern represents the abnormal type of the data stream; According to the acquired abnormal mode, a fault trigger condition corresponding to the abnormal mode is set and acquired, and the fault trigger condition is stored in a storage unit of the FPGA chip; Obtain the state change information of the finite state machine FSM inside the IP core module, set the state trigger conditions under different states according to the state change information, and store the state trigger conditions in the storage unit of the FPGA chip; According to the fault trigger conditions and status trigger conditions stored in the storage unit of the FPGA chip, the input data and output data of the IP core module are monitored. When the fault trigger conditions or status trigger conditions are detected, the IP core module is debugged through the debugging logic circuit set on the FPGA chip to obtain the debugging results; Use the program control flow graph parsing algorithm set on the FPGA chip to perform static analysis on the code of the IP core module and obtain static analysis results; According to the debugging results and static analysis results, the code segments related to the exception in the IP core module are obtained through the association analysis algorithm, and the obtained code segments are marked and modified; The support vector machine (SVM) model is used to extract features from the input data stream and obtain the characteristic patterns in the data stream as abnormal patterns, including: The input data stream is denoised by a double wavelet transform denoising circuit arranged on the FPGA chip to obtain a denoised data stream; According to the denoised data stream, feature values ​​including time domain features, frequency domain features and time-frequency features are extracted, and the extracted feature values ​​are used to form a high-dimensional feature vector; Taking the high-dimensional feature vector as input, the local preservation projection (LPP) algorithm is used to reduce the dimension of the high-dimensional feature vector to obtain the low-dimensional feature vector after dimension reduction. The low-dimensional feature vector is used as input to establish a support vector machine (SVM) model. The low-dimensional feature vector is used as a training sample to train the SVM model. The dual problem of the SVM model is solved by the sequential minimum optimization (SMO) algorithm to obtain the optimal hyperplane parameters of the SVM model. The trained SVM model is used to classify the feature vectors of the data stream, and the abnormal type of the data stream is determined according to the classification result to obtain the abnormal mode of the data stream.

2. The FPGA-based IP core module debugging method according to claim 1, characterized in that: The dual wavelet transform denoising circuit performs dual wavelet transform denoising on the input data stream, including: The dual wavelet transform denoising circuit includes a coiflet wavelet filter and a bior wavelet filter; The coiflet wavelet filter is used to perform forward wavelet transform on the input data stream. The low-frequency coefficients and high-frequency coefficients of the data stream are extracted by multi-level wavelet decomposition of the data stream. The high-frequency coefficients are threshold processed and the high-frequency coefficients less than the threshold are set to zero. The high-frequency coefficients after threshold processing and the low-frequency coefficients are reconstructed by wavelet to obtain the data stream after forward transform. The bior wavelet filter is used to perform multi-level wavelet decomposition on the data stream after forward transformation to extract the low-frequency coefficients and high-frequency coefficients of the data stream after forward transformation; the high-frequency coefficients are subjected to inverse threshold processing, and the high-frequency coefficients greater than the threshold are set to zero to remove the high-frequency details introduced in the forward transformation; the high-frequency coefficients and low-frequency coefficients after inverse threshold processing are subjected to wavelet reconstruction to obtain the denoised data stream output.

3. The FPGA-based IP core module debugging method according to claim 2, characterized in that: Get high-dimensional feature vectors, including: The Bayesian estimation algorithm is used to estimate the statistical characteristics of the denoised data stream, and the optimal sliding window width is solved by maximizing the posterior probability; According to the optimal sliding window width, the sliding average method is used to perform window processing on the data stream, and the mean, variance and kurtosis coefficient of each data window are calculated. The calculated mean, variance and kurtosis coefficient are output as the time domain statistical characteristics of the data stream; The fast Fourier transform algorithm based on the Pinault sequence is used to perform Fourier transform on the denoised data stream, and the power spectrum density and spectrum entropy of the data stream are calculated. The calculated power spectrum density and spectrum entropy are used as the frequency domain feature output of the data stream; The orthogonal matching pursuit algorithm is used to perform adaptive wavelet packet decomposition on the denoised data stream. The projection coefficients of the data stream on different wavelet packet bases are calculated, and the wavelet packet base with the largest projection coefficient is selected as the best matching base to obtain the optimal wavelet packet node of the data stream. The wavelet coefficients of the optimal wavelet packet node are sparsely represented. By setting the sparsity threshold, the wavelet coefficients smaller than the threshold are set to zero to obtain the sparse wavelet coefficients of the data stream. The sparse wavelet coefficients are reconstructed, and the energy distribution and coherence of the wavelet packet nodes at different scales are calculated. The calculated wavelet packet energy spectrum and inter-packet coherence are output as the time-frequency characteristics of the data stream. The obtained mean, variance, kurtosis coefficient, power spectral density, spectral entropy, wavelet packet energy spectrum and inter-packet coherence constitute a high-dimensional feature vector of the data stream.

4. The FPGA-based IP core module debugging method according to claim 3, characterized in that: The high-dimensional feature vector is used as input, and the local preservation projection LPP algorithm is used to reduce the dimension of the high-dimensional feature vector to obtain the low-dimensional feature vector after dimension reduction, including: By calculating the Euclidean distance between any two high-dimensional feature vectors, a distance matrix between high-dimensional feature vectors is constructed; Based on the distance matrix, search for K nearest neighbor vectors for each high-dimensional feature vector to construct the K nearest neighbor structure of the high-dimensional feature vector; Traverse the K nearest neighbor structure of each high-dimensional feature vector. If two high-dimensional feature vectors are each other's K nearest neighbors, fill in 1 in the Laplacian matrix element at the corresponding position, otherwise fill in 0, and construct the Laplacian matrix of the high-dimensional feature vector. The Rayleigh quotient iteration algorithm is used to solve the generalized eigenvalue problem of the Laplace matrix, and the generalized eigenvector corresponding to the minimum non-zero generalized eigenvalue equal to the preset dimensionality reduction amount is obtained. The obtained generalized eigenvector is used as the projection vector of the local preservation projection algorithm to form a projection matrix; The projection matrix is ​​used to project the high-dimensional feature vector to obtain the low-dimensional feature vector after dimensionality reduction.

5. The FPGA-based IP core module debugging method according to claim 4, characterized in that: The Laplace matrix adopts a positive definite matrix; The projection matrix uses an orthogonal matrix.

6. The FPGA-based IP core module debugging method according to any one of claims 1 to 5, characterized in that: The support vector machine SVM model adopts the C-SVM model; The kernel function of the C-SVM model uses the Gaussian kernel function; The expression of Gaussian kernel function is as follows: ; Among them, x and is the sample feature vector input to the kernel function, representing the test sample and support vector in the support vector machine respectively; Represents the test sample x and support vector The Euclidean distance between Represents based on x and Variable kernel width; ; in, is the initial kernel width of the Gaussian kernel function, and its value is predetermined before training; is the kernel width adjustment parameter, which controls the amplitude of kernel width change, and its value range is a positive real number; is the kernel width adjustment parameter, which controls the rate at which the kernel width changes, and its value range is a positive real number.

7. The FPGA-based IP core module debugging method according to claim 6, characterized in that: Use program control flow graph analysis algorithm to perform static analysis on the IP core module code, including: Using lexical analysis and syntax analysis, traverse the source code of the IP core module to obtain the basic blocks in the source code. Each basic block represents a continuous instruction sequence with a single entry and a single exit. Using the control flow construction algorithm, the control flow graph of the IP core module is constructed according to the jump relationship and conditional judgment statements between the basic blocks. The nodes in the control flow graph represent the basic blocks, and the directed edges represent the execution order and conditional judgment relationship between the basic blocks. The loop identification algorithm Tarjan is used to traverse the control flow graph, identify the strongly connected components with the same starting and ending nodes, mark the node sets corresponding to the strongly connected components as loops, obtain the location information of the loops in the source code, and generate an annotated control flow graph with loop information; Using the arrival-set value data flow analysis algorithm, traverse each path on the annotated control flow graph, and obtain the operation logic of the IP core module based on the semantic information of the instructions and the definition-usage relationship of the variables; the operation logic includes the execution order of instructions, the transmission and calculation order of data; Using a pattern matching algorithm, we search for code snippets that match the exception pattern in the operating logic of the IP core module, and establish an association between the operating logic and the code corresponding to the exception pattern. The association is used for fault diagnosis at the source code level.

8. The FPGA-based IP core module debugging method according to claim 7, characterized in that: According to the acquired abnormal mode, set the fault trigger conditions, including: According to the type of abnormal pattern, it is divided into characteristic value exceeding limit abnormality and signal deviation exceeding limit abnormality; among them, characteristic value exceeding limit abnormality indicates that the characteristic parameter value in the data stream of the IP core module exceeds the preset safety threshold range, and the signal deviation exceeding limit abnormality indicates that the deviation of the signal amplitude in the data stream relative to the nominal value exceeds the preset maximum allowable deviation. For feature value exceeding limit exceptions, extract the feature parameter name and upper and lower limits of the safety threshold that caused the exception from the exception pattern, and construct the feature value exceeding limit triggering condition; For the signal deviation exceeding the limit exception, the signal name, nominal value and maximum allowable deviation that caused the exception are extracted from the exception pattern, and the signal deviation exceeding the limit trigger condition is constructed; The constructed characteristic value exceeding limit trigger condition and signal deviation exceeding limit trigger condition are logically combined to form the final fault trigger condition.

9. The FPGA-based IP core module debugging method according to claim 8, characterized in that: The status trigger conditions include signal fluctuation trigger conditions and error code trigger conditions.

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