Semiconductor chip packaging structure and packaging method

Abstract

The present invention discloses a semiconductor chip packaging structure and packaging method, and relates to the field of semiconductor chip packaging technology. A semiconductor chip packaging structure includes: a chip and a substrate, the substrate includes: a chip mounting area, the chip is arranged in the chip mounting area; a non-mounting area; a cavity, including a first cavity and a second cavity, the first cavity is arranged between the chip mounting area and the non-mounting area to separate or partially separate the chip mounting area and the non-mounting area, the second cavity is arranged between the bottom of the chip mounting area and the bottom surface of the substrate; a buffer part, the buffer part is filled in the first cavity and the second cavity. The dual cavity design of the first cavity and the second cavity effectively reduces the mechanical stress transmission of the chip at the bottom and side of the chip mounting area, especially under the action of vibration and impact, reduces the risk of damage to the fragile parts of the connecting device, and ensures the mechanical stability of the components.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a semiconductor chip packaging structure and a packaging method. Background Art

[0002] With the continuous development of semiconductor technology, chip packaging technology has occupied an important position in integrated circuit manufacturing. The design of chip packaging structure not only affects the physical protection effect of the chip, but also directly affects the performance, life and reliability of the chip. However, in practical applications, the chip will be affected by various interferences from the external environment, and vibration is one of the significant factors.

[0003] The impact of vibration on the chip is mainly manifested in the following aspects:

[0004] 1. Performance impact: Vibration can cause changes in the internal structure of the chip, resulting in displacement or deformation of sensitive components, which can cause deformation or distortion of the chip's output waveform, or even direct physical damage to the chip in extreme cases. This situation seriously affects the chip's electrical performance and reduces its working efficiency and reliability.

[0005] 2. Impact on life: Long-term vibration will cause stress concentration inside the chip, resulting in the generation and expansion of microcracks, which will further cause chip failure. At the same time, vibration will also aggravate the oxidation problem inside the chip, accelerate the aging of materials, and cause the stability of the chip's electrical performance to decrease, thereby shortening the chip's service life.

[0006] 3. Impact on reliability: Vibration can damage various connectors and components of the chip, especially fragile areas such as solder joints and leads, which may cause breakage or loosening, directly leading to failure of hardware functions and thus reducing the reliability of the entire chip. Summary of the invention

[0007] The technical problem to be solved by the present invention is to overcome the problem in the prior art that the semiconductor chip packaging structure is easily affected by vibration and interference, and to provide a semiconductor chip packaging structure and a packaging method.

[0008] The present invention solves the above technical problems through the following technical solutions:

[0009] A semiconductor chip packaging structure includes a chip and a substrate, wherein the substrate includes:

[0010] A chip mounting area, wherein the chip is arranged in the chip mounting area;

[0011] Non-installation area;

[0012] A cavity, comprising a first cavity and a second cavity, wherein the first cavity is disposed between the chip mounting area and the non-mounting area to separate or partially separate the chip mounting area and the non-mounting area, and the second cavity is disposed at the bottom of the chip mounting area;

[0013] A buffer portion, the buffer portion comprising:

[0014] A first buffer portion, the topmost end of the first cavity is filled with the first buffer portion, the first buffer portion is used to absorb vibration energy and bond the chip mounting area and the non-mounting area;

[0015] The second buffer portion is arranged below the first buffer portion in the first cavity and in the second cavity.

[0016] In this solution, the chip installation area is partially isolated from the non-installation area by setting the first cavity, reducing the way external vibration is directly transmitted to the chip installation area. The buffer part is filled in the cavity, which can effectively absorb and dissipate vibration energy, reduce the structural stress and displacement of the chip caused by vibration, avoid deformation or distortion of the output waveform, and ensure the stability of the electrical performance of the chip. The dual-cavity design of the first cavity and the second cavity effectively reduces the mechanical stress transmission of the chip at the bottom and sides of the chip installation area, especially under the action of vibration and impact, reduces the risk of damage to fragile parts such as chip solder joints, and ensures the mechanical stability of the chip. The buffer part in the present invention is arranged in the substrate, not directly around the chip, and will not affect the heat dissipation performance of the chip. The first buffer part is filled in the top of the first cavity. While playing a buffering role, it can also play a bonding role and provide structural support.

[0017] Preferably, the viscosity of the first buffer portion is greater than that of the second buffer portion, and the buffering performance of the second buffer portion is greater than that of the first buffer portion.

[0018] Preferably, the semiconductor chip packaging structure further includes a honeycomb structure, which is disposed in the first cavity to connect the chip mounting area and the non-mounting area, and the honeycomb structure is filled with the first buffer portion.

[0019] In this solution, the first buffer part has high viscosity and is mainly used to bond the chip mounting area and the non-mounting area, while absorbing part of the vibration energy. Its high viscosity ensures a firm connection between the chip mounting area and the non-mounting area, provides effective mechanical support and stability, and avoids connection failure due to vibration or thermal expansion. The second buffer part has better buffering performance and is mainly used to fill the first cavity and the second cavity to provide better vibration absorption effect. Its superior buffering performance ensures effective attenuation of external vibration energy, reduces the impact of vibration on the chip, and improves the vibration resistance of the overall packaging structure.

[0020] Preferably, the material of the first buffer part is any one of high temperature epoxy resin, polyimide adhesive or high temperature silicone resin, and the material of the second buffer part is any one of silicone rubber, fluororubber or polyimide foam.

[0021] Preferably, the first cavity and the second cavity are communicated.

[0022] A semiconductor chip packaging method, the method comprising:

[0023] Providing a substrate, the substrate comprising a chip mounting area, a non-mounting area and a circuit layer;

[0024] Performing a subtractive process on the back side at the transition between the chip mounting area and the non-mounting area to form a groove to form a first cavity;

[0025] Performing a subtractive process on the back side of the chip mounting area to form a second cavity;

[0026] Filling the first cavity and the second cavity with a second buffer material;

[0027] performing an additive process on the back side of the substrate to close the first cavity and the second cavity;

[0028] A chip is mounted on the chip mounting area.

[0029] In this solution, the packaging method accurately forms the first cavity and the second cavity by rationally using subtractive and additive processes, and fills them with high-performance buffer materials, thereby ensuring the stability, reliability and long life of the semiconductor chip in a high-vibration environment.

[0030] Preferably, the step of performing a subtractive process on the back side at the transition between the chip mounting area and the non-mounting area to form a groove to form the first cavity specifically includes:

[0031] The circuit layer at the transition is retained, and the structure at the bottom of the circuit layer is completely removed to form a groove;

[0032] The chip mounting area and the non-mounting area are bonded at the top of the groove using a first buffer material.

[0033] Preferably, the step of performing a subtractive process on the back side at the transition between the chip mounting area and the non-mounting area to form a groove to form the first cavity specifically includes:

[0034] retaining the circuit layer at the transition, removing a first portion of the structure at the bottom of the circuit layer, and retaining a second portion;

[0035] Filling the top of the first portion with a first buffer material to bond the chip mounting area and the non-mounting area;

[0036] removing the second portion;

[0037] The top end of the second portion is filled with a first cushioning material.

[0038] In this solution, the retained structure of the first part plays a temporary supporting role, ensuring the accuracy and stability of subsequent process operations, thereby reducing the risk of structural deformation caused by the subtractive process. This method of subtracting materials in steps, retaining part of the structure and gradually filling the first buffer material ensures that there is no deviation between the chip mounting area and the non-mounting area during the formation of the first cavity.

[0039] Preferably, the step of performing a subtractive process on the back side at the transition between the chip mounting area and the non-mounting area to form a groove to form the first cavity specifically includes:

[0040] The circuit layer at the transition is retained, a part of the structure at the bottom of the circuit layer is retained to form a honeycomb structure, and the rest is removed;

[0041] The honeycomb structure is filled with a first buffer material.

[0042] Preferably, the first buffer material is any one of high temperature epoxy resin, polyimide adhesive or high temperature silicone resin, and the second buffer material is any one of silicone rubber, fluororubber or polyimide foam. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a cross-sectional schematic diagram of a semiconductor chip packaging structure according to Embodiment 1 of the present invention;

[0044] Figure 2 It is a schematic diagram of the upper part of the semiconductor chip packaging structure according to Embodiment 1 of the present invention;

[0045] Figure 3 It is a schematic diagram of the upper part of the semiconductor chip packaging structure according to the second embodiment of the present invention;

[0046] Figure 4 This is a first schematic diagram of step S20 of the semiconductor chip packaging method according to Embodiment 3 of the present invention;

[0047] Figure 5 This is a second schematic diagram of step S20 of the semiconductor chip packaging method according to Embodiment 3 of the present invention;

[0048] Figure 6 is a schematic diagram of step S30 of the semiconductor chip packaging method according to embodiment 3 of the present invention;

[0049] Figure 7 is a schematic diagram of step S40 of the semiconductor chip packaging method according to embodiment 3 of the present invention;

[0050] Figure 8 is a schematic diagram of step S50 of the semiconductor chip packaging method according to embodiment 3 of the present invention;

[0051] Fig. 9 FIG. 4 is a schematic diagram of step S20 of the semiconductor chip packaging method according to the fourth embodiment of the present invention.

[0052] Description of reference numerals:

[0053] Chip 100 , substrate 200 , chip mounting area 210 , transition 215 , non-mounting area 220 , first cavity 230 , second portion 232 , honeycomb structure 235 , second cavity 240 , first buffer portion 251 , second buffer portion 252 , first buffer material 253 , second buffer material 254 . DETAILED DESCRIPTION

[0054] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.

[0055] Example 1

[0056] like Figure 1 and Figure 2 As shown, this embodiment provides a semiconductor chip packaging structure, which includes a chip 100 and a substrate 200, wherein the substrate 200 includes a chip mounting area 210, a non-mounting area 220, a cavity and a buffer portion. The chip 100 is arranged in the chip mounting area 210. The cavity includes a first cavity 230 and a second cavity 240, wherein the first cavity 230 is arranged between the chip mounting area 210 and the non-mounting area 220 to separate or partially separate the chip mounting area 210 and the non-mounting area 220, and the second cavity is arranged at the bottom of the chip mounting area 210 to separate the chip 100 from the substrate 200. The buffer portion is filled in the first cavity 230 and the second cavity 240. Among them, the substrate 200 is a PCB circuit board. The chip 100 is a flip chip.

[0057] By setting the first cavity 230, the chip mounting area 210 is isolated from the non-mounting area 220, reducing the way in which external vibration is directly transmitted to the chip mounting area 210. The buffer portion is filled in the cavity, which can effectively absorb and dissipate vibration energy, reduce the structural stress and displacement of the chip caused by vibration, avoid deformation or distortion of the output waveform, and ensure the stability of the electrical performance of the chip. The dual-cavity design of the first cavity 230 and the second cavity 240 effectively reduces the mechanical stress transmission of the chip 100 at the bottom and side of the chip mounting area 210, especially under the action of vibration and impact, reduces the risk of damage to fragile parts such as the solder joints of the chip 100, and ensures the mechanical stability of the chip 100. In addition, the buffer portion in the present invention is arranged in the substrate 200, not directly arranged around the chip 100, and will not affect the heat dissipation performance of the chip 100.

[0058] Specifically, the buffer portion includes a first buffer portion 251 and a second buffer portion 252. The top of the first cavity 230 is filled with the first buffer portion 251, and the first buffer portion 251 is used to absorb vibration energy and bond the chip mounting area 210 and the non-mounting area 220. The second buffer portion 252 is arranged below the first buffer portion 251 in the first cavity 230 and in the second cavity 240. The first buffer portion 251 is filled at the top of the first cavity 230, and can play a bonding role while playing a buffering role, providing structural support.

[0059] Among them, the viscosity of the first buffer part 251 is greater than that of the second buffer part 252, and the buffering performance of the second buffer part 252 is greater than that of the first buffer part 251. The first buffer part 251 has a higher viscosity and is mainly used to bond the chip mounting area 210 and the non-mounting area 220, while absorbing part of the vibration energy. Its higher viscosity ensures a firm connection between the chip mounting area 210 and the non-mounting area 220, provides effective mechanical support and stability, and avoids connection failure caused by vibration or thermal expansion. The second buffer part 252 has better buffering performance and is mainly used to fill the first cavity 230 and the second cavity 240 to provide a better vibration absorption effect. The superiority of its buffering performance ensures the effective attenuation of external vibration energy, reduces the impact of vibration on the chip, and improves the vibration resistance of the overall packaging structure.

[0060] In this embodiment, the first cavity 230 and the second cavity 240 are connected, which is conducive to forming an all-round package and further improving the cushioning performance.

[0061] In this embodiment, the material of the first buffer portion 251 is any one of high temperature epoxy resin, polyimide adhesive or high temperature silicone resin, and the material of the second buffer portion 252 is any one of silicone rubber, fluororubber or polyimide foam.

[0062] Example 2

[0063] The solution of this embodiment is basically the same as that of embodiment 1, except that, in this embodiment, Figure 3 As shown, the semiconductor chip packaging structure also includes a honeycomb structure 235, which is arranged in the first cavity 230 to connect the chip mounting area 210 and the non-mounting area 220, and the honeycomb structure 235 is filled with a first buffer. The honeycomb structure 235 is arranged in the first cavity 230 to connect the chip mounting area 210 and the non-mounting area 220. The honeycomb structure 235 itself has high rigidity and good mechanical properties, and can effectively disperse and conduct vibration stress from the outside. Due to its geometric shape, the honeycomb structure 235 reduces the stress transfer between the non-mounting area 220 and the chip mounting area 210 while providing strong structural support, avoiding chip performance distortion caused by vibration. In addition, the honeycomb structure 235 is filled with a buffer to form a composite structure, which can further absorb vibration energy. Combined with the rigidity of the honeycomb structure 235, while providing support, it can achieve multiple absorption and attenuation of vibration energy and protect the chip from vibration damage.

[0064] in Figure 3 The honeycomb structure 235 is not shown in its entirety, and is only used as an example. The honeycomb structure 235 is at least disposed on a contact surface between the chip mounting area 210 and the non-mounting area 220 .

[0065] Example 3

[0066] like Figure 4-Figure 8 As shown, this embodiment provides a semiconductor chip packaging method for manufacturing a semiconductor chip packaging structure as in Embodiment 1, the method comprising:

[0067] S10, providing a substrate 200, the substrate 200 including a chip mounting area 210, a non-mounting area 220 and a circuit layer (not shown in the figure);

[0068] like Figure 4 and Figure 5 As shown, S20, a groove is formed by a subtractive process on the back side of the transition 215 between the chip mounting area 210 and the non-mounting area 220 to form a first cavity 230;

[0069] like Figure 6 As shown, S30, performing a subtractive process on the back side of the chip mounting area 210 to form a second cavity 240;

[0070] like Figure 7 As shown, S40, filling the first cavity 230 and the second cavity 240 with a second buffer material 254;

[0071] like Figure 8As shown, S50, performing an additive process on the back side of the substrate 200 to close the first cavity 230 and the second cavity 240;

[0072] S60 , mounting the chip on the chip mounting area 210 .

[0073] The packaging method accurately forms the first cavity 230 and the second cavity 240 by rationally using subtractive and additive processes, and fills them with high-performance buffer materials, thereby ensuring the stability, reliability and long life of the semiconductor chip in a high-vibration environment.

[0074] like Figure 4 and Figure 5 As shown, step S20 specifically includes:

[0075] S21, retaining the circuit layer at the transition portion 215, and completely removing the structure at the bottom of the circuit layer to form a groove.

[0076] S22 , using the first buffer material 253 to bond the chip mounting area 210 and the non-mounting area 220 at the top of the groove.

[0077] The first buffer material 253 is any one of high temperature epoxy resin, polyimide adhesive or high temperature silicone resin, and the second buffer material 254 is any one of silicone rubber, fluororubber or polyimide foam.

[0078] Example 4

[0079] like Fig. 9 As shown, the semiconductor chip packaging method provided in this embodiment is basically the same as the method of embodiment 3, except that step S20 specifically includes:

[0080] like Fig. 9 As shown in A in FIG. 2 , S23 , retain the circuit layer at the transition point 215 , remove the first part of the structure at the bottom of the circuit layer, and retain the second part 232 ;

[0081] like Fig. 9 As shown in B, S24, fill the first portion with a first buffer material 253 to bond the chip mounting area 210 and the non-mounting area 220;

[0082] like Fig. 9 As shown in C, S25, removing the second portion 232;

[0083] like Fig. 9 As shown in D in FIG. 5 , S26 , fill the second portion 232 with the first buffer material 253 .

[0084] In this solution, the retained structure of the first part plays a temporary supporting role, ensuring the accuracy and stability of subsequent process operations, thereby reducing the risk of structural deformation caused by the subtractive process. This method of subtracting materials in steps, retaining part of the structure and gradually filling the first buffer material 253 ensures that there is no deviation between the chip mounting area 210 and the non-mounting area 220 during the formation of the first cavity 230.

[0085] Example 5

[0086] The semiconductor chip packaging method provided in this embodiment is used to prepare the semiconductor chip packaging structure in Embodiment 2. The semiconductor chip packaging method provided in this embodiment is basically the same as the method in Embodiment 3, except that step S20 specifically includes:

[0087] S28, retaining the circuit layer at the transition point, retaining a portion of the structure at the bottom of the circuit layer to form a honeycomb structure, and removing the rest.

[0088] S29, filling the honeycomb structure with a first buffer material.

[0089] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. A semiconductor chip packaging structure, characterized in that: It includes a chip, a honeycomb structure and a substrate, wherein the substrate includes: A chip mounting area, wherein the chip is arranged in the chip mounting area; Non-installation area; A cavity, comprising a first cavity and a second cavity, wherein the first cavity is disposed between the chip mounting area and the non-mounting area to separate or partially separate the chip mounting area and the non-mounting area, and the second cavity is disposed at the bottom of the chip mounting area; A buffer portion, comprising a first buffer portion and a second buffer portion, wherein the top of the first cavity is filled with the first buffer portion, the first buffer portion is used to absorb vibration energy and bond the chip mounting area and the non-mounting area, and the second buffer portion is disposed below the first buffer portion in the first cavity and in the second cavity; The honeycomb structure is disposed in the first cavity to connect the chip mounting area and the non-mounting area, and the honeycomb structure is filled with the first buffer portion.

2. The semiconductor chip packaging structure according to claim 1, characterized in that: The viscosity of the first buffer portion is greater than that of the second buffer portion, and the buffering performance of the second buffer portion is greater than that of the first buffer portion.

3. The semiconductor chip packaging structure according to claim 1 or 2, characterized in that: The material of the first buffer part is any one of high temperature epoxy resin, polyimide adhesive or high temperature silicone resin, and the material of the second buffer part is any one of silicone rubber, fluororubber or polyimide foam.

4. The semiconductor chip packaging structure according to claim 1 or 2, characterized in that: The first cavity is communicated with the second cavity.

5. A semiconductor chip packaging method, characterized in that: For preparing the semiconductor chip packaging structure according to any one of claims 1 to 4, the method comprises: Providing a substrate, the substrate comprising a chip mounting area, a non-mounting area and a circuit layer; Performing a subtractive process on the back side at the transition between the chip mounting area and the non-mounting area to form a groove to form a first cavity; Performing a subtractive process on the back side of the chip mounting area to form a second cavity; Filling the first cavity and the second cavity with a second buffer material; performing an additive process on the back side of the substrate to close the first cavity and the second cavity; A chip is mounted on the chip mounting area.

6. The semiconductor chip packaging method according to claim 5, characterized in that: The step of performing a subtractive process on the back side at the transition between the chip mounting area and the non-mounting area to form a groove to form a first cavity specifically includes: The circuit layer at the transition is retained, and the structure at the bottom of the circuit layer is completely removed to form a groove; The chip mounting area and the non-mounting area are bonded at the top of the groove using a first buffer material.

7. The semiconductor chip packaging method according to claim 5, characterized in that: The step of performing a subtractive process on the back side at the transition between the chip mounting area and the non-mounting area to form a groove to form a first cavity specifically includes: retaining the circuit layer at the transition, removing a first portion of the structure at the bottom of the circuit layer, and retaining a second portion; filling the first portion with a first buffer material to bond the chip mounting area and the non-mounting area; removing the second portion; The second portion is filled with a first cushioning material.

8. The semiconductor chip packaging method according to claim 5, characterized in that: The step of performing a subtractive process on the back side at the transition between the chip mounting area and the non-mounting area to form a groove to form a first cavity specifically includes: The circuit layer at the transition is retained, a part of the structure at the bottom of the circuit layer is retained to form a honeycomb structure, and the rest is removed; The honeycomb structure is filled with a first buffer material.

9. The semiconductor chip packaging method according to any one of claims 6 to 8, characterized in that: The first buffer material is any one of high temperature epoxy resin, polyimide adhesive or high temperature silicone resin, and the second buffer material is any one of silicone rubber, fluororubber or polyimide foam.

Images