Semiconductor packaging structure

Abstract

The present invention provides a semiconductor packaging structure, comprising: a housing, including a substrate; a first semiconductor chip, connected to the substrate; a first metal connection portion, connected between the substrate and the first semiconductor chip and electrically connected to the first pole of the first semiconductor chip; a second metal connection portion, spaced apart from the first metal connection portion, connected to the substrate and electrically connected to the second pole of the first semiconductor chip; a first terminal, electrically connected to the first metal connection portion; a second terminal, electrically connected to the second metal connection portion; a first insulating bump, arranged on the substrate and arranged between the first metal connection portion and the second metal connection portion. The technical solution of the present application can effectively solve the problem of poor heat dissipation effect of semiconductor chips in the related art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure. Background Art

[0002] With the continuous development of science and technology, the application scope of power semiconductor devices is becoming wider and wider. For example, power semiconductor devices can be used as rectifiers, oscillators, light emitters, amplifiers or photometers in the fields of radio frequency, microwave and optical semiconductor products. In this field, power semiconductor devices usually include a shell and a semiconductor chip encapsulated in the shell. Usually, the shell is made of polymer insulating material, and the semiconductor chip is connected to the inner surface of the shell through a lining plate with copper on both sides. The setting of the lining plate and the connecting layer between the lining plate and the shell increase the thermal resistance of the heat dissipation path from the semiconductor chip to the shell, which is not conducive to the heat dissipation of the semiconductor chip. Summary of the invention

[0003] The main purpose of the present invention is to provide a semiconductor packaging structure to solve the problem of poor heat dissipation effect of semiconductor chips in the related art.

[0004] In order to achieve the above-mentioned purpose, the present invention provides a semiconductor packaging structure, including: a shell, including a substrate; a first semiconductor chip, connected to the substrate; a first metal connection part, connected between the substrate and the first semiconductor chip and electrically connected to the first pole of the first semiconductor chip; a second metal connection part, spaced apart from the first metal connection part, the second metal connection part is connected to the substrate and electrically connected to the second pole of the first semiconductor chip; a first terminal, electrically connected to the first metal connection part; a second terminal, electrically connected to the second metal connection part; a first insulating bump, arranged on the substrate and arranged between the first metal connection part and the second metal connection part.

[0005] Furthermore, the shell also includes a surrounding plate connected to the substrate, the first metal connecting part and the second metal connecting part are arranged at intervals along a first preset direction, the first insulating protrusion extends along a second preset direction, and the two ends of the first insulating protrusion are respectively connected to two opposite inner surfaces of the surrounding plate, wherein the second preset direction is arranged at an angle to the first preset direction.

[0006] Furthermore, the semiconductor packaging structure also includes a third metal connection part and a third terminal. The third metal connection part is spaced apart from the second metal connection part, and the third metal connection part and the second metal connection part are located on the same side of the first insulating bump. The third metal connection part is electrically connected to the third pole of the first semiconductor chip, and the third terminal is connected to the third metal connection part.

[0007] Furthermore, the shell also includes a panel connected to the substrate, the panel is provided with a first through hole, the first terminal passes through the first through hole, and the semiconductor packaging structure also includes a first insulating panel, the first insulating panel is connected to the outer surface of the panel and is arranged around the first through hole.

[0008] Furthermore, the first terminal is a long plate-like structure, comprising a first plate segment and a second plate segment arranged at an angle, the first plate segment being connected to the first metal connecting portion, the second plate segment passing through the first through hole, and the first plate segment being arranged to block the first through hole.

[0009] Furthermore, the shell also includes a cover plate connected to the enclosure, the first through hole connects the end surface of the enclosure close to the cover plate, the first insulating enclosure includes a first enclosure section and a second enclosure section connected to each other, the first enclosure section is connected to the enclosure, and the second enclosure section is connected to the cover plate.

[0010] Furthermore, a positioning groove for accommodating the second plate segment is arranged on the inner surface of the cover plate, and the positioning groove is arranged corresponding to the second enclosure plate segment.

[0011] Furthermore, the semiconductor package structure further includes an insulating protrusion disposed on the inner surface of the enclosure, and the insulating protrusion is located between the first terminal and the second terminal.

[0012] Furthermore, the semiconductor packaging structure also includes a second semiconductor chip and a second insulating bump, the first insulating bump and the second insulating bump are arranged at intervals, the first semiconductor chip is located on the side of the first insulating bump away from the second insulating bump, the second semiconductor chip is located on the side of the second insulating bump away from the first insulating bump, the second metal connecting part is located between the first insulating bump and the second insulating bump, and the second pole of the second semiconductor chip is electrically connected to the second metal connecting part.

[0013] Furthermore, the semiconductor packaging structure also includes a fourth metal connection part, a fifth metal connection part, a fourth terminal and a fifth terminal located between the first insulating bump and the second insulating bump, the fourth metal connection part and the fifth metal connection part are located on both sides of the second metal connection part, the fourth metal connection part is electrically connected to the third pole of the first semiconductor chip, the fifth metal connection part is electrically connected to the third pole of the second semiconductor chip, the fourth terminal is electrically connected to the fourth metal connection part, and the fifth terminal is electrically connected to the fifth metal connection part.

[0014] Furthermore, the semiconductor packaging structure also includes a sixth metal connection portion and a sixth terminal located on a side of the second insulating bump away from the first insulating bump, the shell also includes a cover plate and a surrounding plate, the surrounding plate is arranged between the cover plate and the substrate, the sixth metal connection portion is electrically connected to the first pole of the second semiconductor chip, one end of the sixth terminal is electrically connected to the sixth metal connection portion, and the other end of the sixth terminal extends to the outside of the inner cavity, the surrounding plate includes a first side plate and a second side plate arranged opposite to or adjacent to each other, the first terminal passes through the first side plate, the sixth terminal passes through the second side plate, and the second terminal, the fourth terminal and the fifth terminal pass through the cover plate.

[0015] Furthermore, the base plate and the enclosure plate are an integrated structure; and / or the cover plate and the enclosure plate are connected by fasteners.

[0016] Furthermore, an arc-shaped chamfered portion is provided between the substrate and the enclosure; and / or, the first metal connection portion and the second metal connection portion are both plate-shaped structures and are made of copper; and / or, the shell is made of ceramic.

[0017] Further, the height of the first insulating protrusion is between 0-3 mm; and / or the width of the first insulating protrusion is between 0-2 mm.

[0018] Furthermore, the semiconductor packaging structure also includes a metal connector, which is connected between the second pole and the second metal connection part of the first semiconductor chip, wherein the metal connector is a bonding wire, and at least part of the bonding wire is located above the first insulating bump; or, the metal connector is a metal strip, and an avoidance hole is provided on the first insulating bump, and the metal strip is inserted into the avoidance hole.

[0019] According to the technical solution of the present invention, the shell includes a substrate, and the shell provides an installation basis for various components of the semiconductor packaging structure. The first pole and the second pole of the first semiconductor chip are located on both sides of the first semiconductor chip. The first metal connecting part is connected to the substrate and electrically connected to the first pole of the first semiconductor chip. The second metal connecting part is connected to the substrate and electrically connected to the second pole of the first semiconductor chip. The first semiconductor chip is connected to the substrate through the first metal connecting part; the second metal connecting part is spaced apart from the first metal connecting part, and the first terminal is electrically connected to the first metal connecting part and the second terminal is electrically connected to the second metal connecting part, so that the first semiconductor chip can be electrically connected to an external device and can form an electrical circuit, thereby realizing the basic function of the first semiconductor chip. The first insulating bump is arranged between the first metal connecting part and the second metal connecting part, so that the first metal connecting part and the second metal connecting part are electrically connected to each other. The surface distance between the two metal connecting parts includes the part on the outer surface of the first insulating protrusion in addition to the part on the substrate, so that the surface distance between the first metal connecting part and the second metal connecting part can be increased, thereby enhancing the insulation performance of the semiconductor packaging structure, and providing guarantee for the realization of the basic functions of the first semiconductor chip; the first semiconductor chip is directly connected to the substrate through the first metal connecting part, that is, the first semiconductor chip is directly connected to the shell through the first metal connecting part. Compared with the scheme of connecting the shell and the first semiconductor chip through the lining plate and the connecting part between the lining plate and the shell in the related art, this embodiment simplifies the heat dissipation path between the first semiconductor chip and the shell, reduces the thermal resistance on the heat dissipation path, so that the heat generated by the first semiconductor chip during operation can be better transferred to the shell, which is more conducive to the heat dissipation of the first semiconductor chip. Therefore, the technical solution of the present application can effectively solve the problem of poor heat dissipation effect of the first semiconductor chip in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0021] Figure 1 A schematic diagram of a three-dimensional structure of a first embodiment of a semiconductor packaging structure according to the present invention is shown;

[0022] Figure 2 Shows Figure 1 A three-dimensional structural schematic diagram of a partial structure of a semiconductor packaging structure;

[0023] Figure 3 Shows Figure 2 A schematic top view of a semiconductor packaging structure;

[0024] Figure 4A schematic diagram of a three-dimensional structure of a second embodiment of a semiconductor package structure according to the present invention is shown;

[0025] Figure 5 Shows Figure 4 A schematic diagram of the split structure of a semiconductor packaging structure;

[0026] Figure 6 Shows Figure 4 A schematic diagram of a split structure of a semiconductor package structure from another angle;

[0027] Figure 7 A schematic diagram showing a three-dimensional structure of a first terminal of another embodiment of a semiconductor package structure according to the present invention;

[0028] Figure 8 A schematic diagram of a three-dimensional structure of a third embodiment of a semiconductor package structure according to the present invention is shown;

[0029] Fig. 9 Shows Figure 4 A three-dimensional structural schematic diagram of a partial structure of a semiconductor packaging structure;

[0030] Fig.10 Shows Figure 5 A schematic top view of a semiconductor packaging structure.

[0031] The above drawings include the following reference numerals:

[0032] a. a first preset direction; b. a second preset direction;

[0033] 10. Shell; 11. Cover plate; 110. Positioning groove; 12. Base plate; 13. Enclosure; 131. First side plate; 132. Second side plate; 14. Inner cavity; 15. First insulating enclosure; 151. First enclosure section; 152. Second enclosure section; 16. Insulating protrusion; 17. First positioning structure; 171. First mounting groove; 172. Mounting block; 18. Second positioning structure; 181. Second mounting groove;

[0034] 20. a first semiconductor chip;

[0035] 31. first metal connection portion; 32. first terminal; 321. first plate segment; 322. second plate segment; 323. first step surface; 324. second step surface;

[0036] 41. a second metal connection portion; 42. a second terminal;

[0037] 51. a first insulating protrusion; 52. a second insulating protrusion;

[0038] 61. a third metal connection portion; 62. a third terminal;

[0039] 70. A second semiconductor chip;

[0040] 81. a fourth metal connection portion; 82. a fourth terminal;

[0041] 91. a fifth metal connection portion; 92. a fifth terminal;

[0042] 101. sixth metal connection portion; 102. sixth terminal;

[0043] 111. Arc chamfered portion; 112. Metal connecting piece. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0046] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0047] like Figures 1 to 3As shown, the present application provides a semiconductor packaging structure. The first embodiment of the semiconductor packaging structure of the present application includes: a shell 10, a first semiconductor chip 20, a first metal connection part 31, a second metal connection part 41, a first terminal 32, a second terminal 42, and a first insulating bump 51; the shell 10 includes a substrate 12; the first semiconductor chip 20 is connected to the substrate 12; the first metal connection part 31 is connected between the substrate 12 and the first semiconductor chip 20 and is electrically connected to the first pole of the first semiconductor chip 20; the second metal connection part 41 is spaced apart from the first metal connection part 31, the second metal connection part 41 is connected to the substrate 12 and is electrically connected to the second pole of the first semiconductor chip 20; the first terminal 32 is electrically connected to the first metal connection part 31; the second terminal 42 is electrically connected to the second metal connection part 41; the first insulating bump 51 is arranged on the substrate 12 and arranged between the first metal connection part 31 and the second metal connection part 41.

[0048] The technical solution of this embodiment is applied, the shell 10 includes a substrate 12, and the shell 10 provides an installation basis for various components of the semiconductor packaging structure. The first pole and the second pole of the first semiconductor chip 20 are located on both sides of the first semiconductor chip 20, the first metal connection part 31 is connected to the substrate 12 and electrically connected to the first pole of the first semiconductor chip 20, the second metal connection part 41 is connected to the substrate 12 and electrically connected to the second pole of the first semiconductor chip 20, and the first semiconductor chip 20 is connected to the substrate 12 through the first metal connection part 31; the second metal connection part 41 is arranged at a distance from the first metal connection part 31, and then the first terminal 32 is electrically connected to the first metal connection part 31 and the second terminal 42 is electrically connected to the second metal connection part 41, so that the first semiconductor chip 20 can be electrically connected to an external device and can form an electrical circuit, thereby realizing the basic function of the first semiconductor chip 20, and the first insulating bump 51 is arranged between the first metal connection part 31 and the second metal connection part 41. The surface distance between the first metal connection part 31 and the second metal connection part 41 includes the part on the outer surface of the first insulating bump 51 in addition to the part on the substrate 12, so that the surface distance between the first metal connection part 31 and the second metal connection part 41 can be increased, thereby enhancing the insulation performance of the semiconductor packaging structure, and providing guarantee for the realization of the basic functions of the first semiconductor chip 20; the first semiconductor chip 20 is directly connected to the substrate 12 through the first metal connection part 31, that is, the first semiconductor chip 20 is directly connected to the shell 10 through the first metal connection part 31. Compared with the scheme of connecting the shell and the semiconductor chip through the liner and the connection part between the liner and the shell in the related art, this embodiment simplifies the heat dissipation path between the first semiconductor chip 20 and the shell 10, reduces the thermal resistance on the heat dissipation path, so that the heat generated by the first semiconductor chip 20 during operation can be better transferred to the shell 10, which is more conducive to the heat dissipation of the first semiconductor chip 20. Therefore, the technical solution of this embodiment can effectively solve the problem of poor heat dissipation effect of semiconductor chips in the related art.

[0049] Specifically, in the present embodiment, the housing 10 includes a cover plate 11, a substrate 12, and a surrounding plate 13 disposed between the cover plate 11 and the substrate 12. An inner cavity 14 is formed between the cover plate 11, the substrate 12, and the surrounding plate 13. The inner cavity 14 is used to accommodate various components of the semiconductor packaging structure. The housing 10 provides an installation basis for the various components of the semiconductor packaging structure. The first pole of the first semiconductor chip 20 is located on the second surface of the first semiconductor chip 20. The first metal connection portion 31 is disposed between the second surface and the substrate 12 and is electrically connected to the first pole of the first semiconductor chip 20. The second pole of the first semiconductor chip 20 is located on the first surface of the first semiconductor chip 20. The first surface is disposed away from the substrate 12 relative to the second surface. The first semiconductor chip 20 is connected to the substrate 12 through the first metal connection portion 31. More specifically, the first pole of the first semiconductor chip 20 refers to the drain of the first semiconductor chip 20, the second pole of the first semiconductor chip 20 refers to the source of the first semiconductor chip 20, and the third pole of the first semiconductor chip 20 refers to the gate of the first semiconductor chip 20. The same is true for the second semiconductor chip 70 mentioned later.

[0050] It should be noted that in the relevant technology, the packaging shell of the power semiconductor device is usually made of polymer insulating material, the power semiconductor chip is arranged on the liner, and the liner is connected to the inner surface of the packaging shell through a connecting layer (generally a metal compound plate structure made of copper or aluminum). Such a setting will not only increase the thermal resistance on the heat dissipation path from the power semiconductor chip to the packaging shell, but also, due to the mismatch between the thermal expansion coefficients of the part of the packaging shell connected to the liner and the liner itself, the liner needs to be pre-bent, thereby increasing the stress on the liner and reducing the reliability of the power semiconductor device.

[0051] In addition, it should be noted that "surface distance" refers to the shortest path along the surface of the insulating material between two conductive parts. "Surface distance" is mainly used to evaluate the insulation performance of the electrical gap at different voltage levels to ensure the safety of the semiconductor packaging structure during normal operation or failure. In the semiconductor packaging structure of this embodiment, the second pole of the first semiconductor chip 20 is mainly to provide current, and the second pole and the first pole together form a current path; the inner cavity of the shell 10 is also filled with insulating colloid to form an insulating colloid part to ensure the insulation performance of the semiconductor packaging structure. The insulating colloid part can be made of silicone gel or silicone rubber. In this embodiment, the first semiconductor chip 20 is a power semiconductor chip.

[0052] like Figures 1 to 3As shown, the first metal connection part 31 and the second metal connection part 41 are arranged at intervals along the first preset direction, the first insulating protrusion 51 extends along the second preset direction, and the two ends of the first insulating protrusion 51 are respectively connected to the two inner surfaces opposite to the enclosure 13, wherein the second preset direction is arranged at an angle with the first preset direction. Specifically, the first insulating protrusion 51 extends, and the two ends of the first insulating protrusion are respectively connected to the two inner surfaces opposite to the enclosure 13, so that the substrate 12 is divided into two mutually isolated regions by the first insulating protrusion 51, namely the first region and the second region, the first metal connection part 31 and the first semiconductor chip 20 are located in the first region, and the second metal connection part 41 is located in the second region. Since the second metal connection part 41 is electrically connected to the second pole of the first semiconductor chip 20, and the first metal connection part 31 is electrically connected to the first pole of the first semiconductor chip 20, the voltage difference between the second metal connection part 41 and the first metal connection part 31 is large, and the first insulating protrusion 51 has a suitable length to ensure the insulation between the second metal connection part 41 and the first metal connection part 31, thereby ensuring the insulation performance of the semiconductor packaging structure.

[0053] like Figures 1 to 3 As shown, the semiconductor packaging structure also includes a third metal connection part 61 and a third terminal 62. The third metal connection part 61 is spaced apart from the second metal connection part 41. The third metal connection part 61 and the second metal connection part 41 are located on the same side of the first insulating bump 51. The third metal connection part 61 is electrically connected to the third pole of the first semiconductor chip 20. One end of the third terminal 62 is connected to the third metal connection part 61, and the other end of the third terminal 62 extends to the outside of the inner cavity 14. Specifically, in the semiconductor packaging structure, the third pole of the first semiconductor chip 20 controls the current flowing from the second pole of the first semiconductor chip 20 to the first pole of the first semiconductor chip 20 by applying voltage. The change in the voltage of the third pole of the first semiconductor chip 20 can accurately control the current passing through the first pole and the second pole of the first semiconductor chip 20. Since the voltage difference between the third pole and the second pole of the first semiconductor chip 20 is much smaller than the voltage difference between the first pole and the second pole of the first semiconductor chip 20, the third metal connection part 61 is arranged in the second area of ​​the substrate 12, that is, the third metal connection part 61 and the second metal connection part 41 are located on the same side of the first insulating bump 51. More specifically, the third metal connection part 61 is located on the side of the second metal connection part 41 away from the first metal connection part 31 to meet the insulation requirements of the semiconductor packaging structure, thereby ensuring the reliability of the semiconductor packaging structure.

[0054] like Figures 1 to 3As shown, the base plate 12 and the enclosure 13 are an integral structure, and the cover plate 11 is connected to the enclosure 13 by fasteners. Specifically, the base plate 12 and the enclosure 13 are integrally formed, which can increase the structural strength of the housing 10. A nut seat is provided on the inner side of the enclosure 13, and a mounting hole is provided on the cover plate 11. The fastener is a bolt, and the bolt is passed through the mounting hole and the nut seat to connect the cover plate 11 to the enclosure 13, which has the advantages of simple structure and reliable connection.

[0055] like Figures 1 to 3 As shown, the first metal connection part 31 and the second metal connection part 41 are both plate-shaped structures and are made of copper; the housing 10 is made of ceramic. Specifically, the first metal connection part 31 and the second metal connection part 41 made of copper have the advantages of good electrical conductivity and good thermal conductivity. The first metal connection part 31 and the second metal connection part 41 are connected to the substrate 12 using an active brazing process. The housing 10 can be made of ceramics such as alumina, aluminum nitride, silicon nitride, etc., and has the advantages of high temperature resistance, corrosion resistance, good thermal conductivity, high structural strength, etc.

[0056] In addition, in the present embodiment, the height of the first insulating protrusion 51 is between 0-3mm; the width of the first insulating protrusion 51 is between 0-2mm. Specifically, such a configuration will not increase the overall weight of the semiconductor package structure too much on the one hand, and can ensure the insulation performance of the semiconductor package structure on the other hand; the height of the first insulating protrusion 51 is greater than 0 and less than or equal to 3mm, and the height of the first insulating protrusion 51 can be 0.7mm, 1mm, 1.5mm, 2mm, 2.6mm or 3mm; the width of the first insulating protrusion 51 is greater than 0 and less than or equal to 2mm, and the width of the first insulating protrusion 51 can be 0.6mm, 0.8mm, 1mm, 1.3mm, 1.75mm or 2mm.

[0057] like Figures 1 to 3 As shown, the semiconductor package structure further includes a metal connector 112, which is connected between the second electrode of the first semiconductor chip 20 and the second metal connecting portion 41. It should be noted that the insulating colloid portion has a surface disposed away from the substrate 12, which is disposed away from the substrate 12 compared to the metal connector 112. Figure 2 For example, the surface of the insulating colloid part away from the substrate 12 is the upper surface of the insulating colloid part, and the upper surface is located above the metal connector 112 so that the metal connector 112 is located inside the insulating colloid part. The metal connector 112 is a bonding wire, and at least part of the bonding wire is located above the first insulating bump 51. In other embodiments not shown in the figure, the metal connector is a metal strip, and the first insulating bump is provided with an avoidance hole, and the metal strip is inserted into the avoidance hole.

[0058] In addition, in the present embodiment, in addition, the first semiconductor chip 20 is provided with a coating except for the electrode portion. The preferred coating may be a PI coating, which may include multiple layers. PI is polyimide. The PI coating can ensure the insulation, long-term temperature resistance and water vapor isolation of the first semiconductor chip 20. Coating the PI coating on the first semiconductor chip 20 has many significant benefits, especially in improving the performance, reliability and durability of the first semiconductor chip 20. The following are several main advantages of using a PI coating: 1. Excellent thermal stability: Polyimide materials have excellent thermal stability and can maintain their physical and chemical properties in high temperature environments. For chips working under high temperature conditions, the PI coating can effectively protect the chip from thermal stress, thereby extending the service life of the chip. PI materials are generally able to withstand high temperatures, which makes it very valuable in high-temperature electronic devices and high-power applications. 2. Electrical insulation performance: The PI coating has good electrical insulation performance, which can prevent electrical short circuits and leakage inside the chip. Its high insulation ensures the safe operation of the chip in high voltage and high frequency environments, reducing the risk of electrical failures. This is particularly important for electronic devices that require high reliability. 3. Structural strength and flexibility: Polyimide materials have both high structural strength and flexibility, and can resist external stress and impact. The PI coating applied on the surface of the chip can provide additional protection to prevent the chip from being damaged during manufacturing, transportation and use. At the same time, the flexibility of the PI coating enables it to adapt to slight deformations and stress changes on the chip surface, maintaining the integrity and effectiveness of the coating. 4. Chemical corrosion resistance: PI materials have excellent chemical corrosion resistance and can resist erosion by various chemical reagents, solvents and corrosive gases. Applying PI coating can effectively protect the chip from chemical corrosion, especially in some harsh working environments such as industrial control, chemical production and environmental monitoring equipment. 5. Low dielectric constant: Polyimide has a low dielectric constant, which is an important advantage for high-speed and high-frequency circuits. Low dielectric constant helps reduce loss and delay during signal transmission, improve signal transmission speed and integrity, and thus improve chip performance and efficiency. 6. Process compatibility: PI coating can be applied by a variety of process methods, such as spin coating, spray coating and dip coating, and the process is relatively simple and suitable for large-scale production. This process compatibility enables PI coating to be widely used in the manufacture of different types of chips and electronic devices, providing a flexible solution.

[0059] In addition, the first metal connection part 31 can be made of copper, and the substrate 12 can be made of ceramic, that is, the first metal connection part 31 and the substrate 12 can be made by copper cladding on a ceramic substrate. The above copper-clad ceramic structure can be made in the following ways: DBC (Direct Bonded Copper): Through the hot melt bonding method, copper foil is directly sintered to the surface of Al2O3 and AlN ceramics at high temperature to form a composite substrate. Thanks to the high eutectic bonding strength between copper foil and ceramic, the copper thickness of the DBC substrate can generally be 100μm-600μm. At the same time, ceramics and copper have good thermal conductivity, and the thermal stability of the DBC substrate is also good. DPC (Direct Plating Copper): It is a ceramic circuit processing technology developed on the basis of ceramic thin film processing. Using ceramic as the substrate for the circuit, a metal layer is composited on the surface of the substrate by sputtering, and the circuit is formed by electroplating and photolithography. AMB (Active Metal Brazing): AMB is developed based on DBC technology. At high temperature, AgCu solder containing active elements Ti and Zr wets and reacts at the interface between ceramic and metal, thereby achieving heterogeneous bonding between ceramic and metal.

[0060] like Figures 4 to 6 As shown, the semiconductor packaging structure of the present application also provides a second embodiment, and the difference between the second embodiment and the first embodiment is that: the shell 10 also includes a panel 13 connected to the substrate 12, and a first through hole is provided on the panel 13, and the first terminal 32 passes through the first through hole. The semiconductor packaging structure also includes a first insulating panel 15, and the first insulating panel 15 is connected to the outer surface of the panel 13 and is arranged around the first through hole.

[0061] Specifically, the enclosure 13 is also provided with a second through hole, the second terminal 42 passes through the second through hole, the first through hole and the second through hole penetrate the inner surface and the outer surface of the enclosure 13, the first insulating enclosure 15 is connected to the outer surface of the enclosure 13, the first insulating enclosure 15 is arranged at the first through hole, the first insulating enclosure 15 is arranged around the outer periphery of the portion where the first terminal 32 passes through the inner cavity, and there is a first surface distance between the portion where the first terminal 32 passes through and the portion where the second terminal 42 passes through. The first surface distance includes not only the portion passing through the outer surface of the enclosure 13 but also the portion passing through the outer surface of the first insulating enclosure 15. Compared with the solution in which the first surface distance only includes the portion passing through the outer surface of the enclosure 13, the first surface distance of this embodiment can be effectively increased, thereby enhancing the insulation performance between the portion where the first terminal 32 passes through and the portion where the second terminal 42 passes through the inner cavity, thereby further enhancing the insulation performance of the semiconductor packaging structure, thereby reducing the possibility of discharge and tracking in the housing 10. In addition, a second insulating enclosure is arranged at the second through hole, and its function and structure are similar to those of the first insulating enclosure 15.

[0062] like Figures 4 to 6 As shown, the first terminal 32 is a long plate-shaped structure. The first terminal 32 includes a first plate segment 321 and a second plate segment 322 set at an angle. The first plate segment 321 is connected to the first metal connecting portion 31, and the second plate segment 322 passes through the first through hole. The first plate segment 321 is set to block the first through hole. Specifically, the formation of the insulating colloid portion needs to be achieved through a glue pouring process. When the insulating colloid is in a flowing state, it is easy to overflow from the first through hole to the outside of the shell 10 during glue pouring. By making the first plate segment 321 block the first through hole, the first terminal 32 can block the first through hole, and then the insulating colloid will not overflow from the first through hole during glue pouring, thereby enhancing the reliability of glue pouring and facilitating degassing after glue pouring. In this embodiment, the structure of the second terminal 42 is similar to that of the first terminal 32, and it also has a similar effect on the second through hole. In this embodiment, the first plate segment 321 and the second plate segment 322 are vertically arranged. If the semiconductor packaging structure is in Figure 5 In terms of posture, the first plate segment 321 extends in the vertical direction, and the second plate segment 322 extends in the lateral direction. In addition, the first terminal 32 also includes a third plate segment. The first plate segment 321 is located between the third plate segment and the second plate segment 322. The first plate segment 321 is connected to the first semiconductor chip 20 through the third plate segment and the first metal connecting part 31. The third plate segment also extends in the lateral direction. The third plate segment can increase the connection area with the first metal connecting part 31, so that the first terminal 32 can be firmly connected to the first metal connecting part 31.

[0063] like Figures 4 to 6 As shown, the housing 10 further includes a cover plate 11 connected to the enclosure 13, the first through hole communicates with the end surface of the enclosure 13 close to the cover plate 11, and the first insulating enclosure 15 includes a first enclosure section 151 and a second enclosure section 152 that are butt-connected, the first enclosure section 151 is connected to the enclosure 13, and the second enclosure section 152 is connected to the cover plate 11. Specifically, the arrangement of the first enclosure section 151 and the second enclosure section 152 makes the first insulating enclosure 15 a split structure, so that the first terminal 32 can first pass through the first enclosure section 151 and then the cover plate 11 is connected to the enclosure 13, so as to achieve the butt connection between the first enclosure section 151 and the second enclosure section 152, and the first insulating enclosure 15 is arranged around the outer periphery of the portion where the first terminal 32 passes through, which has the advantages of easy processing and easy installation.

[0064] like Figures 4 to 6As shown, a positioning groove 110 for accommodating the second plate segment 322 is provided on the inner surface of the cover plate 11, and the positioning groove 110 is provided corresponding to the second enclosure plate segment 152. Specifically, when the cover plate 11 and the enclosure plate 13 are connected, the second plate segment 322 can be accommodated in the positioning groove 110, thereby realizing the positioning function of the positioning groove 110, so that the first terminal 32 can be set at a suitable position. In addition, in this embodiment, other positioning grooves for accommodating the second terminal 42 are also provided on the inner surface of the cover plate 11, and the structures of the other positioning grooves are similar to those of the positioning groove 110.

[0065] like Figures 4 to 6 As shown, the semiconductor package structure further includes an insulating protrusion 16 disposed on the inner surface of the enclosure 13, and the insulating protrusion 16 is located between the first terminal 32 and the second terminal 42. More specifically, the insulating protrusion 16 is located between the first through hole and the second through hole, so that the insulating protrusion 16 is disposed between the portion of the first terminal 32 located in the housing 10 and the portion of the second terminal 42 located in the housing 10, and there is a second creepage distance between the portion of the first terminal 32 located in the housing 10 and the portion of the second terminal 42 located in the housing 10, and the second creepage distance includes a portion passing through the outer surface of the insulating protrusion 16 in addition to the portion passing through the inner surface of the enclosure 13. Compared with the solution in which the second creepage distance only includes a portion passing through the inner surface of the enclosure 13, the second creepage distance of this embodiment can be effectively increased, thereby enhancing the insulation performance between the portion of the first terminal 32 located in the housing 10 and the portion of the second terminal 42 located in the housing 10, thereby enhancing the insulation performance of the semiconductor package structure.

[0066] like Figures 4 to 6 As shown, a first positioning structure 17 is provided between the cover plate 11 and the enclosure 13, and a second positioning structure 18 is provided between the bottom shell 14 and the enclosure 13. Specifically, the first positioning structure 17 includes a first mounting groove 171 and a mounting block 172, the first mounting groove 171 is provided on the upper end surface of the enclosure 13, and the mounting block 172 is provided on the lower surface of the cover plate 11, and the first mounting groove 171 and the mounting block 172 can be plugged and positioned; the second positioning structure 18 includes a second mounting groove 181 provided on the lower end surface of the enclosure 13, and the bottom shell 14 can be directly installed in the second mounting groove 181 to achieve positioning of the bottom shell 14, and the cover plate 11 and the enclosure 13, as well as the bottom shell 14 and the enclosure 13, can be connected by fastening bolts or by bonding.

[0067] like Figure 7As shown, in other embodiments: the width of one end of the first plate segment 321 close to the second plate segment 322 is greater than the width of one end of the second plate segment 322 close to the first plate segment 321, and a first step surface 323 is formed on the side wall of the first terminal 32 corresponding to the connection between the first plate segment 321 and the second plate segment 322. In addition, the width of one end of the first plate segment 321 close to the third plate segment is less than the width of one end of the third plate segment close to the first plate segment 321, and a second step surface 324 is formed on the side wall of the first terminal 32 corresponding to the connection between the first plate segment 321 and the third plate segment. The setting of the first step surface 323 and the second step surface 324 can remind the staff that the first step surface 323 is the boundary point between the first plate segment 321 and the second plate segment 322, and the second step surface 324 is the boundary point between the first plate segment 321 and the third plate segment, so that the staff can bend the first terminal 32 at the first step surface 323 and the second step surface 324.

[0068] like Figures 8 to 10 As shown, the semiconductor packaging structure of the present application also provides a third embodiment, and the difference between the third embodiment and the first embodiment is that: the semiconductor packaging structure also includes a second semiconductor chip 70 and a second insulating bump 52, the first insulating bump 51 and the second insulating bump 52 are arranged at intervals, the first semiconductor chip 20 is located on the side of the first insulating bump 51 away from the second insulating bump 52, the second semiconductor chip 70 is located on the side of the second insulating bump 52 away from the first insulating bump 51, the second metal connecting part 41 is located between the first insulating bump 51 and the second insulating bump 52, and the second pole of the second semiconductor chip 70 is electrically connected to the second metal connecting part 41. Specifically, the first insulating bump 51 and the second insulating bump 52 divide the substrate 12 into a third area, a fourth area and a fifth area which are isolated from each other, wherein the fourth area is located between the first insulating bump 51 and the second insulating bump 52, the third area is located on the side of the first insulating bump 51 away from the second insulating bump 52, and the fifth area is located on the side of the second insulating bump 52 away from the first insulating bump 51, the second metal connection part 41 is located in the fourth area, and the second pole of the first semiconductor chip 20 and the second pole of the second semiconductor chip 70 are both electrically connected to the second metal connection part 41, so that the second pole of the first semiconductor chip 20 and the second pole of the second semiconductor chip 70 share the second terminal 42, thereby forming a 10,000-volt high-voltage half-bridge module, which can determine the number of power semiconductor chips in the third area or the fifth area according to the current requirements of the semiconductor packaging structure; and can also determine the number, thickness and height of the insulating bumps according to the voltage level requirements of the semiconductor packaging structure and the voltage level of the power semiconductor chip used.

[0069] like Figures 8 to 10As shown, the semiconductor package structure further includes a fourth metal connection portion 81, a fifth metal connection portion 91, a fourth terminal 82 and a fifth terminal 92 located between the first insulating bump 51 and the second insulating bump 52. The fourth metal connection portion 81 and the fifth metal connection portion 91 are located on both sides of the second metal connection portion 41. The fourth metal connection portion 81 is electrically connected to the third pole of the first semiconductor chip 20, the fifth metal connection portion 91 is electrically connected to the third pole of the second semiconductor chip 70, one end of the fourth terminal 82 is electrically connected to the fourth metal connection portion 81, and the other end of the fourth terminal 82 extends to the outside of the inner cavity 14, one end of the fifth terminal 92 is electrically connected to the fifth metal connection portion 91, and the other end of the fifth terminal 92 extends to the outside of the inner cavity 14. Specifically, as Figure 5 As shown, the shell 10 is a rectangular structure, the first insulating protrusion 51 and the second insulating protrusion 52 are arranged at intervals along the length direction of the shell 10 (that is, the first preset direction a), and the fourth metal connection part 81 and the fifth metal connection part 91 are located on both sides of the second metal connection part 41 in the width direction of the shell 10 (that is, the second preset direction b). Such an arrangement can make the layout of each metal connection part on the substrate 12 more reasonable and can meet the insulation requirements of the semiconductor packaging structure.

[0070] like Figures 8 to 10 As shown, the semiconductor package structure further includes a sixth metal connection portion 101 and a sixth terminal 102 located on a side of the second insulating protrusion 52 away from the first insulating protrusion 51, the sixth metal connection portion 101 is electrically connected to the first pole of the second semiconductor chip 70, one end of the sixth terminal 102 is electrically connected to the sixth metal connection portion 101, and the other end of the sixth terminal 102 extends to the outside of the inner cavity 14, the enclosure 13 includes a first side plate 131 and a second side plate 132 arranged opposite to each other, the first terminal 32 passes through the first side plate 131, the sixth terminal 102 passes through the second side plate 132, and the second terminal 42, the fourth terminal 82 and the fifth terminal 92 pass through the cover plate 11. Specifically, such an arrangement can make the distances between the first terminal 32 and the second terminal 42, the fourth terminal 82 and the fifth terminal 92 relatively far, and the distances between the sixth terminal 102 and the second terminal 42, the fourth terminal 82 and the fifth terminal 92 are also relatively far, thereby ensuring that the creepage distance between the terminals with a large voltage difference is large, thereby ensuring the insulation performance of the semiconductor package structure.

[0071] like Fig. 9 As shown, an arc chamfered portion 111 is provided between the substrate 12 and the enclosure 13. Specifically, the arc chamfered portion 111, in addition to being able to strengthen the connection strength between the substrate 12 and the enclosure 13, is also conducive to the degassing effect of the degassing step in the process of pouring the insulating colloid to form the insulating colloid portion, thereby reducing the possibility of residual bubbles.

[0072] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0073] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein are interpreted accordingly.

[0074] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: A housing (10) comprising a substrate (12); A first semiconductor chip (20) connected to the substrate (12); A first metal connection portion (31), connected between the substrate (12) and the first semiconductor chip (20) and electrically connected to a first electrode of the first semiconductor chip (20); a second metal connection portion (41) arranged at a distance from the first metal connection portion (31), the second metal connection portion (41) being connected to the substrate (12) and electrically connected to the second electrode of the first semiconductor chip (20); A first terminal (32) electrically connected to the first metal connection portion (31); A second terminal (42) electrically connected to the second metal connection portion (41); A first insulating bump (51) is arranged on the substrate (12) and between the first metal connection portion (31) and the second metal connection portion (41); The housing (10) further comprises an enclosure (13) connected to the substrate (12); the first metal connection portion (31) and the second metal connection portion (41) are arranged at intervals along a first preset direction; the first insulating protrusion (51) extends along a second preset direction; two ends of the first insulating protrusion (51) are respectively connected to two opposite inner surfaces of the enclosure (13); wherein the second preset direction is arranged at an angle to the first preset direction; An insulating colloid portion is formed by injecting insulating colloid into the inner cavity of the shell (10).

2. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure further comprises a third metal connection portion (61) and a third terminal (62); the third metal connection portion (61) is spaced apart from the second metal connection portion (41); the third metal connection portion (61) and the second metal connection portion (41) are located on the same side of the first insulating bump (51); the third metal connection portion (61) is electrically connected to the third electrode of the first semiconductor chip (20); and the third terminal (62) is connected to the third metal connection portion (61).

3. The semiconductor package structure according to claim 1, wherein: The housing (10) further comprises an enclosure (13) connected to the substrate (12), the enclosure (13) being provided with a first through hole, the first terminal (32) passing through the first through hole, and the semiconductor packaging structure further comprises a first insulating enclosure (15), the first insulating enclosure (15) being connected to the outer surface of the enclosure (13) and being arranged around the first through hole.

4. The semiconductor package structure according to claim 3, characterized in that: The first terminal (32) is a long plate-shaped structure, comprising a first plate segment (321) and a second plate segment (322) arranged at an angle, the first plate segment (321) being connected to the first metal connecting portion (31), the second plate segment (322) passing through the first through hole, and the first plate segment (321) being arranged to block the first through hole.

5. The semiconductor package structure according to claim 4, characterized in that: The housing (10) further comprises a cover plate (11) connected to the enclosure (13); the first through hole communicates with an end surface of the enclosure (13) close to the cover plate (11); the first insulating enclosure (15) comprises a first enclosure section (151) and a second enclosure section (152) that are butt-connected; the first enclosure section (151) is connected to the enclosure (13), and the second enclosure section (152) is connected to the cover plate (11).

6. The semiconductor package structure according to claim 5, characterized in that: A positioning groove (110) for accommodating the second plate segment (322) is provided on the inner surface of the cover plate (11), and the positioning groove (110) is arranged corresponding to the second enclosure plate segment (152).

7. The semiconductor package structure according to claim 3, characterized in that: The semiconductor packaging structure further comprises an insulating protrusion (16) arranged on the inner surface of the enclosure (13), wherein the insulating protrusion (16) is located between the first terminal (32) and the second terminal (42).

8. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure further comprises a second semiconductor chip (70) and a second insulating bump (52); the first insulating bump (51) and the second insulating bump (52) are arranged at intervals; the first semiconductor chip (20) is located on a side of the first insulating bump (51) away from the second insulating bump (52); the second semiconductor chip (70) is located on a side of the second insulating bump (52) away from the first insulating bump (51); the second metal connecting portion (41) is located between the first insulating bump (51) and the second insulating bump (52); and the second electrode of the second semiconductor chip (70) is electrically connected to the second metal connecting portion (41).

9. The semiconductor package structure according to claim 8, characterized in that: The semiconductor packaging structure also includes a fourth metal connection part (81), a fifth metal connection part (91), a fourth terminal (82) and a fifth terminal (92) located between the first insulating bump (51) and the second insulating bump (52), the fourth metal connection part (81) and the fifth metal connection part (91) being located on both sides of the second metal connection part (41), the fourth metal connection part (81) being electrically connected to the third pole of the first semiconductor chip (20), the fifth metal connection part (91) being electrically connected to the third pole of the second semiconductor chip (70), the fourth terminal (82) being electrically connected to the fourth metal connection part (81), and the fifth terminal (92) being electrically connected to the fifth metal connection part (91).

10. The semiconductor package structure according to claim 9, characterized in that: The semiconductor packaging structure further comprises a sixth metal connection portion (101) and a sixth terminal (102) located on a side of the second insulating protrusion (52) away from the first insulating protrusion (51); the housing (10) further comprises a cover plate (11) and a surrounding plate (13); the surrounding plate (13) is arranged between the cover plate (11) and the substrate (12); the sixth metal connection portion (101) is electrically connected to a first pole of the second semiconductor chip (70); the sixth terminal (102) is electrically connected to the sixth metal connection portion (101); the surrounding plate (13) comprises a first side plate (131) and a second side plate (132) arranged opposite to or adjacent to each other; the first terminal (32) passes through the first side plate (131); the sixth terminal (102) passes through the second side plate (132); the second terminal (42), the fourth terminal (82) and the fifth terminal (92) pass through the cover plate (11).

11. The semiconductor package structure according to claim 5 or 6, characterized in that: The base plate (12) and the enclosure plate (13) are an integral structure; and / or, The cover plate (11) and the enclosure plate (13) are connected via fasteners.

12. The semiconductor package structure according to any one of claims 1 to 7, characterized in that: An arc-shaped chamfered portion (111) is provided between the base plate (12) and the enclosure plate (13); and / or, The first metal connection part (31) and the second metal connection part (41) are both plate-shaped structures and are made of copper; and / or, The housing (10) is made of ceramic.

13. The semiconductor package structure according to any one of claims 1 to 10, characterized in that: The height of the first insulating protrusion (51) is between 0 and 3 mm; and / or, The width of the first insulating protrusion (51) is between 0 and 2 mm.

14. The semiconductor package structure according to any one of claims 1 to 10, characterized in that: The semiconductor packaging structure further comprises a metal connector (112), wherein the metal connector (112) is connected between the second electrode of the first semiconductor chip (20) and the second metal connecting portion (41), wherein: The metal connection member (112) is a bonding wire, and at least part of the bonding wire is located above the first insulating bump (51); or, The metal connecting piece (112) is a metal strip, and a avoidance hole is provided on the first insulating protrusion (51), and the metal strip is inserted into the avoidance hole.

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