Gating scheduling accuracy measurement method and apparatus

Abstract

The application discloses a kind of methods and equipment for measuring precision of gate scheduling, related to the technical field of gate scheduling measurement, the method comprises: the clock synchronization of measurement end and measured end is carried out, and the time delay estimation value between measurement end and measured end is determined;Based on the first gate configuration information, the first test result of the test message of measured end is obtained;Based on the first test result, the time delay estimation value is corrected, and the optimal time delay estimation value is obtained;Based on the optimal time delay estimation value, the reference time of measurement end and measured end is aligned, based on the gate scheduling value of the gate to be measured, the second gate configuration information is determined;Based on the second gate configuration information, the second test result of the test message of the gate to be measured is obtained;Based on the second test result, the optimal gate length of measurement end is determined;Based on the optimal gate length, the scheduling precision of the gate to be measured is determined.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of gated scheduling measurement, in particular to a gated scheduling precision measurement method and device. BACKGROUND

[0002] In the field of time-sensitive networks (TSN), 802.1Qci gating policy plays a crucial role in improving network reliability through precise regulation and control of data flow. However, despite being a key indicator for measuring TSN performance, the measurement method of 802.1Qci gating scheduling precision has some limitations. Currently, measuring 802.1Qci gating scheduling precision mainly relies on TSN testers, and users need to plan and construct corresponding test processes themselves. For different gating sizes, users need to design different test flows and check whether the start time and interval of the instrument packet meet the requirements, which not only increases the complexity of testing but also reduces efficiency.

[0003] The above content is only used to assist in understanding the technical solutions of the present application and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0004] The main purpose of the present application is to provide a gated scheduling precision measurement method and device, aiming to solve the technical problems of complex measurement process and low measurement efficiency of the traditional 802.1Qci gating scheduling precision measurement method in the prior art.

[0005] To achieve the above purpose, the present application provides a gated scheduling precision measurement method applied to a gated scheduling precision measurement system, wherein the gated scheduling precision measurement system at least includes a measured end and a measurement end. The gated scheduling precision measurement method comprises the following steps:

[0006] Synchronizing the clock of the measurement end and the measured end, and determining the time delay estimation value between the measurement end and the measured end;

[0007] Based on the first gating configuration information, the test packet received by the measurement end is shaped and scheduled to the measured end, and the first test result of the test packet by the measured end is obtained;

[0008] Based on the first test result, the time delay estimation value is corrected to obtain an optimal time delay estimation value;

[0009] Based on the optimal time delay estimation value, the reference time of the measurement end and the measured end is aligned, and based on the gating scheduling value of the to-be-tested gating, the second gating configuration information is determined;

[0010] Based on the second gating configuration information, the test packet received by the measurement end is shaped and scheduled to the measured end configured with the to-be-tested gating, and the second test result of the test packet by the to-be-tested gating is obtained.

[0011] determining an optimal gating length of the measurement end based on the second test result;

[0012] determining a scheduling accuracy of the to-be-tested gate based on the optimal gating length.

[0013] In an embodiment, the first gating configuration information at least includes a first gating cycle period and a first gating length, and the step of shaping and scheduling the test packet received by the measurement end to the to-be-tested end based on the first gating configuration information to obtain the first test result of the to-be-tested end on the test packet further includes:

[0014] setting the first gating cycle period of the measurement end and the to-be-tested end as a cycle period of the to-be-tested gate;

[0015] setting the first gating length of the first gate in the to-be-tested end as a first packet passing time, the first packet passing time allowing the test packet to pass;

[0016] setting the first gating length of the second gate in the to-be-tested end as a first remaining time, the sum of the first packet passing time and the first remaining time being the first gating cycle period, and the first remaining time not allowing the test packet to pass;

[0017] setting the first gating length of the first gate in the measurement end as a second packet passing time, the second packet passing time being equal to twice the first packet passing time, and the second packet passing time allowing the test packet to pass;

[0018] setting the first gating length of the second gate in the to-be-tested end as a second remaining time, the sum of the second packet passing time and the second remaining time being the first gating cycle period, and the second remaining time not allowing the test packet to pass.

[0019] In an embodiment, the step of correcting the delay estimation value based on the first test result to obtain an optimal delay estimation value includes:

[0020] when the first test result is that a first test packet passes and a second test packet is discarded within the first gating cycle period, fine-tuning the delay estimation value;

[0021] when the fine-tuned delay estimation value meets a critical requirement, taking the fine-tuned delay estimation value as the optimal delay estimation value;

[0022] When the fine-tuned time delay estimation value does not meet the critical requirement, adjusting the reference time of the measurement end and the measured end based on the fine-tuned time delay estimation value, and returning to execute the step of shaping and scheduling the test packet received by the measurement end to the measured end based on the first gating configuration information to obtain the first test result of the test packet by the measured end.

[0023] In an embodiment, the second gating configuration information at least includes a second gating cycle period and a second gating length, and the step of determining the second gating configuration information based on the gating scheduling value of the to-be-tested gate includes:

[0024] setting the second gating cycle period of the measurement end and the measured end as the cycle period of the to-be-tested gate;

[0025] configuring the first gate in the measured end as the to-be-tested gate, and the to-be-tested gate allows the test packet to pass through;

[0026] determining a third remaining time according to the second gating cycle period and the gating scheduling value of the to-be-tested gate, and setting the second gating length of the second gate in the measured end as the third remaining time, which does not allow the test packet to pass through;

[0027] determining the second gating length of the measurement end according to the gating scheduling value of the to-be-tested gate.

[0028] In an embodiment, the step of determining the second gating length of the measurement end according to the gating scheduling value of the to-be-tested gate includes:

[0029] when the gating scheduling value of the to-be-tested gate is greater than or equal to the first packet length and less than or equal to the second packet length, setting the second gating length of the first gate in the measurement end as a first preset time, which does not allow the test packet to pass through;

[0030] setting the second gating length of the first gate in the measurement end as a second packet passing time, which allows the test packet to pass through;

[0031] determining a fourth remaining time according to the second gating cycle period, the first preset time, and the second packet passing time, and setting the second gating length of the third gate in the measurement end as the fourth remaining time, which does not allow the test packet to pass through.

[0032] In an embodiment, the step of determining the second gating length of the measurement end according to the gating scheduling value of the to-be-tested gate includes:

[0033] when the gate scheduling value of the to-be-tested gate is greater than the length of the second packet, setting the second gate length of the first gate in the measurement end as a first packet passing time, the first packet passing time allowing the test packet to pass;

[0034] setting the second gate length of the second gate in the measurement end as a second preset time, the second preset time not allowing the test packet to pass;

[0035] setting the second gate length of the third gate in the measurement end as a second packet passing time, the second packet passing time allowing the test packet to pass;

[0036] determining a fifth residual time according to the second gate cycle, the second preset time, the first packet passing time and the second packet passing time, setting the second gate length of the fourth gate in the measurement end as the fifth residual time, the fifth residual time not allowing the test packet to pass.

[0037] In an embodiment, the step of determining the optimal gate length based on the second test result comprises:

[0038] when the second test result is that a first test packet passes and a second test packet is discarded within a second gate cycle, fine-tuning the first preset time;

[0039] when the fine-tuned first preset time meets the critical requirement, taking the fine-tuned first preset time as the optimal gate length;

[0040] The step of determining the scheduling precision of the to-be-tested gate based on the optimal gate length comprises:

[0041] obtaining a first correspondence relationship between the optimal gate length, the second packet passing time and the scheduling precision;

[0042] determining the scheduling precision of the to-be-tested gate based on the optimal gate length, the second packet passing time and the first correspondence relationship.

[0043] In an embodiment, the step of determining the optimal gate length based on the second test result comprises:

[0044] when the second test result is that a first test packet and a second test packet pass and a third test packet is discarded within a second gate cycle, fine-tuning the second preset time;

[0045] when the fine-tuned second preset time meets the critical requirement, taking the fine-tuned second preset time as the optimal gate length;

[0046] The step of determining the scheduling precision of the to-be-tested gate based on the optimal gate length comprises:

[0047] obtaining a second correspondence relationship between an optimal gate length, a first packet passing time and a scheduling precision;

[0048] determining the scheduling precision of the to-be-tested gate based on the optimal gate length, the first packet passing time and the second correspondence relationship.

[0049] In an embodiment, the step of determining the time delay estimation value between the measurement end and the tested end comprises:

[0050] obtaining a third correspondence relationship between an output time delay, a link transmission time delay, a packet receiving time delay, an introduced error and a time delay estimation value;

[0051] determining the time delay estimation value between the measurement end and the tested end according to the output time delay, the link transmission time delay, the packet receiving time delay, the introduced error and the third correspondence relationship.

[0052] In addition, to achieve the above object, the application further provides a gate scheduling precision measurement device, which comprises:

[0053] a data measurement module, configured to synchronize a clock of a measurement end and a tested end, and determine a time delay estimation value between the measurement end and the tested end;

[0054] The data measurement module is further configured to shape and schedule a test packet received by the measurement end to the tested end based on first gate configuration information, to obtain a first test result of the test packet by the tested end;

[0055] The data measurement module is further configured to correct the time delay estimation value based on the first test result, to obtain an optimal time delay estimation value;

[0056] The data measurement module is further configured to align a reference time of the measurement end and the tested end based on the optimal time delay estimation value, and determine second gate configuration information based on a gate scheduling value of a to-be-tested gate;

[0057] The data measurement module is further configured to shape and schedule a test packet received by the measurement end to the tested end based on the second gate configuration information, to obtain a second test result of the test packet by the to-be-tested gate;

[0058] The data measurement module is further configured to determine an optimal gate length of the measurement end based on the second test result;

[0059] a precision analysis module, configured to determine the scheduling precision of the to-be-tested gate based on the optimal gate length.

[0060] In addition, to achieve the above object, the present application also provides a gop scheduling precision measurement device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the gop scheduling precision measurement method as described above.

[0061] In addition, to achieve the above object, the present application also provides a storage medium, which is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the gop scheduling precision measurement method as described above.

[0062] In addition, to achieve the above object, the present application also provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps of the gop scheduling precision measurement method as described above.

[0063] The present application provides a gop scheduling precision measurement method, synchronizes the clock of a measurement end and a measured end, and determines a time delay estimation value between the measurement end and the measured end; based on first gop configuration information, reshapes and schedules a test packet received by the measurement end to the measured end to obtain a first test result of the test packet by the measured end; based on the first test result, corrects the time delay estimation value to obtain an optimal time delay estimation value; based on the optimal time delay estimation value, aligns the reference time of the measurement end and the measured end, determines second gop configuration information based on the gop scheduling value of a to-be-tested gop; based on the second gop configuration information, reshapes and schedules the test packet received by the measurement end to the measured end configured with the to-be-tested gop to obtain a second test result of the test packet by the to-be-tested gop; based on the second test result, determines an optimal gop length of the measurement end; and based on the optimal gop length, determines the scheduling precision of the to-be-tested gop. The present application simplifies the test process, can quickly start measurement without complex setting or adjustment, improves the measurement efficiency, and can be applied to gop measurement of various scales, can maintain consistent performance regardless of the size of the gop, has strong scene adaptability and strong universality, in addition, does not need to rely on high-end test instruments with TSN capability, greatly reduces the hardware cost, and solves the technical problems of complex measurement process and low measurement efficiency of the traditional 802.1Qci gop scheduling precision measurement method. BRIEF DESCRIPTION OF DRAWINGS

[0064] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and serve to explain the principles of the present application.

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings can also provide other drawings based on these drawings for those ordinarily skilled in the art without any creative effort.

[0066] Figure 1 Flowchart of the gating scheduling precision measurement method according to Embodiment 1 of the present application;

[0067] Figure 2 Structure diagram of the measurement system of the gating scheduling precision measurement method according to Embodiment 1 of the present application;

[0068] Figure 3 Flowchart of the solving time delay estimation value of the gating scheduling precision measurement method according to Embodiment 1 of the present application;

[0069] Figure 4 Brief diagram of the solving time delay estimation value of the gating scheduling precision measurement method according to Embodiment 1 of the present application;

[0070] Figure 5 Flowchart of the gating scheduling precision measurement method according to Embodiment 2 of the present application;

[0071] Figure 6 Flowchart of the solving first preset time of the gating scheduling precision measurement method according to Embodiment 2 of the present application;

[0072] Figure 7 Brief diagram of the solving first preset time of the gating scheduling precision measurement method according to Embodiment 2 of the present application;

[0073] Figure 8 Flowchart of the solving second preset time of the gating scheduling precision measurement method according to Embodiment 2 of the present application;

[0074] Figure 9 Brief diagram of the solving second preset time of the gating scheduling precision measurement method according to Embodiment 2 of the present application;

[0075] Figure 10 Module structure diagram of the gating scheduling precision measurement device according to the embodiments of the present application;

[0076] Figure 11 Device structure diagram of the hardware running environment involved in the gating scheduling precision measurement method according to the embodiments of the present application.

[0077] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0078] It should be understood that the specific embodiments described herein are merely intended to explain the technical solutions of the present application, and are not intended to limit the present application.

[0079] In order to better understand the technical solutions of the present application, the following will be described in detail in combination with the drawings of the specification and specific embodiments.

[0080] The main solution of the embodiment of the present application is: synchronizing the clock of the measurement end and the measured end, and determining the time delay estimation value between the measurement end and the measured end; based on the first gating configuration information, shaping and scheduling the test packet received by the measurement end to the measured end to obtain the first test result of the test packet by the measured end; based on the first test result, correcting the time delay estimation value to obtain the optimal time delay estimation value; based on the optimal time delay estimation value, aligning the reference time of the measurement end and the measured end, based on the gating scheduling value of the to-be-tested gate, determining the second gating configuration information; based on the second gating configuration information, shaping and scheduling the test packet received by the measurement end to the measured end to configure the to-be-tested gate, to obtain the second test result of the test packet by the to-be-tested gate; based on the second test result, determining the optimal gating length of the measurement end; based on the optimal gating length, determining the scheduling accuracy of the to-be-tested gate.

[0081] At present, for different gate sizes, users need to design different test flows and check whether the start time and interval of the instrument packet meet the requirements, which not only increases the test complexity, but also reduces the efficiency.

[0082] The present application provides a solution to simplify the test process, without complex settings, to quickly start measurement, improve measurement efficiency, and be applicable to gate measurement of various scales, regardless of the size of the gate, consistent performance can be maintained, strong scene adaptability and strong universality, in addition, without relying on high-end test instruments with TSN capability, greatly reducing the hardware cost, solving the technical problems of complex measurement process and low measurement efficiency of the traditional 802.1Qci gate scheduling accuracy measurement method.

[0083] The embodiment of the present application provides a gate scheduling accuracy measurement method, which refers to Figure 1 , Figure 1 The flowchart of the first embodiment of the gate scheduling accuracy measurement method of the present application.

[0084] In this embodiment, the gate scheduling accuracy measurement method comprises steps S10-S70:

[0085] Step S10, synchronizing the clock of the measurement end and the measured end, and determining the time delay estimation value between the measurement end and the measured end;

[0086] It should be noted that the embodiment is applied to the gate scheduling precision measurement system. The execution subject of the embodiment is the gate scheduling precision measurement system, and the gate scheduling precision measurement system at least includes a measured end and a measurement end, and the measured end is configured to be a gate scheduling end, and the measurement end is configured to be a measurement end Figure 2 The gate scheduling precision measurement system can further be provided with a sending end / receiving end / analysis end, and no specific limitation is made in this regard. The sending end / receiving end / analysis end is usually provided with a traffic processing module, which can send test packets, receive test packets, detect the test packets, and collect the measurement results of the measurement end to analyze and evaluate the 802.1Qci gate scheduling precision. The measurement end and the measured end need to be clock-synchronized, and the measurement end and the measured end are both provided with a clock synchronization module to achieve clock synchronization. In addition to the clock synchronization module, the measurement end is usually provided with a receiving module and a shaping and scheduling module. The receiving module is used to receive test packets, and the shaping and scheduling module is used to shape and schedule the test packets, that is, the measurement end can shape the received test packets and then schedule the test packets to the measured end. In addition, the measured end is usually provided with a traffic control module and a sending module. The traffic control module is used to open the 802.1Qci gate for measurement, and the sending module is used to return the test packets that pass the measurement to the receiving end for tracking. In addition, the measurement end has high requirements for scheduling precision and stability.

[0087] In addition, it should be noted that the gate whose precision needs to be measured in the embodiment is the 802.1Qci gate, that is, the gate to be measured is the 802.1Qci gate, and the gate to be measured is usually configured on the measured end for measurement. If the cycle period of the gate to be measured is T e , the rate at which the traffic generator of the sending end sends test packets needs to be greater than 3 e The length of the test packet is usually 64B, which is the minimum frame length, and can be flexibly adjusted according to actual needs, and no specific limitation is made in this regard.

[0088] It can be understood that there is a time delay between the scheduling of the test packet from the measurement end to the reception of the test packet by the 802.1Qci gate of the measured end, and the time delay estimation value is a value obtained by estimating the time delay.

[0089] In a feasible implementation, the step of determining the time delay estimation value between the measurement end and the measured end can include steps S101-S102:

[0090] In step S101, a third correspondence relationship between an output time delay, a link transmission time delay, a packet reception time delay, an introduced error, and a time delay estimation value is obtained.

[0091] It should be noted that the output time delay refers to the time delay between the shaping and scheduling module and the output port, the link transmission time delay refers to the time delay in the link transmission, and the packet reception time delay refers to the time delay of receiving the packet and transmitting it to the traffic control module. The time t fis a main component of the packet receiving delay, the longer the packet frame length in the store-and-forward mode, the greater the value of the packet receiving delay, the introduced error refers to the error introduced by synchronization and other introduced errors. The third correspondence relationship between the output delay, the link transmission delay, the packet receiving delay, the introduced error and the delay estimation value is a calculation relationship of the delay estimation value, as shown below:

[0092] Δ delay = Δ out + Δ link + Δ in + Δ error

[0093] In the formula, Δ delay represents the delay estimation value, Δ out represents the output delay, Δ link represents the link transmission delay, Δ in represents the packet receiving delay, and Δ error represents the introduced error.

[0094] In step S102, according to the output delay, the link transmission delay, the packet receiving delay, the introduced error and the third correspondence relationship, the delay estimation value between the measurement end and the measured end is determined.

[0095] It can be understood that the output delay, the link transmission delay, the packet receiving delay and the introduced error are substituted into the above-mentioned third correspondence relationship, so that the delay estimation value between the measurement end and the measured end is calculated. Since the delay estimation value is an estimated value, it is not accurate enough and needs to be further corrected subsequently.

[0096] In step S20, based on the first gating configuration information, the test packet received by the measurement end is shaped and scheduled to the measured end, and the first test result of the test packet by the measured end is obtained.

[0097] It should be noted that after the first gating configuration information is set, the test end can shape and schedule the received test packet, send the test packet to be sent within a specified period to the measured end, for example: 2 test packets are sent within a cycle period, so that the packet sending interval and time between test packets meet the measurement requirements. After the test end sends the test packet to the measured end, the corresponding test result, i.e. the first test result, can be obtained at the measured end, which usually includes the passing condition of the test packet, for example: the first packet passes, and the second packet is abandoned (fails to pass).

[0098] In an implementation, before step S20, the first gate cycle period of the measurement end and the measured end is set as the cycle period of the gate to be measured, the first gate length of the first gate in the measured end is set as the first packet passing time, the first gate length of the second gate in the measured end is set as the first residual time, the first gate length of the first gate in the measurement end is set as the second packet passing time, and the first gate length of the second gate in the measured end is set as the second residual time.

[0099] It should be noted that the first gate configuration information at least includes the first gate cycle period and the first gate length. In the embodiment, the first gate cycle period of the measurement end and the measured end is set as the cycle period of the gate to be measured, that is, the cycle period of all the gates in the measurement end and the measured end is T e . The first packet passing time is equal to the time of passing the first preset number of test packets, the first preset number is 1, the first packet passing time is the time of passing one test packet, the first packet passing time allows the test packet to pass, and the first gate is configured as an 802.1Qci gate with a length of the first packet passing time. The sum of the first residual time and the first packet passing time is the first gate cycle period, the corresponding first residual time can be calculated according to the first packet passing time and the first gate cycle period, and the first residual time does not allow the test packet to pass. The second packet passing time is equal to the time of passing the second preset number of test packets, the second preset number is 2, the second packet passing time is the time of passing two test packets, the second packet passing time is equal to twice the first packet passing time, and the second packet passing time allows the test packet to pass. The sum of the second residual time and the second packet passing time is the first gate cycle period, the corresponding second residual time can be calculated according to the second packet passing time and the second gate cycle period, and the second residual time does not allow the test packet to pass.

[0100] In addition, it should be noted that the reference time (Base time) of the measurement end and the measured end is different by the delay estimation value Δ delay .

[0101] It can be understood that after the first gate cycle period and the first gate length of the measurement end are set, in each first gate cycle period, the measurement end sends two test packets to the measured end, and the measured end can only pass one packet.

[0102] Step S30, based on the first test result, correcting the delay estimation value to obtain an optimal delay estimation value;

[0103] It should be noted that the 802.1Qci control is in the ingress direction, when data arrives at the 802.1Qci flow control module, if it is exactly in the gating non-permitting time, it is discarded, if it is the permitting time, it is continued to be forwarded, then in an 802.1Qci gating, if an allowed packet comes at the start time of the gating, only one packet is allowed to pass through before the gating is about to expire, when the second allowed packet comes, the interval between the two packets can be used as a measure of the scheduling accuracy of the 802.1Qci gating, therefore, the test result needs to be observed to correct the data.

[0104] In a possible implementation, the step S30 can include steps S301-S302:

[0105] Step S301, when the first test result is that the first test packet passes in a period and the second test packet is discarded, the time delay estimation value is fine-tuned.

[0106] It should be noted that the first test packet passes in a period and the second test packet is discarded means that the first test packet sent by the test end passes and the second test packet sent by the test end does not pass in each first gating cycle period.

[0107] It can be understood that the receiving condition of the test packet by the measured end is observed, the reference time can be adjusted to make the first test packet pass in a period and the second test packet be discarded, if the condition that the first test packet passes in a period and the second test packet is discarded is met, the time delay estimation value is fine-tuned.

[0108] Step S302, when the fine-tuned time delay estimation value meets the critical requirement, the fine-tuned time delay estimation value is taken as the optimal time delay estimation value; when the fine-tuned time delay estimation value does not meet the critical requirement, the reference time of the measurement end and the measured end is adjusted based on the fine-tuned time delay estimation value, and the step of shaping and scheduling the test packet received by the measurement end to the measured end based on the first gating configuration information to obtain the first test result of the test packet by the measured end is returned to be executed.

[0109] It should be noted that the time delay estimation value meeting the critical requirement means that the time delay estimation value is a critical value, and the time delay estimation value not meeting the critical requirement means that the time delay estimation value is not a critical value. In this embodiment, the time delay estimation value is fine-tuned to be just not discarded by the first test packet, and the time delay estimation value at this time is considered to be a critical value, which meets the critical requirement.

[0110] It can be understood that if the fine-tuned time delay estimation value is a critical value, it is taken as the optimal time delay estimation value, and the optimal time delay estimation value at this time is a more appropriate value and is usually more accurate. If the fine-tuned time delay estimation value is not a critical value, it needs to be further adjusted and returned to step S20 to observe the test result.

[0111] In the embodiment, the reference Figure 3 and Figure 4 The measurement end and the measured end are configured with the same gate cycle period T e (the cycle period of the to-be-measured gate), and the difference between the reference times of the measurement end and the measured end is the time delay estimation value Δ delay The length of gate 1 of the measurement end in one cycle is the time required for 2 test packets to pass, the test packets are allowed to pass, the length of gate 2 is the remaining time of one cycle, and the test packets are not allowed to pass. The length of gate 1 of the measured end is the time required for one test packet to pass, the test packets are allowed to pass, and the length of gate 2 is the remaining time of one cycle, and the test packets are not allowed to pass. After the test packet enters the measurement end, it is shaped and scheduled according to the above configuration of the measurement end gate 1 and gate 2, so that the packet sending interval and time between the test packets meet the measurement requirements. The measurement end sends only 2 packets f1 and f2 in each cycle scheduling period, observes the packet receiving condition, adjusts the reference time of the measurement end until the packet f1 passes and the packet f2 is discarded, fine-tunes the time delay estimation value Δ delay , and confirms whether it is a critical value. If it is, the final time delay estimation value Δ delay is obtained.

[0112] In step S40, the reference times of the measurement end and the measured end are aligned based on the optimal time delay estimation value, and second gate configuration information is determined based on the gate scheduling value of the to-be-measured gate.

[0113] It can be understood that after the appropriate time delay estimation value is found, the reference times of the measurement end and the measured end need to be aligned, that is, the reference time of the measured end is the reference time of the measurement end + the optimal time delay estimation value.

[0114] It should be understood that the second gate configuration information at least includes a second gate cycle period and a second gate length. Since the measured end is configured with the to-be-measured gate, different gate scheduling values of different to-be-measured gates need to be set with different gate lengths, that is, the second gate configuration information needs to be determined according to the gate scheduling value of the to-be-measured gate.

[0115] In step S50, the test packets received by the measurement end are shaped and scheduled to the measured end configured with the to-be-measured gate based on the second gate configuration information, and a second test result of the to-be-measured gate on the test packets is obtained.

[0116] It can be understood that after the second gating configuration information is set, the test end can shape and schedule the received test packet, send the test packet to be sent within a specified period to the measured end, so that the packet sending interval and time between the test packets meet the measurement requirements, and the test end sends the test packet to the measured end. The corresponding test result, i.e., the second test result, can be obtained at the measured end, which usually includes the passing situation of the test packet.

[0117] In step S60, the optimal gating length of the measurement end is determined based on the second test result.

[0118] It should be noted that the optimal gating length is the final gating length of the key gating in the measurement end. Different gating scheduling values of the to-be-tested gating correspond to different second gating configuration information, and different second gating configuration information corresponds to different optimal gating length.

[0119] In step S70, the scheduling accuracy of the to-be-tested gating is determined based on the optimal gating length.

[0120] It can be understood that the scheduling accuracy of the to-be-tested gating is calculated using the optimal gating length of the measurement end.

[0121] It should be understood that after the scheduling accuracy of the to-be-tested gating is obtained, if the actual scheduling accuracy of the to-be-tested gating can be obtained, the calculated scheduling accuracy can be evaluated according to the difference between the actual scheduling accuracy and the calculated scheduling accuracy.

[0122] The embodiment provides a gating scheduling accuracy measurement method. The measurement end and the measured end are clock-synchronized, and a time delay estimation value between the measurement end and the measured end is determined. Based on first gating configuration information, the test packet received by the measurement end is shaped and scheduled to the measured end, and a first test result of the test packet by the measured end is obtained. Based on the first test result, the time delay estimation value is corrected to obtain an optimal time delay estimation value. Based on the optimal time delay estimation value, the reference time of the measurement end and the measured end is aligned. Based on the gating scheduling value of the to-be-tested gating, second gating configuration information is determined. Based on the second gating configuration information, the test packet received by the measurement end is shaped and scheduled to the measured end configured with the to-be-tested gating, and a second test result of the test packet by the to-be-tested gating is obtained. Based on the second test result, the optimal gating length of the measurement end is determined. Based on the optimal gating length, the scheduling accuracy of the to-be-tested gating is determined. The test process is simplified, the measurement can be started quickly without complex setting or adjustment, the measurement efficiency is improved, and the gating measurement of various scales can be applied. Regardless of the size of the gating, consistent performance can be maintained, the scene adaptability and universality are strong, in addition, the high-end test instrument with TSN capability is not needed, and the hardware cost is greatly reduced.

[0123] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as the above embodiment one can refer to the above introduction, and the subsequent will not be described in detail. On this basis, please refer to Figure 5 , the step S40 can include steps S401-S404:

[0124] Step S401, the second gate cycle period of the measurement end and the measured end is set to the cycle period of the to-be-measured gate;

[0125] It should be noted that in this embodiment, the second gate cycle period of the measurement end and the measured end is set to the cycle period of the to-be-measured gate, that is, the cycle period of all gates in the measurement end and the measured end is T e .

[0126] Step S402, the first gate in the measured end is configured as the to-be-measured gate, and the to-be-measured gate allows the test packet to pass;

[0127] It should be noted that the gate 1 of the measured end is configured as the to-be-measured gate (802.1Qci gate), and the to-be-measured gate allows the test packet to pass.

[0128] Step S403, according to the second gate cycle period and the gate scheduling value of the to-be-measured gate, a third remaining time is determined, and the second gate length of the second gate in the measured end is set to the third remaining time, the third remaining time does not allow the test packet to pass;

[0129] It should be noted that the sum of the gate scheduling value of the to-be-measured gate and the third remaining time is the second gate cycle period, according to the second gate cycle period and the gate scheduling value of the to-be-measured gate, the corresponding third remaining time can be calculated, and the third remaining time does not allow the test packet to pass.

[0130] Step S404, according to the gate scheduling value of the to-be-measured gate, the second gate length of the measurement end is determined.

[0131] It should be noted that this embodiment has two scenarios: first, the gate scheduling value of the to-be-measured gate is greater than or equal to the first packet length and less than or equal to the second packet length; second, the gate scheduling value of the to-be-measured gate is greater than the second packet length.

[0132] In one possible implementation, step S304 can include steps A11-A13:

[0133] Step A11, when the gate scheduling value of the to-be-measured gate is greater than or equal to the first packet length and less than or equal to the second packet length, the second gate length of the first gate in the measurement end is set to the first preset time, and the first preset time does not allow the test packet to pass;

[0134] It should be noted that the first message length is the length of one test message, and the second message length is the length of two test messages. The gate scheduling value of the to-be-tested gate being greater than or equal to the first message length and less than or equal to the second message length means that the gate scheduling value of the to-be-tested gate is greater than or equal to the length of one test message and less than the length of two test messages. The first preset time Δ1 needs to be further adjusted subsequently. The first preset time does not allow the test message to pass, that is, the gate 1 of the test end does not allow the test message to pass.

[0135] Step A12, setting the second gate length of the first gate in the measurement end as a second message passing time, the second message passing time allowing the test message to pass;

[0136] It should be noted that the second gate length of the first gate in the measurement end is the time Δ frame2 .

[0137] It can be understood that the size relationship between the first gate and the second gate in the measurement end is: Δ t = Δ1+ Δ frame2 / 2, where Δ t is the actual scheduling accuracy of the to-be-tested gate, Δ frame2 is the second gate length, and Δ1 is the first preset time.

[0138] Step A13, determining a fourth residual time according to the second gate cycle, the first preset time, and the second message passing time, and setting the second gate length of the third gate in the measurement end as the fourth residual time, the fourth residual time not allowing the test message to pass.

[0139] It should be noted that the sum of the first preset time, the second message passing time, and the fourth residual time is the second gate cycle, so that the fourth residual time can be calculated according to the second gate cycle, the first preset time, and the second message passing time: Δ3= Δ e - Δ1- Δ frame2 , where Δ frame2 is the second message passing time, Δ1 is the first preset time, T e is the cycle of the to-be-tested gate, and Δ3 is the fourth residual time.

[0140] Step S60 can include steps A14-A15:

[0141] Step A14, when the second test result is that the first test message passes and the second test message is discarded within the second gate cycle, finely adjusting the first preset time;

[0142] It should be noted that the first test packet passing and the second test packet being discarded in the second gating cycle means that the first test packet sent by the test terminal passes and the second test packet sent by the test terminal does not pass in each second gating cycle.

[0143] It can be understood that the receiving condition of the test terminal for the test packet is observed, the first preset time Δ1 is adjusted so that the first test packet passes and the second test packet is discarded in the second gating cycle, and if the condition that the first test packet passes and the second test packet is discarded in the second gating cycle is met, the first preset time Δ1 is continuously increased in a certain value.

[0144] Step A15, when the fine-tuned first preset time meets the critical requirement, the fine-tuned first preset time is taken as the optimal gating length.

[0145] It should be noted that the first preset time meeting the critical requirement means that the first preset time is a critical value. In this embodiment, the first preset time is continuously increased and adjusted to the first test packet just passing and the second test packet being discarded, and the first preset time at this time is considered as the critical value and meets the critical requirement.

[0146] It can be understood that if the fine-tuned first preset time is the critical value, the fine-tuned first preset time is taken as the optimal gating length and is used for calculating the scheduling precision. If the fine-tuned first preset time is not the critical value, the fine-tuned first preset time needs to be further adjusted and returned to step S50 to observe the test result.

[0147] Step S70 can include steps A16-A17:

[0148] Step A16, obtaining a first corresponding relationship between the optimal gating length, the second packet passing time and the scheduling precision;

[0149] It should be noted that the first corresponding relationship between the optimal gating length, the second packet passing time and the scheduling precision is a calculation relationship of the scheduling precision, and is as follows:

[0150]

[0151] In the formula, Δ represents the scheduling precision of the to-be-tested gating, Δ frame2 represents the second packet passing time, and Δ1 represents the optimal gating length (the first preset time).

[0152] Step A17, determining the scheduling precision of the to-be-tested gating based on the optimal gating length, the second packet passing time and the first corresponding relationship.

[0153] It can be understood that the optimal gate length and the second packet passing time are substituted into the above first correspondence relationship to calculate the scheduling accuracy of the to-be-tested gate.

[0154] In the embodiment, referring to Figure 6 and Figure 7 , the cycle scheduling period of the measurement end and the measured end is T e , the measurement end scheduling adjustment is that gate 1 does not allow the test packet to pass, and the length is Δ1, gate 2 allows the test packet to pass, and the size is the time Δ frame2 needed for the continuous two test packets to just pass. t The two packets are f1 and f2 respectively. The size relationship of gate 1 and gate 2 is: Δ frame2 = Δ1+ Δ t / 2, and the length of gate 3 is Δ3, which does not allow the test packet to pass. The test packet is sent for measurement, and if the test packet is not f1 in a cycle, f2 is discarded, the value of Δ1 is adjusted until the test packet f1 passes and f2 is discarded in each cycle. Then, the value of Δ1 is increased according to the minimum gate scheduling size supported by the measurement end, until the packet f1 just passes and f2 is discarded, and the optimal value of Δ1 is found. Multiple measurements are performed, and the scheduling accuracy of the to-be-tested gate of the measured end obtained from the measurement end is The difference between and Δ t is compared to evaluate the scheduling accuracy.

[0155] In a feasible embodiment, step S304 can include steps B11-B13:

[0156] Step B11, when the gate scheduling value of the to-be-tested gate is greater than the second packet length, the second gate length of the first gate in the measurement end is set to the first packet passing time, and the first packet passing time allows the test packet to pass;

[0157] It should be noted that the gate scheduling value greater than the second packet length means that the gate scheduling value of the to-be-tested gate is greater than the length of two test packets. When the gate scheduling value of the to-be-tested gate is greater than the second packet length, the length of gate 1 in the measurement end is set to the time Δ frame1 of a test packet passing.

[0158] Step B12, the second gate length of the second gate in the measurement end is set to the second preset time, the second preset time does not allow the test packet to pass, and the second gate length of the third gate in the measurement end is set to the second packet passing time, and the second packet passing time allows the test packet to pass;

[0159] It should be noted that the second preset time Δ2 needs to be further adjusted subsequently. The second preset time does not allow the test packet to pass, that is, the gate 2 of the test end does not allow the test packet to pass. Δ2=Δ t -2*Δ frame1 , wherein Δ t represents the actual scheduling accuracy of the to-be-tested gate, Δ frame1 is the first gate length, and Δ2 is the second preset time. The length of the gate 3 in the measurement end is the time Δ3=2*Δ frame1 of passing of two test packets.

[0160] Step B13, according to the second gate cycle, the second preset time, the first packet passing time, and the second packet passing time, determining a fifth residual time, and setting the second gate length of the fourth gate in the measurement end as the fifth residual time, which does not allow the test packet to pass.

[0161] It should be noted that the sum of the second preset time, the first packet passing time, the second packet passing time, and the fifth residual time is the second gate cycle, so that the fifth residual time can be calculated according to the second gate cycle, the first preset time, the second packet passing time, and the second packet passing time: Δ4=Δ e -Δ frame1 -Δ2-Δ3, wherein Δ frame1 is the first packet passing time, Δ2 is the second preset time, T e is the cycle of the to-be-tested gate, Δ3 is the second gate length (the second packet passing time) of the third gate in the measurement end, and Δ4 is the fifth residual time.

[0162] Step S60 can include steps B14-B15:

[0163] Step B14, when the second test result is that the first test packet and the second test packet pass and the third test packet is discarded in the second gate cycle, finely adjusting the second preset time;

[0164] It should be noted that the first test packet and the second test packet pass and the third test packet is discarded in the second gate cycle means that the first test packet and the second test packet sent by the test end pass and the third test packet sent by the test end does not pass in each second gate cycle.

[0165] It can be understood that the receiving condition of the test packet by the observed terminal can be observed, the second preset time Δ2 can be adjusted so that the first test packet and the second test packet pass and the third test packet is discarded in the second gating cycle period, and if the condition that the first test packet and the second test packet pass and the third test packet is discarded in the second gating cycle period is met, the second preset time Δ2 is continuously increased by a certain value.

[0166] Step B15, when the fine-tuned second preset time meets the critical requirement, the fine-tuned second preset time is taken as the optimal gating length.

[0167] It should be noted that the second preset time meeting the critical requirement means that the second preset time is a critical value. In this embodiment, by continuously increasing the second preset time, the second preset time is adjusted to the critical value at which the first test packet and the second test packet just pass and the third test packet is discarded. At this time, the second preset time is considered as the critical value and meets the critical requirement.

[0168] It can be understood that if the fine-tuned second preset time is the critical value, the fine-tuned second preset time is taken as the optimal gating length for calculating the scheduling precision. If the fine-tuned second preset time is not the critical value, the fine-tuned second preset time needs to be further adjusted and the test result is observed again in step S50.

[0169] Step S70 can include steps B16-B17:

[0170] Step B16, obtaining a second correspondence relationship between the optimal gating length, the first packet passing time and the scheduling precision;

[0171] It should be noted that the first correspondence relationship between the optimal gating length, the second packet passing time and the scheduling precision is a calculation relationship of the scheduling precision, and is as follows:

[0172]

[0173] In the formula, indicates the scheduling precision of the to-be-tested gating, Δ frame1 indicates the first packet passing time, and Δ2 indicates the optimal gating length (second preset time).

[0174] Step B17, determining the scheduling precision of the to-be-tested gating based on the optimal gating length, the first packet passing time and the second correspondence relationship.

[0175] It can be understood that the optimal gating length and the first packet passing time are substituted into the above-mentioned second correspondence relationship to calculate the scheduling precision of the to-be-tested gating.

[0176] In this embodiment, the optimal gating length is taken as the reference value of the scheduling precision of the to-be-tested gating. Figure 8 andFigure 9 , the cycle scheduling period of the measurement end and the measured end is T e , the measurement end scheduling adjustment is gate 1 allowing 1 test packet to pass, and the size is the time Δ needed to pass 1 test packet frame1 , gate 2 does not allow test packets to pass, and the size is Δ2=Δ t -2*Δ frame1 , gate 3 allows 2 test packets to pass, and the size is the time Δ3=2*Δ needed to pass two test packets frame1 , gate 4 size is Δ4= e -Δ frame1 -Δ2-Δ3, does not allow test packets to pass. Send test packets for measurement, if test packets are not f1 and f2 pass, f3 is discarded in a period, adjust the value of Δ2, until test packets f1 and f2 pass, f3 is discarded in each period, then increase the value of Δ2 according to the minimum gate scheduling size supported by the measurement end, until test packets f1 and f2 pass just pass, f3 is discarded, and the optimal value of Δ2 is found. Measure multiple times, and the scheduling accuracy of the measured gate of the measured end obtained from the measurement end is Comparison with the difference of Δ t , evaluate the scheduling accuracy.

[0177] The embodiment provides a gate scheduling accuracy measurement method, the second gate cycle period of the measurement end and the measured end is set as the cycle period of the measured gate; the first gate in the measured end is configured as the measured gate, and the measured gate allows test packets to pass; according to the second gate cycle period and the gate scheduling value of the measured gate, a third residual time is determined, and the second gate length of the second gate in the measured end is set as the third residual time, and the third residual time does not allow test packets to pass; according to the gate scheduling value of the measured gate, the second gate length of the measurement end is determined. Simplify the test process, without complex setting or adjustment, the measurement can be started quickly, the measurement efficiency is improved, and the gate measurement of various scales can be applied. Regardless of the change of the gate size, consistent performance can be maintained, the scene adaptability is strong, the universality is strong, in addition, the high-end test instrument with TSN capability is not needed, and the hardware cost is greatly reduced.

[0178] The application also provides a gate scheduling accuracy measurement device, please refer to Figure 10 , the gate scheduling accuracy measurement device comprises:

[0179] The data measurement module 10 is used for clock synchronization between the measurement end and the measured end, and determining the time delay estimation value between the measurement end and the measured end;

[0180] The data measurement module 10 is further configured to shape and dispatch the test packet received by the measurement end to the measured end based on the first gating configuration information, to obtain a first test result of the test packet by the measured end;

[0181] The data measurement module 10 is further configured to correct the time delay estimation value based on the first test result, to obtain an optimal time delay estimation value;

[0182] The data measurement module 10 is further configured to align the reference time of the measurement end and the measured end based on the optimal time delay estimation value, and determine second gating configuration information based on the gating scheduling value of the to-be-tested gating;

[0183] The data measurement module 10 is further configured to shape and dispatch the test packet received by the measurement end to the measured end based on the second gating configuration information, to obtain a second test result of the test packet by the to-be-tested gating;

[0184] The data measurement module 10 is further configured to determine the optimal gating length of the measurement end based on the second test result;

[0185] The precision analysis module 20 is configured to determine the scheduling precision of the to-be-tested gating based on the optimal gating length.

[0186] In a feasible implementation, the data measurement module 10 is further configured to set the first gating cycle period of the measurement end and the measured end as the cycle period of the to-be-tested gating;

[0187] The first gating length of the first gating in the measured end is set as a first packet passing time, and the first packet passing time allows the test packet to pass;

[0188] The first gating length of the second gating in the measured end is set as a first residual time, and the sum of the first residual time and the first packet passing time is the first gating cycle period, and the first residual time does not allow the test packet to pass;

[0189] The first gating length of the first gating in the measurement end is set as a second packet passing time, and the second packet passing time is equal to twice the first packet passing time, and the second packet passing time allows the test packet to pass;

[0190] The first gating length of the second gating in the measured end is set as a second residual time, and the sum of the second residual time and the second packet passing time is the first gating cycle period, and the second residual time does not allow the test packet to pass.

[0191] In an implementation, the data measurement module 10 is further configured to fine-tune the time delay estimation value when the first test result is that a first test packet is passed and a second test packet is discarded in the first gating cycle period.

[0192] When the fine-tuned time delay estimation value meets the critical requirement, the fine-tuned time delay estimation value is taken as the optimal time delay estimation value.

[0193] When the fine-tuned time delay estimation value does not meet the critical requirement, the reference time of the measurement end and the measured end is adjusted based on the fine-tuned time delay estimation value, and the step of shaping and scheduling the test packet received by the measurement end to the measured end to obtain the first test result of the test packet by the measured end is performed again based on the first gating configuration information.

[0194] In an implementation, the data measurement module 10 is further configured to set the second gating cycle period of the measurement end and the measured end as the cycle period of the to-be-tested gating.

[0195] The first gating in the measured end is configured as the to-be-tested gating, and the to-be-tested gating allows the test packet to pass.

[0196] According to the second gating cycle period and the gating scheduling value of the to-be-tested gating, a third residual time is determined, and a second gating length of a second gating in the measured end is set as the third residual time, which does not allow the test packet to pass.

[0197] According to the gating scheduling value of the to-be-tested gating, a second gating length of the measurement end is determined.

[0198] In an implementation, the data measurement module 10 is further configured to set a second gating length of a first gating in the measurement end as a first preset time when the gating scheduling value of the to-be-tested gating is greater than or equal to a first packet length and less than or equal to a second packet length, and the first preset time does not allow the test packet to pass.

[0199] The second gating length of the first gating in the measurement end is set as a second packet passing time, and the second packet passing time allows the test packet to pass.

[0200] According to the second gating cycle period, the first preset time, and the second packet passing time, a fourth residual time is determined, and a second gating length of a third gating in the measurement end is set as the fourth residual time, which does not allow the test packet to pass.

[0201] In an implementation, the data measurement module 10 is further configured to set a second gate length of a second gate in the measurement end as a first packet passing time when the gate scheduling value of the to-be-tested gate is greater than the second packet length, the first packet passing time allowing the test packet to pass;

[0202] set a second gate length of a third gate in the measurement end as a second packet passing time, the second packet passing time allowing the test packet to pass;

[0203] set a second gate length of a third gate in the measurement end as a second packet passing time, the second packet passing time allowing the test packet to pass;

[0204] determine a fifth residual time according to the second gate cycle, the second preset time, the first packet passing time and the second packet passing time, set a second gate length of a fourth gate in the measurement end as the fifth residual time, the fifth residual time not allowing the test packet to pass.

[0205] In an implementation, the data measurement module 10 is further configured to fine tune the first preset time when the second test result is that a first test packet passes and a second test packet is discarded in the second gate cycle;

[0206] when the fine-tuned first preset time meets the critical requirement, take the fine-tuned first preset time as the optimal gate length;

[0207] The step of determining the scheduling accuracy of the to-be-tested gate based on the optimal gate length comprises:

[0208] obtain a first correspondence relationship between the optimal gate length, the second packet passing time and the scheduling accuracy;

[0209] determine the scheduling accuracy of the to-be-tested gate based on the optimal gate length, the second packet passing time and the first correspondence relationship.

[0210] In an implementation, the data measurement module 10 is further configured to obtain a third correspondence relationship between an output delay, a link transmission delay, a packet receiving delay, an introduced error and a delay estimation value;

[0211] determine the delay estimation value between the measurement end and the to-be-tested end according to the output delay, the link transmission delay, the packet receiving delay, the introduced error and the third correspondence relationship.

[0212] The gate scheduling precision measurement device provided in the present application adopts the gate scheduling precision measurement method in the above embodiment, and can solve the technical problems of complex measurement process and low measurement efficiency of the traditional 802.1Qci gate scheduling precision measurement method. Compared with the prior art, the gate scheduling precision measurement device provided in the present application has the same beneficial effects as the gate scheduling precision measurement method provided in the above embodiment, and other technical features in the gate scheduling precision measurement device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0213] The present application provides a gate scheduling precision measurement device, which comprises at least one processor and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the gate scheduling precision measurement method in the above embodiment one.

[0214] Reference will be made to the following description Figure 11 which shows a structural schematic diagram of a gate scheduling precision measurement device suitable for being used to implement the embodiments of the present application. The gate scheduling precision measurement device in the embodiments of the present application can include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, personal digital assistants, tablet computers, portable multimedia players, vehicle-mounted terminals, etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 11 The gate scheduling precision measurement device shown is only an example, and should not bring any limitation to the functions and use range of the embodiments of the present application.

[0215] As Figure 11As shown, the gate scheduling accuracy measurement device can include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to programs stored in a read only memory (ROM) 1002 or loaded from a storage device 1003 into a random access memory (RAM) 1004. Various programs and data required for the operation of the gate scheduling accuracy measurement device are also stored in the RAM 1004. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; the storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the gate scheduling accuracy measurement device to communicate with other devices wirelessly or by wire to exchange data. Although the gate scheduling accuracy measurement device with various systems is shown in the figure, it should be understood that all the shown systems are not required to be implemented or possessed. More or less systems can be alternatively implemented or possessed.

[0216] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by a communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the methods of the embodiments of the present disclosure are performed.

[0217] The gate scheduling accuracy measurement device provided by the present application adopts the gate scheduling accuracy measurement method in the above-mentioned embodiments, and can solve the technical problems of complex measurement process and low measurement efficiency of the traditional 802.1Qci gate scheduling accuracy measurement method. Compared with the prior art, the gate scheduling accuracy measurement device provided by the present application has the same beneficial effects as the gate scheduling accuracy measurement method provided by the above-mentioned embodiments, and other technical features in the gate scheduling accuracy measurement device are the same as the features disclosed in the previous embodiment method, which will not be repeated here.

[0218] It should be understood that various aspects of the disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0219] The present application provides a computer readable storage medium having stored thereon computer readable program instructions (i.e., computer programs) for performing the method of measuring gating scheduling precision in the above embodiments.

[0220] The above computer readable storage medium can be included in the gating scheduling precision measurement device; or can exist separately without being assembled into the gating scheduling precision measurement device.

[0221] The above computer readable storage medium carries one or more programs, which, when executed by the gating scheduling precision measurement device, cause the gating scheduling precision measurement device to: synchronize a measurement end with a measured end in time, and determine a time delay estimation value between the measurement end and the measured end; based on first gating configuration information, shape and schedule a test packet received by the measurement end to the measured end to obtain a first test result of the test packet by the measured end; based on the first test result, correct the time delay estimation value to obtain an optimal time delay estimation value; based on the optimal time delay estimation value, align a reference time of the measurement end and the measured end, and based on a gating scheduling value of a to-be-tested gating, determine second gating configuration information; based on the second gating configuration information, shape and schedule the test packet received by the measurement end to the measured end configured with the to-be-tested gating to obtain a second test result of the test packet by the to-be-tested gating; based on the second test result, determine an optimal gating length of the measurement end; and based on the optimal gating length, determine a scheduling precision of the to-be-tested gating.

[0222] The flowcharts and block diagrams in the attached drawings illustrate the possible implementation architectures, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment, or a part of code containing one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different orders than that shown in the attached drawings. For example, two blocks that are shown in succession can actually be executed substantially in parallel, or they can be executed in reverse order, depending on the involved functions. It should also be noted that each block in the block diagrams and / or flowcharts, and the combination of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0223] The modules described in the embodiments of the present application can be implemented in the form of software or in the form of hardware. In some cases, the name of the module does not constitute a limitation on the module itself.

[0224] The readable storage medium provided by the present application is a computer readable storage medium, which stores computer readable program instructions (i.e., a computer program) for executing the above-mentioned gating scheduling precision measurement method, and can solve the technical problem of complex measurement process and low measurement efficiency of the traditional 802.1Qci gating scheduling precision measurement method. Compared with the prior art, the computer readable storage medium provided by the present application has the same beneficial effects as the gating scheduling precision measurement method provided by the above-mentioned embodiments, and will not be described here.

[0225] The present application also provides a computer program product comprising a computer program, which, when executed by a processor, implements the steps of the gating scheduling precision measurement method as described above.

[0226] The computer program product provided by the present application can solve the technical problem of complex measurement process and low measurement efficiency of the traditional 802.1Qci gating scheduling precision measurement method. Compared with the prior art, the computer program product provided by the present application has the same beneficial effects as the gating scheduling precision measurement method provided by the above-mentioned embodiments, and will not be described here.

[0227] The above only describes some embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation, direct / indirect application in other related technical fields based on the technical concept of the present application, and the content of the present application specification and drawings are included in the patent protection scope of the present application.

Claims

1. A method of measuring the accuracy of a gated schedule, characterized by, The application is applied to a gate scheduling precision measurement system, and the gate scheduling precision measurement system at least comprises a measured end and a measurement end. The method comprises the following steps: synchronizing the clock of the measurement end and the measured end, and determining the time delay estimation value between the measurement end and the measured end; based on the first gate configuration information, shaping and scheduling the test packet received by the measurement end to the measured end to obtain the first test result of the test packet by the measured end; based on the first test result, correcting the time delay estimation value to obtain the optimal time delay estimation value; based on the optimal time delay estimation value, aligning the reference time of the measurement end and the measured end, and based on the gate scheduling value of the to-be-tested gate, determining the second gate configuration information; based on the second gate configuration information, shaping and scheduling the test packet received by the measurement end to the measured end to obtain the second test result of the test packet by the to-be-tested gate; based on the second test result, determining the optimal gate length of the measurement end; 2. The method of claim 1, wherein, based on the optimal gate length, determining the scheduling precision of the to-be-tested gate. The first gate configuration information at least comprises a first gate cycle period and a first gate length, and before the step of shaping and scheduling the test packet received by the measurement end to the measured end to obtain the first test result of the test packet by the measured end based on the first gate configuration information, the method further comprises the following steps: setting the first gate cycle period of the measurement end and the measured end as the cycle period of the to-be-tested gate; setting the first gate length of the first gate in the measured end as the first packet passing time, and the first packet passing time allows the test packet to pass; setting the first gate length of the second gate in the measured end as the first remaining time, and the sum of the first remaining time and the first packet passing time is the first gate cycle period, and the first remaining time does not allow the test packet to pass; setting the first gate length of the first gate in the measurement end as the second packet passing time, and the second packet passing time is equal to twice the first packet passing time, and the second packet passing time allows the test packet to pass; 3. The method of claim 1, wherein, setting the first gate length of the second gate in the measured end as the second remaining time, and the sum of the second remaining time and the second packet passing time is the first gate cycle period, and the second remaining time does not allow the test packet to pass. The step of correcting the time delay estimation value based on the first test result to obtain the optimal time delay estimation value comprises the following steps: when the first test result is that the first test packet passes and the second test packet is discarded within the first gate cycle period, fine-tuning the time delay estimation value; when the fine-tuned time delay estimation value meets the critical requirement, taking the fine-tuned time delay estimation value as the optimal time delay estimation value. When the fine-tuned time delay estimation value does not meet the critical requirement, adjusting the reference time of the measurement end and the measured end based on the fine-tuned time delay estimation value, and returning to execute the step of shaping and scheduling the test packet received by the measurement end to the measured end based on the first gating configuration information to obtain the first test result of the test packet by the measured end.

4. The method of claim 1, wherein, The second gating configuration information at least includes a second gating cycle period and a second gating length, and the step of determining the second gating configuration information based on the gating scheduling value of the to-be-tested gating includes: setting the second gating cycle period of the measurement end and the measured end as the cycle period of the to-be-tested gating; configuring the first gating in the measured end as the to-be-tested gating, and the to-be-tested gating allows the test packet to pass through; determining a third residual time according to the second gating cycle period and the gating scheduling value of the to-be-tested gating, and setting the second gating length of the second gating in the measured end as the third residual time, which does not allow the test packet to pass through; determining the second gating length of the measurement end according to the gating scheduling value of the to-be-tested gating.

5. The method of claim 4, wherein, The step of determining the second gating length of the measurement end according to the gating scheduling value of the to-be-tested gating includes: when the gating scheduling value of the to-be-tested gating is greater than or equal to the first packet length and less than or equal to the second packet length, setting the second gating length of the first gating in the measurement end as a first preset time, which does not allow the test packet to pass through; setting the second gating length of the first gating in the measurement end as a second packet passing time, which allows the test packet to pass through; determining a fourth residual time according to the second gating cycle period, the first preset time and the second packet passing time, and setting the second gating length of the third gating in the measurement end as the fourth residual time, which does not allow the test packet to pass through.

6. The method of claim 4, wherein, The step of determining the second gating length of the measurement end according to the gating scheduling value of the to-be-tested gating includes: when the gating scheduling value of the to-be-tested gating is greater than the second packet length, setting the second gating length of the first gating in the measurement end as a first packet passing time, which allows the test packet to pass through; setting the second gating length of the second gating in the measurement end as a second preset time, which does not allow the test packet to pass through; setting the second gating length of the third gating in the measurement end as a second packet passing time, which allows the test packet to pass through; determining a fifth residual time according to the second gating cycle period, the second preset time, the first packet passing time and the second packet passing time, and setting the second gating length of the fourth gating in the measurement end as the fifth residual time, which does not allow the test packet to pass through.

7. The method of claim 5, wherein, The step of determining the optimal gating length based on the second test result includes: when the second test result is that a first test packet is passed and a second test packet is discarded in a second gate cycle, the first preset time is fine-tuned; when the fine-tuned first preset time meets the critical requirement, the fine-tuned first preset time is taken as the optimal gate length; the step of determining the scheduling precision of the to-be-tested gate based on the optimal gate length comprises: obtaining a first correspondence relationship between the optimal gate length, a second packet passing time and the scheduling precision; determining the scheduling precision of the to-be-tested gate based on the optimal gate length, the second packet passing time and the first correspondence relationship.

8. The method of claim 6, wherein, the step of determining the optimal gate length based on the second test result comprises: when the second test result is that a first test packet and a second test packet are passed and a third test packet is discarded in a second gate cycle, the second preset time is fine-tuned; when the fine-tuned second preset time meets the critical requirement, the fine-tuned second preset time is taken as the optimal gate length; the step of determining the scheduling precision of the to-be-tested gate based on the optimal gate length comprises: obtaining a second correspondence relationship between the optimal gate length, a first packet passing time and the scheduling precision; determining the scheduling precision of the to-be-tested gate based on the optimal gate length, the first packet passing time and the second correspondence relationship.

9. The method of any one of claims 1 to 8, wherein, the step of determining the time delay estimation value between the measurement end and the to-be-tested end comprises: obtaining a third correspondence relationship between an output time delay, a link transmission time delay, a packet receiving time delay, an introduced error and the time delay estimation value; determining the time delay estimation value between the measurement end and the to-be-tested end according to the output time delay, the link transmission time delay, the packet receiving time delay, the introduced error and the third correspondence relationship.

10. A gated dispatch accuracy measurement device, characterized by, the gate scheduling precision measurement device comprises a memory, a processor and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the gate scheduling precision measurement method in any one of claims 1 to 9.

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