Signal receiving device, method, analog-digital hybrid test board and test machine

Abstract

The present application relates to a signal receiving device, method, analog-to-digital hybrid test board and test machine. In a sub-test unit, an external clock chip outputs a sampling clock of a fixed frequency to an analog-to-digital conversion device, and a digital waveform collector receives the original waveform of a fixed frequency output by the analog-to-digital conversion device according to the sampling clock, resamples the original waveform, generates a desired reconstructed waveform of any frequency and sends it to a first communication module. In a main test unit, a reconstructed waveform is received by a second communication module and sent to a waveform receiving module, which stores the received reconstructed waveform in a storage module. By resampling the original waveform of a fixed frequency to generate a desired reconstructed waveform of any frequency, the external clock chip outputs a sampling clock of a fixed frequency to the analog-to-digital conversion device to complete the analog-to-digital conversion, without the need for an external clock chip to adjust the frequency of the sampling clock, thereby simplifying the operation and improving the test efficiency.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a signal receiving device, method, analog-digital hybrid testing board and testing machine. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to test various parameters of the device under test (DUT) to eliminate defective products and control the quality of semiconductor devices before they leave the factory. In analog testing, especially high-speed analog testing, the test signals transmitted to the device under test often have very high requirements for harmonics, signal-to-noise ratio, amplitude, signal frequency, etc. When the tester implements the IQ function, it is necessary to ensure the synchronization of the IQ channels.

[0003] The traditional test signal receiving scheme is to adjust the sampling clock phase of the ADC (analog-to-digital converter) of the IQ channel by changing the frequency of the clock signal output by the clock circuit to synchronize the IQ channel. This method of receiving the test signal by adjusting the sampling clock phase of the ADC has the disadvantages of complex control logic, cumbersome operation, and low test efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a signal receiving device, method, analog-to-digital hybrid test board and test machine that can improve test efficiency in order to address the above problems.

[0005] A first aspect of the present application provides a signal receiving device, including a main test unit and a sub-test unit, wherein:

[0006] The sub-test unit includes a digital waveform collector, a first communication module and an external clock chip;

[0007] The external clock chip outputs a sampling clock of a fixed frequency to the analog-to-digital conversion device; the digital waveform collector connects the analog-to-digital conversion device and the first communication module, and the digital waveform collector receives the original waveform of a fixed frequency output by the analog-to-digital conversion device according to the sampling clock, resamples the original waveform, generates a required reconstructed waveform of any frequency, and sends it to the first communication module;

[0008] The main test unit includes a second communication module, a waveform receiving module and a storage module;

[0009] The second communication module is connected to the first communication module and the waveform receiving module, receives the reconstructed waveform through the second communication module and sends it to the waveform receiving module; the waveform receiving module is connected to the storage module, and stores the received reconstructed waveform in the storage module.

[0010] In one embodiment, the digital waveform collector comprises:

[0011] A synchronous control module, connected to the waveform data processing module and the analog-to-digital conversion device, for receiving the original waveform of a fixed frequency output by the analog-to-digital conversion device, and sending the original waveform to the waveform data processing module after receiving a trigger signal;

[0012] The waveform data processing module is connected to the first communication module, performs resampling processing on the original waveform, generates a required reconstructed waveform of any frequency, and sends it to the first communication module.

[0013] In one embodiment, the synchronization control module includes:

[0014] A synchronous receiving control module, connected to the acquisition signal processing module and more than two analog-to-digital conversion devices, receives the original waveforms output by each of the analog-to-digital conversion devices, and synchronously sends multiple original waveforms to the acquisition signal processing module after receiving a trigger signal;

[0015] The acquisition signal processing module is connected to the waveform data processing module, and is used to synthesize the received multiple original waveforms and output one original waveform to the waveform data processing module.

[0016] In one embodiment, the waveform data processing module includes:

[0017] A calibration module, connected to the synchronization control module, for calibrating the received original waveform and outputting calibrated waveform data;

[0018] The digital resampling module is connected to the calibration module and the first communication module, and is used to resample the calibrated waveform data, generate a required reconstructed waveform of any frequency, and send it to the first communication module.

[0019] In one of the embodiments, the calibration module includes at least one of a DC calibration module, an AC amplitude calibration module and a low-pass filtering module.

[0020] In one embodiment, the digital resampling module includes:

[0021] An input waveform data cache module is connected to the calibration module, the effective position calculation module and the effective data cache module, and is used to cache the calibrated waveform data, and send a start signal to the effective position calculation module when the number of cached data is greater than a set threshold number; and read the effective data corresponding to the effective position from the cached data according to the received read enable signal, and send the read effective data to the effective data cache module for caching;

[0022] The effective position calculation module is connected to the effective coefficient generation module, and is used to calculate according to the set step and initial phase after receiving the start signal, obtain effective position information and send it to the effective coefficient generation module, and send a read enable signal to the input waveform data cache module;

[0023] The effective coefficient generation module is connected to the data calculation module and the effective data cache module, and is used to read coefficients from the pre-stored multiple sets of coefficients according to the effective position information, obtain effective coefficients and send them to the data calculation module, and send a data read enable signal to the effective data cache module;

[0024] The effective data cache module is connected to the data calculation module and is used to read the cached effective data and send it to the data calculation module according to the received data read enable signal;

[0025] The data calculation module is connected to the first communication module and is used to perform convolution calculation according to the received effective coefficients and effective data to obtain a reconstructed waveform and send it to the first communication module.

[0026] In one of the embodiments, the effective data cache module stores the effective data in parallel into continuous internal cache units using a shifting method; and / or the effective coefficient generation module reads out two adjacent groups of coefficients according to the integer position information of the effective position information, and calculates the two groups of coefficients read using a linear interpolation algorithm according to the decimal position information of the effective position information to obtain effective coefficients.

[0027] In one embodiment, the data calculation module performs convolution calculation according to the received effective coefficients and effective data, including:

[0028]

[0029] Among them, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the valid coefficient corresponding to the valid position of the reconstruction point, and DATA_IN represents the valid data corresponding to the valid position.

[0030] In one embodiment, the waveform receiving module includes:

[0031] A receiving control module, connected to the second communication module and the read-write control module, configured to receive the reconstructed waveform through the second communication module and send a write request instruction to the read-write control module;

[0032] The read-write control module is connected to the storage module and is used to store the reconstructed waveform into the storage module according to the write request instruction.

[0033] In one embodiment, the sub-test unit further includes a first service decoding module, which is connected to a host computer, the digital waveform collector and the external clock chip, and performs parameter configuration on the digital waveform collector and the external clock chip according to instructions issued by the host computer; and / or

[0034] The main test unit also includes a second business decoding module, which is connected to the host computer and the waveform receiving module, configures parameters of the waveform receiving module according to instructions issued by the host computer, and performs waveform reading operations on the storage module through the waveform receiving module.

[0035] A second aspect of the present application provides a signal receiving method, comprising:

[0036] The external clock chip in the sub-test unit outputs a fixed frequency sampling clock to the analog-to-digital conversion device;

[0037] The digital waveform collector in the sub-test unit receives the original waveform with a fixed frequency output by the analog-to-digital conversion device according to the sampling clock, performs resampling processing on the original waveform, generates a required reconstructed waveform with any frequency, and sends it to the first communication module in the sub-test unit;

[0038] The second communication module in the main test unit receives the reconstructed waveform and sends it to the waveform receiving module in the main test unit;

[0039] The waveform receiving module stores the received reconstructed waveform into the storage module in the main test unit.

[0040] A third aspect of the present application provides an analog-digital hybrid test board, comprising the above-mentioned signal receiving device.

[0041] A fourth aspect of the present application provides a test machine, comprising a communication board, a backplane and the above-mentioned analog-digital hybrid test board.

[0042] In the above-mentioned signal receiving device, method, analog-to-digital hybrid test board and test machine, in the sub-test unit, the external clock chip outputs a sampling clock of a fixed frequency to the analog-to-digital conversion device, and the digital waveform collector receives the original waveform of the fixed frequency output by the analog-to-digital conversion device according to the sampling clock, resamples the original waveform, generates a required reconstructed waveform of any frequency and sends it to the first communication module. In the main test unit, the reconstructed waveform is received by the second communication module and sent to the waveform receiving module, and the waveform receiving module stores the received reconstructed waveform in the storage module. By resampling the original waveform of the fixed frequency to generate the required reconstructed waveform of any frequency, the external clock chip outputs a sampling clock of a fixed frequency to the analog-to-digital conversion device to complete the analog-to-digital conversion, without the need for the external clock chip to adjust the frequency of the sampling clock, thereby simplifying the operation and improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a structural block diagram of a signal receiving device in one embodiment;

[0044] Figure 2 is a structural principle diagram of a signal receiving device in one embodiment;

[0045] Figure 3 A schematic diagram of the structure of a waveform data processing module in one embodiment;

[0046] Figure 4 is a schematic diagram of the principle of digital resampling in one embodiment;

[0047] Figure 5 FIG. 4 is a flowchart of a signal receiving method in one embodiment. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0050] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0051] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0052] In one embodiment, Figure 1 As shown, a signal receiving device is provided, comprising a sub-test unit 100 and a main test unit 200, wherein:

[0053] The sub-test unit 100 includes a digital waveform collector (Waveform Digitizer, DGT) 110, a first communication module 120 and an external clock chip 130, and may further include an analog-to-digital converter (ADC) 140; the external clock chip 130 outputs a fixed-frequency sampling clock to the analog-to-digital converter 140; the digital waveform collector 110 is connected to the analog-to-digital converter 140 and the first communication module 120, and the digital waveform collector 110 receives the original waveform of the fixed frequency output by the analog-to-digital converter 140 according to the sampling clock, resamples the original waveform, generates a required reconstructed waveform of any frequency and sends it to the first communication module 120. In addition, the external clock chip 130 can also be connected to the digital waveform collector 110, output a fixed-frequency sampling clock to the digital waveform collector 110, and the digital waveform collector 110 receives the waveform according to the sampling clock.

[0054] The main test unit 200 includes a second communication module 210, a waveform receiving module 220 and a storage module 230; the second communication module 210 is connected to the first communication module 120 and the waveform receiving module 220, receives the reconstructed waveform through the second communication module 210 and sends it to the waveform receiving module 220; the waveform receiving module 220 is connected to the storage module 230, and stores the received reconstructed waveform into the storage module 230.

[0055] Among them, the main test unit 200 and the sub-test unit 100 can be the main test board and sub-test board of the test machine respectively, or they can be designed as the same test board. The user can set the parameters of the digital waveform collector 110 according to the actual scene requirements, so that the digital waveform collector 110 generates a reconstructed waveform of any frequency required by the user after resampling the original waveform. The arbitrary frequency of the reconstructed waveform set by the user is less than or equal to the fixed frequency of the sampling clock. The external clock chip 130 can be a PLL (Phase Locked Loop) clock chip, and the storage module 230 can be a DDR (Double Data Rate) storage module composed of DDR4 particles. The first communication module 120 and the second communication module 210 can be a gigabit (such as GTX) communication module, or other types of communication modules. In actual applications, the modules in the main test unit 200 and the modules in the sub-test unit 100 can be interchanged with each other if the functions are met. For example, the digital waveform collector 110 is located in the main test unit 200.

[0056] After receiving the analog waveform output by the device under test, the analog-to-digital conversion device 140 performs analog-to-digital conversion sampling on the analog waveform according to a sampling clock of a fixed frequency, generates an original waveform and sends it to the digital waveform collector 110. The digital waveform collector 110 processes the original waveform to generate a reconstructed waveform of any desired frequency. The device under test can be a semiconductor chip or other device. The number of analog-to-digital conversion devices 140 can be one or more. For example, for the IQ channel of the test machine, a single or multiple analog-to-digital conversion devices 140 can be set for each channel to receive the analog waveform output by the device under test and perform analog-to-digital conversion on the analog waveform based on the sampling clock.

[0057] like Figure 2 As shown, the digital waveform collector 110 may include a synchronization control module 112 and a waveform data processing module 114. The synchronization control module 112 is connected to the waveform data processing module 114 and the analog-to-digital conversion device 140, and is used to receive the original waveform of a fixed frequency output by the analog-to-digital conversion device 140, and send the original waveform to the waveform data processing module 114 after receiving the trigger signal; the waveform data processing module 114 is connected to the first communication module 120, resamples the original waveform, generates a required reconstructed waveform of any frequency and sends it to the first communication module 120. Further, the sub-test unit 100 may also include a first service decoding module 150, which is connected to the host computer, the digital waveform collector 110 and the external clock chip 130, and performs parameter configuration on the digital waveform collector 110 and the external clock chip 130 according to the instructions issued by the host computer.

[0058] Among them, the digital waveform collector 110, the first communication module 120, and the first service decoding module 150 can be set in an FPGA (Field-Programmable Gate Array), and the external clock chip 130 and the analog-to-digital conversion device 140 are located outside the FPGA. The port PLL_CTRL of the first service decoding module 150 is connected to the external clock chip 130 through an SPI (Serial Peripheral Interface) interface, and the parameters of the external clock chip 130 are configured so that the external clock chip 130 outputs a sampling clock of a fixed frequency to the analog-to-digital conversion device 140. The external clock chip 130 can be configured to output the sampling clock at the maximum allowed frequency (such as 400MHz), or it can be configured to output the sampling clock at other frequencies. The port DTG_CTRL of the first service decoding module 150 is connected to the synchronization control module 112 and the waveform data processing module 114 for parameter configuration.

[0059] Continue to refer to Figure 2 The synchronous control module 112 includes a synchronous receiving control module 1122 and an acquisition signal processing module 1124. The synchronous receiving control module 1122 is connected to the acquisition signal processing module 1124 and more than two analog-to-digital conversion devices 140, receives the original waveforms output by each analog-to-digital conversion device 140, and synchronously sends multiple original waveforms to the acquisition signal processing module 1124 after receiving a trigger signal; the acquisition signal processing module 1124 is connected to the waveform data processing module 114, and is used to synthesize the received multiple original waveforms and output one original waveform to the waveform data processing module 114.

[0060] Taking the test machine including IQ channels as an example, each channel is configured with two ADC chips. The acquisition signal processing module 1124, the waveform data processing module 114, the first communication module 120 and the second communication module 210 can be configured for the IQ channels respectively. The synchronous reception control module 1122 receives the two original waveforms of each channel through the LVDS (Low-Voltage Differential Signaling) interface and caches them in the internal FIFO (First Input First Output) buffer. After receiving the trigger signal TRIG sent by the first service decoding module 150, the synchronous reception control module 1122 outputs the two original waveforms of the same channel in the internal FIFO buffer to the corresponding acquisition signal processing module 1124. The acquisition signal processing module 1124 synthesizes the two original waveforms of the same channel into one original waveform and outputs it to the waveform data processing module 114. By synthesizing the two original waveforms into one original waveform of the I channel / Q channel, the influence of noise can be reduced and the SNR index can be improved. The waveform data processing module 114 performs digital signal processing, such as AC (alternating current) calibration, DC (direct current) calibration, resampling control, low-pass filtering, etc., according to the instructions (such as DTG_Digital_CTRL_SIGNAL instructions) issued by the first service decoding module 150, and generates a reconstructed waveform of the required frequency and sends it to the first communication module 120. The first communication module 120 uses a GTX communication module to convert the 32-bit reconstructed waveform into a 64-bit reconstructed waveform and transmit it to the second communication module 210 to increase the communication bandwidth. The second communication module 210 uses a GTX communication module to convert the received 64-bit reconstructed waveform into a 32-bit reconstructed waveform and send it to the waveform receiving module 220.

[0061] Continue to refer to Figure 2 , the sampling clock of the four ADC chips of the IQ two-way is set to a fixed maximum sampling clock (400MHz), but the user's demand is a waveform of any frequency. At this time, the waveform data processing module 114 is required to resample the original waveform sampled at a fixed frequency. At the same time, during the resampling process, the initial phase can be set to change the initial phase of the reconstructed waveform generated by the resampling, so as to realize the adjustable function of any frequency and any phase of the IQ channel. The IQ function can be realized by using an ordinary ADC chip, and the functions of two non-IQ channels can also be realized. There is no need for an external clock chip 130 to adjust the frequency of the sampling clock, which simplifies the operation and improves the test efficiency.

[0062] Furthermore, the synchronous receiving control module 1122 also collects the original waveform and the accompanying clock data_clk output by the analog-to-digital conversion device 140 according to the sampling clock, so as to ensure the synchronization of the output sampled data. Also, taking the test machine including the IQ dual channel as an example, the sampling clocks input to the two ADC chips of each channel are provided by the external clock chip 130, and the external clock chip 130 also transmits the sampling clock to the synchronous receiving control module 1122, so the sampling clock input to the synchronous receiving control module 1122 is of the same source and frequency as the sampling clocks of the four ADC chips, and the synchronous receiving control module 1122 can use the input sampling clock to perform digital sampling on the four ADC chips at the same time.

[0063] Since the output data of the ADC chip is output in the form of DDR double-edge sampling, the synchronous receiving control module 1122 uses the sampling clock input by the external clock chip 130 to simultaneously sample the original waveforms and the accompanying clock data_clk output by the four ADC chips, and judges the double-edge sampling results of the ADC data according to the sampling results of the accompanying clock data_clk of each ADC chip. When the sampling of the accompanying clock data_clk of the ADC is high, the ADC data takes odd sampling, otherwise the ADC data takes even sampling. After obtaining the sampling data results of the four ADC chips, the synchronous receiving control module 1122 arranges the four 16-bit sampling data into 64-bit data according to the channel sequence, and uses the input sampling clock as the write clock to write into the cross-clock domain cache FIFO. After the cross-clock cache FIFO is not empty, the synchronous receiving control module 1122 uses the system clock as the read clock to read out the data in the cache, and completes the cross-clock domain conversion operation. After the cross-clock domain conversion to the system clock, the data synchronization control of the four ADC chips can still be maintained.

[0064] After obtaining the data from the four ADCs based on the system clock, the synchronous receiving control module 1122 divides the 64-bit data into four 16-bit data according to the channel order, and then the acquisition signal processing module 1124 combines the data of ADC0 and ADC1 of the I channel into one channel of data, and combines the data of ADC0 and ADC1 of the Q channel into one channel of data, and directly adds the two channels of data of the I channel, and directly adds the two channels of data of the Q channel. At this time, the synchronous acquisition control of the I channel and Q channel data is completed.

[0065] Among them, after receiving the trigger signal TRIG sent by the first business decoding module 150, the synchronous receiving control module 1122 determines whether the working mode issued by the first business decoding module 150 is the IQ mode. If it is the IQ mode, as long as the trigger signal TRIG of one of the two channels of IQ is pulled high, the synchronous receiving control module 1122 will control the data of the two channels of IQ to start collecting data at the same time, and transmit the data integrated by the I channel and the Q channel to the subsequent waveform data processing module 114 for processing. At this time, the IQ two-channel data can be output synchronously until the collection length is reached and the collection is stopped. At this time, the synchronous receiving control module 1122 will not send the data of the I channel and the Q channel to the waveform data processing module 114; if the trigger signal TRIG is not received, the synchronous receiving control module 1122 will not send the data of the I channel and the Q channel to the waveform data processing module 114; when the working mode is not IQ, the synchronous receiving control module 1122 controls the data collected by the two channels of IQ to be output to the subsequent waveform data processing module 114 according to the trigger signals TRIG of the two channels of IQ.

[0066] It can be understood that the specific structure of the waveform data processing module 114 is not unique. The waveform data processing module 114 may include a calibration module and a digital resampling module. The calibration module is connected to the synchronization control module 112, and is used to calibrate the received original waveform and output the calibrated waveform data; the digital resampling module is connected to the calibration module and the first communication module 120, and is used to resample the calibrated waveform data, generate a required reconstructed waveform of any frequency and send it to the first communication module 120.

[0067] Among them, Figure 3As shown, the calibration module may specifically include at least one of a DC calibration module 40, an AC amplitude calibration module 41, and a low-pass filter module 42. Taking the calibration module including the DC calibration module 40, the AC amplitude calibration module 41, and the low-pass filter module 42 as an example, the DC calibration module 40, the AC amplitude calibration module 41, and the low-pass filter module 42 are all connected to the first service decoding module 150, the DC calibration module 40 is connected to the acquisition signal processing module 1124 in the synchronization control module 112, the AC amplitude calibration module 41 is connected to the DC calibration module 40 and the low-pass filter module 42, and the low-pass filter module 42 is connected to the digital resampling module. The DC calibration module 40 performs DC calibration on the received original waveform according to the DC calibration coefficient sent by the first service decoding module 150, and then sends it to the AC amplitude calibration module 41, so as to ensure that the amplitude accuracy of the channel data meets the index requirements. Since the IQ channel has high requirements for AC flatness, the AC amplitude calibration module 41 is also used to perform AC amplitude calibration on the waveform after DC calibration according to the AC calibration coefficient sent by the first business decoding module 150 to ensure that the amplitude accuracy of the channel data meets the index requirements. The AC amplitude calibration module 42 transmits the waveform after AC amplitude calibration to the low-pass filtering module 42. The low-pass filtering module 42 generates filter coefficients according to the low-pass filter parameters sent by the first business decoding module 150, and performs low-pass filtering on the waveform, which can reduce the influence of high-frequency noise and achieve performance improvement. The waveform processed by the low-pass filtering module 42 is sent to the digital resampling module.

[0068] The external clock chip 130 is set to a fixed maximum sampling clock frequency, and the analog-to-digital conversion device 140 samples the analog waveform based on the maximum sampling clock frequency. The function of the digital resampling module is to resample the original waveform of the maximum sampling clock frequency into a reconstructed waveform of the required frequency. The principle of resampling is to use the SINC function to perform waveform recovery for a continuous signal. Since the digital waveform collector 110 resamples the original waveform of the fixed maximum sampling frequency into a reconstructed waveform of any frequency (less than the fixed maximum sampling frequency), and since the resampled frequency is less than or equal to the fixed maximum sampling rate, the function it implements can be summarized as a sampling function of any decimal multiple. For a known continuous waveform x (n), if you want to restore it to x (t) at any time, use the Sinc function to perform data resampling and recovery. Through the first 8 points and the last 8 points of the position of the valid point to be restored, the actual value of the restored point is obtained through the convolution operation of these 16 data and 16 Sinc continuous coefficients.

[0069] In order to restore the ideal SINC function, in theory, an infinite number of sets of coefficients are needed for calculation, which is obviously not feasible. Therefore, the SINC function model is segmented into 1024 sets of coefficients, each with 16 coefficients, which are stored in ROM. Then, the effective coefficients are read from the ROM based on the effective position information. Since it is impossible to store an infinite number of sets of coefficients, in order to achieve higher accuracy, the stored coefficients are not used directly when calculating the effective coefficients. Instead, each segment of coefficients is considered to be continuous. The effective coefficients of any point can be obtained by using a linear weighted algorithm.

[0070] Based on this, continue to refer to Figure 3 The digital resampling module may include an input waveform data cache module 43, an effective position calculation module 44, an effective coefficient generation module 45, an effective data cache module 46 and a data calculation module 47. The input waveform data cache module 43 is connected to the calibration module, the effective position calculation module 44 and the effective data cache module 46. The effective position calculation module 44 is connected to the effective coefficient generation module 45. The effective coefficient generation module 45 is connected to the data calculation module 47 and the effective data cache module 46. The effective data cache module 46 is connected to the data calculation module 47.

[0071] The input waveform data cache module 43 is specifically connected to the low-pass filter module 42 in the calibration module, and is used to cache the calibrated waveform data, and send a start signal SINC_START to the effective position calculation module 44 when the number of cached data is greater than the set threshold number; and read the valid data corresponding to the effective position from the cached data according to the received read enable signal, and send the read valid data to the effective data cache module 46 for caching; the effective position calculation module 44 is used to obtain the effective position according to the set step and initial phase calculation after receiving the start signal SINC_START. The information is sent to the effective coefficient generation module 45, and a read enable signal is sent to the input waveform data cache module 43; the effective coefficient generation module 45 is used to read coefficients from multiple sets of pre-stored coefficients according to the effective position information, and the effective coefficients are sent to the data calculation module 47, and a data read enable signal is sent to the effective data cache module 46; the effective data cache module 46 is used to read the cached effective data according to the received data read enable signal and send it to the data calculation module 47; the data calculation module 47 is used to perform convolution calculation according to the received effective coefficients and effective data, and obtain the reconstructed waveform and send it to the first communication module 120. The convolution formula is as follows:

[0072]

[0073] Among them, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the valid coefficient corresponding to the valid position of the reconstruction point (there are 16 valid coefficients in total), DATA_IN represents the valid data corresponding to this valid position (also 16 points, the first 8 points and the last 8 points of this valid position), and after 16 multiplications and additions of the valid coefficient and the original waveform, the corresponding reconstruction point of the reconstructed waveform is calculated.

[0074] The value of the threshold number is not unique and can be set according to actual needs. The first service decoding module 150 is connected to the effective position calculation module 44 to configure the step STEP and the initial phase PHASE. By controlling the step STEP and the initial phase PHASE, the digital resampling module can resample the initial waveform of the variable sampling frequency into a reconstructed waveform of the fixed maximum sampling frequency. At the same time, since the digital resampling module performs digital resampling, the phase adjustment of the output waveform can also be achieved, and the accuracy can reach up to 1ps.

[0075] Specifically, after the input waveform data cache module 43 receives the waveform data output by the low-pass filter module 42, it can be cached in an internal cache unit (such as FIFO). When the number of cached data is greater than the set threshold number (such as 16), the input waveform data cache module 43 sends a start signal SINC_START to the effective position calculation module 44. The effective position calculation module 44 starts working after receiving the start signal SINC_START, and performs effective position calculation according to the step STEP and initial phase PHASE information sent by the first business decoding module 150. The effective position can be understood as the position of the reconstructed waveform points, and the calculated effective position information is composed of 16-bit integer + 48-bit decimal. Among them, the initial position of the reconstructed waveform is determined by the initial phase PHASE, and the initial position refers to the effective position of the first point of the reconstructed waveform. The relationship between the reconstructed waveform point position and the original waveform point position is: reconstructed waveform point position = (original waveform point position - 1) * STEP + 1 + PHASE. The point positions of the original waveform are also the point positions of the calibrated waveform data. DC calibration, AC amplitude calibration and filtering processing will not change the point positions of the original waveform.

[0076] Among them, step STEP = fixed maximum sampling rate (frequency of sampling clock) / user set sampling rate (frequency of reconstructed waveform). Since the user set sampling rate is less than or equal to the fixed maximum sampling rate, the value of STEP is greater than or equal to 1, which can be understood as an arbitrary multiple of sampling operation. Among them, step STEP consists of 16-bit integer + 48-bit decimal. Since the fixed maximum sampling is set to 400MHz, the 48-bit decimal can support up to uhz, and the sampling rate resampling with accuracy in uHZ can be achieved. In order to achieve the purpose of uHZ adjustment with sampling rate resolution, assuming A=400MHz=400*2^10*2^10Hz, B=1uHz=(1 / 2^10*2^10)Hz, then A / B=400*2^10*2^10Hz / (1 / 2^10*2^10)Hz=400*2^4 =49bit. Since the SINC algorithm divides the coefficients into 1024 parts, the minimum position information requires 400*2^40 / 1024bit=39bit, and 48bit is used in this solution. Among them, the initial phase PHASE=the number of points in a waveform cycle / (360° / the phase of the reconstructed waveform), and the output result is composed of 16-bit integers + 48-bit decimals, which can perform ps-level phase adjustment.

[0077] After obtaining the effective position information according to the set step STEP and initial phase PHASE, the effective position calculation module 44 outputs the effective position information to the effective coefficient generation module 45, and sends a read enable signal to the input waveform data cache module 43 according to the determined effective position. The input waveform data cache module 43 reads a data and sends it to the effective data cache module 46 according to the read enable signal sent by the effective position calculation module 44. At this time, the data stored in the effective data cache module 46 is the effective data of the effective position. After the effective coefficient generation module 45 calculates the effective coefficient of the effective position, the effective data cache module 46 reads the effective data and sends it to the data calculation module 47 for calculation.

[0078] The effective coefficient generation module 45 can store multiple groups (for example, 1024 groups) of coefficients (16 coefficients in each group) in the internal ROM (read-only memory) unit in advance. After receiving the effective position information, the effective coefficient generation module 45 can read out two adjacent groups of coefficients according to the integer position information of the effective position information, and use a linear interpolation algorithm to calculate the two groups of coefficients read according to the decimal position information of the effective position information to obtain the effective coefficients.

[0079] Specifically, the effective coefficient generation module 45 reads the pre-stored coefficients in the ROM unit according to the effective position information. Since there are only 1024 groups of pre-stored coefficients, the precision of 48-bit decimals cannot be satisfied. At this time, two adjacent groups of coefficients (one group of 16 coefficients) are read out according to the integer position information of the effective position information, and then the two groups of coefficients are calculated according to the decimal position information of the effective position information, using the linear interpolation algorithm: y_coe[n]=COE1[n]*tim_valid+COE2[n]*(1-tim_valid), n is 0-15, and the most accurate effective coefficients (16 coefficients) are obtained. Among them, COE1 represents the first group of coefficients in the two adjacent groups of coefficients read out, COE2 represents the second group of coefficients in the two adjacent groups of coefficients read out (the first group of coefficients and the second group of coefficients are both 16), tim_valid represents the decimal position information in the effective position information, and y_coe represents the effective coefficients (16 coefficients) in the decimal position of the actual effective position information obtained by linear interpolation.

[0080] The valid data cache module 46 can store the valid data in parallel into continuous internal cache units (such as FIFO) by using a shifting method. Specifically, the valid data cache module 46 stores the valid data in parallel into 16 FIFOs by using a shifting method. The specific manifestation of parallel storage is that the latest input data is stored in FIFO1, and the data in the original FIFO1 is stored in FIFO2, and the data in the original FIFO2 is stored in FIFO3, ..., that is, the 16 FIFOs store 16 continuous data.

[0081] After the effective coefficient generation module 45 generates an effective coefficient, it outputs the effective coefficient to the data calculation module 47, and simultaneously initiates a data read enable signal to the effective data cache module 46. According to the data read enable signal, the effective data cache module 46 simultaneously reads out 16 effective data from the 16 FIFOs and outputs them to the data calculation module 47. The data calculation module 47 performs a 16-order convolution calculation based on the effective coefficient output by the effective coefficient generation module 45 and the effective data output by the effective data cache module 46, calculates the resampled reconstructed waveform, and outputs it to the first communication module 120 of the next stage.

[0082] The following is an example. Assumption 1: The user sets the sampling rate (frequency of the reconstructed waveform) to 200Mhz, Assumption 2: Set the phase of the reconstructed waveform to 3.6°, Assumption 3: The original waveform is an analog waveform with a signal frequency of 8Mhz. At this time, the data collected by the ADC is 50 points in a waveform cycle (the number of sampling points in a waveform cycle = fixed maximum sampling rate / signal frequency = 400Mhz / 8Mhz=50). At this time: Step STEP = fixed maximum sampling rate / user set sampling rate = 400M / 200M=2; Initial phase PHASE = number of points in a waveform cycle / (360° / phase of the reconstructed waveform) = 50 / (360 / 3.6)=0.5. Figure 4 As shown in the figure, the effective position of the first point in the reconstructed waveform is determined by the initial phase PHASE, and the number of points in the reconstructed waveform corresponds to the effective position in the original waveform. The relationship between the position of the reconstructed waveform points and the position of the original waveform points is: the position of the reconstructed waveform points = (the position of the original waveform points - 1) * STEP + 1 + PHASE = (the position of the original waveform points - 1) * 2 + 1 + 0.5, such as: 1----1.500, 2----3.500, 3----5.500, 4----7.500. Figure 4 As shown in the figure, it explains the effect of the user-set frequency, waveform points, and initial phase on resampling, as well as their relationship with the effective position.

[0083] In one embodiment, Figure 2 As shown, the main test unit 200 also includes a second service decoding module 240, which is connected to the host computer and the waveform receiving module 220, and performs parameter configuration on the waveform receiving module 220 according to the instructions issued by the host computer, and performs waveform reading operation on the storage module 230 through the waveform receiving module 220. Among them, the second communication module 210, the waveform receiving module 220 and the second service decoding module 240 can be set in the FPGA, and the storage module 230 is located outside the FPGA. The first service decoding module 150 and the second service decoding module 240 are both directly controlled by the host computer, and the host computer independently sends parameter configurations. The two do not affect each other and are two independent modules. The waveform receiving module 220 may specifically include a receiving control module 222 and a receiving control module 224. The receiving control module 222 is connected to the second communication module 210 and the read-write control module 224, and is used to receive the reconstructed waveform through the second communication module 210 and send a write request instruction to the read-write control module 224; the read-write control module 224 is connected to the storage module 230, and is used to store the reconstructed waveform into the storage module 230 according to the write request instruction.

[0084] Among them, the port DTG_CTRL of the second service decoding module 240 is connected to the receiving control module 222, and the parameters of the receiving control module 222 are configured. The port DDR_RQE of the second service decoding module 240 is connected to the read-write control module 224, and the waveform reading operation is performed on the storage module 230 through the read-write control module 224. Specifically, after receiving the reconstructed waveform, the receiving control module 222 initiates a write request instruction of the I channel and / or Q channel to the read-write control module 224 according to the sampling length, storage address and other information issued by the second service decoding module 240, and the read-write control module 224 writes the reconstructed waveform of the I channel and / or Q channel into the storage module 230 according to the write request instruction.

[0085] Reference Figure 2 and Figure 3 , the complete processing process of the original waveform is described below: after the signal receiving device is powered on, the host computer communicates with the first business decoding module 150 and the second business decoding module 240 respectively to issue instructions, the first business decoding module 150 configures parameters of the waveform data processing module 114 and the external clock chip 130, so that the external clock chip 130 outputs a fixed frequency sampling clock to the analog-to-digital conversion device 140, and the second business decoding module 240 configures parameters of the receiving control module 222.

[0086] The synchronous receiving control module 1122 receives the original waveform output by the ADC chip for buffering, and after receiving the trigger signal TRIG sent by the first service decoding module 150, outputs the original waveform to the acquisition signal processing module 1124 for waveform synthesis, and the synthesized original waveform is input into the waveform data processing module 114 for resampling. In the waveform data processing module 114, the DC calibration module 40 and the AC amplitude calibration module 41 perform DC calibration and AC amplitude calibration on the original waveform in sequence according to the configured DC calibration coefficient and AC calibration coefficient, and the pass filter module 42 performs low-pass filtering on the calibrated waveform according to the configured low-pass filter parameters and then sends it to the input waveform data buffer module 43 for buffering. When the number of buffered data is greater than the set threshold number, the input waveform data buffer module 43 sends a start signal SINC_START to the effective position calculation module 44. After receiving the start signal SINC_START, the effective position calculation module 44 calculates the effective position information according to the configured step and initial phase and sends it to the effective coefficient generation module 45, and sends a read enable signal to the input waveform data buffer module 43. The input waveform data buffer module 43 reads the valid data corresponding to the valid position from the buffered data according to the received read enable signal, and sends the read valid data to the valid data buffer module 46 for buffering. The valid coefficient generation module 45 reads the coefficients from the pre-stored multiple sets of coefficients according to the valid position information, obtains the valid coefficients and sends them to the data calculation module 47, and sends the data read enable signal to the valid data buffer module 46. The valid data buffer module 46 reads the buffered valid data according to the received data read enable signal and sends it to the data calculation module 47. The data calculation module 47 performs convolution calculation according to the received valid coefficients and valid data, obtains the reconstructed waveform and sends it to the first communication module 120.

[0087] After receiving the reconstructed waveform through the second communication module 210, the receiving control module 222 sends a write request instruction to the read-write control module 224 according to the parameters configured by the second service decoding module 240, and the read-write control module 224 stores the reconstructed waveform in the storage module 230 according to the write request instruction. The host computer can also send instructions to the read-write control module 224 to read the reconstructed waveform in the storage module 230.

[0088] In one embodiment, Figure 5 As shown, a signal receiving method is also provided, comprising:

[0089] Step S110: the external clock chip in the sub-test unit outputs a sampling clock with a fixed frequency to the analog-to-digital conversion device.

[0090] Step S120: the digital waveform collector in the sub-test unit receives the original waveform of fixed frequency output by the analog-to-digital conversion device according to the sampling clock, resamples the original waveform, generates a reconstructed waveform of any required frequency, and sends it to the first communication module in the sub-test unit.

[0091] Step S130: the second communication module in the main test unit receives the reconstructed waveform and sends it to the waveform receiving module in the main test unit.

[0092] Step S140: the waveform receiving module stores the received reconstructed waveform into the storage module in the main test unit.

[0093] It can be understood that the specific implementation of the above-mentioned signal receiving method has been explained in detail in the above-mentioned signal receiving device, and will not be repeated here.

[0094] In one embodiment, an analog-digital hybrid test board is also provided, comprising the above-mentioned signal receiving device.

[0095] In one embodiment, a test machine is also provided, including a communication board, a backplane and the above-mentioned analog-digital hybrid test board. The communication board is connected to the analog-digital hybrid test board through the backplane. In addition, the test machine also includes a host computer that communicates with the communication board. The host computer can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers and portable wearable devices. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0096] The above-mentioned signal receiving device, method, analog-digital hybrid test board and test machine have the following advantages:

[0097] 1. This application uses an ADC chip to fix the sampling clock frequency. After power-on initialization, there is no need to repeatedly configure the external clock chip, which reduces the clock chip locking time caused by changing the sampling clock and improves test efficiency.

[0098] 2. This application uses an ADC chip to fix the sampling clock frequency, and performs resampling operations through a digital domain algorithm to achieve arbitrary frequency design, which can achieve uHZ resolution adjustment. This indicator requirement is difficult to achieve by the existing method of adjusting the sampling rate through a clock chip.

[0099] 3. This application can realize both IQ functions and non-IQ functions, making it more flexible and convenient to use and improving the efficiency of equipment use.

[0100] 4. The control method of this application facilitates the expansion, reuse, and transplantation of program channels, and can be directly used in other projects. For program updates, only channels need to be added or reduced, which facilitates program code maintenance.

[0101] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A signal receiving device, characterized in that: It includes main test unit and sub-test unit, among which: The sub-test unit includes a digital waveform collector, a first communication module and an external clock chip; The external clock chip outputs a sampling clock of a fixed frequency to the analog-to-digital conversion device; the digital waveform collector connects the analog-to-digital conversion device and the first communication module, and the digital waveform collector receives the original waveform of a fixed frequency output by the analog-to-digital conversion device according to the sampling clock, resamples the original waveform, generates a required reconstructed waveform of any frequency and sends it to the first communication module; wherein the digital waveform collector calculates the effective position information according to the configured parameters, determines the effective coefficient based on the effective position information, and reads the effective data corresponding to the effective position from the original waveform, and then convolves the effective coefficient and the read effective data to obtain the reconstructed waveform; The main test unit includes a second communication module, a waveform receiving module and a storage module; The second communication module is connected to the first communication module and the waveform receiving module, receives the reconstructed waveform through the second communication module and sends it to the waveform receiving module; the waveform receiving module is connected to the storage module, and stores the received reconstructed waveform in the storage module.

2. The signal receiving device according to claim 1, characterized in that: The digital waveform collector comprises: A synchronous control module, connected to the waveform data processing module and the analog-to-digital conversion device, for receiving the original waveform of a fixed frequency output by the analog-to-digital conversion device, and sending the original waveform to the waveform data processing module after receiving a trigger signal; The waveform data processing module is connected to the first communication module, performs resampling processing on the original waveform, generates a required reconstructed waveform of any frequency, and sends it to the first communication module.

3. The signal receiving device according to claim 2, characterized in that: The synchronization control module comprises: A synchronous receiving control module, connected to the acquisition signal processing module and more than two analog-to-digital conversion devices, receives the original waveforms output by each of the analog-to-digital conversion devices, and synchronously sends multiple original waveforms to the acquisition signal processing module after receiving a trigger signal; The acquisition signal processing module is connected to the waveform data processing module, and is used to synthesize the received multiple original waveforms and output one original waveform to the waveform data processing module.

4. The signal receiving device according to claim 2, characterized in that: The waveform data processing module comprises: A calibration module, connected to the synchronization control module, for calibrating the received original waveform and outputting calibrated waveform data; The digital resampling module is connected to the calibration module and the first communication module, and is used to resample the calibrated waveform data, generate a required reconstructed waveform of any frequency, and send it to the first communication module.

5. The signal receiving device according to claim 4, characterized in that: The calibration module includes at least one of a DC calibration module, an AC amplitude calibration module and a low-pass filtering module.

6. The signal receiving device according to claim 4, characterized in that: The digital resampling module comprises: An input waveform data cache module is connected to the calibration module, the effective position calculation module and the effective data cache module, and is used to cache the calibrated waveform data, and send a start signal to the effective position calculation module when the number of cached data is greater than a set threshold number; and read the effective data corresponding to the effective position from the cached data according to the received read enable signal, and send the read effective data to the effective data cache module for caching; The effective position calculation module is connected to the effective coefficient generation module, and is used to calculate according to the set step and initial phase after receiving the start signal, obtain effective position information and send it to the effective coefficient generation module, and send a read enable signal to the input waveform data cache module; The effective coefficient generation module is connected to the data calculation module and the effective data cache module, and is used to read coefficients from the pre-stored multiple sets of coefficients according to the effective position information, obtain effective coefficients and send them to the data calculation module, and send a data read enable signal to the effective data cache module; The effective data cache module is connected to the data calculation module and is used to read the cached effective data and send it to the data calculation module according to the received data read enable signal; The data calculation module is connected to the first communication module and is used to perform convolution calculation according to the received effective coefficients and effective data to obtain a reconstructed waveform and send it to the first communication module.

7. The signal receiving device according to claim 6, characterized in that: The effective data cache module stores the effective data in parallel into continuous internal cache units using a shifting method; and / or the effective coefficient generation module reads out two adjacent groups of coefficients according to the integer position information of the effective position information, and calculates the two groups of coefficients read using a linear interpolation algorithm according to the decimal position information of the effective position information to obtain effective coefficients.

8. The signal receiving device according to claim 6, characterized in that: The data calculation module performs convolution calculation according to the received effective coefficients and effective data, including: ； Among them, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the valid coefficient corresponding to the valid position of the reconstruction point, and DATA_IN represents the valid data corresponding to the valid position.

9. The signal receiving device according to claim 2, characterized in that: The waveform receiving module comprises: A receiving control module, connected to the second communication module and the read-write control module, configured to receive the reconstructed waveform through the second communication module and send a write request instruction to the read-write control module; The read-write control module is connected to the storage module and is used to store the reconstructed waveform into the storage module according to the write request instruction.

10. The signal receiving device according to claim 2, characterized in that: The sub-test unit further includes a first service decoding module, which is connected to the host computer, the digital waveform collector and the external clock chip, and performs parameter configuration on the digital waveform collector and the external clock chip according to instructions issued by the host computer; and / or The main test unit also includes a second business decoding module, which is connected to the host computer and the waveform receiving module, configures parameters of the waveform receiving module according to instructions issued by the host computer, and performs waveform reading operations on the storage module through the waveform receiving module.

11. A signal receiving method, characterized in that: include: The external clock chip in the sub-test unit outputs a fixed frequency sampling clock to the analog-to-digital conversion device; The digital waveform collector in the sub-test unit receives the original waveform of the fixed frequency output by the analog-to-digital conversion device according to the sampling clock, resamples the original waveform, generates a required reconstructed waveform of any frequency and sends it to the first communication module in the sub-test unit; wherein the digital waveform collector calculates the effective position information according to the configured parameters, determines the effective coefficient based on the effective position information and reads the effective data corresponding to the effective position from the original waveform, and then convolves the effective coefficient and the read effective data to obtain the reconstructed waveform; The second communication module in the main test unit receives the reconstructed waveform and sends it to the waveform receiving module in the main test unit; The waveform receiving module stores the received reconstructed waveform into the storage module in the main test unit.

12. An analog-digital hybrid test board, characterized in that: A signal receiving device comprising any one of claims 1-10.

13. A testing machine, characterized in that: It comprises a communication board, a backplane and the analog-digital hybrid test board card as claimed in claim 12.

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