Semiconductor structure and method for manufacturing the same

Abstract

The embodiment of the present disclosure provides a semiconductor structure, including: a substrate; a first dielectric layer disposed on the substrate, which has a first surface away from the substrate; a first bonding pad passing through the first surface and extending to a first depth below the first surface; a second bonding pad passing through the first surface and extending to a second depth below the first surface, the second depth being less than the first depth; a second dielectric layer disposed on the first surface, a first gap and a second gap being disposed in the second dielectric layer, the first gap exposing the top surface of the first bonding pad, and the second gap exposing the top surface of the second bonding pad. The surface depression values ​​of the first bonding pad and the second bonding pad relative to the second dielectric layer in the semiconductor structure provided by the embodiment of the present disclosure are kept consistent by controlling the thickness of the second dielectric layer, thereby avoiding the use of a high-precision surface flattening process.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As the demand for data capacity continues to grow rapidly, increasing packaging density to improve integration and thereby obtain higher storage capacity has become an important goal of integrated circuit manufacturing at this stage. Under this prospect, 3D-IC (three-dimensional integrated circuit) technology has been widely used. It is a technology that stacks and bonds wafers with the same or different functions together. This technology has the advantages of high performance, low cost and high integration.

[0003] Hybrid bonding is a key process in 3D packaging technology, which is used to stack multiple wafers or chips in the vertical direction and realize electrical connection. This technology can significantly improve the integration density of chips, shorten the signal transmission path, reduce power consumption, and reduce the package volume. It is an important technology in the fields of high-performance computing, storage and mobile devices. The high-quality treatment of the bonding surface during the bonding process directly affects the yield of the bonding process. For example, in order to ensure that the metal pads on the bonding surface expand at the same height during the bonding process, the surface flattening process is extremely demanding, otherwise there will be poor bonding between the surfaces bonded to each other. Summary of the invention

[0004] The disclosed embodiments provide a semiconductor structure with a higher bonding yield and a method for manufacturing the same.

[0005] Problems to be solved by the technical spirit of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] Some embodiments of the present disclosure provide a semiconductor structure, including: a substrate; a first dielectric layer disposed on the substrate, the first dielectric layer having a first surface away from the substrate; a first bonding pad, the first bonding pad passing through the first surface and extending to a first depth below the first surface; a second bonding pad, the second bonding pad passing through the first surface of the first dielectric layer and extending to a second depth below the first surface, the second depth being less than the first depth; a second dielectric layer, the second dielectric layer being disposed on the first surface, a first gap and a second gap being disposed in the second dielectric layer, the first gap exposing a top surface of the first bonding pad, and the second gap exposing a top surface of the second bonding pad.

[0007] In a semiconductor structure provided by some embodiments of the present disclosure, a top surface of the first bonding pad and a top surface of the second bonding pad are flush with the first surface.

[0008] In a semiconductor structure provided by some embodiments of the present disclosure, a surface area of ​​a top surface of a first bonding pad exposed by a first gap is smaller than a surface area of ​​a top surface of a second bonding pad exposed by a second gap.

[0009] In a semiconductor structure provided by some embodiments of the present disclosure, the first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the first thickness is greater than the second thickness.

[0010] A semiconductor structure provided by some embodiments of the present disclosure also includes: a first interconnect structure and a second interconnect structure arranged in the first dielectric layer, the bottom surface of the first bonding pad is connected to the first conductive layer through the first interconnect structure, and the bottom surface of the second bonding pad is connected to the second conductive layer through the second interconnect structure.

[0011] In a semiconductor structure provided by some embodiments of the present disclosure, a top surface of the first conductive layer and a top surface of the second conductive layer are at different horizontal planes.

[0012] Some embodiments of the present disclosure also provide a semiconductor structure, including: a substrate; a first dielectric layer arranged on the substrate, the first dielectric layer having a first surface away from the substrate; a first bonding pad, the first bonding pad passes through the first surface and extends to a first depth below the first surface; a second bonding pad, the second bonding pad passes through the first surface and extends to a second depth below the first surface, the second depth is less than the first depth; a second dielectric layer, the second dielectric layer is arranged on the first surface, the first bonding pad and the second bonding pad also extend into the second dielectric layer respectively, and the first bonding pad and the second bonding pad have the same extension depth in the second dielectric layer.

[0013] In a semiconductor structure provided by some embodiments of the present disclosure, a top surface of a first bonding pad and a top surface of a second bonding pad are exposed to a top surface of a second dielectric layer, and a surface area of ​​the top surface of the first bonding pad is smaller than a surface area of ​​a top surface of the second bonding pad.

[0014] In a semiconductor structure provided by some embodiments of the present disclosure, a top surface of the first bonding pad is flush with a top surface of the second bonding pad.

[0015] A semiconductor structure provided by some embodiments of the present disclosure further includes: a first conductive layer and a second conductive layer disposed in a substrate, the first conductive layer connected to a bottom surface of the first bonding pad, and the second conductive layer connected to a bottom surface of the second bonding pad.

[0016] Some embodiments of the present disclosure also provide a semiconductor structure, including: a first substrate; a first dielectric layer disposed on the first substrate, the first dielectric layer having a first surface away from the first substrate; a first bonding pad, the first bonding pad passing through the first surface and extending to a first depth below the first surface; a second bonding pad, the second bonding pad passing through the first surface and extending to a second depth below the first surface, the second depth being less than the first depth; a second dielectric layer, the second dielectric layer being disposed on the first surface, the first bonding pad and the second bonding pad also extending into the second dielectric layer respectively, the first bonding pad and the second bonding pad extending to the same depth in the second dielectric layer, the surface area of ​​the top surface of the first bonding pad being less than the surface area of ​​the top surface of the second bonding pad; a second substrate, the second substrate being disposed on the second substrate There is a third dielectric layer, the third dielectric layer has a second surface away from the second substrate; a third bonding pad, the third bonding pad passes through the second surface and extends to a third depth below the second surface; a fourth bonding pad, the fourth bonding pad passes through the second surface and extends to a fourth depth below the second surface, the fourth depth is less than the third depth; a fourth dielectric layer, the fourth dielectric layer is arranged on the second surface, the third bonding pad and the fourth bonding pad also extend into the fourth dielectric layer respectively, the third bonding pad and the fourth bonding pad have the same extension depth in the fourth dielectric layer, the surface area of ​​the top surface of the first bonding pad is less than the surface area of ​​the top surface of the second bonding pad; the first bonding pad is aligned and bonded with the third bonding pad, the second bonding pad is aligned and bonded with the fourth bonding pad, and the second dielectric layer is aligned and bonded with the fourth dielectric layer.

[0017] Some embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, including: providing a substrate; forming a first dielectric layer on the substrate, the first dielectric layer having a first surface away from the substrate, patterning the first dielectric layer, forming a first groove having a first depth and a second groove having a second depth below the first surface, the second depth being less than the first depth; filling the first groove and the second groove to form a first bonding pad and a second bonding pad, respectively; forming a second dielectric layer covering the first surface and the top surface of the first bonding pad and the top surface of the second bonding pad; etching the second dielectric layer to form a first gap exposing the top surface of the first bonding pad and a second gap exposing the top surface of the second bonding pad in the second dielectric layer.

[0018] In a method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure, the steps of patterning a first dielectric layer and forming a first groove having a first depth and a second groove having a second depth below a first surface include: forming a first mask layer on the first surface, patterning the first mask layer, forming a first mask pattern in the first mask layer, etching downward along the first mask pattern, and forming a first initial groove below the first surface; forming a second mask layer on the first dielectric layer, patterning the second mask layer, forming a second mask pattern in the second mask layer, etching the first dielectric layer along the second mask pattern and the first initial groove, and forming a second groove and a first groove in the first dielectric layer, respectively.

[0019] In a method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure, the steps of filling a first trench and a second trench to respectively form a first bonding pad and a second bonding pad include: forming an initial conductive layer covering the first trench and the second trench, the initial conductive layer simultaneously covering the first surface; flattening the initial conductive layer, and forming a first bonding pad and a second bonding pad flush with the first surface in the first trench and the second trench, respectively, wherein an area of ​​a top surface of the first bonding pad exposed by the first gap is larger than an area of ​​a top surface of the second bonding pad exposed by the second gap.

[0020] In a method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure, before patterning the first dielectric layer, a first conductive layer and a second conductive layer are formed in a substrate, and when the first dielectric layer is etched to form a first groove and a second groove, the first conductive layer is exposed at the bottom of the first groove, and the second conductive layer is exposed at the bottom of the second groove.

[0021] In a method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure, before patterning the first dielectric layer, a first conductive layer and a second conductive layer are formed in a substrate, and when etching the first dielectric layer to form the first groove and the second groove, a first interconnect groove and a second interconnect groove are also formed, the top of the first interconnect groove is connected to the bottom of the first groove, the bottom of the first interconnect groove exposes the first conductive layer, the top of the second interconnect groove is connected to the bottom of the second groove, and the bottom of the second interconnect groove exposes the second conductive layer.

[0022] In a method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure, after forming a first gap and a second gap, a bonding process is performed so that the first bonding pad fills the first gap and the second bonding pad fills the second gap.

[0023] In the semiconductor structure provided by the embodiment of the present disclosure, the top surfaces of the first bonding pad and the second bonding pad are exposed by the first gap and the second gap in the second dielectric layer, respectively, that is, for the first bonding pad and the second bonding pad, the surface depression values ​​relative to the second dielectric layer are uniformly determined by the thickness of the second dielectric layer itself, that is, the surface depression values ​​of the first bonding pad and the second bonding pad can be made the same by controlling the thickness of the second dielectric layer. Thus, it is possible to avoid using a high-precision surface flattening process to control the surface depression values ​​of the first bonding pad and the second bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the embodiments of the present disclosure, and together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0025] Figure 1-Figure 13A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure.

[0026] Fig.14 A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.

[0027] Figure 15-Figure 21 A schematic cross-sectional view of a semiconductor structure corresponding to corresponding steps in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.

[0028] The above drawings show clear embodiments of the present disclosure, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for ease of description, only relevant parts are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

[0030] When a bonding layer is formed above a semiconductor element using a hybrid bonding technique, it generally includes forming a dielectric layer and forming a bonding pad embedded in the dielectric layer. The process of forming the dielectric layer and the bonding pad is accompanied by performing a surface planarization process, such as chemical mechanical polishing (CMP) to remove additional materials on the surface of the bonding layer, and obtain a flat bonding layer surface. The semiconductor element after forming the bonding layer can be prepared to be directly connected to another semiconductor element or device without using an intermediate adhesive. Due to the thermal expansion mismatch between the bonding pad and the dielectric layer in the bonding layer, stress mismatch occurs, for example, the bonding pad is subjected to tensile stress and the dielectric layer material is subjected to compressive stress. This phenomenon of uneven stress can cause deformation and / or warping of semiconductor elements (such as device dies or chips, wafers) due to stress concentration. Therefore, it is necessary to continuously reduce the stress in the bonding layer and control the deformation of semiconductor elements.

[0031] In order to reduce the stress and deformation in the bonding layer caused by the thermal expansion mismatch between the bonding pad and the dielectric layer, in some embodiments, by setting the virtual bonding pad (non-functional bonding pad) and the active bonding pad (functional bonding pad) to be relatively evenly distributed in the dielectric layer, the purpose is to overcome the above stress and deformation by making the distribution of the bonding pad in the dielectric layer more uniform. This is because if the two materials are evenly distributed with each other, the expansion of one material can be absorbed or offset by the contraction of the other material, thereby reducing or controlling the tensile stress and compressive stress. It can be seen that the uniform or nearly uniform distribution of the bonding pad (including the virtual bonding pad and the active bonding pad) in the dielectric layer helps to alleviate the stress caused by the thermal expansion mismatch and reduce deformation. In addition, in order to ensure that all bonding pads are highly consistent after thermal expansion, the surface flattening process is also very demanding, and the surface depression value of each bonding pad needs to be accurately controlled within a very small window, such as the nanometer level. At the same time, in order to make each bonding pad obtain the same surface depression value, the size of the bonding pads must be designed to be the same, which limits the freedom of design. For example, when bonding pads of different areas are needed to meet the requirements of the current density, it can only be achieved by increasing the number of bonding pads. In addition, the additional virtual bonding pads increase the metal density in the bonding layer. The increase in metal density also brings additional challenges to controlling the warpage of semiconductor components. At the same time, too high metal density will also lead to a smaller dielectric layer area, weaker wafer bonding strength, and increased risk of slippage during the bonding process.

[0032] At least based on the above problems, there is a motivation to use simpler and more efficient bonding layer structure design and process to reduce the bonding difficulty and improve the process yield. Figure 1 Schematic cross-sectional view of a semiconductor structure provided by some embodiments of the present disclosure. Figure 1 The embodiments of the present disclosure are described in detail.

[0033] like Figure 1 As shown, the semiconductor structure includes a substrate 10, in which a semiconductor device 20 is disposed. A first dielectric layer 50 is disposed on the substrate 10, and the first dielectric layer 50 has a first surface 51 away from the substrate 10. A first bonding pad 70 is disposed in the first dielectric layer 50, and extends through the first surface 51 of the first dielectric layer 50 to below the first surface 51, and has a first depth D1 below the first surface 51. A second bonding pad 71 is disposed in the first dielectric layer 50, and extends through the first surface 51 of the first dielectric layer 50 to below the first surface 51, and has a second depth D2 below the first surface 51. The second depth D2 is less than the first depth D1.

[0034] The semiconductor structure further includes: a second dielectric layer 60, the second dielectric layer 60 is disposed on the first surface 51 of the first dielectric layer 50, a first gap 601 and a second gap 602 are disposed in the second dielectric layer 60, the first gap 601 exposes the top surface 701 of the first bonding pad 70, and the second gap 602 exposes the top surface 711 of the second bonding pad 71. In some embodiments, the top surface 701 of the first bonding pad 70 is flush or substantially flush with the top surface 711 of the second bonding pad 71.

[0035] In some embodiments, the substrate 10 may be a silicon substrate wafer, a substrate wafer with an epitaxial layer (epi-layer), or a silicon-on-insulator (SOI) substrate wafer. In some embodiments, the substrate 10 may also be a part of a wafer, such as a die or a chip.

[0036] In some embodiments, the semiconductor device 20 may be a CMOS device, a memory device and / or other passive devices, the memory device may include a volatile memory or a non-volatile memory, etc., and the volatile memory may include a DRAM, etc. In some embodiments, when the semiconductor device 20 is a DRAM memory device, it may be a storage element consisting of a transistor and a capacitor, or a collection of multiple storage elements.

[0037] In some embodiments, the first dielectric layer 50 can be a single dielectric layer formed of one dielectric or a composite dielectric layer composed of multiple dielectrics. The second dielectric layer 60 can also be a single dielectric layer formed of one dielectric or a composite dielectric layer composed of multiple dielectrics. In some embodiments, the first dielectric layer 50 and the second dielectric layer 60 are both single dielectric layers formed of one dielectric; in other embodiments, the first dielectric layer 50 is a multi-layer dielectric layer formed of multiple dielectrics, and the second dielectric layer 60 is a single dielectric layer formed of one dielectric. The first dielectric layer 50 and the second dielectric layer 60 can contain the same dielectric material or different dielectric materials. In some embodiments, the second dielectric layer 60 is a dielectric layer that can be used for low-temperature direct bonding. In some embodiments, the first dielectric layer 50 includes an oxide, such as silicon oxide. "Silicon oxide" is referred to herein as a compound containing silicon and oxygen atoms, including any and all stoichiometric possibilities of Si. x O y , x and y can be integers or non-integers. The second dielectric layer 60 includes oxide or nitride, such as silicon oxide or silicon nitride (Si3N4), silicon carbonitride (SiCN), silicon oxynitride (SiON), etc. In some embodiments, the first dielectric layer 50 includes Si x O y , the second dielectric layer 60 includes SiCN. In some embodiments, the first dielectric layer 50 includes Si x O y The second dielectric layer 60 comprises SiCN.

[0038] In the above embodiments, the first bonding pad 70 and the second bonding pad 71 are bonding pads for subsequent direct bonding of the semiconductor structure, such as copper-containing metal pads or other bonding pads that can be used for low-temperature direct bonding. The first bonding pad 70 can be an active bonding pad, which is at least electrically connected to the semiconductor device 20. The second bonding pad 71 can be a virtual bonding pad, which is arranged in the first dielectric layer 50 and does not establish an electrical connection with the semiconductor device 20. In some embodiments, in the first dielectric layer 50 per unit area, the density of the first bonding pad 70 and the second bonding pad 71 is different, and the number of the first bonding pads 70 can be greater than the number of the second bonding pads 71. In some embodiments, the number of the first bonding pads 70 can also be less than the number of the second bonding pads 71.

[0039] In the above embodiment, the first gap 601 and the second gap 602 may completely expose the top surface 701 of the first bonding pad 70 and the top surface 711 of the second bonding pad 71. In some embodiments, the first gap 601 and the second gap 602 may also expose part of the top surface of the first bonding pad 70 and the second bonding pad 71.

[0040] Continue to see Figure 1In some embodiments, the semiconductor structure further includes an interlayer insulating layer 30 disposed on the substrate 10, wherein the interlayer insulating layer 30 is provided with a multilayer metal wiring connected to the semiconductor device 20, wherein the multilayer metal wiring includes a first conductive layer 40, and the first bonding pad 70 is electrically connected to the semiconductor device 20 through the first conductive layer 40. In some embodiments, the first conductive layer 40 may be the topmost metal wiring in the multilayer metal wiring, or may be a metal wiring next to the topmost metal wiring. In some embodiments, the bottom surface of the first bonding pad 70 is directly connected to the first conductive layer 40.

[0041] Some embodiments of the present disclosure also provide a semiconductor structure such as Figure 2 As shown, Figure 2 A schematic cross-sectional view of a semiconductor structure provided by some embodiments of the present disclosure. Figure 1 The difference between the illustrated embodiment is that the first bonding pad 70 and the second bonding pad 71 are both virtual bonding pads, that is, the first bonding pad 70 and the second bonding pad 71 are not electrically connected to the semiconductor device 20. The first bonding pad 70 extends to a first depth D1 below the first surface 51, and the second bonding pad 71 extends to a second depth D2 below the first surface 51, and the first depth D1 is greater than the second depth D2. At this time, an active bonding pad 72 electrically connected to the semiconductor device 20 is also provided in the first dielectric layer 50, and the active bonding pad 72 extends to a depth D3 below the first surface 51. The depth D3 is greater than the first depth D1 and the second depth D2.

[0042] Some embodiments of the present disclosure also provide a semiconductor structure, such as Figure 3 As shown, Figure 3 The schematic cross-sectional view of the semiconductor structure provided by some embodiments of the present disclosure. The interlayer insulating layer 30 also includes a second conductive layer 41. Figure 1 The semiconductor structures of the illustrated embodiments are different in that the first bonding pad 70 and the second bonding pad 71 in the semiconductor structures of these embodiments are both active bonding pads electrically connected to the semiconductor device 20. In these embodiments, the second conductive layer 41 can be a metal wiring layer in the same layer as the first conductive layer 40. That is, the first conductive layer 40 and the second conductive layer 41 are both the topmost metal wiring in the multi-layer metal wiring, and the top surfaces of the first conductive layer 40 and the second conductive layer 40 are in the same horizontal plane. In these embodiments, the bottom surface of the first bonding pad 70 is directly connected to the first conductive layer 40, and the bottom surface of the second bonding pad 71 is connected to the second conductive layer 41 through the second interconnect structure 712.

[0043] Some embodiments of the present disclosure also provide a semiconductor structure, such as Figure 4 As shown, Figure 4 A schematic cross-sectional view of a semiconductor structure provided by some embodiments of the present disclosure. Figure 3The difference between the illustrated embodiments is that the first bonding pad 70 in the semiconductor structure in these embodiments is electrically connected to the first conductive layer 40 through the first interconnect structure 702 .

[0044] exist Figure 3 and Figure 4 In the illustrated embodiment, the first interconnect structure 702 and the second interconnect structure 712 may be made of the same conductive material as the first bonding pad 70 and the second bonding pad 71 , for example, both are copper-containing metals.

[0045] In some embodiments, the first interconnect structure 702 may be formed only in the interlayer insulating layer 30 , and the second interconnect structure 701 may be formed in both the first dielectric layer 50 and the interlayer insulating layer 30 .

[0046] Some embodiments of the present disclosure also provide a semiconductor structure, such as Figure 5 As shown, Figure 5 Schematic cross-sectional view of a semiconductor structure provided by some embodiments of the present disclosure. In these embodiments, the multilayer metal wiring includes a first conductive layer 40 and a second conductive layer 41, and the first conductive layer 40 and the second conductive layer 41 are metal wirings of different layers, that is, the top surfaces of the two are at different horizontal planes. For example, the first conductive layer 40 is the second top metal wiring, and the second conductive layer 41 is the top metal wiring. In these embodiments, the first bonding pad 70 is connected to the first conductive layer 40, and the second bonding pad 71 is connected to the second conductive layer 41. The bottom surface of the first bonding pad 70 can be directly or indirectly connected to the first conductive layer 40, and the bottom surface of the second bonding pad 71 can also be directly or indirectly connected to the second conductive layer 41. When the bottom surface of the first bonding pad 70 is directly connected to the first conductive layer 40, the first bonding pad 70 has a portion extending into the interlayer insulating layer 30, and its first depth D1 below the first surface 51 includes the depth extending in the first dielectric layer 50 and the depth extending in the interlayer insulating layer 30. When the bottom surface of the second bonding pad 71 is directly connected to the second conductive layer 41, the second bonding pad 71 may also have a portion extending into the interlayer insulating layer 30. In this case, the second depth D2 of the second bonding pad 71 below the first surface 51 includes the depth extending in the first dielectric layer 50 and the depth extending in the interlayer insulating layer 30. In some embodiments, the second bonding pad 71 can be directly connected to the second conductive layer 41 by simply extending through the first dielectric layer 50. The specific connection method is not described in detail. Figure 5 In other embodiments, the first bonding pad 70 and the second bonding pad 71 can also be connected by means of Figure 4 The first interconnect structure 702 and the second interconnect structure 712 are shown to achieve electrical connection with the first conductive layer 40 and the second conductive layer 41 .

[0047] In each semiconductor structure provided in the above embodiments, the top surfaces of the first bonding pad 70 and the second bonding pad 71 are exposed by the first gap 601 and the second gap 602 located in the second dielectric layer 60, respectively, that is, for the first bonding pad 70 and the second bonding pad 71, their surface depression values ​​relative to the second dielectric layer 60 are uniformly determined by the thickness of the second dielectric layer 60 itself, and the surface depression values ​​of the first bonding pad 70 and the second bonding pad 71 can be made the same by controlling the thickness of the second dielectric layer 60, thereby avoiding the use of a high-precision surface flattening process to control the surface depression values ​​of the first bonding pad 70 and the second bonding pad 71.

[0048] Continue to see Figures 1 to 5 In other embodiments, the top surface 701 of the first bonding pad 70 and the top surface 711 of the second bonding pad 71 are flush or substantially flush with the first surface 51 of the first dielectric layer 50. In the embodiments of the present disclosure, the top surface 701 of the first bonding pad 70 and the top surface 711 of the second bonding pad 71 are pre-controlled to be flush or substantially flush with the first surface 51 of the first dielectric layer 50, thereby ensuring that the first bonding pad 70 and the second bonding pad 71 have the same surface depression value relative to the second dielectric layer 60.

[0049] Continue to see Figures 1 to 5 In some embodiments, the surface area of ​​the top surface 701 of the first bonding pad 70 exposed by the first gap 601 is smaller than the surface area of ​​the top surface 711 of the second bonding pad 71 exposed by the second gap 602. In these embodiments, the first gap 601 completely exposes the top surface 701 of the first bonding pad 70, and the second gap 602 completely exposes the top surface 711 of the second bonding pad 71. That is, the size of the top surface 701 of the first bonding pad 70 in the horizontal plane is smaller than the size of the top surface 711 of the second bonding pad 71 in the horizontal plane. In these embodiments, by providing the first bonding pad 70 and the second bonding pad 71 with different surface areas, and controlling the first bonding pad 70 and the second bonding pad 71 to have different extension depths, and by controlling the relationship between the two, the first bonding pad 70 and the second bonding pad 71 can obtain the same expansion amount during the subsequent bonding process, and the expansion amount of the first bonding pad 70 and the second bonding pad 71 is filled into the first gap 601 and the second gap 602, thereby achieving equal expansion of the first bonding pad 70 and the second bonding pad 71. In some embodiments, the second bonding pad 72 with a relatively large surface area can be an active bonding pad that requires a high flow density.

[0050] Continue to see Figures 1 to 5In some embodiments, the first dielectric layer 50 has a first thickness, the second dielectric layer 60 has a second thickness, and the first thickness is greater than the second thickness. In some embodiments, the ratio of the first thickness to the second thickness may be in the range of 100 to 2000. For example, the first thickness may be in the range of 2 micrometers to 100 nanometers, and the second thickness may be in the range of 5 nanometers to 0.5 nanometers.

[0051] Continue to see Figure 3 and Figure 4 In some embodiments, the first interconnect structure 702 and / or the second interconnect structure 712 are smaller than the first bonding pad 70 and the second bonding pad 70. The size here can be a physical quantity such as the extension depth, width, top surface area, etc. of the first interconnect structure 702 and / or the second interconnect structure 712.

[0052] The semiconductor structure provided by the above-mentioned embodiments provides the gap required for the expansion of each bonding pad through the second dielectric layer, thereby reducing the difficulty of the flattening process for forming the concave value of the bonding pad surface; each bonding pad can be designed to have different sizes, and the bonding pads with different surface areas can be controlled to have corresponding depths to ensure that the bonding pads with different surface areas can expand to the same height during the temperature increase expansion process, and then a combination of large and small bonding pads can be designed, because the bonding pads with larger surface areas show good application prospects in terms of current density, bonding strength, heat dissipation, etc. In addition, the semiconductor structure provided by the embodiments of the present disclosure can also reduce the number of virtual bonding pads and reduce the metal content of the bonding surface, which will be beneficial to controlling the warping of the semiconductor structure and increasing the stability of the bonding process.

[0053] Some embodiments of the present disclosure also provide other semiconductor structures. Figures 6 to 10 , Figures 6 to 10 A schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure. Figures 1 to 5 After the semiconductor structure shown in the figure is formed, a bonding process is performed. During this process, the first bonding pad 70 and the second bonding pad 71 will expand due to heat, thereby filling the first gap 601 and the second gap 602, and finally forming the following structures: Figures 6 to 10 Schematic diagram of a semiconductor structure. Figure 1 The semiconductor structure shown is formed after bonding process. Figure 6 The semiconductor structure shown, Figure 2 The semiconductor structure shown is formed after bonding process. Figure 7 The semiconductor structure shown, Figure 3 The semiconductor structure shown is formed after bonding process. Figure 8 The semiconductor structure shown, Figure 4 The semiconductor structure shown is formed after bonding process. Fig. 9 The semiconductor structure shown, Figure 5The semiconductor structure shown is formed after bonding process Fig.10 The semiconductor structure shown. In these semiconductor structures, the first bonding pad 70 and the second bonding pad 71 are extended into the second dielectric layer 60 respectively after expansion, and the first bonding pad 70 and the second bonding pad 71 are extended to the same depth in the second dielectric layer 60, so that the top surfaces 701 and 711 of the first bonding pad 70 and the second bonding pad 71 are flush after expansion. Finally, the extension depth of the first bonding pad 70 is D1', and the extension depth of the second bonding pad 71 is D2'. Figure 7 In the semiconductor structure shown, the active bonding pad 72 also extends into the second dielectric layer 60 after expansion, and the extension depth is D3 ′.

[0054] In some embodiments, the surface area of ​​the top surface 701 of the expanded first bonding pad 70 is smaller than the surface area of ​​the top surface 711 of the second bonding pad 71 .

[0055] The other parts of the semiconductor structure after bonding are the same as Figures 1 to 5 The illustrated semiconductor structure and its corresponding embodiments are not described in detail here.

[0056] Some embodiments of the present disclosure also provide a semiconductor structure such as Figures 11 to 13 As shown, Figures 11 to 13 Schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure. Fig.11 As shown, the semiconductor structure includes a first substrate 10 and a second substrate 11, a semiconductor device 20 is arranged in the first substrate 10, an interlayer insulating layer 30 is arranged above the first substrate 10, and a multi-layer metal wiring connected to the semiconductor device 20 is arranged in the interlayer insulating layer 30, including a first conductive layer 40. A first dielectric layer 50 is arranged on the interlayer insulating layer 30, a second dielectric layer 60 is arranged on the first dielectric layer 50, a first bonding pad 70 and a second bonding pad 71 extend through the first surface 51 of the first dielectric layer 50 and extend into the second dielectric layer 60, the first bonding pad 70 extends below the first surface 51 of the first dielectric layer 50 to a first depth D1, and the second bonding pad 71 extends below the first surface 51 of the first dielectric layer 50 to a second depth D2, and D2 is less than D1. The first bonding pad 70 extends to be electrically connected to the first conductive layer 40, and the second bonding pad 71 is not electrically connected to the first conductive layer 40. The first bonding pad 70 and the second bonding pad 71 extend to the same depth in the second dielectric layer 60, so that the top surfaces of the first bonding pad 70 and the second bonding pad 71 are flush or substantially flush with the top surface of the second dielectric layer 60. The surface area of ​​the top surface of the first bonding pad 70 is smaller than the surface area of ​​the top surface of the second bonding pad 71.

[0057] The second substrate 11 includes a semiconductor device 21 disposed therein and an interlayer insulating layer 31 disposed on the second substrate 11. The interlayer insulating layer 31 has a multilayer metal wiring connected to the semiconductor device 21, including a conductive layer 42. A third dielectric layer 52 is disposed on the interlayer insulating layer 31, and a fourth dielectric layer 61 is disposed on the third dielectric layer 52. A third bonding pad 73 and a fourth bonding pad 74 extend through the second surface 53 of the third dielectric layer 52 and extend into the fourth dielectric layer 61. The third bonding pad 73 extends below the second surface 53 of the third dielectric layer 52 to a third depth D4, and the fourth bonding pad 74 extends below the second surface 53 of the third dielectric layer 52 to a fourth depth D5, where D5 is less than D4. The third bonding pad 73 extends to be electrically connected to the conductive layer 42, and the fourth bonding pad 74 is not electrically connected to the conductive layer 42. The third bonding pad 73 and the fourth bonding pad 74 extend to the same depth in the fourth dielectric layer 61, so that the top surfaces of the third bonding pad 73 and the fourth bonding pad 74 are flush or substantially flush with the top surface of the fourth dielectric layer 61. The surface area of ​​the top surface of the third bonding pad 73 is smaller than the surface area of ​​the top surface of the fourth bonding pad 74.

[0058] The first bonding pad 70 is aligned and bonded with the third bonding pad 73 , the second bonding pad 71 is aligned and bonded with the fourth bonding pad 74 , and the second dielectric layer 60 is aligned and bonded with the fourth dielectric layer 61 , thereby forming the semiconductor structure of the embodiment of the present disclosure.

[0059] In some embodiments, the semiconductor device 20 and the semiconductor device 21 may be the same semiconductor device or different semiconductor devices. The first substrate 10 and the second substrate 11 may be substrate wafers of the same type or different types.

[0060] In some embodiments, the first bonding pad 70 and the third bonding pad 73 may not be electrically connected to the conductive layer. Fig.12 As shown. Fig.11 The difference is that, at this time, the first bonding pad 70 and the third bonding pad 73 are both virtual bonding pads. At this time, the first substrate 10 and the second substrate 11 are electrically connected through the bonded active bonding pad 72 and the active bonding pad 75 .

[0061] In some embodiments, the first bonding pad 70, the second bonding pad 71, the third bonding pad 73 and the fourth bonding pad 74 are each connected to a corresponding conductive layer, such as Fig.13 As shown. Fig.12The difference is that, at this time, the first bonding pad 70, the second bonding pad 71, the third bonding pad 73 and the fourth bonding pad 74 are all active bonding pads, the first bonding pad 70 is connected to the first conductive layer 40, the second bonding pad 71 is connected to the second conductive layer 41, the third bonding pad 73 is connected to the conductive layer 42, and the fourth bonding pad 74 is connected to the conductive layer 43. The conductive layer 42 and the conductive layer 43 can be metal wirings of the same layer or metal wirings of different layers. Fig.13 The case where each conductive layer is a metal wiring of a different layer is shown.

[0062] In the semiconductor structures provided by the above embodiments, each bonding pad in the first substrate and the second substrate can achieve a good surface bonding effect, and the sizes of each bonding pad can be set to be different, thereby improving the flexibility of the bonding pad design.

[0063] In some embodiments, each bonding pad in each substrate has more design forms, which can be specifically referred to in Figure 3 and Figure 4 The semiconductor structure thus formed is also included in the present disclosure and will not be described in detail here.

[0064] Some embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, which is now described in detail with reference to the corresponding drawings.

[0065] See also Fig.14 , Fig.14 A flow chart for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes:

[0066] Step S101 is performed to provide a substrate. Fig.15 As shown, a substrate 10 is provided, in which a semiconductor device 20 is arranged, and an interlayer insulating layer 30 is also arranged on the substrate 10, and a multi-layer metal wiring is arranged in the interlayer insulating layer 30, including a first conductive layer 40. The substrate 10 can be a silicon substrate wafer, or a substrate wafer with an epitaxial layer, or a silicon substrate wafer on an insulator. In some embodiments, the substrate 10 can also be a part of a wafer, such as a die or a chip. The semiconductor device 20 can be a CMOS device, a memory device and / or other passive devices, and the memory device can include a volatile memory or a non-volatile memory, etc. The volatile memory can include, for example, a DRAM, etc. In some embodiments, when the semiconductor device 20 is a DRAM memory device, it can be a storage element composed of a transistor and a capacitor, or a collection of multiple storage elements.

[0067] Step S102 is performed to form a first dielectric layer on the substrate, wherein the first dielectric layer has a first surface away from the substrate, and the first dielectric layer is patterned to form a first trench having a first depth and a second trench having a second depth below the first surface, wherein the second depth is less than the first depth. Fig.15 A first dielectric layer 50 is formed on the substrate 10, and the first dielectric layer 50 covers the interlayer insulating layer 30. The first dielectric layer 50 has a first surface 51 away from the substrate 10, and the first dielectric layer 50 is patterned, and a first trench 703 with a first depth D1 and a second trench 713 with a second depth D2 are respectively formed below the first surface 51 of the first dielectric layer 50.

[0068] In some embodiments, the steps of patterning the first dielectric layer to form a first trench having a first depth and a second trench having a second depth below the first surface are as follows: Figures 16 to 18 shown. Figures 16 to 18 A schematic cross-sectional view of a semiconductor structure corresponding to corresponding steps in manufacturing the semiconductor structure.

[0069] See first Fig.16 , forming a first mask layer 80 on the first surface 51 of the first dielectric layer 50, patterning the first mask layer 80 by photolithography, etching and other processes, forming a first mask pattern 801 in the first mask layer 80, and the first mask pattern 801 exposes the first surface 51 of the first dielectric layer 50. Fig.17 After forming the first mask pattern 801, the first dielectric layer 50 is etched downward along the first mask pattern 801 to form a first initial trench 802 below the first surface 51 of the first dielectric layer 50. Fig.18 After forming the first initial groove 802, the first mask layer 80 can be removed first, leaving only the first initial groove 802, and then a second mask layer 81 is formed on the first surface 51 of the first dielectric layer 50, and the second mask layer 81 is patterned by photolithography, etching, and the like, and a second mask pattern 810 is formed in the second mask layer 81. In some embodiments, a third mask pattern 803 is also formed in the second mask layer 81, and the third mask pattern 803 exposes the first initial groove 802. After forming the second mask pattern 810 and the third mask pattern 803, etching is performed downward along the second mask layer 81, and finally a second mask pattern 810 is formed. Fig.15 The first groove 703 and the second groove 713.

[0070] Through the above steps, the extension depths and lateral dimensions of the first groove 703 and the second groove 713 can be controlled more flexibly, thereby obtaining bonding pads with different top surface areas.

[0071] Step S103 is performed to fill the first trench and the second trench to form a first bonding pad and a second bonding pad respectively. Fig.19 After forming the first trench 703 and the second trench 713, an initial conductive layer 90 covering the first trench 703 and the second trench 713 is formed on the first surface 51 of the first dielectric layer 50. Fig. 20After the initial conductive layer 90 is formed, the initial conductive layer 90 is planarized to remove the initial conductive layer 90 on the first surface 51 of the first dielectric layer 50, and the initial conductive layer 90 located in the first groove 703 and the second groove 713 is retained, and finally the first bonding pad 70 and the second bonding pad 71 are formed. The process of forming the first bonding pad 70 and the second bonding pad 71 can adopt the Damascus process. In this process, by performing a surface planarization process, such as CMP, the first bonding pad 70, the second bonding pad 71 and the first surface of the first dielectric layer 50 are finally made flush. In this surface planarization process step, there is no need to control the surface depression value of the first bonding pad 70 and the second bonding pad 71, and it is only necessary to achieve that the surfaces are flush with each other, which reduces the difficulty of the planarization process.

[0072] Continue to perform step S104 to form a second dielectric layer covering the first surface and the top surface of the first bonding pad and the top surface of the second bonding pad. Fig.21 After forming the first bonding pad 70 and the second bonding pad 71, a second dielectric layer 60 is formed on the first surface 51 of the first dielectric layer 50 and on the top surfaces of the first bonding pad 70 and the second bonding pad 71. The second dielectric layer 60 can be formed by a thin film deposition process such as chemical vapor deposition (CVD) and atomic layer deposition (ALD), so as to obtain a uniform and dense thin film with a precisely controlled thickness.

[0073] In some embodiments, the first dielectric layer 50 may be Si x O y The second dielectric layer 60 includes oxide or nitride, such as silicon oxide or silicon nitride (Si3N4), silicon carbonitride (SiCN), silicon oxynitride (SiON), etc. In some embodiments, the first dielectric layer 50 includes Si x O y , the second dielectric layer 60 includes SiCN. In some embodiments, the first dielectric layer 50 includes Si x O y The second dielectric layer 60 comprises SiCN.

[0074] Step S105 is performed to etch the second dielectric layer to form a first gap exposing the top surface of the first bonding pad and a second gap exposing the top surface of the second bonding pad in the second dielectric layer. Fig.21 On the basis of the semiconductor structure shown in the figure, after forming the second dielectric layer 60, the second dielectric layer 60 is subjected to a combination of processes such as photolithography and etching to form a first gap 601 and a second gap 602 in the second dielectric layer 60. The final structure is as shown in FIG. Figure 1 shown.

[0075] In the manufacturing method of the semiconductor structure illustrated in the above embodiment, only one surface planarization process is required when forming the first bonding pad and the second bonding pad to make the surfaces of the first bonding pad, the second bonding pad and the first dielectric layer flush, and then a thin film deposition process is used to form a second dielectric layer with a predetermined thickness. There is no need to use a surface planarization process to control the surface depression value of the second dielectric layer and the first bonding pad and the second bonding pad, thereby omitting the expensive and complex surface planarization process steps.

[0076] In some embodiments, the first groove 703 and the second groove 713 can respectively expose the corresponding metal wiring in the interlayer insulating layer 30, and the first bonding pad 70 and the second bonding pad 71 formed finally are respectively connected to the corresponding conductive layer in the multi-layer metal wiring, and the final structure is as follows: Figure 5 In other embodiments, the first groove 703 and the second groove 713 do not expose the corresponding metal wiring in the interlayer insulating layer 30, and the first bonding pad 70 and the second bonding pad 71 formed finally are not connected to the corresponding conductive layer in the multi-layer metal wiring. The final structure is as shown in FIG. Figure 2 shown.

[0077] In some embodiments, before patterning the first dielectric layer, a first conductive layer and a second conductive layer are further formed in the substrate. The configuration of the first conductive layer and the second conductive layer can be seen in Figure 3 and Figure 4 At this time, when etching the first trench 703 and the second trench 713, a first interconnection trench and a second interconnection trench connected to the bottom of the first trench and / or the second trench are formed below the first trench and / or the second trench, and the first interconnection trench and the second interconnection trench expose corresponding conductive layers respectively. For example, the first interconnection trench exposes the first conductive layer, and the second interconnection trench exposes the second conductive layer. When the initial conductive layer is subsequently formed, the initial conductive layer is also filled into the first interconnection trench and / or the second interconnection trench at the same time, and the final structure is as shown in FIG. Figure 3 and Figure 4 The first trench and the first interconnection trench as well as the second trench and the second interconnection trench may be formed by a dual damascene process.

[0078] In some embodiments, after executing step S105, the method further includes: performing a bonding process so that the first bonding pad fills the first gap and the second bonding pad fills the second gap. Figures 6 to 13 The semiconductor structure shown.

[0079] The bonding process is accompanied by a temperature increase process, and the bonding temperature is usually between 200°C and 400°C. After reaching the bonding temperature to achieve preliminary bonding, in order to further enhance the mechanical and electrical connection of the bonding interface, the bonding structure is annealed to improve the reliability and durability of the bonding. During these processes, the first bonding pad and the second bonding pad will expand due to heat, and the expanded part will fill the first gap and the second gap, thereby forming a good bonding interface, and then bonding well with another semiconductor.

[0080] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure comprising: substrate; A first dielectric layer disposed on the substrate, wherein the first dielectric layer has a first surface away from the substrate; a first bonding pad, the first bonding pad passing through the first surface and extending to a first depth below the first surface; a second bonding pad, the second bonding pad passing through the first surface and extending to a second depth below the first surface, the second depth being less than the first depth; a second dielectric layer, the second dielectric layer being disposed on the first surface, a first gap and a second gap being disposed in the second dielectric layer, the first gap completely exposing the top surface of the first bonding pad, and the second gap completely exposing the top surface of the second bonding pad; A top surface of the first bonding pad and a top surface of the second bonding pad are flush with the first surface; A surface area of ​​a top surface of the first bonding pad completely exposed by the first gap is smaller than a surface area of ​​a top surface of the second bonding pad completely exposed by the second gap.

2. The semiconductor structure according to claim 1, characterized in that: The first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the first thickness is greater than the second thickness.

3. The semiconductor structure according to claim 1, characterized in that: Also includes: A first conductive layer and a second conductive layer are disposed in the substrate, wherein the first conductive layer is connected to a bottom surface of the first bonding pad, and the second conductive layer is connected to a bottom surface of the second bonding pad.

4. The semiconductor structure according to claim 3, characterized in that: Also includes: A first interconnect structure and a second interconnect structure are arranged in the first dielectric layer, the bottom surface of the first bonding pad is connected to the first conductive layer through the first interconnect structure, and the bottom surface of the second bonding pad is connected to the second conductive layer through the second interconnect structure.

5. The semiconductor structure according to claim 3, characterized in that: A top surface of the first conductive layer and a top surface of the second conductive layer are at different levels.

6. A semiconductor structure comprising: substrate; A first dielectric layer disposed on the substrate, wherein the first dielectric layer has a first surface away from the substrate; a first bonding pad, the first bonding pad passing through the first surface and extending to a first depth below the first surface; a second bonding pad, the second bonding pad passing through the first surface and extending to a second depth below the first surface, the second depth being less than the first depth; a second dielectric layer, wherein the second dielectric layer is disposed on the first surface, the first bonding pad and the second bonding pad further extend into the second dielectric layer respectively, and the first bonding pad and the second bonding pad have the same extension depth in the second dielectric layer; The top surface of the first bonding pad and the top surface of the second bonding pad are completely exposed to the top surface of the second dielectric layer, and the surface area of ​​the top surface of the first bonding pad is smaller than the surface area of ​​the top surface of the second bonding pad; A first conductive layer and a second conductive layer are disposed in the substrate, wherein the first conductive layer is connected to the bottom surface of the first bonding pad, the second conductive layer is connected to the bottom surface of the second bonding pad, and the first conductive layer and the second conductive layer are different layers.

7. The semiconductor structure according to claim 6, characterized in that: A top surface of the first bonding pad is flush with a top surface of the second bonding pad.

8. A semiconductor structure comprising: a first substrate; A first dielectric layer disposed on the first substrate, wherein the first dielectric layer has a first surface away from the first substrate; a first bonding pad, the first bonding pad passing through the first surface and extending to a first depth below the first surface; a second bonding pad, the second bonding pad passing through the first surface and extending to a second depth below the first surface, the second depth being less than the first depth; a second dielectric layer, wherein the second dielectric layer is disposed on the first surface, the first bonding pad and the second bonding pad further extend into the second dielectric layer respectively, the first bonding pad and the second bonding pad have the same extension depth in the second dielectric layer, and the surface area of ​​the top surface of the first bonding pad is smaller than the surface area of ​​the top surface of the second bonding pad; a second substrate, on which a third dielectric layer is disposed, and the third dielectric layer has a second surface away from the second substrate; a third bonding pad, the third bonding pad passing through the second surface and extending to a third depth below the second surface; a fourth bonding pad, the fourth bonding pad passing through the second surface and extending to a fourth depth below the second surface, the fourth depth being less than the third depth; a fourth dielectric layer, wherein the fourth dielectric layer is disposed on the second surface, the third bonding pad and the fourth bonding pad further extend into the fourth dielectric layer respectively, the third bonding pad and the fourth bonding pad have the same extension depth in the fourth dielectric layer, and the surface area of ​​the top surface of the third bonding pad is smaller than the surface area of ​​the top surface of the fourth bonding pad; The first bonding pad is aligned and bonded with the third bonding pad, the second bonding pad is aligned and bonded with the fourth bonding pad, and the second dielectric layer is aligned and bonded with the fourth dielectric layer; A first conductive layer and a second conductive layer are provided between the first substrate and the first dielectric layer, wherein the first conductive layer and the second conductive layer are different layers; Two conductive layers are arranged between the second substrate and the third dielectric layer, wherein the first bonding pad is connected to the first conductive layer, the second bonding pad is connected to the second conductive layer, the third bonding pad is connected to one of the two conductive layers, and the fourth bonding pad is connected to the other of the two conductive layers.

9. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; Forming a first dielectric layer on the substrate, the first dielectric layer having a first surface away from the substrate, patterning the first dielectric layer, forming a first trench having a first depth and a second trench having a second depth below the first surface, wherein the second depth is less than the first depth; Filling the first groove and the second groove to form a first bonding pad and a second bonding pad respectively, wherein the top surface of the first bonding pad and the top surface of the second bonding pad are flush with the first surface; forming a second dielectric layer covering the first surface and the top surface of the first bonding pad and the top surface of the second bonding pad; The second dielectric layer is etched to form a first gap completely exposing the top surface of the first bonding pad and a second gap completely exposing the top surface of the second bonding pad in the second dielectric layer, and the area of ​​the top surface of the first bonding pad completely exposed by the first gap is smaller than the area of ​​the top surface of the second bonding pad completely exposed by the second gap.

10. The manufacturing method according to claim 9, characterized in that: The step of patterning the first dielectric layer to form a first trench having a first depth and a second trench having a second depth below the first surface comprises: forming a first mask layer on the first surface, patterning the first mask layer, forming a first mask pattern in the first mask layer, etching downward along the first mask pattern, and forming a first initial trench below the first surface; A second mask layer is formed on the first dielectric layer, the second mask layer is patterned, a second mask pattern is formed in the second mask layer, the first dielectric layer is etched along the second mask pattern and the first initial groove, and the second groove and the first groove are respectively formed in the first dielectric layer.

11. The manufacturing method according to claim 9, characterized in that: The step of filling the first trench and the second trench to form a first bonding pad and a second bonding pad respectively comprises: forming an initial conductive layer covering the first trench and the second trench, wherein the initial conductive layer also covers the first surface; The initial conductive layer is planarized, and the first bonding pad and the second bonding pad flush with the first surface are formed in the first trench and the second trench, respectively.

12. The manufacturing method according to claim 9, characterized in that: Before patterning the first dielectric layer, a first conductive layer and a second conductive layer are formed in the substrate. When the first dielectric layer is etched to form the first trench and the second trench, the first conductive layer is exposed at the bottom of the first trench, and the second conductive layer is exposed at the bottom of the second trench.

13. The manufacturing method according to claim 9, characterized in that: Before patterning the first dielectric layer, a first conductive layer and a second conductive layer are formed in the substrate, and when the first dielectric layer is etched to form the first groove and the second groove, a first interconnection groove and a second interconnection groove are also formed, the top of the first interconnection groove is connected to the bottom of the first groove, the bottom of the first interconnection groove exposes the first conductive layer, the top of the second interconnection groove is connected to the bottom of the second groove, and the bottom of the second interconnection groove exposes the second conductive layer.

14. The manufacturing method according to claim 9, characterized in that: After forming the first gap and the second gap, a bonding process is performed so that the first bonding pad fills the first gap and the second bonding pad fills the second gap.

Images