Semiconductor Devices

Abstract

The present application provides a semiconductor device, comprising: a semiconductor epitaxial wafer including an active region and an edge terminal region surrounding the active region; a plurality of source regions are arranged in the active region; a gate electrode layer of a first conductive layer is arranged in the active region, and a gate bus layer connected to the gate electrode layer is arranged in the edge terminal region; an interlayer dielectric layer covers the first conductive layer; a second conductive layer is arranged on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least arranged in the active region and electrically connected to the source region; the gate pad is at least arranged in the edge terminal region and electrically connected to the gate bus layer; the first conductive layer also includes a capacitor plate layer, the gate electrode layer and the gate bus layer are both insulated from the capacitor plate layer; the source pad is electrically connected to the capacitor plate layer; a portion of the gate pad is stacked with a portion of the capacitor plate layer and isolated by a dielectric layer, and the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer. The semiconductor device reduces the risk of crosstalk.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] As the core component in power electronics systems, power semiconductor devices have always been an indispensable electronic component in modern life. They are widely used in consumer electronic devices, automotive electronic systems, smart grids, various industrial equipment, power locomotives, aerospace, and ship systems. SiC MOSFET (silicon carbide-based metal oxide semiconductor field effect transistor) devices have the advantages of high input impedance, good temperature stability, excellent high-frequency and high-voltage performance, and a large safe operating area. At present, it has become the mainstream device in the development of high-voltage and high-frequency fields.

[0003] However, existing semiconductor devices are prone to crosstalk. Summary of the invention

[0004] The semiconductor device provided in the present application is intended to solve the problem that crosstalk is prone to occur in existing semiconductor devices.

[0005] In order to solve the above technical problems, the first technical solution adopted by the present application is: providing a semiconductor device, the semiconductor device comprising a semiconductor epitaxial wafer, including an active area and an edge terminal area surrounding the active area;

[0006] A plurality of source regions, arranged in the active region;

[0007] A first conductive layer includes a gate electrode layer and a gate bus layer electrically connected to each other; the gate electrode layer is arranged in the active area, and the gate bus layer is arranged in the edge terminal area;

[0008] an interlayer dielectric layer, covering the first conductive layer;

[0009] A second conductive layer is disposed on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge terminal region and electrically connected to the gate bus layer;

[0010] Among them, the first conductive layer also includes a capacitor plate layer, the gate electrode layer and the gate bus layer are insulated from the capacitor plate layer; the source pad is electrically connected to the capacitor plate layer; part of the gate pad and part of the capacitor plate layer are stacked and isolated by a dielectric layer, and the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer.

[0011] In order to solve the above technical problems, the second technical solution adopted by the present application is: to provide a semiconductor device, the semiconductor device comprising:

[0012] A semiconductor epitaxial wafer, comprising an active region and an edge termination region surrounding the active region;

[0013] A plurality of source regions, arranged in the active region;

[0014] A first conductive layer includes a gate electrode layer and a gate bus layer electrically connected to each other; the gate electrode layer is arranged in the active area, and the gate bus layer is arranged in the edge terminal area;

[0015] an interlayer dielectric layer, covering the first conductive layer;

[0016] A second conductive layer is disposed on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge terminal region and electrically connected to the gate bus layer;

[0017] Part of the gate electrode layer or part of the gate bus layer is stacked with part of the source pad and isolated by a dielectric layer, and the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer.

[0018] In order to solve the above technical problems, the third technical solution adopted by the present application is: to provide a semiconductor device, the semiconductor device comprising:

[0019] A semiconductor epitaxial wafer, comprising an active region and an edge termination region surrounding the active region;

[0020] A plurality of source regions, arranged in the active region;

[0021] A first conductive layer includes a gate electrode layer and a gate bus layer electrically connected to each other; the gate electrode layer is arranged in the active area, and the gate bus layer is arranged in the edge terminal area;

[0022] an interlayer dielectric layer, covering the first conductive layer;

[0023] A second conductive layer is disposed on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge terminal region and electrically connected to the gate bus layer;

[0024] Part of the source pad and part of the gate pad are stacked and isolated by a dielectric layer, thereby forming a gate-source capacitor, and the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer.

[0025] Different from the prior art, the beneficial effect of the present application is that the semiconductor device provided by the present application includes a semiconductor epitaxial wafer, a plurality of source regions, a first conductive layer, an interlayer dielectric layer and a second conductive layer, the semiconductor epitaxial wafer includes an active region and an edge terminal region surrounding the active region; the plurality of source regions are arranged in the active region; the first conductive layer includes a gate electrode layer and a gate bus layer electrically connected to each other; the gate electrode layer is arranged in the active region, and the gate bus layer is arranged in the edge terminal region; the interlayer dielectric layer covers the first conductive layer; the second conductive layer is arranged on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least arranged in the active region and electrically connected to the source region; the gate pad is at least arranged in the edge terminal region and electrically connected to the gate bus layer. Among them, the semiconductor device is made by making the first conductive layer further include a capacitor plate layer, and making the gate electrode layer and the gate bus layer insulated from the capacitor plate layer; the source pad is electrically connected to the capacitor plate layer; part of the gate pad is stacked with part of the capacitor plate layer and isolated by a dielectric layer, so that an additional gate-source capacitor is formed by the gate pad covering part of the capacitor plate layer, the dielectric layer, and the part where the capacitor plate layer and the gate pad are stacked, thereby increasing the ratio of Ciss to Crss to reduce the risk of crosstalk in the semiconductor device. At the same time, the design only involves the change of the gate pad position, which is minor and does not affect the reliability of the active area and the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0027] Figure 1 is an equivalent circuit diagram of a semiconductor device;

[0028] Figure 2 A top view of some embodiments of the semiconductor device provided in the present application;

[0029] Figure 3 for Figure 2 A cross-sectional view of a portion of the structure of the semiconductor device along line AA' shown;

[0030] Figure 4a A schematic diagram of the area division of a semiconductor device;

[0031] Figure 4b for Figure 2 The semiconductor device shown does not include a top view of the second conductive layer;

[0032] Figure 5 for Figure 4b A partial structural cross-sectional view of the structure shown along line AA';

[0033] Figure 6a for Figure 2 Another cross-sectional view of a portion of the structure of the semiconductor device along line AA' shown;

[0034] Figure 6b for Figure 6a The enlarged view of the M in the middle;

[0035] Figure 7 For Figure 6a A schematic structural diagram of a second conductive layer formed on the semiconductor device shown;

[0036] Figure 8 for Figure 2 Another top view of the semiconductor device shown does not include the interlayer dielectric layer and the second conductive layer;

[0037] Fig. 9 for Figure 8 A partial structural cross-sectional view of the structure shown along line BB';

[0038] Fig.10 For Figure 3 A schematic diagram of a structure in which a passivation layer is formed on the structure shown;

[0039] Fig.11 Top views of other embodiments of the semiconductor device provided by the present application;

[0040] Fig.12 An embodiment of the present application provides Fig.11 A partial structural cross-sectional view of the semiconductor device shown along line CC';

[0041] Fig.13 A partial structural cross-sectional view of a semiconductor device along line CC' provided by another embodiment of the present application;

[0042] Fig.14 and Fig.15 A partial structural cross-sectional view of a semiconductor device along line CC' provided in different embodiments of the present application;

[0043] Fig.16 A flowchart of a method for preparing a semiconductor device provided in one embodiment of the present application;

[0044] Fig.17 For semiconductor epitaxial wafer Fig.16A schematic diagram of the structure of some intermediate products after processing in step S2;

[0045] Fig.18 For semiconductor epitaxial wafer Fig.16 A schematic diagram of the structure of some intermediate products after processing in step S3;

[0046] Fig.19 for Fig.18 A partial structural cross-sectional view of the semiconductor device shown along line CC';

[0047] Fig. 20 A top view of a portion of the intermediate product structure of the semiconductor epitaxial wafer after step S5;

[0048] Fig.21 for Fig. 20 A partial structural cross-sectional view of the structure shown along line CC';

[0049] Fig. 22 For semiconductor epitaxial wafer Fig.16 A top view of a portion of the intermediate product structure after processing in step S6;

[0050] Fig.23 for Fig. 22 The structure shown is a partial cross-sectional view along the CC' line.

[0051] Description of Reference Numerals

[0052] 1-semiconductor epitaxial wafer; A1-active area; A2-edge terminal area; A3-annular routing area; A4-pad area; 11-terminal structure; 12-well area; 13-well area contact area; 18-drain electrode; 2-source area; 3-first conductive layer; 31-gate electrode layer; 31a-gate structure; 32-gate bus layer; 33-capacitor plate layer; 4-interlayer dielectric layer; 41-first opening; 42-second opening; 43-third opening; 44-fourth opening; 5-second conductive layer; 51-source pad; 52-gate pad; 6-dielectric layer; 61-opening; 7a-gate insulation layer; 7b-routing insulation layer; 7c-passivation layer; 71-fifth opening; 72-sixth opening. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] The terms "first", "second" and "third" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second" and "third" can explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of this application are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0055] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0056] In actual applications, there are a large number of converters, a large part of which have upper and lower tube structures, such as half-bridge, three-phase full-bridge, three-level, etc. When the active tube performs switching action, its own driving voltage has no obvious oscillation or burrs, while the driving voltage of the synchronous rectifier tube will have burrs. That is to say, in the bridge circuit, the active switching action of the device will affect the Vgs (maximum gate-source voltage) of its opposite tube, and this phenomenon is crosstalk.

[0057] See also Figure 1 , Figure 1 It is an equivalent circuit diagram of a semiconductor device. Among them, Cds (source-drain parasitic capacitance), Cgd (gate-drain parasitic capacitance), Cgs (gate-drain parasitic capacitance) are the junction capacitances of the interfered tube, Rg (int) is the internal resistance of the device gate bus layer, Rg (ext) is the external drive resistance, and the turn-off drive voltage is V DRV（off） .

[0058] Affected by the switch action of the pair of tubes, the voltage Vds at the disturbed tube end increases by dV when the pair of tubes is turned on. DS(on) / dt speed rises, and when the action tube is turned off, it increases by dV DS(off) / dt speed decreases. The gate bus voltage positive spike V CK-on(max) and the negative voltage spike V in the gate bus layer when turning off the crosstalk CK-off(min) They are:

[0059] V CK-on(max) =V DRV（off） + Cgd*dV DS(on) / dt*Rg(1- )

[0060] V CK-off(min) =V DRV（off） + Cgd*dV DS(off) / dt*Rg(1- )

[0061] It can be seen from the above formula that the larger the Cgd, the larger the displacement current, which leads to severe crosstalk; the larger the Cgs, the slower the displacement current charges it, which plays a role in alleviating crosstalk. Therefore, general module users require the ratio of Ciss to Crss to be greater than 200, or even greater than 400; however, most existing semiconductor devices cannot meet the requirement that the ratio of Ciss to Crss (i.e., Ciss / Crss) is greater than 400, which makes semiconductor devices prone to crosstalk problems. Among them, Ciss is the input capacitance; Crss is the reverse capacitance.

[0062] To this end, the embodiment of the present application provides a new semiconductor device, which increases Cgs by adding an additional gate-source capacitance structure, thereby increasing the ratio of Ciss to Crss, thereby reducing the risk of crosstalk in the semiconductor device, while not affecting the reliability of the semiconductor device.

[0063] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0064] See also Figures 2 to 5 , Figure 2 A top view of some embodiments of the semiconductor device provided in the present application; Figure 3 for Figure 2 A partial structural cross-sectional view of the semiconductor device shown along line AA'; Figure 4b A schematic diagram of the area division of a semiconductor device; Figure 4b for Figure 2 The semiconductor device shown does not include a top view of the second conductive layer; Figure 5 for Figure 4b The structure shown is a partial cross-sectional view along line AA'.

[0065] The present application provides a semiconductor device, which may be a SiC MOSFET (silicon carbide-based metal oxide semiconductor field effect transistor) device. The semiconductor device includes a semiconductor epitaxial wafer 1, a plurality of source regions 2, a first conductive layer 3, an interlayer dielectric layer 4, and a second conductive layer 5.

[0066] Among them, Figure 2 and Figure 3 As shown, the semiconductor epitaxial wafer 1 includes an active region A1 and an edge terminal region A2 surrounding the active region A1; a plurality of source regions 2 are arranged in the semiconductor epitaxial wafer 1 and located in the active region A1, and each source region 2 extends from one side of the active region A1 to the other side opposite to the active region A1. Figure 3 As shown, the edge terminal region A2 is provided with a terminal structure 11 for protecting the device from damage such as overvoltage or overcurrent, etc. The terminal structure 11 may be a field limiting ring structure or a junction terminal extension region (JTE region), wherein the functions and structures of the field limiting ring structure and the junction terminal extension region are prior arts and are not described in detail herein.

[0067] like Figure 3 As shown, the first conductive layer 3 includes a gate electrode layer 31 and a gate bus layer 32 electrically connected to each other. The gate electrode layer 31 is disposed on the semiconductor epitaxial wafer 1 and is located in the active area A1, and the gate electrode layer 31 includes a plurality of gate structures 31a spaced apart along the first direction Y, and the orthographic projection of each gate structure 31a on the semiconductor epitaxial wafer 1 is located between the two source areas 2. In some embodiments, the first conductive layer 3 is a doped polysilicon layer or a conductive metal, which is not limited here, as long as it has a conductive function.

[0068] In some embodiments, the semiconductor device further includes a plurality of well regions 12 and a plurality of well region contact regions 13. The plurality of well regions 12 and the plurality of well region contact regions 13 are arranged in the semiconductor epitaxial wafer 1. The plurality of well regions 12, the plurality of well region contact regions 13 and the plurality of source regions 2 are arranged in a one-to-one correspondence. The well regions 12, the well region contact regions 13 and the source regions 2 all extend from one side of the active region A1 to the other side opposite to the active region A1 in the semiconductor epitaxial wafer 1 along the surface of the semiconductor epitaxial wafer 1.

[0069] Among them, the semiconductor epitaxial wafer 1 and the source region 2 have a first conductivity type, and the ion doping concentration of the source region 2 is greater than the ion doping concentration of the semiconductor epitaxial wafer 1; the well region 12 and the well region contact region 13 have a second conductivity type, and the ion doping concentration of the well region contact region 13 is greater than the ion doping concentration of the well region 12.

[0070] The first conductivity type may be one of N-type and P-type, and the second conductivity type may be the other of N-type and P-type. The present application takes the first conductivity type as N-type and the second conductivity type as P-type as an example.

[0071] Combination Figure 2 and Figure 3 The gate bus layer 32 is disposed in the edge terminal region A2; and the gate bus layer 32 surrounds the active region A1 and is connected to the end of each gate structure 31a. Figure 4b The gate bus layer 32 is specifically connected to the end of each gate structure 31a along the second direction X. The multiple gate structures 31a are arranged at intervals in the first direction Y, and the gate bus layer 32 surrounds the periphery of all gate structures 31a.

[0072] Specifically, the embodiment of the present application sets the gate bus layer 32 on the edge terminal area A2. Compared with the prior art of setting the gate bus layer 32 on the active area A1, the area of ​​the active area A1 can be saved, so that the semiconductor device is basically the active area A1 except for the edge terminal area A2, thereby improving the current outflow capacity of the device and reducing the on-resistance. The gate bus layer 32 is connected to the end of each gate structure 31a extending to the edge of the active area A1, and the gate bus layer 32 can drive each gate structure 31a, thereby not affecting the reliability of the device.

[0073] Combination Figure 3 , the interlayer dielectric layer 4 covers the first conductive layer 3. The second conductive layer 5 is arranged on the side of the interlayer dielectric layer 4 away from the semiconductor epitaxial wafer 1. The second conductive layer 5 includes a source pad 51 and a gate pad 52; the source pad 51 and the gate pad 52 are used to electrically connect the device to an external device. Among them, the source pad 51 is at least arranged in the active area A1 and is electrically connected to the source area 2. The gate pad 52 is at least arranged in the edge terminal area A2 and is electrically connected to the gate bus layer 32.

[0074] Specifically, the gate pad 52 can be completely disposed in the edge terminal area A2 and disposed around the active area A1. Alternatively, at least a portion of the gate pad 52 extends to the active area A1 and is insulated from the source pad 51, which can be specifically designed as required. The materials of the source pad 51 and the gate pad 52 include, but are not limited to, any one or a combination of aluminum, copper, tungsten, silver or nickel.

[0075] The interlayer dielectric layer 4 specifically covers each gate structure 31a, and is used to isolate each gate structure 31a; and Figure 5 In the active area A1, the interlayer dielectric layer 4 has a third opening 43 in the area corresponding to each source area 2, so that at least a portion of each source area 2 is exposed through the third opening 43 corresponding thereto, and a portion of the source pad 51 extends into the third opening 43 and contacts and is electrically connected to the source area 2.

[0076] In a specific embodiment, the semiconductor device further includes a plurality of ohmic contact metals (not shown), which are respectively disposed in each third opening 43 and are electrically connected to the corresponding source region 2; the source pad 51 specifically forms an ohmic contact metal contact with each source region 2, so as to be electrically connected to the source region 2 through the ohmic contact metal. The material of the ohmic contact metal includes, but is not limited to, any one or a combination of Ti, Ni, Al, Au, Ta or W.

[0077] Further, combined with Figure 3 and Figure 5 The interlayer dielectric layer 4 also covers the gate bus layer 32 to isolate the gate bus layer 32, and in the edge terminal area A2, the interlayer dielectric layer 4 has a fourth opening 44 in a region corresponding to the gate bus layer 32, so that at least a portion of the gate bus layer 32 is exposed through the fourth opening 44. A portion of the gate pad 52 extends into the fourth opening 44 and contacts and is electrically connected to the gate bus layer 32.

[0078] In some embodiments, the material of the interlayer dielectric layer 4 may be silicon oxide or silicon nitride, etc., and the thickness of the interlayer dielectric layer 4 is 800nm-1000nm. For example, the thickness of the interlayer dielectric layer 4 may be 800nm, 850nm, 900nm, 950nm or 1000nm, etc., which is not limited here. The design is specifically based on the actual device size.

[0079] In one embodiment, see Figure 3 , the first conductive layer 3 also includes a capacitor plate layer 33, the gate electrode layer 31 and the gate bus layer 32 are insulated from the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; a portion of the gate pad 52 is stacked with a portion of the capacitor plate layer 33 and isolated by a dielectric layer 6; wherein the thickness of the dielectric layer 6 is less than the thickness of the interlayer dielectric layer 4. Specifically, the gate bus layer 32 can be arranged around the periphery of the capacitor plate layer 33 and spaced from the capacitor plate layer 33. In this way, in the process of forming the semiconductor device, a portion can be cut out on the original gate bus layer 32 to serve as the capacitor plate layer 33; in this way, the capacitor plate layer 33 can be formed without increasing the area of ​​the semiconductor device.

[0080] In some embodiments, the thickness of the dielectric layer 6 may be 50-200 nanometers; for example, the thickness of the dielectric layer 6 may be 50 nm, 80 nm, 110 nm, 140 nm, 170 nm or 200 nm, etc., which is not limited here. The dielectric layer 6 is a thermally oxidized silicon oxide layer.

[0081] The gate-source capacitance (C gs) to increase Cgs as much as possible, thus making the range of Ciss / Crss adjustable.

[0082] In the above scheme, the first conductive layer 3 further includes a capacitor plate layer 33, and the gate electrode layer 31 and the gate bus layer 32 are insulated from the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; a portion of the gate pad 52 is stacked with a portion of the capacitor plate layer 33 and isolated by the dielectric layer 6, so that an additional gate-source capacitor is formed by the gate pad 52 covering the portion of the capacitor plate layer 33, the dielectric layer 6, and the portion where the capacitor plate layer 33 and the gate pad 52 are stacked, thereby increasing the Ciss / Crss ratio to reduce the risk of crosstalk in the semiconductor device.

[0083] At the same time, it is easy to understand that the core of the above scheme is to cut out a part of the original first conductive layer 3 for use as the capacitor plate layer 33; for example, if the capacitor plate layer 33 is located in the edge terminal area A2, it is equivalent to cutting out a part of the original gate bus layer 32 for use as the capacitor plate layer 33, and then forming an additional gate-source capacitor, thereby achieving the purpose of increasing Ciss / Crss. This design only involves the change of the position of the gate pad 52, and because the capacitor plate layer 33 will not affect the connection between the gate pad 52 and the source pad 51 and other structures of the active area A1, the change is small and will not affect the reliability of the original semiconductor device, greatly improving the anti-crosstalk capability of the semiconductor device. At the same time, the area of ​​the semiconductor device will not be increased.

[0084] In some embodiments, the capacitor plate layer 33 is disposed in the same layer as the gate electrode layer 31 and the gate bus layer 32, and is made of the same material. In this way, in the process of manufacturing the semiconductor device, the capacitor plate layer 33, the gate electrode layer 31 and the gate bus layer 32 can be formed simultaneously using the same process step, thus not adding process steps and saving costs.

[0085] In some embodiments, in combination Figure 5 , the capacitor plate layer 33 is located in the edge terminal area A2; the interlayer dielectric layer 4 has a first opening 41, so that the capacitor plate layer 33 is partially exposed to form a first exposed portion; the dielectric layer 6 is disposed in the first opening 41 and covers the first exposed portion. Part of the gate pad 52 extends into the first opening 41 and is located on the surface of the dielectric layer 6 away from the first exposed portion.

[0086] By placing the capacitor plate layer 33 in the edge terminal area A2, an additional gate-source capacitor structure can be formed. Compared with placing the capacitor plate layer 33 in the active area A1, the area of ​​the active area A1 can be saved, so that the semiconductor device is basically the active area A1 except for the edge terminal area A2, thereby improving the current output capacity of the device. There is no need to consider the limitation of the occupied area.

[0087] The following are two ways to achieve electrical connection between the source pad 51 and the capacitor plate layer 33 .

[0088] In one embodiment, in combination Figure 3 and Figure 5 , the dielectric layer 6 has an opening 61; a portion of the source pad 51 contacts the first exposed portion through the first opening 41 and the opening 61 in sequence to be electrically connected to the capacitor plate layer 33. It can be understood that a portion of the source pad 51 extends into the first opening 41 and further extends into the opening 61 to contact the first exposed portion. Among them, the portion of the source pad 51 extending into the first opening 61 and the portion of the gate pad 52 extending into the first opening 41 can be spaced apart to achieve insulation between the two.

[0089] In another embodiment, see Figures 6a to 7 , Figure 6a for Figure 2 Another cross-sectional view of a portion of the structure of the semiconductor device along line AA' shown; Figure 6b for Figure 6a The enlarged view of the M in the middle; Figure 7 For Figure 6a Schematic diagram of the structure of forming a second conductive layer on the semiconductor device shown. The interlayer dielectric layer 4 has a second opening 42 spaced apart from the first opening 41, so that the capacitor plate layer 33 is partially exposed to form a second exposed portion; that is, the portion of the capacitor plate layer 33 exposed by the second opening 42 forms the second exposed portion. A portion of the source pad 51 extends into the second opening 42 and contacts the second exposed portion to achieve electrical connection between the source pad 51 and the capacitor plate layer 33.

[0090] Combination Figure 3 and Figure 7 It is easy to understand that this solution is Figure 3 The corresponding embodiment allows a larger area of ​​the gate pad 52 to extend into the first opening 41 to be stacked with the capacitor plate layer 33; thereby effectively increasing the relative area of ​​the gate pad 52 and the capacitor plate layer 33, increasing the Cgs value, and further reducing the risk of crosstalk in the semiconductor device.

[0091] The following is an introduction to the specific location of the capacitor plate layer 33 in the edge terminal area A2 provided in different embodiments of the present application.

[0092] In one embodiment, in combination Figure 4a and Figure 4b, the edge terminal area A2 includes a ring-shaped routing area A3 and a pad area A4. The ring-shaped routing area A3 surrounds the periphery of the active area A1. The pad area A4 is connected to the ring-shaped routing area A3 and is located on one side of the active area A1. Among them, the cross-sectional area of ​​the pad area A4 is larger than the cross-sectional area of ​​the ring-shaped routing area A3 located on each side of the active area A1; the capacitor plate layer 33 is specifically located in the pad area A4. In this way, a capacitor plate layer 33 with a larger area can be set in the edge terminal area A2, so that a gate pad 52 with a larger area can be set relative to the capacitor plate layer 33 to further increase the gate-source capacitance value.

[0093] In some embodiments, the pad area A4 is located inside the annular wiring area A3 ; that is, located on a side of the annular wiring area A3 close to the active area A1 .

[0094] In a specific embodiment, the edge terminal area A2 includes a ring-shaped routing area A3 surrounding the active area A1 and a pad area A4 connected to the ring-shaped routing area A3; the ring-shaped routing area A3 includes a first edge area and a second edge area arranged relatively along a first direction Y, and a third edge area and a fourth edge area arranged relatively along a second direction X; the first edge area to the fourth edge area are arranged to form a closed loop structure, and the active area A1 is located in the closed loop structure. The pad area A4 is specifically connected to the first edge area, and is located on the side of the first edge area facing the second edge area, and is located between the active area A1 and the first edge area. Part of the source area 2 specifically extends from the third edge area to the fourth edge area.

[0095] In one embodiment, the pad area A4 extends along the first direction Y, and the active area A1 extends to opposite sides of the pad area A4 along the second direction X; that is, part of the active area A1 is located on both sides of the pad area A4 along the second direction X, so that the area of ​​the active area A1 can be increased as much as possible within a limited area. The first direction Y is perpendicular to the second direction X.

[0096] In another embodiment, see Figures 8 to 9 , Figure 8 for Figure 2 Another top view of the semiconductor device shown does not include the interlayer dielectric layer 4 and the second conductive layer 5; Fig. 9 for Figure 8 The structure shown is a partial structural cross-sectional view along the BB' line; Figure 4b The corresponding embodiment is different in that: the gate bus layer 32 includes a ring-shaped routing layer located in the ring-shaped routing area A3 and a pad layer located in the pad area A4; the capacitor plate layer 33 is located in the second edge area and located on the inner side of the ring-shaped routing layer. In this way, it is beneficial to lengthen the capacitor plate layer 33 along the first direction Y. Specifically, the portion of the ring-shaped routing layer located in the second edge area surrounds the entire capacitor plate layer 33 and is spaced apart from the capacitor plate layer 33.

[0097] Of course, in other embodiments, the capacitor plate layer 33 may also be disposed in the third edge region and the fourth edge region, as long as it is insulated from various layer structures and the ring wiring layer disposed in the active region A1.

[0098] In some embodiments, see Fig.10 , Fig.10 For Figure 3 Schematic diagram of the structure in which a passivation layer is formed on the structure shown; the semiconductor device also includes a plurality of well regions 12, a plurality of well region contact regions 13, a gate insulating layer 7a, a wiring insulating layer 7b, a passivation layer 7c and a drain electrode 18.

[0099] A plurality of well regions 12 and a plurality of well region contact regions 13 are arranged in the semiconductor epitaxial wafer 1. The plurality of well regions 12, the plurality of well region contact regions 13 and the plurality of source regions 2 are arranged in a one-to-one correspondence. The well regions 12, the well region contact regions 13 and the source regions 2 all extend in the semiconductor epitaxial wafer 1 along the surface of the semiconductor epitaxial wafer 1.

[0100] The gate insulating layer 7a is at least disposed in the active area A1; the gate electrode layer 31 is disposed on a side of the gate insulating layer 7a away from the semiconductor epitaxial wafer 1, so that the gate electrode layer 31 is isolated from the semiconductor epitaxial wafer 1, the well region 12, the well region contact region 13 and / or the source region 2 through the gate insulating layer 7a. In one embodiment, part of the gate insulating layer 7a further extends to the edge terminal region A2 to connect with the wiring insulating layer 7b.

[0101] The wiring insulation layer 7b is disposed on the semiconductor epitaxial wafer 1 and located in the edge terminal area A2; the gate bus layer 32 is disposed on the surface of the wiring insulation layer 7b away from the semiconductor epitaxial wafer 1. The wiring insulation layer 7b isolates the gate bus layer 32 from the semiconductor epitaxial wafer 1 and the terminal structure 11.

[0102] The materials of the gate insulating layer 7a and the wiring insulating layer 7b may be silicon oxide or silicon nitride, etc., which is not limited here, as long as the first conductive layer 3 and the semiconductor epitaxial wafer 1 can be dielectrically isolated.

[0103] In some embodiments, the thickness of the wiring insulation layer 7b is greater than the thickness of the gate insulation layer 7a, wherein the thickness refers to the dimension along the direction of the semiconductor epitaxial wafer 1 toward the gate insulation layer 7a.

[0104] The semiconductor device may be a planar gate semiconductor device or a trench gate semiconductor device. When the semiconductor device is a planar gate semiconductor device, see Fig.10, the gate insulating layer 7a is disposed on the surface of the semiconductor epitaxial wafer 1, the gate electrode layer 31 is disposed on the surface of the gate insulating layer 7a away from the semiconductor epitaxial wafer 1, the gate insulating layer 7a is used to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1, and when the gate insulating layer 7a and the gate electrode layer 31 are also extended and disposed on the well region 12 and at least a part of the well region contact region 13, the gate insulating layer 7a is also used to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1, the well region 12 and the well region contact region 13. When the semiconductor device is a trench gate semiconductor device, which is not shown in the figure, the gate structure 31a extends along the surface of the semiconductor epitaxial wafer 1 and inside the semiconductor epitaxial wafer 1, and the gate insulating layer 7a wraps the gate electrode layer 31 to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1, the well region 12, the well region contact region 13 and the source region 2.

[0105] The passivation layer 7c covers the second conductive layer 5. Specifically, the passivation layer 7c covers the source pad 51 to isolate the source pad 51, and the passivation layer 7c has a fifth opening 71 in a region corresponding to the source pad 51, so that a portion of the source pad 51 is exposed through the fifth opening 71. Further, the passivation layer 7c also covers the gate pad 52 to isolate the gate pad 52, and the passivation layer 7c has a sixth opening 72 in a region corresponding to the gate pad 52, so that a portion of the gate pad 52 is exposed through the sixth opening 72.

[0106] The drain electrode 18 is disposed on a surface of the semiconductor epitaxial wafer 1 away from the source region 2 . The material of the drain electrode 18 may be the same as or similar to that of the gate pad 52 and / or the source pad 51 .

[0107] The semiconductor device provided in this embodiment is provided by making the first conductive layer 3 further include a capacitor plate layer 33, and making the gate electrode layer 31 and the gate bus layer 32 insulated from the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; the gate pad 52 is partially stacked with the capacitor plate layer 33 and isolated by the dielectric layer 6, so that an additional gate-source capacitor is formed by the gate pad 52 covering the capacitor plate layer 33, the dielectric layer 6 and the stacked portion of the capacitor plate layer 33 and the gate pad 52, thereby increasing Ciss / Crss, having a wide adjustment range, and improving the ability of the semiconductor device to resist crosstalk. At the same time, it does not affect the reliability of the active area A1 and the semiconductor device.

[0108] In one embodiment, see Figure 11 to Figure 12 , Fig.11 Top views of other embodiments of the semiconductor device provided by the present application; Fig.12 An embodiment of the present application provides Fig.11The semiconductor device shown is a partial structural cross-sectional view along the CC' line; a second semiconductor device is provided, which is different from the semiconductor device provided by the first embodiment mentioned above in that: the first conductive layer 3 does not include the capacitor plate layer 33; a portion of the gate bus layer 32 is stacked with a portion of the source pad 51 and is isolated by the dielectric layer 6.

[0109] In this embodiment, the first opening 41 exposes a portion of the gate bus layer 32. The dielectric layer 6 is disposed in the first opening 41 and covers the portion of the gate bus layer 32 exposed through the first opening 41. A portion of the source pad 51 extends into the first opening 41 and is located on the surface of the dielectric layer 6 away from the first exposed portion. It can be understood that in this embodiment, the portion of the gate bus layer 32 covered by the dielectric layer 6, the dielectric layer 6, and the portion of the source pad 51 covering the dielectric layer 6 together form an additional gate-source capacitance (Cgs), thereby increasing Ciss / Crss to reduce the risk of crosstalk in the semiconductor device.

[0110] Compared with the first semiconductor device, the first conductive layer 3 does not need to be separated into a capacitor plate layer 33, and a portion of the gate bus layer 32 area can be directly sacrificed to prepare Cgs. However, this solution may be incompatible with the original design of the semiconductor device, and will also limit the margin for packaging wire bonding.

[0111] In one embodiment, see Fig.13 , Fig.13 A partial structural cross-sectional view of a semiconductor device along line CC' provided in another embodiment of the present application; a third semiconductor device is provided, which is different from the semiconductor device provided in the first embodiment in that: the first conductive layer 3 does not include a capacitor plate layer 33; a portion of the gate electrode layer 31 is stacked with a portion of the source pad 51 and is isolated by a dielectric layer 6.

[0112] Specifically, a seventh opening is further provided on the interlayer dielectric layer 4, and the seventh opening exposes a portion of the gate electrode layer 31 away from the semiconductor epitaxial wafer 1 to form a third exposed portion; the dielectric layer 6 is provided in the seventh opening and covers the third exposed portion. A portion of the source pad 51 extends into the seventh opening and is located on the surface of the dielectric layer 6 away from the first exposed portion; so that the third exposed portion, the dielectric layer 6, and the portion of the source pad 51 covering the dielectric layer 6 together form an additional gate-source capacitor (C gs ), thereby increasing Ciss / Crss to reduce the risk of crosstalk in semiconductor devices.

[0113] The dielectric layer 6 can be obtained by oxidizing the surface of the gate electrode layer 31 .

[0114] Compared with the first semiconductor device, in this solution, the first conductive layer 3 also does not need to be separated into a capacitor plate layer 33, and a portion of the gate electrode layer 31 area can be directly sacrificed to prepare Cgs. However, in this case, due to the large current in the active area A1, which is prone to heat generation, the complex structure and high stress, it is more likely to cause a gate-source short circuit.

[0115] In one embodiment, see Fig.14 and Fig.15 , which is a partial structural cross-sectional view of the semiconductor device provided by different embodiments of the present application along the line CC'; the difference from the semiconductor device provided by the first embodiment is that: the first conductive layer 3 does not include the capacitor plate layer 33; the portion of the source pad 51 and the portion of the gate pad 52 are stacked and isolated by the dielectric layer 6, thereby forming a capacitor Cgs. That is, the portion of the source pad 51 and the gate pad 52 stacked and arranged cooperates with the dielectric layer 6 to form the capacitor Cgs.

[0116] In one embodiment, Fig.14 As shown, the dielectric layer 6 is located in the edge terminal area A2 and is located at the portion of the surface of the gate pad 52 away from the semiconductor epitaxial wafer 1; a portion of the source pad 51 extends to the surface of the dielectric layer 6 away from the semiconductor epitaxial wafer 1 to be stacked with a portion of the gate pad 52.

[0117] In another embodiment, Fig.15 As shown, the dielectric layer 6 is located in the active area A1 and at the surface of the source pad 51 away from the semiconductor epitaxial wafer 1; the gate pad 52 extends to the surface of the dielectric layer 6 away from the semiconductor epitaxial wafer 1 to be stacked with the gate pad 52.

[0118] In one embodiment, see Fig.16 , Fig.16 A flowchart of a method for preparing a semiconductor device provided in one embodiment of the present application; a method for preparing a semiconductor device is also provided, which can be used to prepare a first semiconductor device, and the preparation methods of other semiconductor devices are similar to this method. The method includes:

[0119] Step S1: providing a semiconductor epitaxial wafer 1, wherein the semiconductor epitaxial wafer 1 comprises an active area A1 and an edge termination area A2.

[0120] In some embodiments, the semiconductor epitaxial wafer 1 includes a stacked substrate (not shown) and a semiconductor epitaxial layer (not shown). In some embodiments, the substrate is a SiC substrate, the crystal form is 4H SiC, and the SiC epitaxial layer is grown on the SiC substrate using a vapor deposition process.

[0121] Step S2: forming a plurality of well regions 12, a plurality of well region contact regions 13 and a plurality of source regions 2 in the active region A1.

[0122] For details, please see Fig.17 , Fig.17 For semiconductor epitaxial wafer Fig.16 Schematic diagram of the structure of some intermediate products after the step S2 in FIG. 1 ; ion implantation can be performed on the active area A1 of the semiconductor epitaxial wafer 1 to form a plurality of well regions 12, a plurality of well region contact regions 13 and a plurality of source regions 2. Among them, the plurality of well regions 12, the plurality of well region contact regions 13 and the plurality of source regions 2 all extend along the surface of the semiconductor epitaxial wafer 1 and inside the semiconductor epitaxial wafer 1; and the plurality of well regions 12, the plurality of well region contact regions 13 and the plurality of source regions 2 extend from the active area A1 to the edge of the active area A1. The plurality of well regions 12 are arranged at intervals, and each well region 12 is provided with a connected well region contact region 13 and source region 2.

[0123] Please continue to see Fig.17 In step S2, a terminal structure 11 is also formed simultaneously in the edge terminal area A2 to protect the device from damage such as overvoltage or overcurrent.

[0124] Step S3: activating the semiconductor epitaxial wafer 1 at high temperature, and forming a wiring insulation layer 7 b on the first surface of the semiconductor epitaxial wafer 1 in the region located in the edge termination region A2 .

[0125] Specifically, the dielectric material layer may be grown by thermal oxidation growth, then oxidized and annealed at a temperature ranging from 1200° C. to 1450° C., for 10 min to 30 min, and for 30 min to 300 min, and finally patterned to form the wiring insulation layer 7 b located in the edge terminal region A2 .

[0126] See also Figure 18 to Figure 19 , Fig.18 For semiconductor epitaxial wafer Fig.16 A schematic diagram of the structure of some intermediate products after processing in step S3; Fig.19 for Fig.18 The semiconductor device is shown in a partial structural cross-sectional view along line CC'. The wiring insulation layer 7b surrounds the active area A1.

[0127] Step S4: forming a first conductive layer 3 on the first surface of the semiconductor epitaxial wafer 1; the first conductive layer 3 includes a capacitor plate layer 33, and a gate electrode layer 31 and a gate bus layer 32 electrically connected to each other; the gate electrode layer 31 is arranged in the active area A1, and the gate bus layer 32 is arranged in the edge terminal area A2; the gate electrode layer 31 and the gate bus layer 32 are both insulated from the capacitor plate layer 33.

[0128] Combination Fig. 9In the specific implementation process, before step S4, it also includes forming a gate insulating layer 7a on the surface of the semiconductor device. The gate insulating layer 7a can be formed by the same process as the wiring insulating layer 7b; however, due to the different thicknesses of the two, the wiring insulating layer 7b and the gate insulating layer 7a are not formed in the same step, and the order of the two is not specific.

[0129] The gate electrode layer 31 is formed on the surface of the gate insulating layer 7a facing away from the semiconductor epitaxial wafer 1 ; the gate bus layer 32 and the capacitor plate layer 33 are formed on the surface of the wiring insulating layer 7b facing away from the semiconductor epitaxial wafer 1 .

[0130] In the specific implementation process, the gate electrode layer 31, the gate bus layer 32 and the capacitor plate layer 33 can be formed in the same step by magnetron sputtering or vapor deposition. Specifically, the gate material can be formed on the entire surface of the semiconductor epitaxial wafer 1 formed with the wiring insulation layer 7b and the gate insulation layer 7a, wherein the gate material can be polysilicon or a conductive metal material, and then the gate material is patterned to form a plurality of gate electrode layers 31, gate bus layers 32 and capacitor plate layers 33.

[0131] Step S5 : forming an interlayer dielectric layer 4 on the first conductive layer 3 , and making the interlayer dielectric layer 4 expose at least a portion of the capacitor plate layer 33 .

[0132] Combination Figure 20 to Figure 21 , Fig. 20 A top view of a portion of the intermediate product structure of the semiconductor epitaxial wafer after step S5; Fig.21 for Fig. 20 The structure shown is a partial cross-sectional view along line CC'. In some embodiments, the interlayer dielectric layer 4 is formed by magnetron sputtering or vapor deposition, and the material of the interlayer dielectric layer 4 can be silicon oxide or silicon nitride.

[0133] The interlayer dielectric layer 4 has a first opening 41 , and the first opening 41 partially exposes the capacitor plate layer 33 and forms a portion to be converted.

[0134] Step S6 : performing oxidation treatment on the portion of the capacitor plate layer 33 exposed from the interlayer dielectric layer 4 to form a dielectric layer 6 .

[0135] See also Figure 22 to Figure 23 , Fig. 22 For semiconductor epitaxial wafer Fig.16 A top view of a portion of the intermediate product structure after processing in step S6; Fig.23 for Fig. 22The structure shown is a partial structural cross-sectional view along the CC' line. Specifically, a mature silicon oxidation process can be used to obtain a high-quality thermally oxidized silicon oxide dielectric layer 6. In the specific implementation process, the portion to be converted is specifically oxidized so that the portion of the portion to be converted away from the semiconductor epitaxial wafer 1 is oxidized to form a dielectric layer 6, and the portion of the portion to be converted that is not oxidized forms a first exposed portion.

[0136] Step S7: patterning the interlayer dielectric layer 4 to expose at least a portion of the source region 2 and at least a portion of the gate bus layer 32; and patterning the dielectric layer 6 or the interlayer dielectric layer 4 to expose a portion of the first exposed portion.

[0137] Among them, combined Figure 5 The interlayer dielectric layer 4 has a third opening 43 and a fourth opening 44; the third opening 43 is located in the active area A1, so that at least part of the source area 2 is exposed; the fourth opening 44 is located in the edge terminal area A2, so that at least part of the gate bus layer 32 is exposed.

[0138] In some implementations, such as Figure 5 As shown, an opening 61 may be further formed on the dielectric layer 6 to expose a portion of the first exposed portion, and the source pad 51 formed subsequently may be electrically connected to the electrode pad layer through the opening 61. Figure 6a As shown, a second opening 42 is formed on the interlayer dielectric layer 4 to expose a portion of the first exposed portion, ie, the second exposed portion mentioned above, so that the source pad 51 contacts the second exposed portion through the second opening 42 .

[0139] In some specific implementations, an ohmic contact metal may be formed in each third opening 43. The ohmic contact metal may be formed in the third opening 43 by evaporation or magnetron sputtering and patterning, and the annealing process temperature ranges from 800° C. to 1100° C. and the time ranges from 60s to 300s.

[0140] Step S8: forming a second conductive layer 5 on the interlayer dielectric layer 4; the second conductive layer 5 includes a source pad 51 and a gate pad 52; the source pad 51 is at least arranged in the active area A1 and electrically connected to the source area 2; the gate pad 52 is at least arranged in the edge terminal area A2 and electrically connected to the gate bus layer 32.

[0141] Combination Figure 2 and Figure 3 In some embodiments, a metal layer is formed on the entire surface of the interlayer dielectric layer 4 by evaporation or magnetron sputtering, and then patterned to form a source pad 51 and a gate pad 52 at least partially located in the edge terminal area A2.

[0142] The source pad 51 is arranged on the interlayer dielectric layer 4 and extends into each third opening 43 and is connected to the ohmic contact metal in each third opening 43, and further connected to each source region 2. The gate pad 52 is arranged on the interlayer dielectric layer 4 and extends into the fourth opening 44 and is connected to the gate bus layer 32.

[0143] Step S9: forming a passivation layer 7c covering the source pad 51 and the gate pad 52; wherein the passivation layer 7c has an eighth opening in a region corresponding to the source pad 51, and has a ninth opening in a region corresponding to the gate pad 52.

[0144] The passivation layer 7c can be formed by the same process as the interlayer dielectric layer 4, which will not be described in detail here.

[0145] Combination Fig.10 Specifically, the passivation layer 7c is used to isolate the source pad 51 and to isolate the gate pad 52.

[0146] Step S10 : forming a drain pad on a side of the semiconductor epitaxial wafer 1 away from the source pad 51 and the gate pad 52 .

[0147] In some embodiments, the surface of the substrate facing away from the source pad 51 and the gate pad 52 may be thinned first, and then the drain pad may be formed. Specifically, an ohmic contact may be formed on the back of the semiconductor epitaxial wafer 1 first, and then a metal layer may be formed on the back of the semiconductor epitaxial wafer 1 as a drain pad by evaporation or magnetron sputtering.

[0148] Specifically, the method for preparing a semiconductor device provided in an embodiment of the present application forms a capacitor plate layer 33 disposed on the same layer as the gate electrode layer 31 and the gate bus layer 32, and insulates the gate electrode layer 31 and the gate bus layer 32 from the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; a portion of the gate pad 52 is stacked with a portion of the capacitor plate layer 33 and isolated by a dielectric layer 6, so that an additional gate-source capacitor is formed by the gate pad 52 covering a portion of the capacitor plate layer 33, the dielectric layer 6, and a portion of the capacitor plate layer 33 stacked with the gate pad 52, thereby increasing the ratio of Ciss to Crss to reduce the risk of crosstalk in the semiconductor device. At the same time, the design only involves a change in the position of the gate pad 52, and does not affect the reliability of the active area A1 and the semiconductor device. In addition, by setting the gate bus layer 32 on the edge terminal area A2, compared with setting the gate bus layer 32 on the active area A1 in the prior art, the area of ​​the active area A1 can be saved, so that the semiconductor device is basically the active area A1 except for the edge terminal area A2, thereby improving the current outflow capacity of the device and reducing the on-resistance. The gate bus layer 32 is connected to the end of each gate structure 31a extending to the edge of the active area A1, and the gate bus layer 32 can drive each gate structure 31a, thereby not affecting the reliability of the device.

[0149] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor epitaxial wafer, comprising an active region and an edge termination region surrounding the active region; A plurality of source regions, arranged in the active region; A first conductive layer includes a gate electrode layer and a gate bus layer electrically connected to each other; the gate electrode layer is arranged in the active area, and the gate bus layer is arranged in the edge terminal area; an interlayer dielectric layer, covering the first conductive layer; A second conductive layer is disposed on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge terminal region and electrically connected to the gate bus layer; Among them, the first conductive layer also includes a capacitor plate layer, the gate electrode layer and the gate bus layer are insulated from the capacitor plate layer; the source pad is electrically connected to the capacitor plate layer; part of the gate pad and part of the capacitor plate layer are stacked and isolated by a dielectric layer, and the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer.

2. The semiconductor device according to claim 1, wherein: The capacitor plate layer is located in the edge terminal area; The interlayer dielectric layer has a first opening, so that the capacitor plate layer is partially exposed to form a first exposed portion; the dielectric layer is arranged in the first opening and covers the first exposed portion; a portion of the gate pad extends into the first opening and is located on the surface of the dielectric layer away from the first exposed portion.

3. The semiconductor device according to claim 2, characterized in that The dielectric layer has an opening; the source pad contacts the first exposed portion through the first opening and the opening in sequence; or The interlayer dielectric layer has a second opening spaced apart from the first opening, so that the capacitor plate layer is partially exposed to form a second exposed portion; the source pad contacts the second exposed portion through the second opening.

4. The semiconductor device according to claim 2, characterized in that The edge terminal area includes a ring-shaped wiring area surrounding the active area and a pad area connected to the ring-shaped wiring area; the capacitor plate layer is located in the pad area.

5. The semiconductor device according to claim 4, characterized in that The pad area is located inside the annular wiring area, and the active area extends to two opposite sides of the pad area.

6. The semiconductor device according to claim 2, wherein: The edge terminal area includes a ring-shaped routing area surrounding the active area and a pad area connected to the ring-shaped routing area; the ring-shaped routing area includes a first edge area and a second edge area arranged opposite to each other along a first direction, and a third edge area and a fourth edge area arranged opposite to each other along a second direction; a portion of the source area extends from the third edge area to the fourth edge area; the pad area is connected to the first edge area, the gate bus layer includes a ring-shaped routing layer located in the ring-shaped routing area and a pad layer located in the pad area; the capacitor plate layer is located in the second edge area and on the inner side of the ring-shaped routing layer.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The first conductive layer is a doped polysilicon layer; the dielectric layer is a thermally oxidized silicon oxide layer.

8. The semiconductor device according to any one of claims 1 to 6, characterized in that: The thickness of the interlayer dielectric layer is 800-1000 nanometers; the thickness of the dielectric layer is 50-200 nanometers.

9. The semiconductor device according to any one of claims 1 to 6, characterized in that: The semiconductor device is a SiC MOSFET, and further comprises: A plurality of well regions and a plurality of well region contact regions; the plurality of well regions, the plurality of well region contact regions and the plurality of source regions are arranged in one-to-one correspondence; A gate insulating layer is provided at least in the active area; the gate electrode layer is provided on a side of the gate insulating layer away from the semiconductor epitaxial wafer; A wiring insulation layer is arranged in the edge terminal area; the gate bus layer is arranged on a side of the wiring insulation layer away from the semiconductor epitaxial wafer; a passivation layer, covering the second conductive layer; A drain electrode is disposed on a surface of the semiconductor epitaxial wafer away from the source region; Among them, in the active area, the interlayer dielectric layer has a third opening, so that at least part of the source area is exposed and in contact with the source pad; in the edge terminal area, the interlayer dielectric layer has a fourth opening, so that at least part of the gate bus layer is exposed and in contact with the gate pad; the passivation layer has a fifth opening and a sixth opening, the fifth opening exposes part of the source pad, and the sixth opening exposes part of the gate pad.

10. A semiconductor device, characterized in that: include: A semiconductor epitaxial wafer, comprising an active region and an edge termination region surrounding the active region; A plurality of source regions, arranged in the active region; A first conductive layer includes a gate electrode layer and a gate bus layer electrically connected to each other; the gate electrode layer is arranged in the active area, and the gate bus layer is arranged in the edge terminal area; an interlayer dielectric layer, covering the first conductive layer; A second conductive layer is disposed on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge terminal region and electrically connected to the gate bus layer; Part of the gate electrode layer or part of the gate bus layer is stacked with part of the source pad and isolated by a dielectric layer, and the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer; The interlayer dielectric layer has a first opening, so that part of the gate electrode layer or part of the gate bus layer is exposed to form a first exposed portion; the dielectric layer is arranged in the first opening and covers the first exposed portion; part of the source pad extends into the first opening and is located on the surface of the dielectric layer away from the first exposed portion.

11. The semiconductor device according to claim 10, characterized in that The first conductive layer is a doped polysilicon layer; the dielectric layer is a thermally oxidized silicon oxide layer.

12. The semiconductor device according to claim 10, characterized in that The thickness of the interlayer dielectric layer is 800-1000 nanometers; the thickness of the dielectric layer is 50-200 nanometers.

13. The semiconductor device according to claim 10, characterized in that The semiconductor device is a SiC MOSFET, and further comprises: A plurality of well regions and a plurality of well region contact regions; the plurality of well regions, the plurality of well region contact regions and the plurality of source regions are arranged in one-to-one correspondence; A gate insulating layer is arranged in the active area; the gate electrode layer is arranged on a side of the gate insulating layer away from the semiconductor epitaxial wafer; A wiring insulation layer is arranged in the edge terminal area; the gate bus layer is arranged on a side of the wiring insulation layer away from the semiconductor epitaxial wafer; a passivation layer, covering the second conductive layer; A drain electrode is disposed on a surface of the semiconductor epitaxial wafer away from the source region; Among them, in the active area, the interlayer dielectric layer, the gate electrode layer and the gate insulation layer have a third opening, so that the source area is exposed and in contact with the source pad; in the edge terminal area, the interlayer dielectric layer has a fourth opening, so that the gate bus layer is exposed and in contact with the gate pad; the passivation layer has a fifth opening and a sixth opening, the fifth opening exposes part of the source pad, and the sixth opening exposes part of the gate pad.

14. A semiconductor device, characterized in that: include: A semiconductor epitaxial wafer, comprising an active region and an edge termination region surrounding the active region; A plurality of source regions, arranged in the active region; A first conductive layer includes a gate electrode layer and a gate bus layer electrically connected to each other; the gate electrode layer is arranged in the active area, and the gate bus layer is arranged in the edge terminal area; an interlayer dielectric layer, covering the first conductive layer; A second conductive layer is disposed on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and electrically connected to the source region; the gate pad is at least disposed in the edge terminal region and electrically connected to the gate bus layer; Part of the source pad and part of the gate pad are stacked and isolated by a dielectric layer, thereby forming a gate-source capacitor, and the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer.

15. The semiconductor device according to claim 14, characterized in that The dielectric layer is located in the edge termination region and is located on a portion of the surface of the gate pad away from the semiconductor epitaxial wafer; a portion of the source pad extends to a surface of the dielectric layer away from the semiconductor epitaxial wafer; or The dielectric layer is located in the active area and on a portion of the surface of the source pad away from the semiconductor epitaxial wafer; a portion of the gate pad extends to the surface of the dielectric layer away from the semiconductor epitaxial wafer.

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