Pulse load power supply system with integrated supercapacitor energy storage and power control method thereof

Abstract

The present invention discloses a pulse load power supply system with integrated supercapacitor energy storage and a power control method thereof, comprising a power supply, a bidirectional DC / DC converter, a supercapacitor, a control host computer, a pulse load and a driving power electronic device thereof, wherein the power supply is electrically connected to the driving power electronic device and the bidirectional DC / DC converter, the bidirectional DC / DC converter is electrically connected to the supercapacitor, and the pulse load is electrically connected to the driving power electronic device; the bidirectional DC / DC converter and the driving power electronic device are communicatively connected to the control host computer. The present invention realizes smooth switching of constant current, constant power and constant voltage when the supercapacitor is charging, thereby improving the safety and stability of the system; when the supercapacitor is discharging, the DC / DC converter is operated in a voltage control loop to provide a stable voltage for the operation of the pulse load. In order to meet the high-power output scenario, a multi-phase converter can be used, and the proposed current sharing control method realizes current sharing control when there are differences in the phase parameters of the multi-phase converter, thereby improving the efficiency and reliability of the system.

Description

Technical Field

[0001] The present invention belongs to the field of electricity, and in particular relates to a pulse load power supply system integrated with supercapacitor energy storage and a power control method thereof. Background Art

[0002] With the continuous development of power electronics technology, pulse loads with high peak-to-average power bit points are widely used in various fields such as military defense, industry and agriculture, environmental science, medicine, and scientific experiments. For example, electroacoustic transducers, as communication detection equipment in the field of low-frequency detection and communication, are short-duration pulse loads. They consume no power when not in operation, but consume high peak power when in operation. The single-phase inverter, as its driving power electronic device, amplifies the power of the input signal to the required level to drive the electroacoustic transducer. The output peak power is high but the duty cycle is small, which can impact the input power system and affect the safety and stability of the system.

[0003] To solve this problem, you can use the following methods:

[0004] 1. Increase the input power level to provide pulse peak power, but this will result in capacity waste.

[0005] 2. Directly connecting the energy storage element in parallel to the DC bus has a simple circuit structure and control method, but due to voltage ripple limitation, a large number of electrolytic capacitors need to be connected in parallel, resulting in a large device size and weight, reducing equipment reliability.

[0006] 3. Using a bidirectional DC / DC converter, whose ports are connected to the DC bus and the energy storage capacitor respectively, can cause the voltage of the energy storage capacitor to fluctuate greatly, thereby reducing the capacitance. When working under pulse load, the energy storage capacitor can be discharged quickly to provide voltage support. However, when a multi-phase converter is used to output high power, due to the differences in the parameters of the power semiconductors and inductors of each phase of the converter, there is an imbalance in the current between the phases, which reduces the efficiency of the converter and affects the reliability of the device. Summary of the Invention

[0007] In order to solve the above problems, the present invention discloses a pulse load power supply system with integrated supercapacitor energy storage and a power control method thereof.

[0008] To achieve the above object, the technical solution of the present invention is:

[0009] A pulse load power supply system with integrated supercapacitor energy storage is characterized by including a power supply, a bidirectional DC / DC converter, a supercapacitor, a control host computer, a pulse load, and a driving power electronic device for the pulse load, wherein the power supply is electrically connected to the driving power electronic device for the pulse load and the bidirectional DC / DC converter, the bidirectional DC / DC converter is electrically connected to the supercapacitor, and the pulse load is electrically connected to the driving power electronic device for the pulse load; the bidirectional DC / DC converter and the driving power electronic device for the pulse load are communicatively connected to the control host computer PC; the bidirectional DC / DC converter is used to control the charging and discharging of the supercapacitor to provide the required peak power for the pulse load, and the control host computer is used to control the operating status of the pulse load driving power electronic device and the bidirectional DC / DC converter, and to realize real-time status monitoring.

[0010] Further improvement, the bidirectional DC / DC converter is a bidirectional Buck / Boost converter, a bidirectional Cuk converter or an isolated bidirectional DC / DC converter; the pulse load driving power electronic device is a single-phase half-bridge converter, a single-phase full-bridge DC / AC converter, a single-phase push-pull DC / AC converter or a DC / DC converter.

[0011] Further improvement, the bidirectional Buck / Boost is a four-phase interleaved parallel bidirectional Buck / Boost converter, the four-phase interleaved parallel bidirectional Buck / Boost converter includes a power circuit module, an isolated voltage sampling chip, an isolated current sampling chip, an A / D converter chip, a voltage comparator, an FPGA and an isolated gate drive chip, the power circuit module includes a high-voltage side filter capacitor C Bus , high-voltage side filter capacitor C Bus The positive electrode is electrically connected to the drain of the first switching device S1, the drain of the third switching device S3, the drain of the fifth switching device S5 and the drain of the seventh switching device S7, and the high-voltage side filter capacitor C Bus The negative electrode is electrically connected to the source of the second switching device S2, the source of the fourth switching device S4, the source of the sixth switching device S6, the source of the eighth switching device S8 and the super capacitor C Super The drain of the second switching device S2 is electrically connected to the source of the first switching device S1 and one end of the fourth filter inductor L4; the drain of the fourth switching device S4 is electrically connected to the source of the third switching device S3 and one end of the third filter inductor L3; the drain of the sixth switching device S6 is electrically connected to the source of the fifth switching device S5 and one end of the second filter inductor L2; the drain of the eighth switching device S8 is electrically connected to the source of the seventh switching device S7 and one end of the first filter inductor L1; the other end of the first filter inductor L1, the other end of the second filter inductor L2, the other end of the third filter inductor L3 and the other end of the fourth filter inductor L4 are all electrically connected to the supercapacitor C Super The positive electrode;

[0012] The sampling ends of the isolated voltage sampling chip and the isolated current sampling chip are electrically connected to the super capacitor C Super The positive electrode of the first filter inductor L1, the other end of the second filter inductor L2, the other end of the third filter inductor L3 and the other end of the fourth filter inductor L4, the output end is electrically connected to the A / D converter chip and the voltage comparator; the A / D converter chip and the voltage comparator are electrically connected to the FPGA and the isolated gate driver chip, the isolated gate driver chip is electrically connected to the gate of the first switching device S1, the gate of the second switching device S2, the gate of the third switching device S3, the gate of the fourth switching device S4, the gate of the fifth switching device S5, the gate of the sixth switching device S6, the gate of the seventh switching device S7 and the gate of the eighth switching device S8; the FPGA is connected to the control host computer PC for communication;

[0013] In the power circuit module, the phase difference between the PWM control signals of adjacent half-bridge circuits is 90°, and the PWM phase difference between the upper and lower bridge arms of each half-bridge circuit is 180°.

[0014] Further improvement, the single-phase full-bridge DC / AC converter includes a DC side power decoupling capacitor C h , DC side power decoupling capacitor C h The positive electrode is electrically connected to the drain of the ninth switching device S9 and the drain of the eleventh switching device S 11 The drain, DC side power decoupling capacitor C h The negative electrode is electrically connected to the tenth switching device S 10 The source of the twelfth switching device S 12 The source of the tenth switching device S 10 The drain is electrically connected to the source of the ninth switching device S9 and the filter inductor L f One end of the filter inductor L f The other end is electrically connected to the filter capacitor C o The positive electrode of the twelfth switching device S 12 The drain of the eleventh switching device S is electrically connected to 11 The source and filter capacitor C o of the negative electrode.

[0015] Further improvement, the first switch device S1, the second switch device S2, the third switch device S3, the fourth switch device S4, the fifth switch device S5, the sixth switch device S6, the seventh switch device S7, the eighth switch device S8, the ninth switch device S9, the tenth switch device S 10 , the eleventh switching device S 11 and the twelfth switching device S 12 Both are metal oxide semiconductor field effect transistors.

[0016] A further improvement is that the pulse load power supply system with integrated supercapacitor energy storage is as described in any one of claims 2-5, and the specific steps are as follows: controlling the host computer PC to control the coordinated work of the bidirectional DC / DC converter and the single-phase full-bridge DC / AC converter through the network port, first, after the system is powered on and initialized, the FPGA continuously processes the voltage and current sampling signals of the bidirectional DC / DC converter and the output signal of the protection circuit, and when software or hardware protection occurs, the PWM signal is blocked, and the signal is uploaded to the host computer PC to control the shutdown of the entire system device; when no protection occurs, the host computer PC sends control information to the single-phase full-bridge DC / AC converter and the bidirectional DC / DC converter to control the entire The operating status of the system device is designed based on the wave transmission cycle of the single-phase full-bridge DC / AC converter to design the Buck / Boost mode operation cycle of the bidirectional DC / DC converter, so as to control the supercapacitor charging and discharging cycle to smooth the pulse power of the single-phase full-bridge DC / AC converter: when the single-phase full-bridge DC / AC converter is on standby, the bidirectional DC / DC converter operates in Buck mode and the supercapacitor is charged; when the single-phase full-bridge DC / AC converter is on, the bidirectional DC / DC converter operates in Boost mode and the supercapacitor is discharged. If no protection occurs and the PC host computer does not issue a shutdown command, the above supercapacitor charging and discharging and single-phase full-bridge DC / AC converter standby working process are cycled.

[0017] Further improvements have been made to the system, which operates in two working modes: supercapacitor charging and supercapacitor discharging. In supercapacitor charging mode, the single-phase full-bridge DC / AC converter does not work, and the input power supply achieves the set constant current I through the Buck mode in a competitive manner among the voltage loop, current loop, and power loop. Buck_L_ref , constant power P o_ref and constant voltage V Super_ref The output is switched smoothly, charging the supercapacitor to the set voltage V Super_ref The bidirectional DC / DC converter finally works in the voltage loop to maintain the supercapacitor voltage stability. In the supercapacitor discharge mode, the single-phase full-bridge DC / AC converter works. Through loop competition, the Boost mode of the bidirectional DC / DC converter works in the voltage loop to make the supercapacitor discharge quickly to maintain the high-voltage side DC bus voltage stability, and provide peak power to the load together with the power supply.

[0018] For further improvement, the specific steps are as follows:

[0019] The current and voltage signals collected by the isolated voltage sampling chip and the isolated current sampling chip are converted into sampled digital signals by the A / D converter chip and transmitted to the FPGA. After digital low-pass filtering, the filtered voltage and current values are taken as the feedback signals of the voltage loop and current loop respectively. When the supercapacitor is charging, the bidirectional DC / DC converter works in Buck mode, and the set V Super_ref , I Buck_L_ref and P o_ref By controlling the host computer and sending it to the FPGA, the voltage loop feedback value is the low voltage port voltage filter value V Super , the duty cycle d is calculated by the PI controller v ; Competition between current loop and power loop: take min(P o_ref / V Super ,I Buck_L_ref ) as a reference value, min means taking the minimum value; the first phase inductor current filter value i L1 is the feedback value, and the duty cycle d is calculated by the PI controller pi ; Competition among current loop, power loop and voltage loop: take D Buck =min(d pi ,d v ) is the duty cycle of the first switching device S1, the third switching device S3, the fifth switching device S5 and the seventh switching device S7, and the duty cycle of the second switching device S2, the fourth switching device S4, the sixth switching device S6 and the eighth switching device S8 is 1-D Buck -D dead , in order to prevent the upper and lower bridge arms of the power circuit module from being turned on at the same time, D dead is the dead zone duty cycle; when the supercapacitor is discharged, the bidirectional DC / DC converter works in Boost mode, V Bus_ref , I Boost_L_ref and P o_ref By controlling the host computer and sending it to the FPGA, the voltage loop feedback value is the high-voltage port voltage filter value V Bus , the duty cycle d is calculated by the PI controller v ; Competition between current loop and power loop: take min(P o_ref / V Super ,I Boost_L_ref ) as a reference value, the first phase inductor current filter value i L1 is the feedback value, and the duty cycle d is calculated by the PI controller pi ; Competition among current loop, power loop and voltage loop: take D Boost =min(d pi ,d v) is the duty cycle of the second switch device S2, the fourth switch device S4, the sixth switch device S6 and the eighth switch device S8, and the duty cycle of the first switch device S1, the third switch device S3, the fifth switch device S5 and the seventh switch device S7 of the synchronous tube is 1-D Boost -D dead Among them, the duty cycles of the eight switching tubes are modulated by PWM to generate four-phase eight-channel PWM signals with adjacent bridge arms shifted by 90 degrees, upper and lower bridge arms complementary, and dead time.

[0020] As a further improvement, the voltage loop, current loop, and power loop compete in the following manner:

[0021] The average value of the first filter inductor L1, the second filter inductor L2, the third filter inductor L3 and the fourth filter inductor L4 is the reference value, each inductor current i Ln is the feedback value, and the duty cycle of each phase current calculated by the PI controller is di Ln and the average The difference As the output of each phase current sharing control loop, the sum of the output of each phase current sharing control loop and the output of the competition control loop without current sharing control is used as the duty cycle of each phase switch device; for the buck mode: As the duty ratio of the first switching device S1, the third switching device S3, the fifth switching device S5 and the seventh switching device S7, 1-D n -D dead As the duty ratios of the second switching device S2, the fourth switching device S4, the sixth switching device S6 and the eighth switching device S8, for the Boost mode: As the duty ratio of the second switching device S2, the fourth switching device S4, the sixth switching device S6 and the eighth switching device S8, 1-D n -D dead as duty ratios of the first switching device S1, the third switching device S3, the fifth switching device S5, and the seventh switching device S7;

[0022] The PI controller increment Δu(k) and output u(k) are:

[0023] Δu(k)=u(k)-u(k-1)=k p [e(k)-e(k-1)]+k i e(k)

[0024] u(k)=u(k-1)+Δu(k)

[0025] Among them, k p 、k iare the proportional control coefficient and integral control coefficient of the PI controller, respectively. e(k) and e(k-1) are the input error values of the PI controller at the current and previous sampling moments, respectively. e(k) = reference value - feedback value. u(k) and u(k-1) are the output control quantities (i.e., the duty cycle of the main switch) of the PI controller at the current and previous sampling moments, respectively. Δu(k) is the output control increment.

[0026] According to the DC bus voltage V Bus Set the maximum supercapacitor charging voltage V Supermax =V Super_ref And the minimum discharge voltage V Supermin =V L , pulse load peak power P pulsemax and its pulse power duty cycle T pulse For supercapacitor value C Super Proposed restrictions:

[0027]

[0028] Advantages of the present invention:

[0029] The power supply system of the present invention uses a control host computer to simultaneously issue control instructions to the pulse load driving power electronic equipment and the bidirectional DC / DC converter to make them work together, and controls the bidirectional DC / DC converter to perform periodic charging and discharging to reduce the peak and fill the valley of the periodic pulse load power, thereby improving the safety and stability of the system operation. The power supply system provided utilizes the characteristics of high power density and high cycle life of supercapacitors to charge slowly when the load is not working to absorb redundant power; and discharge quickly when the load is working to quickly support the DC bus voltage. The proposed control method realizes smooth switching of constant current, constant power and constant voltage through competitive output of voltage, current and power control loops: when the supercapacitor is charging, the smooth switching of constant current, constant power and constant voltage is realized, thereby improving the safety and stability of the system; when the supercapacitor is discharging, the DC / DC converter is operated in the voltage control loop to provide a stable voltage for the operation of the pulse load. In order to meet the high-power output scenario, a multi-phase converter can be used. The proposed current sharing control method realizes current sharing control when there are differences in the phase parameters of the multi-phase converter, thereby improving the efficiency and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is an architecture diagram of a pulse load power supply system with integrated supercapacitor energy storage proposed by the present invention;

[0031] Figure 2 A diagram showing the system structure and circuit topology in an embodiment of the present invention;

[0032] Figure 3The hardware structure and functional structure diagram of the four-phase interleaved parallel bidirectional Buck / Boost converter in an embodiment of the present invention;

[0033] Figure 4 This is a system workflow diagram in an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of the power control method proposed in the present invention;

[0035] Figure 6 This is a schematic diagram of the competitive control strategy for the voltage loop, current loop, and power loop proposed in the present invention;

[0036] Figure 7 This is a block diagram of the multi-phase converter current sharing control strategy proposed in the present invention applied to the Buck mode control strategy;

[0037] Figure 8 This is a block diagram of the multi-phase converter current sharing control strategy proposed in the present invention applied to the Boost mode control strategy;

[0038] Figure 9 This is a simulation waveform of the input voltage, current and power of the supercapacitor when charging the supercapacitor in Buck mode according to an embodiment of the present invention;

[0039] Figure 10 This is a simulated waveform diagram of the supercapacitor output voltage, current, power, and DC bus voltage during supercapacitor discharge in Boost mode in an embodiment of the present invention;

[0040] Figure 11 This is a simulated waveform diagram of the supercapacitor output voltage, current, power, and DC bus voltage during supercapacitor discharge in Boost mode in an embodiment of the present invention (expanded);

[0041] Figure 12 1 is a diagram of the output voltage simulation waveform of a single-phase full-bridge DC / AC converter in an embodiment of the present invention (overall);

[0042] Figure 13 1 is a diagram of a simulated output voltage waveform of a single-phase full-bridge DC / AC converter according to an embodiment of the present invention (expanded);

[0043] Figure 14 This is a simulation waveform diagram of the inductor current in Buck mode of the current sharing control strategy in an embodiment of the present invention (overall);

[0044] Figure 15 This is a diagram of the simulated inductor current waveform in the Buck mode of the current sharing control strategy according to an embodiment of the present invention (expanded);

[0045] Figure 16 This is a simulation waveform diagram of the inductor current in the Boost mode of the current sharing control strategy according to an embodiment of the present invention (overall);

[0046] Figure 17 This is a simulation waveform diagram of the inductor current in the Boost mode of the current sharing control strategy according to an embodiment of the present invention (partially expanded); Figure 18 This is a simulated waveform diagram of the inductor current in the Boost mode of the current sharing control strategy in an embodiment of the present invention (fully expanded). DETAILED DESCRIPTION

[0047] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0048] Example

[0049] like Figure 1 As shown, the present invention proposes a pulse load power supply system architecture with integrated supercapacitor energy storage, which includes a pulse load and its driving power electronic equipment, a bidirectional DC / DC converter, a power supply, a supercapacitor, and a control host computer. The pulse load driving power electronic equipment includes but is not limited to single-phase half-bridge, single-phase full-bridge and single-phase push-pull DC / AC converters and DC / DC converters; the bidirectional DC / DC converter includes but is not limited to bidirectional Buck / Boost, bidirectional Cuk and isolated bidirectional DC / DC converters; the power supply is connected in parallel to the bidirectional DC / DC converter port and is connected to the input port of the pulse load driving power electronic equipment; the pulse load is connected to the output port of its driving power electronic equipment; the two ends of the supercapacitor are connected to the other port of the bidirectional DC / DC converter; the control host computer communicates with the bidirectional DC / DC converter and the pulse load driving power electronic equipment through a network port. The bidirectional DC / DC converter is used to control the charging and discharging of the supercapacitor to provide the required peak power for the pulse load, and the control host computer is used to control the working state of the pulse load driving power electronic equipment and the bidirectional DC / DC converter, and to realize real-time state monitoring.

[0050] like Figure 2 As shown, in the embodiment of the present invention, the DC bus voltage is greater than the supercapacitor charging voltage, and there is no electrical isolation requirement. In order to further reduce the volume of the system device and improve the converter efficiency, the bidirectional DC / DC converter is selected as a four-phase interleaved parallel bidirectional Buck / Boost converter, and the high-voltage side filter capacitor C BusThe four-phase interleaved parallel bidirectional Buck / Boost converter is composed of switching devices S1, S2, S3, S4, S5, S6, S7, and S8, and filter inductors L1, L2, L3, and L4. The high-side port of the four-phase interleaved parallel bidirectional Buck / Boost converter is connected to the power supply, and the low-voltage side port is connected to the supercapacitor. S1, S2, S3, S4, S5, S6, and S7, S8 form four half-bridge circuits, the midpoints of the half-bridge circuits are connected to one end of the filter inductors L1, L2, L3, and L4 respectively, the drains of S1, S3, S5, and S7 are connected to the positive electrode of the power supply, the other ends of the filter inductors L1, L2, L3, and L4 are connected to the positive electrode of the supercapacitor, and the negative electrode of the power supply is connected to the sources of S2, S4, S6, and S8 and the negative electrode of the supercapacitor.

[0051] The pulse load driving power electronic device is selected as a single-phase full-bridge DC / AC converter, which is connected to the DC side power decoupling capacitor C h , switching devices S9, S 10 、S 11 、S 12 , filter inductor L f , filter capacitor C o The DC input port of the single-phase full-bridge DC / AC converter is connected to the power supply, and the AC output port is connected to the load. The switching devices S9 and S 10 and S 11 、S 12 Two half-bridge circuits are formed, with switching devices S9 and S 11 The drain and DC side power decoupling capacitor C h The positive electrode of the switch is connected to the positive electrode of the power supply. 10 、S 11 The source and DC side power decoupling capacitor C h The negative pole of the filter inductor L is connected to the negative pole of the power supply. f One end and filter capacitor C o One end is connected to form a low-pass filter, the input end is connected to the midpoint of the two half-bridge circuits, and the output end is connected to the pulse load R o .

[0052] The control host computer is a PC, which is connected to the four-phase interleaved parallel bidirectional Buck / Boost converter and the single-phase full-bridge DC / AC converter through a network port, controls the operating mode of the four-phase interleaved parallel bidirectional Buck / Boost (voltage, current, power reference value, charge and discharge cycle, and start and stop signal) and performs status monitoring (two-port voltage, current, and protection information), while also controlling the operating status of the single-phase full-bridge DC / AC converter (modulation index, carrier, wave transmission cycle, and start and stop signal).

[0053] In this embodiment, the switching devices S1-S 10A metal oxide semiconductor field effect transistor.

[0054] like Figure 3 As shown in the embodiment of the present invention, the four-phase interleaved parallel bidirectional Buck / Boost converter includes a power circuit module, an auxiliary power circuit module, an isolation sampling circuit module, a control circuit module, an isolation drive circuit module and a protection circuit module, and all modules are integrated on a printed circuit board. Figure 2 The four-phase interleaved parallel bidirectional DC / DC converter is used to realize supercapacitor charging and discharging; the auxiliary power supply module is composed of LDO and DC-DC power supply module, which is used to power each chip; the isolation sampling module is composed of voltage and current isolation sampling chip and A / D conversion chip, which is used to sample the two-port voltage and four-phase inductor current and convert them into digital signals before sending them to the control module; the control module is mainly composed of FPGA chip, which is used to process the sampled digital signals and generate eight-way PWM signals, and at the same time process the protection signals, set the software voltage and current protection thresholds, and transmit the software and hardware protection signals to the control host PC; the isolation drive module is mainly composed of isolated gate driver chip The structure is used to amplify the PWM signal generated by the control module and connect it to the gate of S1~S8 to control the switching of S1~S8, wherein the phase difference of the PWM control signals of adjacent half-bridge circuits is 90°, and the PWM phase difference of the upper and lower bridge arms of each half-bridge circuit is 180°; the protection module is mainly composed of a voltage comparator, which compares the voltage output by the isolation sampling chip with the set protection voltage, and is used for port voltage overvoltage protection and inductor current overcurrent protection. When the protection is triggered, a protection signal is generated to control the isolation drive module to output a low level to block the PWM signal, so that S1~S8 are turned off, and the protection signal is transmitted to the host computer at the same time to control the single-phase full-bridge DC / AC converter to stop working.

[0055] like Figure 4As shown, in the embodiment of the present invention, the host computer PC controls the coordinated work of the bidirectional DC / DC converter and the single-phase full-bridge DC / AC converter through the network port. First, after the system is powered on and initialized, the FPGA continuously processes the voltage and current sampling signals of the bidirectional DC / DC converter and the output signal of the protection circuit. When software or hardware protection occurs, the PWM signal is blocked and the signal is uploaded to the host computer PC to control the shutdown of the entire system device. When no protection occurs, the host computer PC can send control information to the single-phase full-bridge DC / AC converter and the bidirectional DC / DC converter to control the operating status of the entire system device. Based on the single-phase full-bridge DC / AC converter, the FPGA continuously processes the voltage and current sampling signals of the bidirectional DC / DC converter and the output signal of the protection circuit. When the software or hardware protection occurs, the PWM signal is blocked and the signal is uploaded to the host computer PC to control the shutdown of the entire system device. When the protection does not occur, the host computer PC can send control information to the single-phase full-bridge DC / AC converter and the bidirectional DC / DC converter to control the operating status of the entire system device. The wave generation cycle of the C / AC converter is designed to match the Buck / Boost mode operation cycle of the bidirectional DC / DC converter, thereby controlling the supercapacitor charge and discharge cycle to smooth the pulse power of the single-phase full-bridge DC / AC converter: when the single-phase full-bridge DC / AC converter is in standby mode, the bidirectional DC / DC converter operates in Buck mode and the supercapacitor charges; when the single-phase full-bridge DC / AC converter is in operation, the bidirectional DC / DC converter operates in Boost mode and the supercapacitor discharges. If no protection occurs and the PC host computer does not issue a shutdown command, the above supercapacitor charge and discharge and single-phase full-bridge DC / AC converter standby operation process are cycled.

[0056] The power control method proposed in this embodiment includes:

[0057] like Figure 5 As shown, according to the characteristics of small duty cycle of pulse load peak power, the system works in two working modes: low-power charging and high-power discharging of supercapacitors. In the low-power charging mode of supercapacitors, the single-phase full-bridge DC / AC converter does not work, and the input power supply achieves a constant current I through the competition of voltage, current and power loops in Buck mode. Buck_L_ref , constant power P o_ref and constant voltage V Super_ref The output is switched smoothly, charging the supercapacitor to the set voltage V Super_ref And make the converter finally work in the voltage loop to maintain the supercapacitor voltage stability; in the supercapacitor high-power discharge mode, the single-phase full-bridge DC / AC converter works, through loop competition, Boost mode works in the voltage loop to make the supercapacitor discharge quickly to maintain the high-voltage side DC bus voltage stability, and provide peak power to the load together with the power supply.

[0058] like Figure 6 As shown, this embodiment provides a method for controlling voltage, current, and power loop competition, which is implemented as follows:

[0059] After the sampled digital signals of the two-port voltage and the four-phase inductor current are transmitted to the FPGA, they are digitally low-pass filtered and the filtered voltage and current values are taken as the feedback signals of the voltage loop and the current (power) loop respectively. When the supercapacitor is charging, the converter works in Buck mode and the voltage loop reference value V Super_ref , current loop reference value I Buck_L_ref And the single-phase power loop reference value P o_ref The voltage loop feedback value is the low voltage port voltage filter value V Super , the duty cycle calculated by the PI controller is d v Competition between current loop and power loop: take min(P o_ref / V Super ,I Buck_L_ref ) as a reference value, the first phase inductor current filter value i L1 is the feedback value, and the duty cycle calculated by the PI controller is d pi ; Competition among current loop, power loop and voltage loop: take D Buck =min(d pi ,d v ) as the duty cycle of the main switches S1, S3, S5, and S7. To improve the efficiency of the converter, a synchronous rectification control method is adopted, that is, the duty cycle of the synchronous tubes S2, S4, S6, and S8 is 1-D Buck -D dead , where D is used to prevent the upper and lower bridge arms from being turned on at the same time. dead is the dead zone duty cycle. When the supercapacitor is discharged, the converter works in Boost mode, and the voltage loop reference value V Bus_ref , current loop reference value I Boost_L_ref And the single-phase power loop reference value P o_ref The voltage loop feedback value is the high voltage port voltage filter value V Bus , the duty cycle calculated by the PI controller is d v Competition between current loop and power loop: take min(P o_ref / V Super ,I Boost_L_ref ) as a reference value, the first phase inductor current filter value i L1 is the feedback value, and the duty cycle calculated by the PI controller is d pi ; Competition among current loop, power loop and voltage loop: take D Boost =min(d pi ,d v ) The duty cycle of the main switch tubes S2, S4, S6, and S8, and the duty cycle of the synchronous tubes S1, S3, S5, and S7 are 1-D Boost -D deadAmong them, the duty cycles of S1 to S8 are modulated by PWM to generate four-phase eight-channel PWM signals with adjacent bridge arms shifted by 90 degrees, upper and lower bridge arms complementary, and dead time.

[0060] When there are differences in circuit parameters such as inductance values between phases of a multi-phase converter, the converter will experience phase current imbalance, which will affect the efficiency and operational stability of the converter. This embodiment provides a current sharing control method for a multi-phase converter, which is applied to the above-mentioned current loop, power loop, and voltage loop competitive control method. The method is implemented as follows:

[0061] like Figure 7 、 Figure 8 As shown, in Figure 6 Without current sharing control, the average current automatic current sharing method is used to take the average value of the four-phase inductor sampling current. is the reference value, the inductor current of each phase i Ln is the feedback value, and the duty cycle of each phase current calculated by the PI controller is di Ln and its average value The difference As the output of each phase current sharing control loop, the sum of the output of each phase current sharing control loop and the output of the competition control loop without current sharing control is used as the duty cycle of each phase main switch. In this embodiment, for the BUCK mode: As the duty cycle of S1, S3, S5, and S7, 1-D n -D dead As the duty cycle of S2, S4, S6, and S8, for Boost mode: As the duty cycle of S2, S4, S6, and S8, 1-D n -D dead As the duty cycle of S1, S3, S5, and S7.

[0062] In this embodiment, the PI controller applies the incremental PI control principle, that is, the PI controller increment Δu(k) and output u(k) are respectively:

[0063] Δu(k)=u(k)-u(k-1)=k p [e(k)-e(k-1)]+k i e(k)

[0064] u(k)=u(k-1)+Δu(k)

[0065] Among them, k p 、k iare the proportional control coefficient and integral control coefficient of the PI controller, respectively. e(k) and e(k-1) are the input error values of the PI controller at the current and previous sampling moments, respectively. e(k) = reference value - feedback value. u(k) and u(k-1) are the output control quantities (i.e., the duty cycle of the main switch) of the PI controller at the current and previous sampling moments, respectively. Δu(k) is the output control increment.

[0066] In this embodiment, according to the DC bus voltage V Bus Set the maximum supercapacitor charging voltage V Supermax =V Super_ref And the minimum discharge voltage V Supermin =V L , pulse load peak power P pulsemax and its pulse power duty cycle T pulse For supercapacitor value C Super Proposed restrictions:

[0067]

[0068] Figures 9 to 18 This is the simulation result of this embodiment.

[0069] Figure 9 Corresponding to Figure 5 In the supercapacitor charging stage, the average value of the supercapacitor charging voltage, current, and power after filtering out the switching frequency harmonics is V Super_aver , I Super_aver and P Super_aver The waveform shows that the use of a pulse load power supply system with integrated supercapacitor energy storage and its power control method provided by the present invention can achieve smooth switching of supercapacitor constant current, power and voltage charging, thereby improving the safety and stability of the system.

[0070] Figures 10 to 13 Corresponding to Figure 5 The supercapacitor discharge stage in Figure 10 It shows that the supercapacitor discharge maintains the DC bus voltage V Bus Stable, providing stable voltage and peak power for the operation of the single-phase full-bridge DC / AC converter, reducing the power level of the power supply; Figure 11 for Figure 10 Waveform expansion diagram; Figure 12 It shows that under the stable DC bus voltage provided by supercapacitor discharge, the single-phase full-bridge DC / AC converter can achieve stable AC voltage output and provide peak power for pulse loads; Figure 13 for Figure 12 Waveform expansion diagram;

[0071] Figures 14 to 18 The simulation waveforms of the current sharing control strategy are as follows:Ln and its average value after filtering out switching frequency harmonics i Ln_aver The waveform of Figure 14 This is the overall waveform of Buck mode. Figure 15 for Figure 14 Expand the waveform. Figure 16 This is the overall waveform of Buck mode. Figure 17 for Figure 16 Partially expanded waveform, Figure 18 for Figure 16 The fully expanded waveform shows that current sharing control in both Buck and Boost modes of the converter can be achieved when a multi-phase circuit is used.

[0072] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and the embodiments. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A power control method for a pulse load power supply system with integrated supercapacitor energy storage, characterized in that: The pulse load power supply system with integrated supercapacitor energy storage includes a power supply, a bidirectional DC / DC converter, a supercapacitor, a control host computer PC, a pulse load, and a driving power electronic device for the pulse load. The power supply is electrically connected to the driving power electronic device for the pulse load and the bidirectional DC / DC converter, the bidirectional DC / DC converter is electrically connected to the supercapacitor, and the pulse load is electrically connected to the driving power electronic device for the pulse load; the bidirectional DC / DC converter and the driving power electronic device for the pulse load are communicatively connected to the control host computer PC; the bidirectional DC / DC converter is used to control the charging and discharging of the supercapacitor to provide the required peak power for the pulse load, and the control host computer PC is used to control the working status of the driving power electronic device for the pulse load and the bidirectional DC / DC converter, and realize real-time status monitoring; The bidirectional DC / DC converter is a bidirectional Buck / Boost converter, a bidirectional Cuk converter or an isolated bidirectional DC / DC converter; the driving power electronic device of the pulse load is a single-phase half-bridge converter, a single-phase full-bridge DC / AC converter, a single-phase push-pull DC / AC converter or a DC / DC converter; The bidirectional Buck / Boost is a four-phase interleaved parallel bidirectional Buck / Boost converter, which includes a power circuit module, an isolated voltage sampling chip, an isolated current sampling chip, an A / D converter chip, a voltage comparator, an FPGA and an isolated gate drive chip. The power circuit module includes a high-voltage side filter capacitor (C Bus ), high-voltage side filter capacitor (C Bus ) is electrically connected to the drain of the first switching device (S1), the drain of the third switching device (S3), the drain of the fifth switching device (S5) and the drain of the seventh switching device (S7), and the high-voltage side filter capacitor (C Bus ) is electrically connected to the source of the second switching device (S2), the source of the fourth switching device (S4), the source of the sixth switching device (S6), the source of the eighth switching device (S8) and the super capacitor (C Super ); the drain of the second switching device (S2) is electrically connected to the source of the first switching device (S1) and one end of the fourth filter inductor (L4); the drain of the fourth switching device (S4) is electrically connected to the source of the third switching device (S3) and one end of the third filter inductor (L3); the drain of the sixth switching device (S6) is electrically connected to the source of the fifth switching device (S5) and one end of the second filter inductor (L2); the drain of the eighth switching device (S8) is electrically connected to the source of the seventh switching device (S7) and one end of the first filter inductor (L1); the other end of the first filter inductor (L1), the other end of the second filter inductor (L2), the other end of the third filter inductor (L3) and the other end of the fourth filter inductor (L4) are all electrically connected to the supercapacitor (C Super )’s positive electrode; The sampling ends of the isolated voltage sampling chip and the isolated current sampling chip are electrically connected to the super capacitor (C Super ), the positive electrode of the first filter inductor (L1), the other end of the second filter inductor (L2), the other end of the third filter inductor (L3) and the other end of the fourth filter inductor (L4), and the output end is electrically connected to the A / D converter chip and the voltage comparator; the A / D converter chip and the voltage comparator are electrically connected to the FPGA and the isolated gate driver chip, and the isolated gate driver chip is electrically connected to the gate of the first switching device (S1), the gate of the second switching device (S2), the gate of the third switching device (S3), the gate of the fourth switching device (S4), the gate of the fifth switching device (S5), the gate of the sixth switching device (S6), the gate of the seventh switching device (S7) and the gate of the eighth switching device (S8); the FPGA is connected to the control host computer PC for communication; In the power circuit module, the PWM control signal phase difference between adjacent half-bridge circuits is 90°, and the PWM phase difference between the upper and lower bridge arms of each half-bridge circuit is 180°; the single-phase full-bridge DC / AC converter includes a DC side power decoupling capacitor (C h ), DC side power decoupling capacitor (C h ) is electrically connected to the drain of the ninth switching device (S9) and the drain of the eleventh switching device (S 11 ) drain, DC side power decoupling capacitor (C h ) is electrically connected to the negative electrode of the tenth switching device (S 10 ) and the source of the twelfth switching device (S 12 ) source; the tenth switching device (S 10 ) is electrically connected to the source of the ninth switching device (S9) and the filter inductor (L f ) one end, the filter inductor (L f ) is electrically connected to the other end of the filter capacitor (C o ) anode; the twelfth switching device (S 12 ) is electrically connected to the drain of the eleventh switching device (S 11 ) source and filter capacitor (C o ) of the negative electrode; The specific steps are as follows: the host computer PC is controlled through the network port to control the coordinated work of the bidirectional DC / DC converter and the single-phase full-bridge DC / AC converter. First, after the system is powered on and initialized, the FPGA continuously processes the voltage and current sampling signals of the bidirectional DC / DC converter and the output signal of the protection circuit. When software or hardware protection occurs, the PWM signal is blocked and the signal is uploaded to the host computer PC to control the shutdown of the entire system device. When no protection occurs, the host computer PC is controlled to send control information to the single-phase full-bridge DC / AC converter and the bidirectional DC / DC converter to control the operating status of the entire system device. Based on the single-phase full-bridge DC The Buck / Boost mode operation cycle of the bidirectional DC / DC converter is designed based on the wave generation cycle of the DC / AC converter, thereby controlling the supercapacitor charge and discharge cycle to smooth the pulse power of the single-phase full-bridge DC / AC converter: when the single-phase full-bridge DC / AC converter is in standby mode, the bidirectional DC / DC converter operates in Buck mode and the supercapacitor is charged; when the single-phase full-bridge DC / AC converter is in operation, the bidirectional DC / DC converter operates in Boost mode and the supercapacitor is discharged. If no protection occurs and the control host PC does not issue a shutdown command, the above supercapacitor charge and discharge and single-phase full-bridge DC / AC converter standby operation process is repeated; The system works in two working modes: supercapacitor charging and supercapacitor discharging. In supercapacitor charging mode, the single-phase full-bridge DC / AC converter does not work, and the input power supply realizes the set constant current I through the Buck mode of the bidirectional DC / DC converter in a competitive manner among the voltage loop, current loop and power loop. Buck_L_ref , constant power P o_ref and constant voltage V Super_ref The output is switched smoothly, charging the supercapacitor to the set voltage V Super_ref The bidirectional DC / DC converter ultimately operates in the voltage loop to maintain the supercapacitor voltage stability. In the supercapacitor discharge mode, the single-phase full-bridge DC / AC converter operates. Through loop competition, the bidirectional DC / DC converter's Boost mode operates in the voltage loop to rapidly discharge the supercapacitor to maintain the high-voltage side DC bus voltage stability, and together with the power supply, provides peak power to the load. The specific steps are as follows: The current and voltage signals collected by the isolated voltage sampling chip and the isolated current sampling chip are converted into sampled digital signals by the A / D converter chip and transmitted to the FPGA. After digital low-pass filtering, the filtered voltage and current values are taken as the feedback signals of the voltage loop and current loop respectively. When the supercapacitor is charging, the bidirectional DC / DC converter works in Buck mode, and the set V Super_ref , I Buck_L_ref and P o_ref By controlling the host PC and sending it to the FPGA, the voltage loop feedback value is the low voltage port voltage filter value V Super , the duty cycle d is calculated by the PI controller v ; Competition between current loop and power loop: take min(P o_ref / V Super ,I Buck_L_ref ) as a reference value, min() means taking the minimum value; The first phase inductor current filter value i L1 is the feedback value, and the duty cycle d is calculated by the PI controller pi ; Competition among current loop, power loop and voltage loop: take D Buck =min(d pi ,d v ) is used as the duty cycle of the first switching device (S1), the third switching device (S3), the fifth switching device (S5) and the seventh switching device (S7), and the duty cycle of the second switching device (S2), the fourth switching device (S4), the sixth switching device (S6) and the eighth switching device (S8) is 1-D Buck -D dead , in order to prevent the upper and lower bridge arms of the power circuit module from being turned on at the same time, D dead is the dead zone duty cycle; when the supercapacitor is discharged, the bidirectional DC / DC converter works in Boost mode, and the voltage loop reference value V Bus_ref , current loop reference value I Boost_L_ref And the single-phase power loop reference value P o_ref By controlling the host PC and sending it to the FPGA, the voltage loop feedback value is the high-voltage port voltage filter value V Bus , the duty cycle d is calculated by the PI controller v ; Competition between current loop and power loop: take min(P o_ref / V Super ,I Boost_L_ref ) as a reference value, the first phase inductor current filter value i L1 is the feedback value, and the duty cycle d is calculated by the PI controller pi ; Competition among current loop, power loop and voltage loop: take D Boost =min(d pi ,d v ) is used as the duty cycle of the second switching device (S2), the fourth switching device (S4), the sixth switching device (S6) and the eighth switching device (S8), and the duty cycle of the first switching device (S1), the third switching device (S3), the fifth switching device (S5) and the seventh switching device (S7) is 1-D Boost -D dead The duty cycles of the eight switching tubes are modulated by PWM to generate four-phase, eight-channel PWM signals with adjacent bridge arms shifted by 90 degrees, upper and lower bridge arms complementary, and with dead time. Without current sharing control, the average current of the first filter inductor (L1), the second filter inductor (L2), the third filter inductor (L3) and the fourth filter inductor (L4) is taken based on the average current automatic current sharing method. is the reference value, each inductor current i Ln is the feedback value, and the duty cycle of each phase current calculated by the PI controller is di Ln and the average The difference As the output of each phase current sharing control loop, the sum of the output of each phase current sharing control loop and the output of the competition control loop without current sharing control is used as the duty cycle of each phase switch device; for the buck mode: As the duty ratio of the first switching device (S1), the third switching device (S3), the fifth switching device (S5) and the seventh switching device (S7), 1-D n -D dead As the duty ratios of the second switching device (S2), the fourth switching device (S4), the sixth switching device (S6) and the eighth switching device (S8), for the Boost mode: As the duty ratio of the second switching device (S2), the fourth switching device (S4), the sixth switching device (S6) and the eighth switching device (S8), 1-D n -D dead as duty ratios of the first switching device (S1), the third switching device (S3), the fifth switching device (S5), and the seventh switching device (S7); The PI controller increment Δu(k) and output u(k) are: Δu(k)=u(k)-u(k-1)=k p [e(k)-e(k-1)]+k i e(k) u(k)=u(k-1)+Δu(k) Among them, k p 、k i are the proportional control coefficient and integral control coefficient of the PI controller, e(k) and e(k-1) are the PI controller input error values at the current and previous sampling moments, e(k) = reference value - feedback value, u(k) and u(k-1) are the PI controller output control quantities at the current and previous sampling moments, Δu(k) is the output control increment; according to the DC bus voltage V Bus Set the maximum supercapacitor charging voltage V Supermax =V Super_ref And the minimum discharge voltage V Supermin =V L , pulse load peak power P pulsemax and its pulse power duty cycle T pulse For supercapacitor value C Super Proposed restrictions: a first switching device (S1), a second switching device (S2), a third switching device (S3), a fourth switching device (S4), a fifth switching device (S5), a sixth switching device (S6), a seventh switching device (S7), an eighth switching device (S8), a ninth switching device (S9), a tenth switching device (S1), a 10 ), the eleventh switching device (S 11 ) and the twelfth switching device (S 12 ) are metal oxide semiconductor field effect transistors.

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