Semiconductor structure and manufacturing method thereof, and memory

Abstract

An embodiment of the present disclosure provides a semiconductor structure, a method for manufacturing the same, and a memory, wherein the semiconductor structure includes: a semiconductor layer, including multiple active areas and an isolation structure separating the multiple active areas; a plurality of contact plugs arranged in an array, located on the semiconductor layer, each contact plug including a first portion and a second portion located on the first portion; wherein the resistivity of the second portion is less than the resistivity of the first portion; and each first portion is in contact with a portion of the active area and a portion of the isolation structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure, a manufacturing method thereof, and a memory. Background Art

[0002] As the integration of semiconductor devices increases, the size and critical dimensions of semiconductor devices continue to shrink, and the reliability requirements for semiconductor devices continue to increase, how to better electrically lead out the active area of ​​semiconductor devices has become an urgent problem to be solved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and a memory.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, including:

[0005] a semiconductor layer comprising an active region and an isolation structure separating the active regions;

[0006] A contact plug is located on the semiconductor layer, the contact plug comprising a first portion and a second portion located on the first portion; wherein the resistivity of the second portion is less than the resistivity of the first portion; and the first portion contacts a portion of the active area and a portion of the isolation structure.

[0007] In the above solution, the material of the first portion includes a doped semiconductor having a first doping concentration; the second portion includes a doped semiconductor having a second doping concentration; and the second doping concentration is greater than the first doping concentration.

[0008] In the above solution, the range of the first doping concentration is: 8.6E20atoms / cm 3 ~1.5E21atoms / cm 3 The second doping concentration range is: 8.6E20atoms / cm 3 ~2.0E21atoms / cm 3 .

[0009] In the above solution, both the first portion and the second portion include a single crystal structure.

[0010] In the above solution, the ratio of the height of the first portion to the height of the second portion is in the range of 1:9 to 1:4.

[0011] In the above solution, the ratio of the height to the width of the contact plug is greater than or equal to 5:1.

[0012] In the above solution, the semiconductor structure further includes a word line structure located in the semiconductor layer and a bit line structure located on the semiconductor layer;

[0013] The word line structure passes through a portion of the active area;

[0014] The bit line structure covers a portion of the active area; the projection of the bit line structure on the surface of the semiconductor layer intersects with the projection of the word line structure on the surface of the semiconductor layer and forms a grid pattern;

[0015] The projection of the contact plug on the surface of the semiconductor layer is located in the grid;

[0016] The semiconductor structure further includes: a storage node located on the contact plug; the storage node is electrically connected to the contact plug.

[0017] In the above solution, the active region includes a first source / drain region located in the middle and a second source / drain region located at both ends;

[0018] The projection of the word line structure on the surface of the semiconductor layer is located between the first source / drain region and the second source / drain region;

[0019] The projection of the bit line structure on the surface of the semiconductor layer covers a portion of the first source / drain region and is electrically connected to the first source / drain region;

[0020] The contact plug is electrically connected to the second source / drain region.

[0021] According to a second aspect of an embodiment of the present disclosure, a memory is provided, comprising: a semiconductor structure as described in any one of the above solutions.

[0022] In the above solution, the memory includes a dynamic random access memory.

[0023] According to a third aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0024] A substrate structure is provided; the substrate structure includes a semiconductor layer and a structural layer formed on the semiconductor layer, wherein a contact hole is formed in the structural layer; wherein the semiconductor layer includes an active area and an isolation structure separating the active area, and the contact hole exposes a portion of the active area and a portion of the isolation structure;

[0025] Using a first process, forming a first portion at the bottom of the contact hole; the first portion is in contact with a portion of the active area and a portion of the isolation structure exposed by the contact hole;

[0026] A second process is used to form a second portion on the first portion; wherein the first portion and the second portion together constitute a contact plug; and the first process is different from the second process.

[0027] In the above solution, the first process is used to form the first portion at the bottom of the contact hole, including:

[0028] Using a deposition process to form a first material layer that at least covers the bottom of the contact hole;

[0029] The first material layer located at the bottom of the contact hole is annealed by using a laser annealing process to obtain the first portion located at the bottom of the contact hole.

[0030] In the above solution, the first material layer also covers the sidewalls of the contact hole and is used to define the top surface of the contact hole structure; and obtaining the first portion located at the bottom of the contact hole includes:

[0031] annealing the first material layer at the bottom of the contact hole using a laser annealing process to obtain the first portion at the bottom of the contact hole and the remaining first material layer at the sidewalls of the contact hole and at the top surface defining the contact hole structure;

[0032] The remaining first material layer is removed to obtain the first portion.

[0033] In the above solution, the first material layer includes a polycrystalline structure; and the first portion includes a single crystal structure.

[0034] In the above solution, the material of the first material layer includes polysilicon; the material of the first portion includes single crystal silicon; the doping element of the first portion includes phosphorus;

[0035] The gas sources used in the deposition process include silane and phosphine, the temperature range used is: 450°C ~ 500°C, and the pressure range used is: 1 torr ~ 3 torr;

[0036] When the laser annealing process is used, the temperature range used is 1400° C. to 1500° C., and the crystallization time is 10 ns to 100 ns.

[0037] In the above solution, the second process is used to form the second part on the first part, including:

[0038] An epitaxial growth process is adopted to form a second material layer on the first portion, which at least fills the contact hole, to obtain the second portion.

[0039] In the above solution, obtaining the second part includes:

[0040] Using an epitaxial growth process, forming a second material layer on the first portion to fill the contact hole and cover a top surface defining the contact hole structure;

[0041] A planarization process is used to remove at least the second material layer located on the top surface used to define the contact hole structure to obtain the second portion; the top surface of the second portion is flush with the top surface used to define the contact hole structure.

[0042] In the above scheme, the second material layer includes a single crystal structure; the second part includes a single crystal structure; the first part has a doping element with a first doping concentration; the second part has a doping element with a second doping concentration; the second doping concentration is greater than the first doping concentration.

[0043] In the above solution, the material of the second material layer includes single crystal silicon; the material of the second portion includes single crystal silicon; the doping element of the second portion includes phosphorus;

[0044] When the epitaxial growth process is adopted, the gas sources used include silane and phosphine, the temperature range used is 550° C. to 600° C., and the pressure range used is 30 torr to 50 torr.

[0045] In the above solution, the base structure further includes a word line structure located in the semiconductor layer and a bit line structure located on the semiconductor layer;

[0046] Forming the base structure includes:

[0047] forming the word line structure in the semiconductor layer; the word line structure passes through a portion of the active area;

[0048] forming the bit line structure on the semiconductor layer; wherein the projection of the bit line structure on the surface of the semiconductor layer intersects with the projection of the word line structure on the surface of the semiconductor layer and forms a grid pattern;

[0049] The contact holes are formed in the grid.

[0050] According to a fourth aspect of an embodiment of the present disclosure, a semiconductor structure is provided, wherein the semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of the above-mentioned schemes.

[0051] In each embodiment of the present disclosure, the first part and the second part constitute a contact plug, and the contact plug contacts the portion of the active area and the portion of the isolation structure exposed at the bottom of the contact hole through the first part. In addition, compared with the scheme of directly forming the contact plug on the portion of the active area and the portion of the isolation structure exposed at the bottom of the contact hole, the contact plug constituted by the first part and the second part provided in each embodiment of the present disclosure has a more uniform top surface morphology, which is conducive to forming a second part with lower resistivity on the first part (the resistivity of the second part is less than the resistivity of the first part); since the top surface of the first part has a more uniform top surface morphology, the second part formed on the first part can obtain a second part with even lower resistivity; in this way, the contact plug constituted by the first part and the second part has a lower resistivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1A and Figure 1B They are respectively a top view and a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Figure 2A and Figure 2B Schematic diagrams of top view and cross-section of a memory provided in an embodiment of the present disclosure;

[0054] Figure 3 A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

[0055] Figures 4A to 4G A schematic top view or cross-sectional view of a manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure is provided.

[0056] Description of reference numerals:

[0057] 10-semiconductor structure; 101-substrate; 103-semiconductor layer; 105-active area; 107-isolation structure; 109-structural layer; 111-contact hole; 113-first material layer; 113'-remaining first material layer; 115-first portion; 117-second material layer; 119-second portion; 121-contact plug; WL-word line; BL-bit line; BLC-bit line contact; DL1-first dotted line; DL2-second dotted line; H1-first height; H2-second height; H3-third height; H4-fourth height; W1-first width; 20-memory; 200-storage structure; 201-first source / drain region; 202-second source / drain region; 203-isolation layer. DETAILED DESCRIPTION

[0058] Exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0059] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0060] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0061] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0062] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, identify the presence of features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] As used herein, the term "aspect ratio" refers to the ratio of depth (or height) to width (or diameter). The term "high aspect ratio" refers to a ratio of depth (or height) to width (or diameter) of at least 5:1. In practical applications, "aspect ratio" or "high aspect ratio" can be used to describe the dimensional characteristics of contact plugs, pillar structures, elongated structures, contact holes, openings, through-holes and / or trenches. For example, a contact hole with a high aspect ratio refers to a contact hole with a depth to width ratio of 5:1.

[0064] As the size of semiconductor devices, such as dynamic random access memory (DRAM), continues to shrink, the size of transistors in the semiconductor devices is also shrinking. The shrinking size poses greater challenges to the performance of the transistors.

[0065] As the size of DRAM memory cells becomes smaller and smaller, its array architecture is 2 Go to 6F 2 Then go to 4F 2 ; The memory architecture has evolved from planar array transistors to recessed gate array transistors, from recessed gate array transistors to buried channel array transistors, and then from buried channel array transistors to vertical channel array transistors.

[0066] DRAM consists of memory cells (storage bits) arranged in an array. Each memory cell consists of a transistor and a capacitor. The transistor acts as a switch between the capacitor and the bit line (BL) and can be activated by a word line (WL) coupled to the control terminal of the transistor. The memory cell can store binary information as a charge on the capacitor.

[0067] The semiconductor structure involved in the embodiments of the present disclosure is to be used in subsequent processes to form at least a portion of a final semiconductor device.

[0068] The memory involved in the embodiments of the present disclosure includes but is not limited to DRAM, and the following description only uses DRAM as an example. It should be noted that the description of DRAM in the following embodiments is only used to illustrate the present disclosure and is not used to limit the scope of the present disclosure.

[0069] With the development of DRAM technology, the size of memory cells is getting smaller and smaller. How to reduce the resistance of the contact plug between the active area of ​​the transistor and the capacitor has become an urgent problem to be solved.

[0070] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and a memory.

[0071] Here and below, the first and second directions are two orthogonal directions perpendicular to the thickness / height of each process layer; the third direction is a direction parallel to the thickness / height of each process layer, and can also be understood as the stacking direction of the formed process layers. For example, the first direction is represented by the X direction in the drawings, or the direction in which the word lines WL extend; the second direction is represented by the Y direction in the drawings, or the direction in which the bit lines BL extend; and the third direction is represented by the Z direction in the drawings, or the direction in which the contact plugs extend.

[0072] Figure 1A and Figure 1B They are respectively a top view schematic diagram and a cross-sectional view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0073] It should be noted that Figure 1B for Figure 1A Schematic diagram of the cross-section along the BB section (XZ plane), Figure 1B It represents a plane along the XZ plane and passing through a row of contact holes (including a portion of the active area) extending along the first direction, and does not pass through the word line extending in the first direction.

[0074] To clearly show the relative positional relationship between the contact plugs arranged in the first direction and the second direction and the word lines, bit lines, and active areas, Figure 1A The outer contours of the word lines, bit lines, and active areas are shown in perspective; among them, the word lines WL, the bit lines BL, and part of the active area 105 are shown in perspective.

[0075] According to a first aspect of an embodiment of the present disclosure, a semiconductor structure 10 is provided, comprising:

[0076] The semiconductor layer 103 includes an active region 105 and an isolation structure 107 separating the active region 105;

[0077] The contact plug 121 is located on the semiconductor layer 103 and includes a first portion 115 and a second portion 119 located on the first portion 115 ; wherein the resistivity of the second portion 119 is less than the resistivity of the first portion 115 ; the first portion 115 contacts a portion of the active area 105 and a portion of the isolation structure 107 .

[0078] In some embodiments, the material of the first portion 115 includes a doped semiconductor having a first doping concentration; the second portion 119 includes a doped semiconductor having a second doping concentration; and the second doping concentration is greater than the first doping concentration.

[0079] In some embodiments, the doping element of the first portion 115 and the doping element of the second portion 119 include N-type doping elements.

[0080] In some embodiments, the first doping concentration is in the range of 8.6E20 atoms / cm 3 ~1.5E21atoms / cm 3 The second doping concentration range is 8.6E20atoms / cm 3 ~2.0E21atoms / cm 3 .

[0081] In some embodiments, the first portion 115 and the second portion 119 each include a single crystal structure.

[0082] In some embodiments, the material of the first portion 115 and the material of the second portion 119 both include single crystal silicon.

[0083] In some embodiments, the ratio of the height of the first portion 115 to the height of the second portion 119 is in a range of 1:9 to 1:4. Figure 1B The height of the first portion is a third height H3, the height of the second portion is a fourth height H4, and the ratio of the third height H3 to the fourth height H4 is in the range of 1:9 to 1:4.

[0084] In some embodiments, the ratio of the height to the width of the contact plug 121 is greater than or equal to 5:1. The width of the contact plug 121 may be a characteristic dimension of the contact plug 121, referring to Figure 1B The characteristic dimension of the contact plug 121 has a first width W1 , the height of the contact plug 121 has a first height H1 , and the ratio of the first height H1 to the first width W1 is greater than or equal to 5:1.

[0085] In some embodiments, the bottom surface of the first portion 115 is lower than or equal to the top surface of the active region 105, and the top surface of the first portion 115 is higher than the top surface of the active region 105. Figure 1B The height of the first portion 115 of the contact plug 121 is a third height H3, that is, the distance between the top surface and the bottom surface of the first portion 115 in the height direction of the contact plug 121 is the third height H3, and the distance between the bottom surface of the contact plug 121 and the top surface of the active area 105 in the height direction of the contact plug 121 is a second height H2, wherein the second height H2 is less than the third height H3.

[0086] In some embodiments, the height of the first portion 115 ranges from 10 nm to 20 nm. Figure 1B The height of the first portion 115 of the contact plug 121 is a third height H3 , and the range of the third height H3 is 10 nm to 20 nm.

[0087] In some embodiments, the substrate structure further includes a word line structure (including word lines WL) located in the semiconductor layer 103 and a bit line structure (including bit lines BL) located on the semiconductor layer 103 ;

[0088] The word line structure (including the word line WL) passes through a portion of the active area 105 ( Figure 1B not shown);

[0089] The bit line structure (including the bit line BL) covers part of the active area 105 ( Figure 1B ); the projection of the bit line structure on the surface of the semiconductor layer 103 intersects with the projection of the word line structure on the surface of the semiconductor layer 103 and forms a grid pattern;

[0090] The projection of the contact plug 121 on the surface of the semiconductor layer 103 is located in the grid;

[0091] The semiconductor structure 10 further includes a storage node located on the contact plug 121 ; the storage node is electrically connected to the contact plug 121 .

[0092] In some embodiments, the active region 105 includes a first source / drain region 201 located in the middle and second source / drain regions 202 located at both ends;

[0093] The projection of the word line structure on the surface of the semiconductor layer 103 is located between the first source / drain region 201 and the second source / drain region 202;

[0094] The projection of the bit line structure on the surface of the semiconductor layer 103 covers a portion of the first source / drain region 201 and is electrically connected to the first source / drain region 201;

[0095] The contact plug 121 is electrically connected to the second source / drain region 202 .

[0096] In each embodiment of the present disclosure, the first part and the second part constitute a contact plug, and the contact plug contacts the portion of the active area and the portion of the isolation structure exposed at the bottom of the contact hole through the first part. In addition, compared with the scheme of directly forming the contact plug on the portion of the active area and the portion of the isolation structure exposed at the bottom of the contact hole, the contact plug constituted by the first part and the second part provided in each embodiment of the present disclosure has a more uniform top surface morphology (here, the uniform top surface morphology may include the top surface area, top surface flatness, crystallinity, etc.), which is conducive to forming a second part with lower resistivity on the first part (the resistivity of the second part is less than the resistivity of the first part); since the top surface of the first part has a more uniform top surface morphology, the second part formed on the first part can obtain a second part with even lower resistivity; in this way, the obtained contact plug constituted by the first part and the second part has an even lower resistivity.

[0097] It should be noted that the scheme for forming contact plugs involved in the embodiments of the present disclosure is not limited to application in memories, but can be applied in any other scenario where a contact plug needs to be formed in a trench with a high aspect ratio and the structure exposed at the bottom of the trench is relatively complex (such as when both active areas and isolation areas exist).

[0098] It should be noted that the semiconductor structure provided by the embodiment of the present disclosure is similar to the semiconductor structure manufactured by the manufacturing method of the semiconductor structure in the following embodiments. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the following embodiments for understanding, and no further details will be given here.

[0099] Figure 2A and Figure 2B They are respectively a top view and a cross-sectional view of a memory provided in an embodiment of the present disclosure.

[0100] It should be noted that Figure 2B for Figure 2A Schematic diagram of the cross-section along the BB section (XZ plane), Figure 2B It represents a plane along the XZ plane and passing through a row of contact holes (including a portion of the active area) extending in the first direction, and does not pass through the word lines extending in the first direction.

[0101] To clearly show the relative positional relationship between the contact plugs and the word lines and bit lines arranged in an array along the first direction and the second direction, Figure 2A The outer contours of the word lines and bit lines are shown in perspective; the outer contours of the word lines WL and bit lines BL are shown in perspective.

[0102] Figure 2A and Figure 2B As shown, a second aspect of the embodiments of the present disclosure provides a memory 20 , comprising: a semiconductor structure 10 as described in any one of the above embodiments.

[0103] Figure 2A and Figure 2B As shown, in some embodiments, the memory 20 includes but is not limited to DRAM. In some embodiments, the DRAM includes an array unit area ( Figure 2A and Figure 2B Part shown) and the core area / peripheral circuit area coupled to the array unit area ( Figure 2A and Figure 2B not shown);

[0104] The array cell area of ​​the DRAM includes: a storage structure (storage node) 200, located on the semiconductor structure 10 of any of the above embodiments, electrically connected to the semiconductor structure 10 through a contact plug 121, and used for storing information;

[0105] The core area / peripheral circuit area of ​​the DRAM is coupled to the array unit area and is configured to: receive a read or write command; and read or rewrite information stored in the storage structure in the array unit area in response to the read or write command.

[0106] Exemplarily, the storage structure 200 is located in the isolation layer 203 and includes capacitors. The capacitors represent logical “1” and “0” by the amount of charge stored therein.

[0107] The core area / peripheral circuit of the DRAM is configured to: receive a read or write command; and read or rewrite information stored in the capacitor in response to the read or write command.

[0108] In practical applications, the capacitor is located within isolation layer 203. The first electrode layer of the capacitor is electrically connected to the second source / drain region via a contact plug. The second electrode layer of the capacitor is electrically connected to a reference voltage, which may be ground or another voltage. Materials for isolation layer 203 include, but are not limited to, silicon nitride, silicon oxide, or silicon oxynitride.

[0109] Figure 3 A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.

[0110] like Figure 3 As shown, a third aspect of the embodiments of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0111] S301, providing a substrate structure; the substrate structure includes a semiconductor layer and a structural layer formed on the semiconductor layer, wherein a contact hole is formed in the structural layer; wherein the semiconductor layer includes an active area and an isolation structure separating the active area, and the contact hole exposes a portion of the active area and a portion of the isolation structure;

[0112] S302, using a first process to form a first portion at the bottom of the contact hole; the first portion is in contact with a portion of the active area and a portion of the isolation structure exposed by the contact hole;

[0113] S303 , using a second process to form a second portion on the first portion; wherein the first portion and the second portion together constitute a contact plug; the first process is different from the second process.

[0114] It should be understood that Figure 3 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 3 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0115] Figures 4A to 4G This is a schematic top view or cross-sectional view of a manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure. Figure 3 、 Figures 4A to 4G , the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0116] It should be noted that Figure 4A A schematic top view on the XY plane of a semiconductor structure manufacturing process provided in an embodiment of the present disclosure; Figures 4B to 4G It is a schematic cross-sectional view on the XZ plane of a manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure.

[0117] Figure 4B for Figure 4A Schematic diagram of the cross-section along the BB section (XZ plane), Figures 4B to 4G represents a plane along the XZ plane that passes through a row of contact holes (including part of the active area) extending in the first direction, and does not pass through the word lines extending in the first direction. Figures 4C to 4G The corresponding XY plane top view diagram can be referred to Figure 4A Combined with Figures 4C to 4G The production processes shown separately are understood and will not be shown here or below.

[0118] To clearly show the relative positional relationship between the contact holes and the word lines, bit lines, and active areas arranged in an array along the first direction and the second direction, Figure 4A The outlines of the word lines, bit lines, and active areas are shown in perspective, where the outlines of the word lines WL and bit lines BL are shown in perspective, and the outline of the remaining portion of the active area excluding the portion exposed by the contact hole is shown in perspective ( Figure 4A The portion enclosed by the first dotted line DL1, the second dotted line DL2 and the contact hole outline).

[0119] Here, a first process is used to form a first portion at the bottom of the contact hole; a second process is used to form a second portion on the first portion; wherein the first process is different from the second process.

[0120] In this way, the first process may include a deposition process and a laser annealing process, and the second process includes an epitaxial growth process; or, the first process includes a deposition process and a rapid thermal annealing process, and the second process includes an epitaxial growth process; or, the first process includes a solid phase crystallization process, and the second process includes an epitaxial growth process, etc.

[0121] For example, refer to Figure 3 、 Figures 4C to 4G The first process includes a deposition process and a laser annealing process. The first portion formed using the first process can fully fill the bottom of the contact hole, and the bottom surface of the first portion can fully contact the portion of the active area exposed at the bottom of the contact hole. Compared to the area of ​​the portion of the active area exposed at the bottom of the contact hole, the top surface of the first portion has a larger contact area, and the difference in the top surface area of ​​each first portion is smaller, which facilitates the formation of the second portion on the first portion.

[0122] The second process includes an epitaxial growth process. Since the top surface of the first portion has a larger contact area and the difference between the top surface areas of the first portions is smaller, the second portion formed on the first portion using the second process has better uniformity and can have a higher doping concentration.

[0123] Compared with directly using the second process to form a contact plug filling the contact hole on the bottom of the contact hole exposing a portion of the active area, the first process is first used to form the first part (base layer), and then the second process is used to form the second part on the first part, which has better uniformity; compared with directly using the first process to form a contact plug filling the contact hole on the bottom of the contact hole exposing a portion of the active area, the first process is used to form the first part, and then the second process is used to form the second part on the first part, which can avoid problems such as premature sealing and filling voids due to excessively high aspect ratio.

[0124] Execute step S301, refer to Figure 3 、 Figure 4A and Figure 4B , providing a base structure.

[0125] The substrate structure may include a semiconductor layer 103 and contact holes 111 arranged in an array on the semiconductor layer; wherein the semiconductor layer 103 includes an active area 105 and an isolation structure 107 separating the active area, and the contact hole 111 exposes part of the active area 105 and part of the isolation structure 107.

[0126] The base structure may include a substrate 101, which may include silicon germanium, gallium arsenide, or other suitable semiconductor materials. Substrate 101 may be a semiconductor-on-insulator, such as silicon-on-insulator. The substrate may include a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer overlying another different type of semiconductor layer, such as a silicon layer overlying a silicon germanium layer. In other examples, the compound semiconductor substrate may include a multilayer silicon structure, or the silicon substrate may include a multilayer compound semiconductor structure.

[0127] Semiconductor layer 103 is located within substrate 101 and includes active regions 105 and isolation structures 107 separating the active regions. Active regions 105 are doped with impurity ions as needed, which may be N-type or P-type. In one embodiment, the doping includes well region doping and source / drain region doping. Isolation structures 107 may include, but are not limited to, shallow trench isolation structures, and materials for isolation structures 107 may include, but are not limited to, silicon oxide.

[0128] The contact hole 111 is located in the structural layer 109 on the semiconductor layer 103. The contact hole exposes a portion of the active area and a portion of the isolation structure. A subsequent process may form a contact plug 112 in the contact hole 111 for electrically leading out the portion of the active area exposed by the contact hole (see the following). Figure 4G ).

[0129] In some embodiments, the bottom surface of the contact hole 111 is lower than or equal to the top surface of the active area 105. In some specific embodiments, the depth of the contact hole 111 is a first height H1, and the distance between the bottom surface of the contact hole 111 and the top surface of the active area 105 in the depth direction of the contact hole 111 is a second height H2, where H1>H2.

[0130] In some specific embodiments, the ratio of the depth to the width of the contact hole 111 may be greater than or equal to 5:1.

[0131] refer to Figure 4A and Figure 4B , in some embodiments, the substrate structure further includes a word line structure located in the semiconductor layer and a bit line structure located on the semiconductor layer;

[0132] Forming a base structure, including:

[0133] forming a word line structure in the semiconductor layer; the word line structure passes through a portion of the active area;

[0134] forming a bit line structure on the semiconductor layer; wherein a projection of the bit line structure on the surface of the semiconductor layer intersects with a projection of the word line structure on the surface of the semiconductor layer and forms a grid pattern;

[0135] Contact holes are formed in the grid.

[0136] A word line structure buried in the active area 105 is formed in the semiconductor layer 103. The word line structure includes a word line WL and a gate dielectric layer ( Figure 4A and Figure 4B The word lines (not shown) may be formed from various metal layers and by various etching and / or patterning techniques applied to various regions of the substrate. The metal layer materials include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. Exemplarily, the word lines WL include titanium nitride and tungsten stacked in sequence. A gate dielectric layer is located between the word lines WL and the active area 105. The gate dielectric layer materials include, but are not limited to, silicon oxide.

[0137] A bit line structure covering the active area 105 is formed in the semiconductor layer 103. The bit line structure includes a bit line BL and a structural layer 109 separating the bit lines BL, and can be formed by various metal layers and various etching and / or patterning techniques on various regions of the substrate. The material of the metal layer includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. The material of the structural layer 109 includes, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride. Exemplarily, the bit line BL includes polysilicon, titanium nitride, and tungsten stacked in sequence; the structural layer 109 includes silicon nitride, silicon oxide, and silicon nitride that sequentially cover the bit line BL. The bit line BL is electrically connected to the active area 105 through a bit line contact (BLC). The material of the bit line contact BLC may include polysilicon.

[0138] The projection of the bitline structure (including the bitline BL) on the surface of the semiconductor layer intersects with the projection of the wordline structure (including the wordline WL) on the surface of the semiconductor layer, forming a grid pattern. Contact holes 111 are formed in the structural layer 109 of the bitline structure, wherein the projection of the contact holes on the surface of the semiconductor layer is in the grid.

[0139] refer to Figure 4A and Figure 4B In some embodiments, the active region includes a first source / drain region 201 located in the middle and second source / drain regions 202 located at both ends;

[0140] The projection of the word line structure (including the word line WL) on the surface of the semiconductor layer is located between the first source / drain region 201 and the second source / drain region 202;

[0141] The projection of the bit line structure (including the bit line BL) on the surface of the semiconductor layer covers a portion of the first source / drain region 201 and is electrically connected to the first source / drain region 201;

[0142] The contact hole 111 exposes a portion of the second source / drain region 202 .

[0143] In this way, the direction in which the active area 105 extends intersects with the direction in which the bit line BL extends; the word line WL and the bit line BL intersect perpendicularly, and each active area 105 intersects with two word lines WL and one bit line BL. In the semiconductor structure formed, each memory cell occupies 6 cell array areas, i.e., 6F. 2 .

[0144] The contact hole 111 is used to form a contact plug, which is electrically connected to the second source / drain region 202 (see below). Figure 4G ).

[0145] Step S302 is performed to form a first portion of the contact plug.

[0146] In some embodiments, reference Figures 4C to 4E , using a first process to form a first portion at the bottom of the contact hole, including:

[0147] Using a deposition process to form a first material layer that at least covers the bottom of the contact hole;

[0148] The first material layer at the bottom of the contact hole is annealed by using a laser annealing process to obtain a first portion at the bottom of the contact hole.

[0149] Here, the deposition process can specifically be a furnace tube deposition process. The first material layer formed by the furnace tube deposition process can conformally fill the bottom of the contact hole, and the bottom surface of the first material layer can fully contact the active area exposed at the bottom of the contact hole. At the same time, the top surface of the first material layer can be a flat transfer plane.

[0150] A laser annealing process is used to anneal the first material layer filling the bottom of the contact hole. During the annealing process, the first material layer becomes a liquid phase. After annealing, the first material layer at the bottom of the contact hole is recrystallized from the liquid phase into a first part. The recrystallization of the first material layer can fully fill the bottom of the contact hole, thereby obtaining the first part that fully fills the bottom of the contact hole. In this way, the first part has a top surface morphology with better uniformity (including top surface area, top surface flatness, etc.), which is conducive to forming a second part with lower resistivity in the subsequent process; and has a bottom surface morphology that is in closer contact with the portion of the active area and the portion of the isolation structure exposed by the contact hole, reflecting a smaller basic resistance with the portion of the active area exposed by the contact hole, providing a good foundation for the subsequent formation of the second part.

[0151] The second portion is formed on the first portion using an epitaxial growth process. It is understood that, compared to the area of ​​the active region exposed at the bottom of the contact hole, the second material layer deposited on the first portion using the epitaxial growth process has better crystal uniformity, a higher doping concentration, and therefore a lower resistivity, because the top surface of the first portion has a larger contact area and the difference in top surface area between the first portions is smaller.

[0152] In some embodiments, reference Figure 4C The first material layer also covers the sidewalls of the contact hole and is used to define the top surface of the contact hole structure; obtaining a first portion located at the bottom of the contact hole, including:

[0153] refer to Figure 4D , using a laser annealing process to anneal the first material layer located at the bottom of the contact hole to obtain a first portion located at the bottom of the contact hole and a remaining first material layer located at the sidewall of the contact hole and at the top surface for defining the contact hole structure;

[0154] refer to Figure 4E , removing the remaining first material layer to obtain the first part.

[0155] like Figure 4C As shown, a furnace tube deposition process including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) can be used to conformally deposit the first material layer 113 on the bottom, sidewall and top surface (top surface of the structural layer 109 between the contact holes) of the contact hole 111.

[0156] In-situ doping may also be employed, using furnace deposition processes including but not limited to PVD, CVD, or ALD, whereby a gas containing doping atoms is introduced during deposition to form a first material layer 113 of doping elements having a first doping concentration.

[0157] The first material layer formed using the furnace deposition process can non-selectively fill the bottom of the contact hole and fully contact the bottom surface and sidewalls of the contact hole. This means that the first material layer can fully contact the surface of the exposed active area at the bottom of the contact hole. At the same time, it can ensure that the first material layer can obtain a high doping concentration.

[0158] Here, the material of the first material layer 113 may include a polycrystalline structure. Specifically, the material of the first material layer 113 may include but is not limited to polycrystalline silicon.

[0159] Here, the doping element of the first doping concentration includes an N-type doping element. The first doping concentration is in the range of 8.6E20 atoms / cm 3 ~1.5E21atoms / cm 3 .

[0160] In some embodiments, the height of the first material layer 113 at the bottom of the contact hole ranges from 10 nm to 20 nm.

[0161] It should be noted that the height of the first material layer 113 at the bottom of the contact hole should not be too small or too large. If the height of the first material layer 113 at the bottom of the contact hole is too small (less than 10nm), it will not be conducive to the first material layer fully filling the bottom of the contact hole; if the height of the first material layer 113 at the bottom of the contact hole is too large (greater than 20nm), this will result in incomplete annealing of the first material layer by the subsequent laser annealing process, and the first material layer 113 at the bottom of the contact hole cannot be converted from a polycrystalline structure or fully converted into a single crystal structure.

[0162] like Figure 4D As shown, a laser annealing process may be used to perform annealing on the first material layer 113 located at the bottom, sidewall, and top surface (the top surface of the structural layer 109 between the contact holes) of the contact hole.

[0163] Here, the laser annealing process can fully recrystallize the first material layer 113 at the bottom of the contact hole.

[0164] In some embodiments, a laser annealing process may be used to convert the crystal structure of the first material layer 113 at the bottom of the contact hole from a polycrystalline structure to a single crystal structure.

[0165] For example, the material of the first material layer 113 is polysilicon, and the laser annealing process can crystallize the portion of the first material layer 113 at the bottom of the contact hole that contacts the active region 105 (see FIG. Figure 4D Because the active area is single crystal silicon, the portion of the first material layer 113 in contact with the active area 105 is crystallized and then recrystallized into single crystal silicon, and the other portions (the first material layer 113 on the sidewall of the contact hole 111 and the top surface of the structural layer 109, refer to Figure 4D The remaining first material layer 113') is still polysilicon. In this way, the remaining first material layer 113' has an etching selectivity ratio with the first portion 115. In the subsequent process, Figure 4E , which is conducive to removing the remaining first material layer 113 ′ to obtain the first portion 115 located at the bottom of the contact hole.

[0166] In some other specific embodiments, the material of the first material layer is polycrystalline silicon, and the laser annealing process can cause the portion of the first material layer located at the bottom of the contact hole to be crystallized and then recrystallized into single crystal silicon, wherein there is still a portion of the first material layer ( Figure 4D Not shown), this part of the first material layer is still polysilicon, and the first material layer 113 on the sidewall of the contact hole 111 and the top surface of the structure layer 109 is still polysilicon. In the subsequent process, refer to Figure 4E, removing part of the first material layer located on the first portion, and removing the first material layer located on the sidewall of the contact hole and the top surface of the structural layer, to obtain a first portion 115 located at the bottom of the contact hole.

[0167] In some embodiments, the first material layer comprises a polycrystalline structure; and the first portion comprises a single crystalline structure.

[0168] The material of the first material layer and the material of the first portion may include silicon, silicon germanium, gallium arsenide, or other suitable semiconductor materials. The first material layer includes a polycrystalline structure, and the first portion includes a single crystal structure.

[0169] Compared to solutions that use a polycrystalline first material layer to fill the bottom of the contact hole without laser annealing, in the disclosed embodiment, a laser annealing process is used to anneal the first material layer filling the bottom of the contact hole. During the annealing process, the first material layer transforms into a liquid phase. After annealing, the first material layer at the bottom of the contact hole recrystallizes from the liquid phase into a first portion, fully filling the bottom of the contact hole. The polycrystalline first material layer transforms into a liquid phase and recrystallizes from the liquid phase into a single crystal phase, resulting in a first portion 115 having a single crystal structure. The first portion 115 having a single crystal structure has a more uniform top surface morphology (including top surface area and top surface flatness), facilitating the formation of a lower resistivity second portion in subsequent processing. Furthermore, the first portion 115 has a bottom surface morphology that is in closer contact with the portion of the active area and isolation structure exposed by the contact hole, resulting in a lower base resistance relative to the portion of the active area exposed by the contact hole.

[0170] Compared to the polycrystalline first material layer 113, the single-crystal first portion 115 has fewer grain boundaries (interfaces between adjacent grains) at a microscopic level and exhibits a lower resistivity at a macroscopic level. For example, the resistance of the polycrystalline first material layer 113 at the same doping concentration is ten times greater than that of the single-crystal first material layer at the same doping concentration. The single-crystal first portion at the same doping concentration has a lower resistance.

[0171] In practical applications, the laser annealing process requires controlling the laser energy density, the duration of the laser heating process, and the laser annealing temperature. Specifically, the height of the first material layer 113 at the bottom of the contact hole to be laser annealed ranges from 10nm to 20nm, and the laser annealing temperature ranges from 1400°C to 1500°C. The energy absorbed by the first material layer 113 at the bottom of the contact hole is high enough to transform into a liquid phase during the annealing process. After annealing, the first material layer 113 at the bottom of the contact hole crystallizes from the liquid phase into a single crystal, resulting in the first portion 115 at the bottom of the contact hole.

[0172] In some embodiments, the material of the first material layer includes polysilicon; the material of the first portion includes single crystal silicon; the doping element of the first portion includes phosphorus;

[0173] The gas sources used in the deposition process include silane and phosphine, the temperature range used is: 450°C ~ 500°C, and the pressure range used is: 1 torr ~ 3 torr;

[0174] When the laser annealing process is used, the temperature range used is 1400° C. to 1500° C., and the crystallization time is 10 ns to 100 ns.

[0175] For example, refer to Figure 4C A furnace tube deposition process is used with a temperature range of 450°C to 500°C, a pressure range of 1 torr to 3 torr, and a time range of 30 minutes to 45 minutes. The gas sources used include silane (flow rate range of 750 sccm to 900 sccm) and phosphine (flow rate range of 200 sccm to 300 sccm). A first material layer can be formed to fill the bottom of the contact hole. The first material layer is doped with phosphorus and has a doping concentration range of 8.6E20 atoms / cm 3 ~1.5E21atoms / cm 3 of polysilicon.

[0176] For example, refer to Figure 4D The laser annealing process uses a temperature range of 1400°C to 1500°C, a pressure range of standard atmospheric pressure (ATM), a crystallization time range of 10ns to 100ns, and a laser output wavelength of 532nm. This can convert the polysilicon filling the bottom of the contact hole into a phosphorus-doped layer with a doping concentration range of 8.6E20 atoms / cm 3 ~1.5E21atoms / cm 3 In practical applications, laser annealing can be performed in an inert gas atmosphere.

[0177] Here, the crystallization time should not be too short or too long: the crystallization time is controlled between 10ns and 100ns, and the first material layer near the bottom of the contact hole is fully crystallized from polycrystalline silicon to single crystal silicon under the induction of the single crystal silicon substrate; if the crystallization time is too short, for example, less than 10ns, it is not conducive to the first material layer near the bottom of the contact hole to be fully crystallized into single crystal silicon; if the crystallization time is too long, for example, greater than 100ns, it will cause too much single crystal silicon to appear on the side wall of the contact hole, affecting the next step of epitaxial growth of the second part, resulting in the generation of gaps, which is not conducive to obtaining a low-resistivity contact plug.

[0178] like Figure 4EAs shown, a selective epitaxial in-situ etching process can be used to remove the remaining first material layer 113' located on the sidewalls and top surface of the contact hole (the top surface of the structural layer 109 between the contact holes), leaving the first portion 115 at the bottom of the contact hole. By utilizing the etching selectivity between the remaining first material layer 113' and the first portion 115, the remaining first material layer 113' can be selectively removed to obtain the first portion 115 at the bottom of the contact hole.

[0179] For example, refer to Figure 4E , using a selective epitaxial in-situ etching process, the temperature range used is: 700 ℃ ~ 750 ℃; the pressure range used is: 5 torr ~ 30 torr; the time range used is: 180s ~ 300s; the etching gas used includes monobasic acid HC (the flow range of HC is 150sccm ~ 300sccm); the polysilicon on the first part 115 can be removed, the polysilicon on the sidewall and top surface of the contact hole (the top surface of the structural layer 109 between the contact holes) can be removed, and the single crystal silicon at the bottom of the contact hole is retained to obtain the first part filling the bottom of the contact hole; wherein the first part has a phosphorus doping element with a doping concentration range of 8.6E20atoms / cm 3 ~1.5E21atoms / cm 3 In some specific embodiments, the height of the first portion may range from 10 nm to 20 nm.

[0180] It should be noted that the laser annealing process can act on local structures, components or layers of the semiconductor structure, and although the temperature is high, the action time is short, and it will not cause unnecessary damage to other structures, components or layers in the semiconductor structure.

[0181] Since the top surface of the first part has a larger contact area and the difference between the top surface areas of each first part is smaller, the first part has a uniform crystal structure after recrystallization. The second material layer deposited on the first part using the first part as a seed crystal using an epitaxial growth process makes the crystallization uniformity of the second material layer better, and also enables the second material layer to have a higher doping concentration.

[0182] In some embodiments, the bottom surface of the first portion 115 is lower than or equal to the top surface of the active region 105, and the top surface of the first portion 115 is higher than the top surface of the active region 105. In some specific embodiments, the thickness of the first portion 115 is a third height H3, and the distance between the top surface of the first portion 115 and the top surface of the active region 105 in the thickness direction of the first portion 115 is the difference between the third height H3 and the second height H2.

[0183] In some embodiments, the height of the first portion 115 ranges from 10 nm to 20 nm. Figure 4E The first portion 115 has a third height H3, and the third height H3 ranges from 10 nm to 20 nm.

[0184] It should be noted that the height of the first part 115 should not be too small or too large. If the height of the first part 115 is too small (less than 10 nm), it is not conducive to the first part 115 being able to fully fill the bottom of the contact hole; if the height of the first part 115 is too large (greater than 20 nm), for example, because the doping concentration in the first part 115 is lower than the doping concentration in the second part, the proportion of the first part 115 in the contact plug finally formed is too large, resulting in the inability to further increase the doping concentration of the contact plug, thereby limiting the further reduction of the resistivity of the contact plug.

[0185] Step S303 is performed to form a second portion of the contact plug.

[0186] In some embodiments, a second process is used to form a second portion on the first portion, including:

[0187] An epitaxial growth process is adopted to form a second material layer at least filling the contact hole on the first part to obtain the second part.

[0188] like Figure 4E 、 Figure 4F As shown, a selective epitaxial growth process may be used to form a second material layer 117 on the first portion 115 to at least fill the contact hole and cover the top surface of the contact hole and the contact hole.

[0189] Alternatively, an in-situ doping method may be used, wherein a selective epitaxial growth process is employed and a gas containing doping atoms is introduced simultaneously to form the second material layer 117 of the doping element having the second doping concentration.

[0190] The second material layer 117 epitaxially grown on the first portion 115 has the same crystal structure as the first portion 115. For example, the first portion 115 has a single crystal structure, the second material layer 117 epitaxially grown on the first portion 115 also has a single crystal structure, and the second portion 119 obtained after planarizing the second material layer 117 has a single crystal structure.

[0191] Here, the material of the second material layer 117 may include but is not limited to a single crystal structure. Specifically, the material of the second material layer 117 may include but is not limited to single crystal silicon.

[0192] Here, the doping element of the second doping concentration includes an N-type doping element. The second doping concentration is in the range of 8.6E20 atoms / cm3 ~2.0E21atoms / cm 3 .

[0193] In some embodiments, the second material layer 117 has a second doping concentration of the doping element, the first material layer 113 has a first doping concentration of the doping element, and the second doping concentration is greater than the first doping concentration.

[0194] Compared with the solution using the furnace deposition process, when the second material layer 117 having the second doping concentration of the doping element is formed by the epitaxial growth process, the second doping concentration can be further increased, and the resistance value of the obtained second portion is further reduced. For example, the second doping concentration is 8.6E20atoms / cm 3 Increased to 2.0E21 atoms / cm 3 , further reducing the resistance value of the second part.

[0195] In some embodiments, obtaining the second portion comprises:

[0196] like Figure 4F As shown, an epitaxial growth process is used to form a second material layer on the first portion to fill the contact hole and cover the top surface for defining the contact hole structure;

[0197] like Figure 4G As shown, a planarization process is used to remove at least the second material layer located on the top surface for defining the contact hole structure to obtain a second portion; the top surface of the second portion is flush with the top surface for defining the contact hole structure.

[0198] like Figure 4F As shown, a selective epitaxial growth process may be used to form a second material layer 117 on the first portion 115 to fill the contact hole and cover the top surface for defining the contact hole structure.

[0199] like Figure 4G As shown, a chemical mechanical polishing (CMP) process can be used to planarize the second material layer 117, remove the second material layer 117 located on the top surface of the contact hole (the top surface of the structural layer 109 between the contact holes), and retain the second material layer 117 located in the contact hole.

[0200] Second material layer 117 located in the contact hole forms second portion 119. The top surface of the second portion is flush with the top surface of the contact hole (the top surface of structural layer 109 between the contact holes). In some embodiments, the second material layer comprises a single crystal structure; the second portion comprises a single crystal structure; the first portion has a doping element with a first doping concentration; the second portion has a doping element with a second doping concentration; and the second doping concentration is greater than the first doping concentration.

[0201] The material of the second material layer and the material of the second portion may include silicon, silicon germanium, gallium arsenide, or other suitable semiconductor materials, and both the second material layer and the first portion include a single crystal structure.

[0202] The doping concentration range of the first part is 8.6E20atoms / cm 3 ~1.5E21atoms / cm 3 The doping concentration range of the second part is 1.5E21atoms / cm 3 ~2.0E21atoms / cm 3 .

[0203] In some embodiments, the material of the second material layer includes single crystal silicon; the material of the second portion includes single crystal silicon; the doping element of the second portion includes phosphorus;

[0204] When the epitaxial growth process is adopted, the gas sources used include silane and phosphine, the temperature range used is 550° C. to 600° C., and the pressure range used is 30 torr to 50 torr.

[0205] For example, refer to Figure 4F A selective epitaxial growth process is used, with a temperature range of 550° C. to 600° C., a pressure range of 30 torr to 50 torr, and a time range of 180 seconds to 300 seconds. The gas sources used include silane (with a flow rate of 180 sccm to 270 sccm) and phosphine (with a flow rate of 30 sccm). A second material layer can be formed on the first portion to at least fill the contact hole and cover the top surface and the contact hole. The second material layer is doped with phosphorus and has a doping concentration of 8.6E20 atoms / cm 3 ~2.0E21atoms / cm 3 of single crystal silicon.

[0206] For example, refer to Figure 4G A chemical mechanical polishing process can be used, with a grinding head speed range of 90 rpm to 100 rpm, a wafer speed range of 85 rpm to 96 rpm, and a polishing liquid flow range of 180 sccm to 200 sccm. The second material layer on the top surface of the contact hole can be removed, while the second material layer in the contact hole is retained, resulting in a second portion located on the first portion. The second portion is flush with the top surface (top surface of the structural layer 109) used to define the contact hole structure. The second portion is doped with phosphorus and has a doping concentration range of 8.6E20 atoms / cm 3 ~2.0E21atoms / cm 3In some specific embodiments, the ratio of the height of the first portion to the height of the second portion may be in a range of 1:9 to 1:4.

[0207] In this way, a first part 115 filling the bottom of the contact hole and a second part 119 located on the first part are obtained. The first part and the second part constitute a contact plug 121. The contact plug fills the contact hole, and the top surface of the contact plug is flush with the top surface used to define the contact hole structure (the top surface of the structural layer 109).

[0208] In some embodiments, the first material layer includes a polycrystalline structure, and the second material layer includes a single crystal structure; the first portion and the second portion both include a single crystal structure; the first portion has a doping element with a first doping concentration; the second portion has a doping element with a second doping concentration; and the second doping concentration is greater than the first doping concentration.

[0209] The materials of the first part and the second part may both include silicon, silicon germanium, gallium arsenide, or other suitable semiconductor materials, and the materials of the first part and the second part have the same or similar crystal structures; the second part can be epitaxially grown using the material of the first part as a seed crystal, so that the material of the second part has the same or similar crystal structure as the material of the first part.

[0210] In some embodiments, the material of the first material layer includes polycrystalline silicon; the material of the first portion includes single crystal silicon; the material of the second material layer includes single crystal silicon; the material of the second portion includes single crystal silicon; the doping element of the first portion and the doping element of the second portion both include phosphorus;

[0211] The first material layer is formed by a furnace deposition process; the first portion is formed by a laser annealing process; and the first material layer is formed by an epitaxial growth process. For details, please refer to the above Figures 4C to 4G Please understand and I will not elaborate on it here.

[0212] In some embodiments, the ratio of the height of the first portion to the height of the second portion is in a range of 1:9 to 1:4. Figure 4G The height of the first portion 115 is a third height H3, and the height of the second portion 119 is a fourth height H4. The ratio of the third height H3 to the fourth height H4 ranges from 1:9 to 1:4. The sum of the heights of the first portion 115 and the second portion 119 can be substantially the same as the height of the contact hole, that is, the sum of the third height H3 and the fourth height H4 can be substantially the same as the first height H1. Substantially the same can be understood as meaning that within the allowable range of process errors and the normal tolerance range of process losses, even if the dimensions, performance, and other values ​​are different or similar, they are considered the same.

[0213] In some embodiments, the height of the first portion 115 ranges from 10 nm to 20 nm. In some embodiments, the height of the contact plug 121 ranges from 80 nm to 120 nm.

[0214] In some embodiments, the ratio of the height of the first portion 115 to the height of the second portion 119 ranges from 1:9 to 1:4.

[0215] In some embodiments, the ratio of the height to the width of the contact plug 121 is greater than or equal to 5:1. Compared to the solution of manufacturing a contact plug in a contact hole with a high aspect ratio through a one-step process, in the embodiment of the present disclosure, a contact plug 121 with a lower resistivity is manufactured in the contact hole 111 with a high aspect ratio through a two-step process. In some specific embodiments, when depositing a polycrystalline structure in a contact hole with a high aspect ratio through a one-step process, it is impossible to achieve a high doping concentration, and / or air gaps are easily formed, resulting in a contact plug with a higher resistivity; in the embodiment of the present disclosure, a highly doped single-crystal contact plug can be manufactured in a contact hole with a high aspect ratio through a two-step process, which can reduce the resistivity of the contact plug. For example, the polycrystalline structure here can be polycrystalline silicon; the single-crystal structure can be single-crystal silicon.

[0216] In some embodiments, a bottom surface of the first portion 115 is lower than or equal to a top surface of the active region 105 , and a top surface of the first portion 115 is higher than a top surface of the active region 105 .

[0217] Thus, on the one hand, the contact plug formed by the first portion and the second portion has better crystallographic uniformity (including uniformity of crystallization rate and uniformity of crystal grain size). For example, since both the first portion and the second portion comprise a single crystal structure, the contact plug formed by the first portion and the second portion having a single crystal structure has fewer grain boundaries (interfaces between adjacent crystal grains) at the microscopic level and exhibits lower resistivity at the macroscopic level compared to a contact plug having a polycrystalline first portion and a polycrystalline second portion. On the other hand, because the top surface of the first portion has a larger contact area and a more uniform top surface morphology (including top surface area and top surface flatness), the second portion formed on the first portion has better crystallographic uniformity (including uniformity of crystallization rate and uniformity of crystal grain size) than a contact plug formed directly on the bottom of the contact hole, exposing a portion of the active area to fill the contact hole. This allows for a higher doping concentration, resulting in a second portion with lower resistivity, and thus a contact plug formed by the first portion and the second portion having lower resistivity.

[0218] In various embodiments of the present disclosure, the first portion and the second portion constitute a contact plug. The contact plug is in full contact with a portion of the active area and a portion of the isolation structure exposed at the bottom of the contact hole through the first portion. Furthermore, compared to the portion of the active area exposed at the bottom of the contact hole, the top surface of the first portion has a larger area, which facilitates the formation of a second portion with lower resistivity on the first portion (the resistivity of the second portion is lower than that of the first portion).

[0219] Since the top surface of the first part has a larger contact area and a more uniform top surface morphology (including top surface area size, top surface flatness, etc.), the second part formed on the first part can obtain a second part with a lower resistivity; in this way, the contact plug composed of the first part and the second part has a lower resistivity.

[0220] According to a fourth aspect of an embodiment of the present disclosure, a semiconductor structure is provided, which is manufactured by the method for manufacturing a semiconductor structure according to any one of the above-mentioned solutions.

[0221] Here, please refer to the above for details. Figures 4A to 4G The manufacturing method of the semiconductor structure is provided for understanding and will not be described in detail here.

[0222] The semiconductor structure obtained by the method for manufacturing a semiconductor structure provided in the embodiment of the present disclosure is similar to the semiconductor structure in the above embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0223] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a base structure; The base structure includes a semiconductor layer and a structural layer formed on the semiconductor layer, wherein a contact hole is formed in the structural layer; wherein the semiconductor layer includes an active area and an isolation structure separating the active area, and the contact hole exposes a portion of the active area and a portion of the isolation structure; Using a first process, forming a first portion at the bottom of the contact hole; the first portion is in contact with a portion of the active area and a portion of the isolation structure exposed by the contact hole; forming a second portion on the first portion using a second process; wherein the first portion and the second portion together constitute a contact plug; and the first process is different from the second process; The step of forming the first portion at the bottom of the contact hole by using the first process includes: Using a deposition process to form a first material layer that at least covers the bottom of the contact hole; annealing the first material layer at the bottom of the contact hole using a laser annealing process to obtain the first portion at the bottom of the contact hole; The step of forming the second portion on the first portion by using a second process includes: forming a second material layer on the first portion to at least fill the contact hole by an epitaxial growth process, thereby obtaining the second portion; The second material layer includes a single crystal structure; the second portion includes a single crystal structure; the first portion has a doping element with a first doping concentration; the second portion has a doping element with a second doping concentration; and the second doping concentration is greater than the first doping concentration.

2. The production method according to claim 1, characterized in that The first material layer also covers the sidewalls of the contact hole and is used to define the top surface of the contact hole structure; The obtaining of the first portion located at the bottom of the contact hole comprises: annealing the first material layer at the bottom of the contact hole using a laser annealing process to obtain the first portion at the bottom of the contact hole and the remaining first material layer at the sidewalls of the contact hole and at the top surface defining the contact hole structure; The remaining first material layer is removed to obtain the first portion.

3. The production method according to claim 1, characterized in that The first material layer includes a polycrystalline structure; and the first portion includes a single crystal structure.

4. The production method according to claim 3, characterized in that: The material of the first material layer includes polysilicon; the material of the first portion includes single crystal silicon; the doping element of the first portion includes phosphorus; The gas sources used in the deposition process include silane and phosphine, the temperature range used is: 450°C ~ 500°C, and the pressure range used is: 1 torr ~ 3 torr; When the laser annealing process is adopted, the annealing temperature range is 1400° C. to 1500° C., and the annealing time is 10 ns to 100 ns.

5. The production method according to claim 1, characterized in that: The obtaining of the second part comprises: Using an epitaxial growth process, forming a second material layer on the first portion to fill the contact hole and cover a top surface defining the contact hole structure; A planarization process is used to remove at least the second material layer located on the top surface used to define the contact hole structure to obtain the second portion; the top surface of the second portion is flush with the top surface used to define the contact hole structure.

6. The production method according to claim 1, characterized in that: The material of the second material layer includes single crystal silicon; the material of the second portion includes single crystal silicon; and the doping element of the second portion includes phosphorus; When the epitaxial growth process is adopted, the gas sources used include silane and phosphine, the temperature range used is 550° C. to 600° C., and the pressure range used is 30 torr to 50 torr.

7. The production method according to claim 1, characterized in that: The base structure further includes a word line structure located in the semiconductor layer and a bit line structure located on the semiconductor layer; Forming the base structure includes: forming the word line structure in the semiconductor layer; the word line structure passes through a portion of the active area; forming the bit line structure on the semiconductor layer; wherein the projection of the bit line structure on the surface of the semiconductor layer intersects with the projection of the word line structure on the surface of the semiconductor layer and forms a grid pattern; The contact holes are formed in the grid.

8. A semiconductor structure manufactured according to any one of claims 1 to 7, characterized in that: include: a semiconductor layer comprising an active region and an isolation structure separating the active regions; a contact plug located on the semiconductor layer, the contact plug comprising a first portion and a second portion located on the first portion; wherein the resistivity of the second portion is lower than the resistivity of the first portion; and the first portion contacts a portion of the active region and a portion of the isolation structure; The material of the first portion includes a doped semiconductor with a first doping concentration; the second portion includes a single crystal structure and a doped semiconductor with a second doping concentration; the second doping concentration is greater than the first doping concentration.

9. The semiconductor structure according to claim 8, wherein: The range of the first doping concentration is: 8.6E20atoms / cm 3 ~1.5E21atoms / cm 3 The second doping concentration range is: 8.6E20atoms / cm 3 ~2.0E21atoms / cm 3 .

10. The semiconductor structure according to claim 8, wherein: The first portions each include a single crystal structure.

11. The semiconductor structure according to claim 8, wherein: The ratio of the height of the first portion to the height of the second portion is in a range of 1:9 to 1:

4.

12. The semiconductor structure according to claim 8, wherein: The ratio of the height to the width of the contact plug is greater than or equal to 5:

1.

13. The semiconductor structure according to claim 8, wherein: The semiconductor structure further includes a word line structure located in the semiconductor layer and a bit line structure located on the semiconductor layer; The word line structure passes through a portion of the active area; The bit line structure covers a portion of the active area; The projection of the bit line structure on the surface of the semiconductor layer intersects with the projection of the word line structure on the surface of the semiconductor layer and forms a grid pattern; The projection of the contact plug on the surface of the semiconductor layer is located in the grid; The semiconductor structure further includes: a storage node located on the contact plug; The storage node is electrically connected to the contact plug.

14. The semiconductor structure according to claim 13, wherein: The active region includes a first source / drain region located in the middle and a second source / drain region located at both ends; The projection of the word line structure on the surface of the semiconductor layer is located between the first source / drain region and the second source / drain region; The projection of the bit line structure on the surface of the semiconductor layer covers a portion of the first source / drain region and is electrically connected to the first source / drain region; The contact plug is electrically connected to the second source / drain region.

15. A memory, characterized in that: include: The semiconductor structure according to any one of claims 8 to 14.

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