Pixel circuit, display panel, and display device

Abstract

This application discloses a pixel circuit, a display panel, and a display device. The pixel circuit includes: a driving module, whose first terminal is electrically connected to a first power supply terminal and whose second terminal is electrically connected to a light-emitting element, for providing driving current to the light-emitting element; the driving module includes a driving transistor; a threshold compensation module, electrically connected between the control terminal and the first terminal of the driving module, for compensating the threshold voltage of the driving transistor; the threshold compensation module includes a first transistor; and a data writing module, electrically connected to the second terminal of the driving module, for writing data signals to the driving module; the driving transistor is a P-type transistor, and the first transistor is an N-type transistor. According to the embodiments of this application, the leakage current problem of the driving transistor can be improved, thereby improving the brightness flicker problem.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a pixel circuit, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display devices.

[0003] The pixel circuit is used to drive the light-emitting element, providing the driving current required for the display, and to control whether the light-emitting element enters the light-emitting stage. Leakage current in the driving transistor of the pixel circuit will cause changes in the driving current, resulting in flickering of the brightness of the light-emitting element. Summary of the Invention

[0004] This application provides a pixel circuit, a display panel, and a display device that can improve the leakage current problem of the driving transistor, thereby improving the brightness flicker problem.

[0005] In a first aspect, embodiments of this application provide a pixel circuit, comprising: a driving module, wherein a first terminal is electrically connected to a first power supply terminal and a second terminal is electrically connected to a light-emitting element, for providing a driving current to the light-emitting element, the driving module including a driving transistor; a threshold compensation module, electrically connected between a control terminal and the first terminal of the driving module, for compensating the threshold voltage of the driving transistor, the threshold compensation module including a first transistor; and a data writing module, electrically connected to the second terminal of the driving module, for writing data signals to the driving module; the driving transistor is a P-type transistor and the first transistor is an N-type transistor.

[0006] Secondly, embodiments of this application provide a display panel including the pixel circuit described in the first aspect embodiment.

[0007] Thirdly, embodiments of this application provide a display device, including the display device described in the second aspect embodiment.

[0008] In this embodiment, the driving transistor needs to generate a driving current. A type-type transistor has higher mobility, and selecting a type-type transistor for the driving transistor can provide relatively strong driving capability. A type-type transistor has lower leakage current. The first transistor is connected to the gate of the driving transistor. Selecting a type-type transistor for the first transistor can reduce the leakage current problem at the gate of the driving transistor, thereby improving the brightness flicker problem.

[0009] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0010] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0011] Figure 1 This illustration shows a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0012] Figure 2 This illustration shows another structural diagram of the pixel circuit provided in an embodiment of this application;

[0013] Figure 3 This illustration shows yet another structural schematic of the pixel circuit provided in an embodiment of this application;

[0014] Figure 4 This illustration shows yet another structural schematic of the pixel circuit provided in an embodiment of this application;

[0015] Figure 5 Show Figure 1 A timing diagram;

[0016] Figure 6 Show Figure 1 Another timing diagram;

[0017] Figure 7 Show Figure 1 Another timing diagram;

[0018] Figure 8 Show Figure 1 Another timing diagram;

[0019] Figure 9 Show Figure 1 Another timing diagram;

[0020] Figure 10 Show Figure 2 A timing diagram;

[0021] Figure 11 Show Figure 3 A timing diagram;

[0022] Figure 12 Show Figure 4 A timing diagram;

[0023] Figure 13 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application;

[0024] Figure 14 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0025] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0028] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0029] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "electrical connection" should be interpreted broadly. For example, it can refer to a direct connection or an indirect connection through an intermediate medium, or it can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0030] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0031] This application provides a pixel circuit, a display panel, and a display device. The various embodiments of this application will be described below with reference to the accompanying drawings.

[0032] Figures 1 to 4 Four circuit structures for pixel circuits provided in embodiments of this application are illustrated. For example... Figures 1 to 4 As shown, the pixel circuit 10 is electrically connected to the light-emitting element 20.

[0033] Specifically, the pixel circuit 10 includes a driving module 11, a threshold compensation module 12, and a data writing module 13. The driving module 11 has its first terminal electrically connected to a first power supply terminal PVDD, and its second terminal electrically connected to the light-emitting element 20. The driving module 11 provides driving current to the light-emitting element 20 and includes a driving transistor M0. The gate of the driving transistor M0 is the control terminal of the driving module 11, the first electrode of the driving transistor M0 is the first terminal of the driving module 11, and the second electrode of the driving transistor M0 is the second terminal of the driving module 11. For ease of explanation, this paper uses an example where the gate of the driving transistor M0 is electrically connected to the first node N1, the first electrode of the driving transistor M0 is electrically connected to the second node N2, and the second electrode of the driving transistor M0 is electrically connected to the third node N3.

[0034] A threshold compensation module 12 is electrically connected between the control terminal and the first terminal of the drive module 11. The threshold compensation module 12 is used to compensate the threshold voltage of the drive transistor M0, and includes a first transistor M1. A data writing module 13 is electrically connected to the second terminal of the drive module 11 and is used to write data signals to the drive module 11. For example, the data writing module 13 includes a second transistor M2. In this document, the gate of a transistor is used as the control terminal of its module, the first terminal of the transistor is used as the first terminal of its module, and the second terminal of the transistor is used as the second terminal of its module.

[0035] Among them, the driving transistor M0 is a P-type transistor, and the first transistor M1 is an N-type transistor.

[0036] The driving transistor M0 needs to generate a driving current. P-type transistors have higher mobility, so using a P-type transistor for driving transistor M0 can provide relatively strong driving capability. N-type transistors have lower leakage current. The first transistor M1 is connected to the gate of driving transistor M0. Using an N-type transistor for the first transistor M1 can reduce the leakage current problem at the gate of driving transistor M0, thereby improving the brightness flicker problem.

[0037] The first and second terminals of the driving transistor are its source and drain. If the potential difference between the source / drain and its gate remains large for an extended period, it can cause ion polarization within the driving transistor, resulting in an electric field inside the transistor and increasing its threshold voltage. This increased threshold voltage affects the magnitude of the driving current flowing into the light-emitting element, thus impacting display uniformity.

[0038] The pixel circuit of this application breaks with the conventional pixel circuit design. In a conventional design, when the driving transistor is a P-type transistor, the threshold compensation transistor is connected between the gate and the second terminal of the driving transistor, and the data writing transistor is connected to the first terminal of the driving transistor. In this connection method, the threshold compensation transistor can only perform threshold compensation, which limits the flexibility of adjusting the bias state of the driving transistor.

[0039] The pixel circuit provided in this application embodiment has a first transistor connected between the gate and first electrode of the driving transistor, and a data writing module connected to the second electrode of the driving transistor. By controlling the state of the first transistor, the potential of the gate and first electrode of the driving transistor can be adjusted through the signal transmitted by the first transistor. By controlling the state of the data writing module, data can be written or the potential of the second electrode of the driving transistor can be adjusted through the signal transmitted by the data writing module. For example, when the gate of the driving transistor is reset using a reset signal, the first transistor can be turned on. In this way, the reset signal can also be transmitted to the first electrode of the driving transistor. That is, during the reset phase, when the first transistor is turned on, the gate and first electrode of the driving transistor can be reset simultaneously, thereby adjusting the potential difference between the gate and the first electrode of the driving transistor to adjust the bias state of the driving transistor. In this application embodiment, it is possible for the first transistor to act not only in the threshold compensation phase but also in the reset phase, enabling more flexible adjustment of the bias state of the driving transistor.

[0040] In some embodiments, such as Figures 1 to 4As shown, the pixel circuit also includes a first reset module 14, which is electrically connected to the control terminal or the first terminal of the driving module 11. The first reset module 14 is used to write a first reset signal Vref1 to the control terminal and / or the first terminal of the driving module 11.

[0041] For example, the control terminal of the first reset module 14 is connected to the first scan signal S1, and the first reset module 14 is turned on or off under the control of the first scan signal S1.

[0042] The control terminal of the threshold compensation module 12 is connected to the second scanning signal S2. Under the control of the second scanning signal S2, the threshold compensation module 12 is turned on or off.

[0043] Understandably, when the first reset module 14 is electrically connected to the first terminal of the drive module 11, in order to write the first reset signal Vref1 to the control terminal of the drive module 11, both the first reset module 14 and the threshold compensation module 12 can be turned on, so that the first reset signal Vref1 is written to the control terminal of the drive module 11 through the first reset module 14 and the threshold compensation module 12 in sequence.

[0044] The control terminal of the drive module 11 needs to write data signals and generate drive current according to the written data signals. The control terminal of the drive module 11 is reset by the first reset signal Vref1 to ensure the effective writing of data signals.

[0045] For example, the first reset module 14 includes a third transistor M3, and the type of the third transistor M3 can be set according to the connection position of the first reset module 14.

[0046] In some embodiments, such as Figure 1 and Figure 4 As shown, the first reset module 14 is electrically connected to the control terminal of the drive module 11, and the first reset module 14 includes an N-type transistor. That is, if the gate of the third transistor M3 is connected to the gate of the drive transistor M0, the third transistor M3 is an N-type transistor. Since the N-type transistor has lower leakage current, this can improve the leakage current problem of the gate of the drive transistor, thereby improving the flicker problem.

[0047] Or, such as Figure 2 or Figure 3 As shown, the first reset module 14 is electrically connected to the first terminal of the drive module 11, and the first reset module 14 includes a P-type transistor or an N-type transistor. Figure 2 As shown, if the third transistor M3 is connected to the first terminal of the driving transistor M0, then the third transistor M3 is a P-type transistor. Alternatively, as... Figure 3 As shown, if the third transistor M3 is connected to the first terminal of the driving transistor M0, then the third transistor M3 is an N-type transistor. Figure 2 and Figure 3 In the structure shown, the gates of the third transistor M3 and the driving transistor M0 are not directly connected (the gates of the third transistor M3 and the driving transistor M0 are connected by the first transistor M1). Therefore, the third transistor M3 does not significantly affect the gate leakage current of the driving transistor M0, and the type of the third transistor M3 can be chosen arbitrarily. Furthermore, Figure 2 and Figure 3 In the circuit structure shown, the gate of the driving transistor M0 is directly connected to the first transistor M1. In other words, the leakage path of the gate of the driving transistor M0 is only the first transistor M1. From this perspective, the leakage path of the gate of the driving transistor M0 can be reduced, thereby improving the gate leakage problem of the driving transistor M0.

[0048] In some embodiments, combined with Figures 1 to 4 The circuit structure shown and Figures 5 to 12 As shown in the timing diagram, the conduction period of the first reset module 14 and the conduction period of the threshold compensation module 12 at least partially overlap.

[0049] For ease of explanation, the period during which both the first reset module 14 and the threshold compensation module 12 are turned on is designated as period a. During period a, both the first scan signal S1 and the second scan signal S2 are at the on level. It can be understood that if the transistor controlled by the scan signal is an N-type transistor, the on level is high; if the transistor controlled by the scan signal is a P-type transistor, the on level is low. Figures 5 to 6 as well as Figure 11 and Figure 12 In the timing sequence shown, during time period a, the conduction levels of both the first scan signal S1 and the second scan signal S2 are high. Figure 10 In the timing sequence shown, during time period a, the conduction level of the first scan signal S1 is low, and the conduction level of the second scan signal S2 is high.

[0050] During time period a, both the first reset module 14 and the threshold compensation module 12 are turned on. The first reset signal Vref1 can be written to the gate (first node N1) and the first electrode (second node N2) of the driving transistor M0. In this way, the gate (first node N1) and the first electrode (second node N2) of the driving transistor M0 can be reset at the same time, thereby adjusting the potential difference between the gate and the first electrode of the driving transistor to adjust the bias state of the driving transistor.

[0051] In some embodiments, please refer to the reference Figure 1 and Figure 5 The first reset module 14 is turned on during the reset phase. Figure 5In the timing sequence shown, the first scan signal S1 is at a high level during both time period t12 and time period a. Therefore, Figure 5 In the timing diagram shown, the reset phase includes time period t12 and time period a.

[0052] The conduction period of the threshold compensation module 12 includes a first time period b1 and a second time period b2. The first time period b1 does not overlap with the reset phase (time period t12 and time period a), while the second time period b2 partially overlaps with the reset phase. The portion of the reset phase that does not overlap with the second time period b2 is located between the first time period b1 and the second time period b2. Figure 5 In the timing diagram shown, time period a is the overlapping period between the second time period b2 and the reset phase. Time period t12 does not overlap with the second time period b2, and time period t12 is located between the first time period b1 and the second time period b2. It can be understood that the reset phase (time period t12 and time period a) is after the first time period b1.

[0053] When the threshold compensation module 12 is turned on, the gate of the driving transistor M0 and its first electrode are connected. It is understood that the data signal Data can only be written to the gate of the driving transistor M0 when the threshold compensation module 12 is turned on. Additionally, if the bias adjustment signal DVH needs to be written to the gate of the driving transistor, the threshold compensation module 12 also needs to be turned on. In this embodiment, the on-time of the threshold compensation module 12 includes a first time period b1 and a second time period b2, thus enabling not only data writing but also creating conditions for writing the bias adjustment signal.

[0054] As an example, such as Figures 1 to 4 As shown, the pixel circuit includes a bias adjustment module 15, which is connected to the second terminal (third node N3) or the first terminal (second node N2) of the driving module 11. The bias adjustment module 15 is used to write a bias adjustment signal to the driving module. The bias adjustment signal can be used to adjust the bias state of the driving transistor, adjust the voltage of the first terminal N1 and the second terminal N2 of the driving transistor M0, reduce the potential difference between the gate potential and the drain potential of the driving transistor M0, thereby balancing the threshold voltage offset phenomenon of the driving transistor M0, reducing the degree of threshold voltage offset of the driving transistor M0, and improving the display uniformity of the display panel.

[0055] In some embodiments, the operation of the pixel circuit includes a bias adjustment stage, during which the bias adjustment module is turned on. The bias adjustment stage includes at least a first bias adjustment stage, which is located after the data writing stage of the pixel circuit.

[0056] Different grayscale levels correspond to different data signals for the driving transistors, resulting in different bias degrees for the different transistors. In this embodiment, the first bias adjustment stage occurs after the data writing stage. Writing the bias adjustment signal to the driving transistors can correct their characteristics. By writing a uniform bias signal after the data signal of the current image is written, the characteristics of the driving transistors in each pixel circuit are ensured to be more similar before the data signal is written, thus improving the flicker problem.

[0057] In some embodiments, the bias adjustment stage further includes a second bias adjustment stage, which is located before the data writing stage of the pixel circuit.

[0058] The second bias adjustment stage occurs before the data writing stage. The bias adjustment signal is written to the driving transistor in advance to correct the characteristics of the driving transistor. Before the data signal of the current screen is written, the characteristics of the driving transistor in each pixel circuit are uniformly written with a bias signal, which ensures that the characteristics of the driving transistor in each pixel circuit are more similar before the data signal is written. This eliminates the bias voltage effect of the previous screen on the driving transistor, improves the ghosting problem when switching between display screens, and improves the display effect.

[0059] It should be noted that the operation of the pixel circuit may include either the first bias adjustment stage or the second bias adjustment stage, or the operation of the pixel circuit may include both the first bias adjustment stage and the second bias adjustment stage.

[0060] In some embodiments, when the operation of the pixel circuit includes both a first bias adjustment stage and a second bias adjustment stage, the durations of the first bias adjustment stage and the second bias adjustment stage are different.

[0061] However, the duration of a frame is fixed. A frame includes a non-light-emitting phase (during which the light-emitting control signal EM is at a cutoff level, such as a high level) and a light-emitting phase (during which the light-emitting control signal EM is at a conduction level, such as a low level). The non-light-emitting phase includes not only the bias adjustment phase but also the data writing phase, the reset phase, etc. Therefore, it is quite important to balance the various phases within a certain time frame.

[0062] The longer the bias adjustment phase, the more fully the bias adjustment signal can be written to the driving transistor, thus enabling a more thorough and effective adjustment of the driving transistor's bias state. However, since the length of a frame is fixed, a longer bias adjustment phase means less time can be allocated to other phases, which is detrimental to ensuring the effectiveness of each phase.

[0063] In this embodiment, the durations of the first bias adjustment stage and the second bias adjustment stage are different. This allows for flexible matching of the adjustment needs of different bias adjustment stages. Furthermore, the different durations of the first and second bias adjustment stages create conditions for keeping the total duration of the bias adjustment stages constant. In other words, it can take into account the adjustment needs of different bias adjustment stages without excessively occupying the duration of other stages, thus also helping to ensure the effectiveness of other stages.

[0064] For example, the duration of the first bias adjustment stage and the second bias adjustment stage can be set according to the actual bias state adjustment requirements of the product. For instance, the duration of the first bias adjustment stage may be longer than the duration of the second bias adjustment stage, or the duration of the first bias adjustment stage may be shorter than the duration of the second bias adjustment stage.

[0065] Of course, depending on actual needs, the duration of the first bias adjustment phase can be set to be equal to the duration of the second bias adjustment phase.

[0066] In some embodiments, when the operation of the pixel circuit includes both a first bias adjustment stage and a second bias adjustment stage, the voltage of the bias adjustment signal is different in the first bias adjustment stage and the second bias adjustment stage.

[0067] In this application, the driving transistor is a P-type transistor, and the bias adjustment signal DVH is a high-level signal.

[0068] The higher the voltage of the bias adjustment signal, the easier it is to write the bias adjustment signal into the driving transistor, thus enabling more thorough and effective adjustment of the bias state of the driving transistor. However, the higher the voltage of the bias adjustment signal, the greater the power consumption required. Therefore, it is important to save power while ensuring the effectiveness of different bias adjustment stages.

[0069] In this embodiment, the voltage of the bias adjustment signal is different in the first bias adjustment stage and the second bias adjustment stage. This allows for flexible matching of the adjustment requirements of different bias adjustment stages. Furthermore, the voltage of the bias adjustment signal is large in the first bias adjustment stage and small in the second bias adjustment stage. This means that the larger bias adjustment voltage can fully and effectively adjust the bias state of the driving transistor, while the smaller bias adjustment voltage can save power consumption. Therefore, it is important to achieve both effectiveness in different bias adjustment stages and power saving.

[0070] For example, the voltage magnitudes of the bias adjustment signal in the first and second bias adjustment stages can be set according to the actual product's bias state adjustment requirements. For instance, the voltage of the bias adjustment signal in the first bias adjustment stage may be greater than its voltage in the second bias adjustment stage, or the voltage of the bias adjustment signal in the first bias adjustment stage may be less than its voltage in the second bias adjustment stage.

[0071] Of course, depending on actual needs, the voltage of the bias adjustment signal in the first bias adjustment stage can be set to be equal to its voltage in the second bias adjustment stage.

[0072] The following provides an illustrative description of the operation of the pixel circuit, including both the first bias adjustment stage and the second bias adjustment stage.

[0073] For example, the data writing module 13 is turned on or off under the control of the third scan signal S3, and the bias adjustment module 15 is turned on or off under the control of the fourth scan signal S4. The following explanation assumes that the first scan signal S1 and the second scan signal S2 are at a high level, and the third scan signal S3 and the fourth scan signal S4 are at a low level.

[0074] As an example, please refer to the reference. Figure 1 and Figure 5 The working process of a pixel circuit includes:

[0075] During time period t11, the bias adjustment module 15 and the threshold compensation module 12 are turned on, and the bias adjustment signal DVH is written into the second terminal, the first terminal and the gate of the driving transistor M0 to realize the adjustment of the first bias state of the driving transistor (abbreviated as OBS).

[0076] During time period t12, the first reset module 14 is turned on, and the first reset signal Vref1 is written into the gate of the driving transistor M0 to reset the gate of the driving transistor M0.

[0077] During time period a, the first reset module 14 and the threshold compensation module 12 are turned on, and the first reset signal Vref1 is written into the gate and the first electrode of the driving transistor M0 to achieve the reset of the gate and the first electrode of the driving transistor M0.

[0078] During time period t13, the data writing module 13 and the threshold compensation module 12 are turned on, the data signal Data is written to the gate of the driving transistor M0, and the threshold compensation module 12 compensates the threshold voltage of the driving transistor to realize the writing of the data signal.

[0079] During time period t14, the bias adjustment module 15 is turned on, and the bias adjustment signal DVH is written into the second terminal of the driving transistor M0 to realize the adjustment of the second bias state of the driving transistor (abbreviated as OBS).

[0080] The first time period b1 covers time period t11, and the second time period b2 covers time period t13.

[0081] Understandably, the data writing phase includes time period t13, while time periods t11 and t14 are two bias adjustment phases. Time period t14 is the first bias adjustment phase following the data writing phase, and time period t11 is the second bias adjustment phase preceding the data writing phase. Furthermore, time period t11 overlaps with the conduction period of the threshold compensation module, while time period t14 does not overlap with the conduction period of the threshold compensation module. In other words, the first bias adjustment phase does not overlap with the conduction period of the threshold compensation module, but the second bias adjustment phase overlaps with the conduction period of the threshold compensation module.

[0082] As another example, please refer to the reference. Figure 1 and Figure 6 The working process of a pixel circuit includes:

[0083] During time period t21, the bias adjustment module 15 and the threshold compensation module 12 are turned on, and the bias adjustment signal DVH is written into the second terminal, the first terminal and the gate of the driving transistor M0 to realize the adjustment of the first bias state of the driving transistor.

[0084] During time period a, the first reset module 14 and the threshold compensation module 12 are turned on, and the first reset signal Vref1 is written into the gate and the first electrode of the driving transistor M0 to achieve the reset of the gate and the first electrode of the driving transistor M0.

[0085] During time period t23, the data writing module 13 and the threshold compensation module 12 are turned on, the data signal Data is written to the gate of the driving transistor M0, and the threshold compensation module 12 compensates the threshold voltage of the driving transistor to realize the writing of the data signal.

[0086] During time period t24, the bias adjustment module 15 is turned on, and the bias adjustment signal DVH is written to the second terminal of the driving transistor M0 to adjust the second bias state of the driving transistor.

[0087] Understandably, the data writing phase includes time period t23, while time periods t21 and t24 are two bias adjustment phases. Time period t24 is the first bias adjustment phase following the data writing phase, and time period t21 is the second bias adjustment phase preceding the data writing phase. Furthermore, time period t21 overlaps with the conduction period of the threshold compensation module, while time period t24 does not overlap with the conduction period of the threshold compensation module. In other words, the first bias adjustment phase does not overlap with the conduction period of the threshold compensation module, but the second bias adjustment phase overlaps with the conduction period of the threshold compensation module.

[0088] Comprehensive reference Figure 5 and Figure 6 Understandably, the bias adjustment phase following the data writing phase is called the first bias adjustment phase (i.e., Figure 5 The time period t14 and Figure 6 The bias adjustment phase before the data writing phase (time period t24) is called the second bias adjustment phase (i.e., Figure 5 The time period t11 and Figure 6 During time period t21, the first bias adjustment phase does not overlap with the conduction period of the threshold compensation module, while the second bias adjustment phase overlaps with the conduction period of the threshold compensation module. Understandably, when the bias adjustment phase overlaps with the conduction period of the threshold compensation module, the bias adjustment signal can be written to the second, first, and gate terminals of the driving transistor. When the bias adjustment phase does not overlap with the conduction period of the threshold compensation module, the bias adjustment signal can be written to the second terminal of the driving transistor. Since the state of the threshold compensation module differs in the two bias adjustment phases, the location where the bias adjustment signal is written to the driving transistor differs, thus allowing for flexible adjustment of the bias state.

[0089] As yet another example, please refer to the reference. Figure 1 and Figure 9 The working process of a pixel circuit includes:

[0090] During time period t51, the bias adjustment module 15 is turned on, and the bias adjustment signal DVH is written into the second terminal of the driving transistor M0 to realize the adjustment of the first bias state of the driving transistor.

[0091] During time period t52, the first reset module 14 is turned on, and the first reset signal Vref1 is written into the gate of the driving transistor M0 to reset the gate of the driving transistor M0.

[0092] During time period a, the first reset module 14 and the threshold compensation module 12 are turned on, and the first reset signal Vref1 is written into the gate and the first electrode of the driving transistor M0 to achieve the reset of the gate and the first electrode of the driving transistor M0.

[0093] During time period t53, the data writing module 13 and the threshold compensation module 12 are turned on, the data signal Data is written to the gate of the driving transistor M0, and the threshold compensation module 12 compensates the threshold voltage of the driving transistor to realize the writing of the data signal.

[0094] During time period t54, the bias adjustment module 15 is turned on, and the bias adjustment signal DVH is written into the second terminal of the driving transistor M0 to adjust the second bias state of the driving transistor.

[0095] Understandably, the data writing phase includes time period t53, while time periods t51 and t54 are two bias adjustment phases. Time period t54 is the first bias adjustment phase following the data writing phase, and time period t51 is the second bias adjustment phase preceding the data writing phase. Here, time periods t51 and t54 do not overlap with the conduction time of the threshold compensation module.

[0096] Additionally, please refer to the following: Figure 1 and Figure 5 The high-level period of the first scan signal S1 is the reset phase of the first reset module 14, and the high-level period of the second scan signal S2 is the conduction period of the threshold compensation module 12. The reset phase includes time period t52 and time period a, and the conduction period of the threshold compensation module 12 includes time period b3. Here, the start time of the reset phase is earlier than the start time of the conduction period of the threshold compensation module, and the end time of the reset phase is earlier than the end time of the conduction period of the threshold compensation module.

[0097] When a data signal is written to the gate of the driving transistor, the threshold compensation module needs to be turned on and the first reset module needs to be turned off. In this embodiment, the start time of the reset phase is earlier than the start time of the conduction period of the threshold compensation module, and the end time of the reset phase is earlier than the end time of the conduction period of the threshold compensation module. This ensures that the reset of the driving transistor is completed before the data signal is written, and that there is time to complete the writing of the data signal after the reset.

[0098] The above provides an example of including a bias adjustment stage before and after the data writing stage. As described above, a bias adjustment stage may also be provided only before the data writing stage, or only after the data writing stage.

[0099] For example, please refer to the reference. Figure 1 as well as Figure 7 or Figure 8 or in conjunction with references Figure 2 and Figure 10 Or, in conjunction with references Figure 3 and Figure 11 In these examples, there is only a bias adjustment phase after the data writing phase.

[0100] As an example, please refer to the reference. Figure 1 and Figure 7 The working process of a pixel circuit includes:

[0101] During time period t32, the first reset module 14 is turned on, and the first reset signal Vref1 is written into the gate of the driving transistor M0 to reset the gate of the driving transistor M0.

[0102] During time period a, the first reset module 14 and the threshold compensation module 12 are turned on, and the first reset signal Vref1 is written into the gate and the first electrode of the driving transistor M0 to achieve the reset of the gate and the first electrode of the driving transistor M0.

[0103] During time period t33, the data writing module 13 and the threshold compensation module 12 are turned on, the data signal Data is written to the gate of the driving transistor M0, and the threshold compensation module 12 compensates the threshold voltage of the driving transistor to realize the writing of the data signal.

[0104] During time period t34, the bias adjustment module 15 is turned on, and the bias adjustment signal DVH is written into the second terminal of the driving transistor M0 to adjust the bias state of the driving transistor.

[0105] Additionally, please refer to the following: Figure 1 and Figure 7 The high-level period of the first scan signal S1 is the reset phase of the first reset module 14, and the high-level period of the second scan signal S2 is the conduction period of the threshold compensation module 12. The reset phase includes time period t32 and time period a, and the conduction period of the threshold compensation module 12 includes time period b4. Here, the start time of the reset phase is earlier than the start time of the conduction period of the threshold compensation module, and the end time of the reset phase is earlier than the end time of the conduction period of the threshold compensation module.

[0106] As another example, please refer to the reference. Figure 1 and Figure 8 The working process of a pixel circuit includes:

[0107] During time period a, the first reset module 14 and the threshold compensation module 12 are turned on, and the first reset signal Vref1 is written into the gate and the first electrode of the driving transistor M0 to achieve the reset of the gate and the first electrode of the driving transistor M0.

[0108] During time period t43, the data writing module 13 and the threshold compensation module 12 are turned on, the data signal Data is written to the gate of the driving transistor M0, and the threshold compensation module 12 compensates the threshold voltage of the driving transistor to realize the writing of the data signal.

[0109] During time period t44, the bias adjustment module 15 is turned on, and the bias adjustment signal DVH is written to the second terminal of the driving transistor M0 to adjust the bias state of the driving transistor.

[0110] Here, the on-level (high level) of the second scan signal S2 overrides the on-level (high level) of the first scan signal S1.

[0111] As yet another example, please refer to the reference. Figure 2 and Figure 10 It should be noted that, Figure 2 and Figure 10 The diagram illustrates the operation of the pixel circuit, with the first scan signal S1 at a low level. The operation of the pixel circuit includes:

[0112] During time period a, the first reset module 14 and the threshold compensation module 12 are turned on, and the first reset signal Vref1 is written into the gate and the first electrode of the driving transistor M0 to achieve the reset of the gate and the first electrode of the driving transistor M0.

[0113] During time period t63, the data writing module 13 and the threshold compensation module 12 are turned on, the data signal Data is written to the gate of the driving transistor M0, and the threshold compensation module 12 compensates the threshold voltage of the driving transistor to realize the writing of the data signal.

[0114] During time period t64, the bias adjustment module 15 is turned on, and the bias adjustment signal DVH is written to the second terminal of the driving transistor M0 to adjust the bias state of the driving transistor.

[0115] Here, the on-level (high level) of the second scan signal S2 overrides the on-level (low level) of the first scan signal S1.

[0116] As yet another example, please refer to the reference. Figure 3 and Figure 11 It should be noted that the working process of the pixel circuit includes:

[0117] During time period a, the first reset module 14 and the threshold compensation module 12 are turned on, and the first reset signal Vref1 is written into the gate and the first electrode of the driving transistor M0 to achieve the reset of the gate and the first electrode of the driving transistor M0.

[0118] During time period t73, the data writing module 13 and the threshold compensation module 12 are turned on, the data signal Data is written to the gate of the driving transistor M0, and the threshold compensation module 12 compensates the threshold voltage of the driving transistor to realize the writing of the data signal.

[0119] During time period t74, the bias adjustment module 15 is turned on, and the bias adjustment signal DVH is written to the second terminal of the driving transistor M0 to adjust the bias state of the driving transistor.

[0120] Here, the on-level (high level) of the second scan signal S2 overrides the on-level (high level) of the first scan signal S1.

[0121] In some embodiments, the duration of the conduction period of the threshold compensation module is longer than the duration of the reset phase, and the conduction period of the threshold compensation module covers the reset phase.

[0122] Please refer to the reference. Figure 1 and Figure 6The second scan signal S2 is on during time period b, which is the on-time period of the threshold compensation module 12; the first scan signal S1 is on during time period a, which is the on-time period of the first reset module 14, i.e., time period a is the reset phase. The duration of time period b is longer than the duration of time period a, and time period b covers time period a. Here, "covers" means that the start time of time period a is not earlier than the start time of time period b, and the end time of time period a is not later than the end time of time period b. In other examples, the meaning of one time period covering another time period is the same, and will not be explained for each one.

[0123] During time period a, both the first reset module and the threshold compensation module are turned on, and the first reset signal can be written to the gate and its first electrode of the driving transistor, which also simultaneously resets the gate and its first electrode of the driving transistor. As described above, if the bias adjustment signal DVH needs to be written to the gate of the driving transistor, the threshold compensation module 12 also needs to be turned on. In this embodiment, the conduction period of the threshold compensation module 12 is relatively long, which not only allows for the reset of the driving transistor during its conduction period but also creates conditions for the writing of the bias adjustment signal.

[0124] In some embodiments, the conduction period of the threshold compensation module and the conduction period of the first reset module at least partially overlap, and the duration of the overlap is less than the duration of the bias adjustment phase.

[0125] Please refer to the reference. Figure 1 and Figure 5 The overlapping portion of the conduction period of the threshold compensation module 12 and the conduction period of the first reset module 14 is period a. The bias adjustment stage includes a first period b1 and a second period b2. The duration of the bias adjustment stage is the sum of the durations of the first period b1 and the second period b2. The duration of period a is less than the duration of the bias adjustment stage, and the duration of period a is less than the duration of the second period b2.

[0126] Alternatively, please refer to the following: Figure 1 and Figure 6 The overlapping portion of the conduction period of the threshold compensation module 12 and the conduction period of the first reset module 14 is time period a. The bias adjustment stage includes time period b. The duration of the bias adjustment stage is the duration of time period b. The duration of time period a is less than the duration of time period b.

[0127] Alternatively, please refer to the following: Figure 1 and Figure 9 The overlapping portion of the conduction period of the threshold compensation module 12 and the conduction period of the first reset module 14 is time period a. The bias adjustment stage includes time period t51 and time period t54. The duration of the bias adjustment stage is the sum of the durations of time period t51 and time period t54. The duration of time period a is less than the duration of the bias adjustment stage.

[0128] Alternatively, please refer to the following: Figure 3 and Figure 11 The overlapping portion of the conduction period of the threshold compensation module 12 and the conduction period of the first reset module 14 is time period a. The bias adjustment stage includes time period t74, and the duration of the bias adjustment stage is the duration of time period t74. The duration of time period a is less than the duration of time period t74.

[0129] During the bias adjustment stage, the bias adjustment signal is written to the driving transistor, reducing the potential difference between the source and / or drain and the gate of the driving transistor, weakening the degree of ion polarization inside the driving transistor, thereby reducing the threshold voltage offset of the driving transistor, improving the threshold voltage offset phenomenon and hysteresis effect of the driving transistor, thereby improving the brightness difference of each frame at low frequencies and improving display uniformity.

[0130] During time period a, the gate of the driving transistor is reset simultaneously with the first terminal of the driving transistor. This reduces the recovery from the hysteresis of the driving transistor. In other words, the longer time period a is, the less conducive it is to recovering the hysteresis problem of the driving transistor. In this embodiment, the duration of time period a is set to be shorter than the duration of the bias adjustment phase, allowing for a relatively long bias adjustment of the driving transistor, which can better eliminate the performance problems caused by the hysteresis of the driving transistor.

[0131] In some embodiments, please refer to the reference Figure 4 and Figure 12 The data writing module 13 is multiplexed as the bias adjustment module 15. The pixel circuit includes a write frame f1 and a hold frame f2 in one frame refresh cycle. The data writing module 13 is used to write the data signal Data to the drive module 11 in the write frame f1 and to write the bias adjustment signal DVH to the drive module 11 in the hold frame f2.

[0132] In this embodiment of the application, by multiplexing the data writing module and the bias adjustment module, both the writing of data signals and the writing of bias adjustment signals can be realized while simplifying the circuit structure.

[0133] The data writing module 13 is turned on or off under the control of the third scan signal S3. For example, the on level of the third scan signal S3 is low. The operation of the pixel circuit includes a write frame f1 and a hold frame f2. The write frame f1 includes time period t82, time period a, and time period t83, and the hold frame f2 includes time period t84.

[0134] During time period t82, the first reset module 14 is turned on, and the first reset signal Vref1 is written into the gate of the driving transistor M0 to reset the gate of the driving transistor M0.

[0135] During time period a, the first reset module 14 and the threshold compensation module 12 are turned on, and the first reset signal Vref1 is written into the gate and the first electrode of the driving transistor M0 to achieve the reset of the gate and the first electrode of the driving transistor M0.

[0136] During time period t83, the data writing module 13 and the threshold compensation module 12 are turned on, the data signal Data is written to the gate of the driving transistor M0, and the threshold compensation module 12 compensates the threshold voltage of the driving transistor to realize the writing of the data signal.

[0137] During time period t84, the data writing module 13 is turned on, and the bias adjustment signal DVH is written to the second terminal of the driving transistor M0 to adjust the bias state of the driving transistor.

[0138] For example, such as Figures 1 to 4 As shown, the pixel circuit also includes a transistor M4, which is used to write a second reset signal Vref2 to the first electrode of the light-emitting element 20 to reset the light-emitting element 20. The transistor M4 is turned on or off under the control of the fifth scan signal S5.

[0139] When the bias adjustment module 15 and the data writing module 13 are not reused, the bias adjustment module 15 is controlled by the fourth scan signal S4, and the timing of the fifth scan signal S5 and the fourth scan signal S4 can be the same.

[0140] When the bias adjustment module 15 and the data writing module 13 are multiplexed, the data writing module 13 is controlled by the third scan signal S3, and the timing of the fifth scan signal S5 and the third scan signal S3 can be the same.

[0141] For example, such as Figures 1 to 4 As shown, the pixel circuit also includes transistors M5 and M6, which are used to control whether the light-emitting element emits light. Transistors M5 and M6 are controlled by the light-emitting control signal EM. When the light-emitting control signal EM is at a cutoff level (e.g., high level), the light-emitting element does not emit light; when the light-emitting control signal EM is at a conduction level (e.g., low level), the light-emitting element can emit light.

[0142] It should be noted that for N-type transistors, the on-level is high and the off-level is low. That is, when the gate potential of an N-type transistor is high, its first and second terminals are connected; when the gate potential is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the gate potential of a P-type transistor is low, its first and second terminals are connected; when the gate potential is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa; no distinction is made here. Additionally, the on-level and off-level in this embodiment are general terms; the on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0143] This application also provides a display panel. Figure 13 This diagram illustrates the structure of a display panel according to one embodiment of the present application. Figure 13 As shown, the display panel 100 provided in this application embodiment may include the pixel driving circuit described in any of the above embodiments. Figure 13 The display panel shown can be an organic light-emitting diode (OLED) display panel.

[0144] Those skilled in the art should understand that, in other implementations of this application, the display panel may also be a micro light-emitting diode (Micro LED) display panel, etc.

[0145] The display panel provided in this application embodiment has the beneficial effects of the pixel driving circuit provided in this application embodiment. For details, please refer to the specific description of the pixel driving circuit in the above embodiments. This embodiment will not repeat the description here.

[0146] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 14 , Figure 14 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 14 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 14This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0147] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel circuit, characterized in that, include: A driving module, having a first terminal electrically connected to a first power supply terminal and a second terminal electrically connected to a light-emitting element, is used to provide driving current to the light-emitting element. The driving module includes a driving transistor. A threshold compensation module is electrically connected between the control terminal and the first terminal of the drive module, and is used to compensate the threshold voltage of the drive transistor. The threshold compensation module includes a first transistor. The data writing module is electrically connected to the second end of the driving module and is used to write data signals to the driving module. The driving transistor is a P-type transistor, and the first transistor is an N-type transistor; The pixel circuit further includes a first reset module, which is electrically connected to the control terminal or the first terminal of the driving module and is used to write a first reset signal to the control terminal and / or the first terminal of the driving module. The first reset module is turned on during the reset phase. The conduction period of the threshold compensation module includes a first period and a second period. The first period does not overlap with the reset phase, and the second period partially overlaps with the reset phase. The portion of the reset phase that does not overlap with the second period is located between the first period and the second period.

2. The pixel circuit according to claim 1, characterized in that, The first reset module is electrically connected to the control terminal of the drive module, and the first reset module includes an N-type transistor; Alternatively, the first reset module is electrically connected to the first terminal of the drive module, and the first reset module includes a P-type transistor or an N-type transistor.

3. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes a bias adjustment module, which is electrically connected to the second or first terminal of the driving module and is used to write a bias adjustment signal to the driving module.

4. The pixel circuit according to claim 3, characterized in that, The operation of the pixel circuit includes a bias adjustment stage, during which the bias adjustment module is turned on. The bias adjustment stage includes at least a first bias adjustment stage, which is located after the data writing stage of the pixel circuit.

5. The pixel circuit according to claim 4, characterized in that, The bias adjustment stage further includes a second bias adjustment stage, which is located before the data writing stage of the pixel circuit.

6. The pixel circuit according to claim 5, characterized in that, The first bias adjustment phase and the conduction period of the threshold compensation module do not overlap, while the second bias adjustment phase and the conduction period of the threshold compensation module overlap.

7. The pixel circuit according to claim 5, characterized in that, The durations of the first bias adjustment phase and the second bias adjustment phase are different.

8. The pixel circuit according to claim 5, characterized in that, The voltage of the bias adjustment signal is different in the first bias adjustment stage and the second bias adjustment stage.

9. The pixel circuit according to claim 4, characterized in that, The pixel circuit further includes a first reset module, wherein the conduction period of the threshold compensation module at least partially overlaps with the conduction period of the first reset module, and the duration of the overlap is less than the duration of the bias adjustment phase.

10. The pixel circuit according to claim 3, characterized in that, The data writing module is multiplexed as the bias adjustment module. The pixel circuit includes a write frame and a hold frame in one frame refresh cycle. The data writing module is used to write a data signal to the driving module in the write frame and to write a bias adjustment signal to the driving module in the hold frame.

11. A display panel, characterized in that, Includes the pixel circuit according to any one of claims 1 to 10.

12. A display device, characterized in that, Includes the display panel according to claim 11.

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