A semiconductor device and a manufacturing method thereof
By employing a bonding layer structure with alternating distributions of thermally conductive and adhesive materials in semiconductor devices, the problem of heat dissipation difficulties in semiconductor chips has been solved, achieving efficient heat transfer and structural stability, and improving the chip's heat dissipation capacity and lifespan.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2024-08-05
- Publication Date
- 2026-05-22
Smart Images
Figure CN118983283B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] Advances in semiconductor technology have increased the processing speed and integration of electronic chips, but have also highlighted the problem of heat dissipation. Since the 1990s, the clock speed of computer chips has increased, leading to a corresponding increase in heat generation power and density. Although mitigation measures exist, the heat generation continues to grow rapidly, with technologies such as image processing and AI causing high-performance chips to generate significant heat and exhibit complex hotspot distribution.
[0003] Chip heat dissipation methods include active and passive cooling. Active cooling is driven by a power source (such as electricity) and mainly includes methods such as air cooling, water cooling, and heat pipe cooling. Passive cooling refers to methods that do not require an external power source and rely solely on natural convection or heat conduction, mainly including natural air cooling and heat sink cooling. Heat generated by a chip can typically be dissipated through two pathways: first, through the solder balls or leads to the PCB circuit board, but due to the limited contact area between the solder balls or leads and the chip, their thermal conductivity is relatively limited; second, heat is transferred upwards to the package casing and then carried away by an external active heat sink. Currently, research on improving the heat dissipation capacity of chip packages mainly focuses on optimizing the heat dissipation path and enhancing heat transfer capabilities. The former aims to optimize the package structure to enable more efficient heat conduction; the latter explores how to enhance the thermal conductivity of thermal interface materials. However, due to the low thermal conductivity of thermal interface materials such as thermal grease and adhesives, the optimization of the package heat dissipation path is somewhat limited, and the chip heat dissipation problem remains severe.
[0004] Traditional chip substrate materials, such as silicon and silicon-on-insulator (SOI), have relatively low thermal conductivity. For example, the thermal conductivity of single-crystal Si is 150 W / mK, and that of SiO2 is only 7.6 W / mK. This makes it difficult for heat inside the chip to be effectively transferred to the heat sink on the package surface, causing the internal temperature to rise and posing a serious threat to the chip's performance, stability, and lifespan. Summary of the Invention
[0005] The purpose of this application is to provide a semiconductor device and a method for manufacturing the same, which improves the heat dissipation capability of the semiconductor device.
[0006] To achieve the above objectives, in a first aspect, this application provides a semiconductor device comprising: a semiconductor structure, a first bonding layer, a second substrate, and a second bonding layer. The semiconductor structure includes a first substrate and a chip disposed on the first substrate. The first bonding layer is disposed on the side of the first substrate opposite to the chip. The first bonding layer includes a first thermally conductive material portion and a first adhesive material portion alternately distributed along a direction parallel to the surface of the first substrate. The thermal conductivity of the second substrate is greater than that of the first substrate. The second substrate has a bonding surface. The second bonding layer is disposed on the bonding surface of the second substrate, and the second bonding layer includes a second thermally conductive material portion and a second adhesive material portion alternately distributed along a direction parallel to the bonding surface. The second thermally conductive material portion of the second bonding layer corresponds one-to-one with the first thermally conductive material portion of the first bonding layer, and the second adhesive material portion of the second bonding layer corresponds one-to-one with the first adhesive material portion of the first bonding layer. The second substrate and the semiconductor structure are bonded together by the second bonding layer and the first bonding layer, respectively.
[0007] In the above technical solution, the second substrate and the semiconductor structure are bonded together by the second bonding layer and the first bonding layer, respectively. The thermal conductivity of the second substrate is greater than that of the first substrate included in the semiconductor structure. Therefore, the heat generated by the chip in operation can be dissipated to the external environment through the second substrate, which has better thermal conductivity, after passing through the first substrate. This achieves rapid heat dissipation and prevents the chip's performance and efficiency from being affected by high temperatures. Furthermore, in the first and second bonding layers that bond the second substrate and the first substrate together, the first thermally conductive material portion of the first bonding layer corresponds one-to-one with the second thermally conductive material portion of the second bonding layer and is bonded together. This allows the heat generated during chip operation to be quickly transferred to the second substrate through the first and second thermally conductive material portions, preventing the heat dissipation rate from being affected by poor thermal conductivity of the bonding materials. Furthermore, because the first and second adhesive material portions have high bonding strength, when the second adhesive material portion of the second bonding layer corresponds one-to-one with the first adhesive material portion of the first bonding layer and is bonded together, the structural stability between the first and second substrates can be improved, thereby increasing the lifespan of the semiconductor device. Therefore, the semiconductor device provided in this application not only enables a stable and firm bond between the thermally conductive second substrate and the first substrate of the semiconductor structure through the first and second adhesive material portions, but also ensures a high heat transfer rate between the first and second substrates through the first and second thermally conductive material portions, further reducing the risk of chip performance degradation due to high temperatures.
[0008] As one possible implementation, the first thermally conductive material portion and the first adhesive material portion are alternately distributed in a strip, comb, lattice, or concentric circle manner along a direction parallel to the surface of the first substrate. In this case, there are multiple examples of the distribution pattern between the first thermally conductive material portion and the first adhesive material portion, and the heat dissipation efficiency corresponding to different examples may be different. Therefore, appropriate examples can be set according to the needs of different actual application scenarios, thereby improving the applicability of the semiconductor device provided in this application in different application scenarios.
[0009] As one possible implementation, the first thermally conductive material portion and the first adhesive material portion have the same thickness. This prevents situations where portions of the first and second thermally conductive material portions or adhesive material portions in the first and second bonding layers are not in contact due to a height difference between them. This ensures that heat generated by the chip can be quickly conducted through the first and second bonding layers to the thermally conductive second substrate, reducing the risk of the chip overheating. Simultaneously, it ensures that the semiconductor device has high structural strength. Furthermore, the first thermally conductive material portion and the first adhesive material portion of the same thickness form a flat first bonding layer. Compared to solutions with different thicknesses, the bonding force direction is more consistent when the thickness is the same, resulting in greater structural strength of the bonding connection between the semiconductor structure and the second substrate, and the resulting semiconductor device has better shock resistance.
[0010] As one possible implementation, along a direction parallel to the surface of the first substrate, the ratio of the width of a single first thermally conductive material portion to the width of a single first adhesive material portion is greater than or equal to 1 / 4 and less than or equal to 2 / 3.
[0011] As described above, the first thermally conductive material portion exhibits better thermal conductivity than the first adhesive material portion. Furthermore, the first adhesive material portion possesses higher bonding strength compared to the first thermally conductive material portion. Therefore, in practical applications, if the semiconductor device's chip generates significant heat during operation, and its heat dissipation requirements exceed structural strength requirements, the ratio of the width of a single first thermally conductive material portion to the width of a single first adhesive material portion can be set within a larger range to ensure that the chip is less affected by height during operation. Conversely, if the semiconductor device's chip requires higher structural strength than heat dissipation during operation, the ratio of the width of a single first thermally conductive material portion to the width of a single first adhesive material portion can be set within a smaller range to ensure higher structural reliability of the semiconductor device and improve the applicability of the semiconductor device provided in this application across different application scenarios.
[0012] As one possible implementation, along a direction parallel to the surface of the first substrate, the ratio of the width of a single first thermally conductive material portion to the width of the first bonding layer is greater than or equal to 1 / 4 and less than or equal to 2 / 3. The application principle of the beneficial effect in this case is the same as the application principle of the beneficial effect of the ratio of the width of a single first thermally conductive material portion to the width of a single first adhesive material portion being greater than or equal to 1 / 4 and less than or equal to 2 / 3 mentioned above, and will not be repeated here.
[0013] As one possible implementation, the first thermally conductive material and the second thermally conductive material are made of the same material. Bonding the first and second thermally conductive material parts, which are made of the same material, is less complex and avoids the risk of deformation of the bonding layer due to the use of different materials during long-term use after the semiconductor device is manufactured. This could potentially damage the chip structure or cause the semiconductor structure to separate from the second substrate, making it difficult to conduct heat to the second substrate and significantly reducing the heat dissipation capacity of the semiconductor device.
[0014] As one possible implementation, the material of the first thermally conductive material may include copper, aluminum, silver, or gold.
[0015] As one possible implementation, the first adhesive material part and the second adhesive material part are made of the same material.
[0016] As one possible implementation, the material of the first adhesive material includes polyimide, benzocyclobutene, or SU8 photoresist.
[0017] As one possible implementation, the second substrate is made of diamond and / or silicon carbide. In this case, traditional chip substrate materials such as silicon and silicon-on-insulator (SOI) have relatively low thermal conductivity. For example, the thermal conductivity of single-crystal Si is 150 W / mK, and that of SiO2 is 7.6 W / mK, while the thermal conductivity of diamond is as high as 2000 W / mK or more, and that of silicon carbide is 490 W / mK. Using a second substrate made of diamond and / or silicon carbide can significantly improve the heat dissipation of semiconductor devices.
[0018] As one possible implementation, the thickness of the first substrate is less than the thickness of the second substrate. In this case, the thickness of the first substrate, which has relatively poor thermal conductivity in the semiconductor device, is smaller. This allows the heat generated by the chip to be quickly transferred to the second substrate after passing through the thinner first substrate, and then quickly dissipated to the external environment by the more thermally conductive second substrate, further reducing the risk of the chip overheating.
[0019] As one possible implementation, the thickness of the first substrate is 8 μm and less than or equal to 100 μm.
[0020] Secondly, this application also provides a method for manufacturing a semiconductor device. The method includes: first, providing a semiconductor structure, the semiconductor structure including a first substrate and a chip disposed on the first substrate; next, forming a first bonding layer disposed on a side of the first substrate away from the chip, the first bonding layer including a first thermally conductive material portion and a first adhesive material portion alternately distributed along a direction parallel to the surface of the first substrate; next, providing a second substrate, the second substrate having a thermal conductivity greater than that of the first substrate. The second substrate has a bonding surface. Next, forming a second bonding layer on the bonding surface, the second bonding layer including a second thermally conductive material portion and a second adhesive material portion alternately distributed along a direction parallel to the bonding surface. Next, bonding the second substrate and the semiconductor structure together through the second bonding layer and the first bonding layer, such that the second thermally conductive material portion of the second bonding layer corresponds one-to-one with the first thermally conductive material portion of the first bonding layer, and the second adhesive material portion of the second bonding layer corresponds one-to-one with the first adhesive material portion of the first bonding layer.
[0021] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided in this application are the same as the beneficial effects of the semiconductor device of the above-mentioned technical solution, and will not be repeated here.
[0022] As one possible implementation, forming a first bonding layer disposed on the side of the silicon substrate away from the chip includes: forming a first thermally conductive material portion on the side of the semiconductor structure away from the chip; next, selectively etching the first thermally conductive material portion to form a first space to be filled penetrating the first thermally conductive material portion; and then forming a first adhesive material portion within the first space to be filled.
[0023] When using the above technical solution, during selective etching of the first thermally conductive material portion, the portion that does not need to form the first space to be filled is protected by a mask. Then, the first space to be filled is formed through processes such as wet etching or dry etching. Finally, the first thermally conductive material portion is removed. A precursor solution for the first adhesive material portion is spin-coated onto the side of the semiconductor structure away from the chip, filling the first space to be filled. The precursor solution for the first adhesive material portion is then dried and cured to form the first adhesive material portion within the first space to be filled. An appropriate amount of precursor solution for the first adhesive material portion is selected based on actual process requirements. If the formed first adhesive material portion is higher than the first thermally conductive material portion, a planarization process is used to make the two portions the same height to facilitate subsequent bonding processes.
[0024] As one possible implementation, forming a second bonding layer on the bonding surface includes: forming a second thermally conductive material portion on the bonding surface; then, selectively etching the second thermally conductive material portion to form a second space to be filled penetrating the second thermally conductive material portion; and finally, forming a second adhesive material portion within the second space to be filled.
[0025] As one possible implementation, forming a first bonding layer disposed on the side of the first substrate away from the chip includes: forming a first thermally conductive material layer on the side of the semiconductor structure away from the chip; next, forming a first mask on a portion of the first thermally conductive material layer; next, under the protection of the first mask, electroplating to form a second thermally conductive material layer on a portion of the first thermally conductive material layer; next, using an etching process to remove the first mask and the portion of the first thermally conductive material layer not covered by the second thermally conductive material layer, forming a first space to be filled, and obtaining a first thermally conductive material portion, the first thermally conductive material portion including the second thermally conductive material layer and the remaining first thermally conductive material layer; next, spin-coating a precursor solution for the first adhesive material portion onto the side of the semiconductor structure away from the chip; next, drying and curing the precursor solution for the first adhesive material portion to form a first adhesive material portion within the first space to be filled.
[0026] When the above technical solution is adopted, the appropriate amount of precursor solution for the first adhesive material part is selected according to the actual process requirements. If the first adhesive material part is higher than the first thermally conductive material part, the first adhesive material part is processed by a planarization process to make the two parts have the same height, so as to facilitate the subsequent bonding process.
[0027] As one possible implementation, forming a second thermally conductive material portion on the bonding surface includes: forming a third thermally conductive submaterial layer on the bonding surface; next, forming a second mask on a portion of the third thermally conductive submaterial layer; next, under the protection of the second mask, electroplating a fourth thermally conductive submaterial layer on a portion of the third thermally conductive submaterial layer; next, using an etching process to remove the second mask and the portion of the third thermally conductive submaterial layer not covered by the fourth thermally conductive submaterial layer, forming a second space to be filled, and obtaining a second thermally conductive material portion, which includes the fourth thermally conductive submaterial layer and the remaining third thermally conductive submaterial layer; next, spin-coating a precursor solution for a second adhesive material portion onto the side of the semiconductor structure away from the chip; and drying and curing the precursor solution for the second adhesive material portion to form a second adhesive material portion within the second space to be filled.
[0028] As one possible implementation, the vacuum level when bonding the second substrate and the semiconductor structure together is greater than or equal to 1 × 10⁻⁶. -3 Pa, and less than or equal to 1 × 10 -7 Pa.
[0029] As one possible implementation, the temperature at which the second substrate and the semiconductor structure are bonded together is greater than or equal to 150°C and less than or equal to 300°C.
[0030] As one possible implementation, the pressure when bonding the second substrate and the semiconductor structure together is greater than or equal to 100N and less than or equal to 100,000N.
[0031] As one possible implementation, the bonding time for bonding the second substrate and the semiconductor structure together is greater than or equal to 30 min and less than or equal to 600 min. Attached Figure Description
[0032] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0033] Figure 1 This is a schematic diagram of a semiconductor structure with a carrier and a surface coated with temporary bonding material in an embodiment of this application;
[0034] Figure 2 This is a schematic diagram illustrating the temporary bonding of the semiconductor structure and the carrier in an embodiment of this application;
[0035] Figure 3 This is a schematic diagram illustrating the thinning of the first substrate in an embodiment of this application;
[0036] Figure 4 This is a schematic diagram of the formation of a first bonding layer on a first substrate and a second bonding layer on a second substrate in an embodiment of this application;
[0037] Figure 5 This is a schematic diagram illustrating the temporary bonding of the semiconductor structure and the second substrate in an embodiment of this application;
[0038] Figure 6 This is a schematic diagram showing the removal of the carrier in an embodiment of this application;
[0039] Figure 7 This is a schematic diagram illustrating the cutting of the semiconductor structure from the second substrate in an embodiment of this application;
[0040] Figure 8 This is a schematic diagram of removing the temporary bonding layer in an embodiment of this application.
[0041] Figure label:
[0042] 100 - Semiconductor structure; 101 - First substrate;
[0043] 102 - Chip; 201 - Carrier;
[0044] 202 - Temporary bonding layer; 310 - First bonding layer;
[0045] 311 - First thermally conductive material section; 312 - First adhesive material section;
[0046] 320 - Second bonding layer; 321 - Second thermally conductive material section;
[0047] 322 - Second adhesive material section; 400 - Second substrate. Detailed Implementation
[0048] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0049] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.
[0051] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0052] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0053] With the development of semiconductor technology and the increasing demand for semiconductor chip performance, the heat generated by chips is growing significantly. Therefore, in addition to achieving better heat conduction and dissipation outside the chip package, better heat dissipation design for the chip itself is also necessary. In current technologies, chip substrates mostly use silicon substrates or silicon-on-insulator (SiO2) substrates. Both of these substrates have extremely poor thermal conductivity; Si has a thermal conductivity of 150 W / mK, and SiO2 has a thermal conductivity of only 7.6 W / mK. This makes it difficult for heat inside the chip to be conducted to the package and external heat dissipation structures, adversely affecting the normal operation of the chip.
[0054] To address the aforementioned problems, in a first aspect, embodiments of this application provide a semiconductor device. Please refer to... Figure 8 The semiconductor device provided in this application includes a semiconductor structure 100, a first bonding layer 310, a second substrate 400, and a second bonding layer 320. The semiconductor structure 100 includes a first substrate 101 and a chip 102 disposed on the first substrate 101. The first bonding layer 310 is disposed on the side of the first substrate 101 opposite to the chip 102. The first bonding layer 310 includes a first thermally conductive material portion 311 and a first adhesive material portion 312 alternately distributed along a direction parallel to the surface of the first substrate 101. The second substrate 400 has a higher thermal conductivity than the first substrate 101. The second substrate 400 has a bonding surface. The second bonding layer 320 is disposed on the bonding surface of the second substrate 400. The second bonding layer 320 includes a second thermally conductive material portion 321 and a second adhesive material portion 322 that are alternately distributed along the direction parallel to the bonding surface. The second thermally conductive material portion 321 of the second bonding layer 320 corresponds one-to-one with the first thermally conductive material portion 311 of the first bonding layer 310, and the second adhesive material portion 322 of the second bonding layer 320 corresponds one-to-one with the first adhesive material portion 312 of the first bonding layer 310. The second substrate 400 is bonded to the first bonding layer 310 through the second bonding layer 320.
[0055] When using the above technical solution, please refer to Figure 8The second substrate 400 and the semiconductor structure 100 are bonded together by the second bonding layer 320 and the first bonding layer 310, respectively. The thermal conductivity of the second substrate 400 is greater than that of the first substrate 101 included in the semiconductor structure 100. At this time, the heat generated by the chip 102 included in the semiconductor structure 100 when it is in operation can be dissipated to the external environment through the second substrate 400 with better thermal conductivity after passing through the first substrate 101. This enables the heat generated by the chip 102 to be dissipated quickly, preventing the chip 102 from affecting its working performance and efficiency due to high temperature. Secondly, in the first bonding layer 310 and the second bonding layer 320 that bond the second substrate 400 and the first substrate 101 together, the first thermally conductive material portion 311 of the first bonding layer 310 corresponds one-to-one with the second thermally conductive material portion 321 of the second bonding layer 320 and is bonded together. This allows the heat generated during the operation of the chip 102 to be quickly transferred to the second substrate 400 through the first substrate 101 via the highly thermally conductive first thermally conductive material portion 311 and the second thermally conductive material portion 321, preventing the heat dissipation rate from being affected by the poor thermal conductivity of the bonding materials. Furthermore, because the first adhesive material portion 312 and the second adhesive material portion 322 have high bonding strength, when the second adhesive material portion 322 of the second bonding layer 320 corresponds one-to-one with the first adhesive material portion 312 of the first bonding layer 310 and is bonded together, the structural stability between the first substrate 101 and the second substrate 400 can be improved, thereby increasing the lifespan of the semiconductor device. Therefore, the semiconductor device provided in this application embodiment can not only stably and firmly bond the thermally conductive second substrate 400 to the first substrate 101 of the semiconductor structure 100 through the first adhesive material portion 312 and the second adhesive material portion 322, but also ensure a high heat transfer rate between the first substrate 101 and the second substrate 400 through the first thermally conductive material portion 311 and the second thermally conductive material portion 321, further reducing the risk of the chip 102 deteriorating due to high temperature.
[0056] In practical applications, this application does not specifically limit the structure, material, and size of the semiconductor structure 100, as long as it can be applied to the semiconductor device provided in this application. The first substrate 101 included in the semiconductor structure 100 can be any semiconductor substrate, such as a silicon substrate or silicon-on-insulator (SiI), as long as a first bonding layer 310 can be formed on the side of the first substrate 101 opposite to the chip 102, and the thermal conductivity of the first substrate 101 is less than that of the second substrate 400. Preferably, the first substrate 101 uses a silicon substrate or a SiI substrate. Because the processes for manufacturing the chip 102 on a silicon substrate or a SiI substrate are mature in the prior art, the manufacturing difficulty of the semiconductor structure 100 provided in this application can be reduced, and the compatibility between the semiconductor device process provided in this application and the existing chip 102 process can be improved, which is beneficial to improving the yield of the semiconductor device.
[0057] Regarding the thickness of the first substrate 101, it is understandable that the thermal conductivity of the first substrate 101 is worse than that of the second substrate 400. In the heat transfer path from the device to the outside environment, because the thermal conductivity of the first substrate 101 is lower than that of the second substrate 400, the thickness of the first substrate 101 has the greatest impact on the thermal resistance of the semiconductor device compared to the thickness of the second substrate 400. If the thickness of the first substrate 101 is larger, the thermal resistance of the semiconductor device will be larger. Based on this, the thickness of the first substrate 101 can be set according to the heat dissipation requirements of the chip 102 in the actual application scenario.
[0058] Preferably, the thickness of the first substrate 101 is less than the thickness of the second substrate 400. In this case, the thickness of the first substrate 101, which has relatively poor thermal conductivity in the semiconductor device, is smaller. This facilitates the rapid transfer of heat generated by the chip 102 to the second substrate 400 after passing through the thinner first substrate 101, and then the heat is quickly dissipated to the external environment by the more thermally conductive second substrate 400, further reducing the risk of overheating of the chip 102.
[0059] For example, the thickness of the first substrate 101 can be greater than or equal to 8 μm and less than or equal to 100 μm. For instance, the thickness of the first substrate 101 can be 8 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, or 100 μm, etc.
[0060] Regarding the chip 102 included in the semiconductor structure 100, the dimensions of the chip 102 are not limited in this embodiment. The semiconductor structure 100 including the chip 102 can be a bare circuit with dimensions ranging from 100μm×100μm to 10cm×10cm and a thickness ranging from 30μm to 725μm. Alternatively, the semiconductor structure 100 including the chip 102 can be an entire circuit wafer with dimensions ranging from 2 inches to 12 inches. The type of chip 102 is also not specifically limited in this embodiment. The chip 102 can be an independent device such as a discrete semiconductor device, a MEMS device, an optoelectronic device, a memory, or a processor, or a functional chip with complex circuitry. Specifically, the chip 102 can be a high-power chip with high heat dissipation requirements or a low-power chip with relatively low heat dissipation requirements.
[0061] For the first bonding layer 310 mentioned above, please refer to Figure 8 It is disposed on the side of the first substrate 101 away from the chip 102, and includes a first thermally conductive material portion 311 and a first adhesive material portion 312 that are alternately distributed along a direction parallel to the surface of the first substrate 101.
[0062] In terms of materials, the embodiments of this application do not specifically limit the types of materials for the first thermally conductive material part 311 and the first adhesive material part 312, as long as they meet the requirements for heat dissipation and structural strength in the actual application scenario.
[0063] For example, the material of the first thermally conductive material portion 311 can be copper, aluminum, silver, gold, or any other metal or alloy with high thermal conductivity that can be used for metal bonding. The first thermally conductive material portion 311 is the main body for heat conduction of the first bonding layer 310. The heat generated by the chip 102 is conducted through the first substrate 101. When passing through the first bonding layer 310, the heat is mainly conducted to the second substrate 400 through the first thermally conductive material portion 311.
[0064] For example, the material of the first adhesive material portion 312 may include polyimide, benzocyclobutene, SU8 photoresist, or other polymers, as long as they can provide good adhesion. Preferably, the material of the first adhesive material portion 312 is polyimide.
[0065] In terms of distribution, the first thermally conductive material portion 311 and the first adhesive material portion 312 can be alternately distributed in the first bonding layer 310 in any manner. It is understood that when the arrangement of the first thermally conductive material portion 311 and the first adhesive material portion 312 is different, the corresponding heat dissipation efficiency may be different. Therefore, the arrangement of the first thermally conductive material portion 311 and the first adhesive material portion 312 can be set according to the needs of different practical application scenarios to improve the applicability of the semiconductor device provided in this application embodiment under different application scenarios.
[0066] For example, the first thermally conductive material portion 311 and the first adhesive material portion 312 can be arranged in an alternating pattern such as strips, combs, dot matrix, or concentric circles. Specifically, a suitable distribution pattern can be selected based on the material and bonding strength requirements of the first thermally conductive material portion 311 and the first adhesive material portion 312, or a suitable distribution pattern can be selected based on the temperature distribution of the chip 102.
[0067] In terms of thickness, the first thermally conductive material portion 311 and the first adhesive material portion 312 can have the same thickness. This prevents situations where the height difference between the first thermally conductive material portion 311 and the first adhesive material portion 312 causes some portions of the first bonding layer 310 and the second bonding layer 320 to not contact each other, or some portions of the first adhesive material portion 312 and the second adhesive material portion 322 to not contact each other. This ensures that the heat generated by the chip 102 can be quickly conducted through the first bonding layer 310 and the second bonding layer 320 to the thermally conductive second substrate 400, reducing the risk of overheating of the chip 102. Simultaneously, it also ensures that the semiconductor device has high structural strength. In addition, the first thermally conductive material portion 311 and the first adhesive material portion 312 of the same thickness form a first bonding layer 310 with a flat surface. Compared with the solution with different thicknesses, the bonding force direction is more consistent when the thickness is the same, the structural strength of the bonding connection between the semiconductor structure 100 and the second substrate 400 is greater, and the resulting semiconductor device has better shock resistance.
[0068] Of course, the thicknesses of the first thermally conductive material portion 311 and the first adhesive material portion 312 can also be different, as long as the heat dissipation and structural strength of the semiconductor device meet the actual requirements.
[0069] Regarding the arrangement ratio of the first thermally conductive material portion 311 and the first adhesive material portion 312 within the first bonding layer 310, it is understood that, as mentioned above, the first thermally conductive material portion 311 has better thermal conductivity than the first adhesive material portion 312. Conversely, the first adhesive material portion 312 has higher bonding strength than the first thermally conductive material portion 311. In other words, the first bonding layer 310 includes the first thermally conductive material portion 311 and the first adhesive material portion 312, which have different functions. Therefore, the arrangement ratio of the first thermally conductive material portion 311 and the first adhesive material portion 312 within the first bonding layer 310 can be determined according to the actual application scenario's requirements for heat dissipation and structural strength of the semiconductor device; no specific limitation is made here.
[0070] For example, along a direction parallel to the surface of the first substrate 101, the ratio of the width of a single first thermally conductive material portion 311 to the width of a single first adhesive material portion 312 can be greater than or equal to 1 / 4 and less than or equal to 2 / 3. In this case, in practical applications, if the chip 102 included in the semiconductor device generates a lot of heat during operation, and its heat dissipation requirement is higher than the structural strength requirement, the ratio of the width of a single first thermally conductive material portion 311 to the width of a single first adhesive material portion 312 can be set within a larger range to ensure that the chip 102 is less affected by height during operation. If the structural strength requirement of the chip 102 included in the semiconductor device is higher than the heat dissipation requirement during operation, the ratio of the width of a single first thermally conductive material portion 311 to the width of a single first adhesive material portion 312 can be set within a smaller range to ensure that the semiconductor device has high structural reliability and improve the applicability of the semiconductor device provided in this application embodiment in different application scenarios.
[0071] For example, along a direction parallel to the surface of the first substrate 101, the ratio of the width of a single first thermally conductive material portion 311 to the width of the first bonding layer 310 is greater than or equal to 1 / 4 and less than or equal to 2 / 3. The application principle of the beneficial effect in this case can be referred to the application principle of the beneficial effect of the ratio of the width of a single first thermally conductive material portion 311 to the width of a single first adhesive material portion 312 being greater than or equal to 1 / 4 and less than or equal to 2 / 3 as described above, and will not be repeated here.
[0072] Regarding the second substrate 400, since its thermal conductivity is greater than that of the first substrate 101, it can better conduct the heat generated by the chip 102 to the outside of the semiconductor device, achieving better heat dissipation. Therefore, from a material perspective, this application embodiment does not specifically limit the material of the second substrate 400, as long as the thermal conductivity of the second substrate 400 is greater than that of the first substrate 101.
[0073] For example, the material of the second substrate 400 can be diamond or semi-silicon carbide. Diamond has a thermal conductivity of over 2000 W / mK, and silicon carbide has a thermal conductivity of 490 W / mK. The first substrate 101 is selected as a silicon substrate or silicon-on-insulator, and the thermal conductivity of its materials is as follows: the thermal conductivity of single crystal silicon is 150 W / mK, and the thermal conductivity of SiO2 is 7.6 W / mK, which is significantly lower than the thermal conductivity of the material of the second substrate 400. The second substrate 400 can conduct away the heat generated by the chip 102 by virtue of its significantly higher thermal conductivity than that of the first substrate 101.
[0074] Secondly, please refer to Figure 4The second substrate 400 also has a bonding surface, which is the side of the second substrate 400 opposite to the first substrate 101. A second bonding layer 320 is formed on the bonding surface. The second bonding layer 320 includes a second thermally conductive material portion 321 and a second adhesive material portion 322 that are alternately distributed along a direction parallel to the bonding surface. The second thermally conductive material portion 321 of the second bonding layer 320 corresponds one-to-one with the first thermally conductive material portion 311 of the first bonding layer 310, and the second adhesive material portion 322 of the second bonding layer 320 corresponds one-to-one with the first adhesive material portion 312 of the first bonding layer 310.
[0075] In terms of materials, the materials and distribution of the second thermally conductive material portion 321 and the second adhesive material portion 322 included in the second bonding layer 320 can be referenced to the materials and distribution of the first thermally conductive material portion 312 and the first adhesive material portion 310 included in the first bonding layer 310, as described above, and will not be repeated here. The material of the second thermally conductive material portion 321 included in the second bonding layer 320 can be the same as or different from the material of the first thermally conductive material portion 311. Similarly, the material of the second adhesive material portion 322 included in the second bonding layer 320 can be the same as or different from the material of the first adhesive material portion 312.
[0076] It is worth noting that the first thermally conductive material portion 311 and the second thermally conductive material portion 321, which are made of the same material, are bonded together, which reduces the difficulty of the bonding process. This also avoids the deformation of the bonding layer caused by the use of different materials during long-term use after the semiconductor device is manufactured, which could lead to damage to the chip 102 structure or separation of the semiconductor structure 100 from the second substrate 400, making it difficult for heat to be conducted to the second substrate 400 and greatly reducing the heat dissipation capacity of the semiconductor device. The application principle of the beneficial effect of the second adhesive material portion 322 being made of the same material as the first adhesive material portion 312 can be referred to the previous text and will not be repeated here.
[0077] Secondly, please refer to Figures 1 to 8 This application also provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes the following manufacturing steps:
[0078] First, a semiconductor structure 100 is provided, which includes a first substrate 101 and a chip 102 disposed on the first substrate 101. Specifically, the material, size, and type of the semiconductor structure 100 can be referred to the previous text, and will not be repeated here.
[0079] In the actual manufacturing process, please refer to some embodiments. Figures 1-3Before forming the first bonding layer 310, the manufacturing method of the semiconductor device may further include the step of providing a carrier 201. This carrier 201 is used to protect the chip 102 disposed on the first substrate 101 from the influence of the clamping mechanism when the first substrate 101 of the semiconductor structure 100 is thinned, and to prevent damage to the semiconductor structure 100 during transfer due to its small thickness after the thickness of the first substrate 101 has been reduced to a certain range. Specifically, the material of the carrier 201 can be any material capable of protecting the semiconductor structure 100, such as silicon carbide, silicon, silicon oxide, or sapphire, as long as it can be applied to the manufacturing method of the semiconductor device provided in this application embodiment. Next, the carrier 201 and the semiconductor structure 100 can be cleaned to remove surface contaminants. A temporary bonding layer 202 is coated on the chip 102 by spin coating, spraying, or other methods. The material of the temporary bonding layer 202 may include photoresists such as ProTEK B3, HT-10.10, and TN108, and may also include organic polymers and high-temperature paraffin. The thermal stability temperature of the material of the temporary bonding layer 202 can be between 150°C and 300°C, and the temporary bonding material can be dissolved in organic and / or alkaline inorganic reagents such as acetone. Next, the semiconductor structure 100 is bonded to the carrier 201 to facilitate subsequent thinning of the first substrate 101.
[0080] Next, please refer to Figure 3The first substrate 101 on the back side of the temporarily bonded chip 102 is thinned. Specifically, the method for thinning the first substrate 101 can be determined based on the amount of thinning and the actual application scenario, and is not specifically limited here. For example, the first substrate 101 can first undergo coarse thinning. The thinning technique used in this coarse thinning process can be either a thinning machine or mechanical polishing, or a combination of both. The thickness of the semiconductor structure 100 after coarse thinning can range from 30μm to 150μm. A thinner semiconductor structure 100 has a thinner first substrate 101. As the first substrate 101 has a lower thermal conductivity in the heat transfer path of the chip 102, it has the greatest impact on the heat dissipation capacity of the entire semiconductor device. Under the premise of ensuring the strength of the semiconductor structure 100, the smaller the thickness of the first substrate 101, the better the heat dissipation of the entire device. Next, the semiconductor structure 100 undergoes fine thinning. The fine thinning technique can be dry etching, wet etching, or a combination of both. Dry etching can be performed using a capacitive plasma etching machine (CCP) or an inductive plasma etching machine (ICP). The type of etchant used in the wet etching process can be determined based on the material of the first substrate 101, and is not specifically limited here. For example, if the material of the first substrate 101 includes silicon, tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), etc., can be used. As another example, if the material of the first substrate 101 includes silicon oxide, HF solution, etc., can be used. After fine thinning, the thickness of the semiconductor structure 100 ranges from 10 μm to 100 μm. Next, the finely thinned semiconductor structure 100 undergoes chemical mechanical polishing and cleaning.
[0081] It is worth noting that, compared to performing only coarse thinning on the semiconductor structure 100, this embodiment of the application employs a combination of coarse and fine thinning processes. This allows the side of the first substrate 101 facing away from the chip 102 to have a higher degree of flatness after thinning, which is beneficial for improving the strength of subsequent bonding. Furthermore, compared to performing only fine thinning on the semiconductor structure 100, this embodiment of the application uses a combination of coarse and fine thinning processes, which can increase the thinning rate and improve the manufacturing efficiency of the semiconductor device.
[0082] In addition, if the thickness of the first substrate 101 in the provided semiconductor structure meets the requirements of the actual application scenario and will not cause damage to the semiconductor structure 100 during the transfer process, the temporary bonding carrier 201 and the above-mentioned thinning treatment of the first substrate 101 are not required.
[0083] Next, as Figure 4As shown, a first bonding layer 310 is formed on the side of the first substrate 101 opposite to the chip 102. The first bonding layer 310 includes a first thermally conductive material portion 311 and a first adhesive material portion 312 that are alternately distributed along a direction parallel to the surface of the first substrate 101.
[0084] Specifically, the materials, thicknesses, and distribution patterns of the first thermally conductive material portion 311 and the first adhesive material portion 312 can be referred to the preceding text and will not be repeated here. In the actual manufacturing process, according to the above scheme, this application provides two manufacturing processes, Embodiment 1 and Embodiment 2, regarding the formation of the first bonding layer 310. It should be noted that Embodiment 1 and Embodiment 2 are only used to more clearly illustrate the technical solutions provided by the embodiments of this application, and should not be used to limit the protection scope of the embodiments of this application.
[0085] Example 1:
[0086] like Figure 4 As shown, a first thermally conductive material portion 311 is formed on the side of the semiconductor structure 100 opposite to the chip 102. Next, the first thermally conductive material portion 311 is selectively etched to form a first space to be filled that extends through the first thermally conductive material portion 311. Then, a first adhesive material portion 312 is formed within the first space to be filled.
[0087] In the actual manufacturing process, processes such as vapor deposition or sputtering can be used to form a solid-layer first thermally conductive material portion 311 on the side of the first substrate 101 facing away from the chip 102. Next, processes such as photolithography and etching can be used to selectively etch the first thermally conductive material portion 311, removing the portion corresponding to the formation of the first adhesive material portion 312 on the side of the first substrate 101 facing away from the chip 102, thus forming a first space to be filled. Alternatively, a photoresist or other mask structure can be formed at the location of the first space to be filled before forming the first thermally conductive material portion 311. Then, after forming the first thermally conductive material portion 311, a process such as peeling can be used to remove the mask structure and the portion of the first thermally conductive material portion 311 corresponding to the first space to be filled. Next, a solution method can be used to spin-coat a precursor solution of the first adhesive material portion 312 onto the side of the semiconductor structure 100 facing away from the chip 102, filling the first space to be filled with the precursor solution of the first adhesive material portion 312. Next, the precursor solution of the first adhesive material portion 312 is dried and cured to form the first adhesive material portion 312 in the first space to be filled. The appropriate amount of precursor solution for the first adhesive material portion 312 is selected according to actual process requirements. If the formed first adhesive material portion 312 is higher than the first thermally conductive material portion 311, a planarization process is used to make the heights of the two portions the same to facilitate subsequent bonding processes.
[0088] It should be noted that the preceding explanation uses the example of manufacturing the first thermally conductive material part 311 first, and does not imply that the first thermally conductive material part 311 can be manufactured first, followed by the first adhesive material part 312. In actual applications, the formation sequence of the first adhesive material part 312 can precede the formation sequence of the first thermally conductive material part 311.
[0089] Example 2:
[0090] like Figure 4 As shown, the formation of the first thermally conductive material portion 311 on the side of the semiconductor structure 100 away from the chip 102 may also include the following steps: a first thermally conductive submaterial layer may be formed on the side of the semiconductor structure 100 away from the chip 102 using a process such as physical vapor deposition. Next, a first mask may be formed on a portion of the first thermally conductive submaterial layer using a process such as photolithography. The material of the first mask may include photoresist. Then, under the protection of the first mask, a second thermally conductive submaterial layer is electroplated on a portion of the first thermally conductive submaterial layer to form a second thermally conductive submaterial layer; then, an etching process (such as wet etching) is used to remove the first mask and remove the portion of the first thermally conductive submaterial layer not covered by the second thermally conductive submaterial layer, forming a first space to be filled, and obtaining the first thermally conductive material portion 311. This first thermally conductive material portion 311 includes the second thermally conductive submaterial layer and the remaining first thermally conductive submaterial layer. Next, the precursor solution of the first adhesive material portion 312 is spin-coated onto the side of the semiconductor structure 100 opposite to the chip 102. The precursor solution of the first adhesive material portion 312 is dried and cured to form the first adhesive material portion 312 in the first space to be filled. The amount of precursor solution used for the first adhesive material portion 312 can be selected according to actual process requirements. If the formed first adhesive material portion 312 is higher than the first thermally conductive material portion, a planarization process can be used to make the heights of the two portions the same, facilitating subsequent bonding processes. Furthermore, compared to Embodiment 1, Embodiment 2 uses an electroplating process to manufacture part of the first thermally conductive material portion 311, which helps reduce thermal damage to the chip 102 caused by manufacturing the first thermally conductive material portion 311 on the first substrate 101, thus improving the yield of the semiconductor device.
[0091] It should be noted that when the material of the first thermally conductive material portion 311 includes a metallic thermally conductive material, a diffusion barrier layer can be formed on the side of the first substrate 101 opposite to the chip 102 before forming the first thermally conductive material portion 311 or the first thermally conductive sub-material layer. This prevents metal ions in the first thermally conductive material portion 311 from diffusing to the chip 102 through the thinner first substrate 101 during manufacturing, thereby affecting the overall operation of the chip 102. The material of the diffusion barrier layer may include tantalum, etc. The thickness of the diffusion barrier layer is not specifically limited in this embodiment.
[0092] Next, a second substrate 400 is provided, which has a bonding surface. Specifically, the material of the second substrate 400 and the location of the bonding surface on the second substrate 400 can be referred to the previous text, and will not be repeated here.
[0093] Next, as Figure 4 As shown, a second bonding layer 320 is formed on the bonding surface. The second bonding layer 320 includes a second thermally conductive material portion 321 and a second adhesive material portion 322 alternately distributed along a direction parallel to the bonding surface. Specifically, the materials, thicknesses, and distribution patterns of the second thermally conductive material portion 321 and the second adhesive material portion 322 can be referred to the preceding text and will not be repeated here. In the actual manufacturing process, according to the above scheme, this application provides two manufacturing processes for forming the second bonding layer 320: Embodiment 3 and Embodiment 4. Embodiments 3 and 4 are only used to more clearly illustrate the technical solution of this application and should not be used to limit the protection scope of the embodiments of this application.
[0094] Example 3:
[0095] like Figure 4 As shown, a second thermally conductive material portion 321 is formed on the bonding surface of the second substrate. Next, the second thermally conductive material portion 321 is selectively etched to form a first space to be filled penetrating the second thermally conductive material portion 321. Then, a second adhesive material portion 322 is formed within the second space to be filled.
[0096] In the actual manufacturing process, processes such as vapor deposition or sputtering can be used to form a continuous layer of the second thermally conductive material portion 321 on the bonding surface of the second substrate 400. Next, processes such as photolithography and etching can be used to selectively etch the second thermally conductive material portion 321, removing the portion corresponding to the area where the second adhesive material portion 322 is formed on the bonding surface of the second substrate 400, thus forming the second space to be filled. Alternatively, a photoresist or other mask structure can be formed at the location of the second space to be filled before forming the second thermally conductive material portion 321. Then, after forming the second thermally conductive material portion 321, a process such as peeling can be used to remove the mask structure and the portion of the second thermally conductive material portion 321 corresponding to the second space to be filled. Next, a solution method can be used to spin-coat a precursor solution of the second adhesive material portion 322 onto the bonding surface of the second substrate 400, filling the second space to be filled with the precursor solution of the second adhesive material portion 322. Next, the precursor solution of the second adhesive material portion 322 is dried and cured to form the second adhesive material portion 322 in the second space to be filled. The appropriate amount of precursor solution for the second adhesive material portion 322 is selected according to actual process requirements. If the formed second adhesive material portion 322 is higher than the second thermally conductive material portion 321, a planarization process is used to make the two portions the same height to facilitate subsequent bonding processes.
[0097] It should be noted that the preceding explanation uses the example of manufacturing the second thermally conductive material part 321 first, and does not imply that the second thermally conductive material part 321 can be manufactured first, followed by the second adhesive material part 322. In actual applications, the formation sequence of the second adhesive material part 322 can precede the formation sequence of the second thermally conductive material part 321.
[0098] Example 4:
[0099] The formation of the second thermally conductive material portion 321 on the bonding surface of the second substrate 400 may also include the following steps: a third thermally conductive submaterial layer may be formed on the bonding surface of the second substrate 400 using a process such as physical vapor deposition. Next, a second mask may be formed on a portion of the third thermally conductive submaterial layer using a process such as photolithography. The material of the second mask may include photoresist. Then, under the protection of the second mask, a fourth thermally conductive submaterial layer is formed by electroplating on a portion of the third thermally conductive submaterial layer; then, an etching process (such as wet etching) is used to remove the second mask and remove the portion of the third thermally conductive submaterial layer not covered by the fourth thermally conductive submaterial layer, forming a second space to be filled, and obtaining the second thermally conductive material portion 321. This second thermally conductive material portion 321 includes the fourth thermally conductive submaterial layer and the remaining third thermally conductive submaterial layer. Next, the precursor solution of the second adhesive material portion 322 is spin-coated onto the bonding surface of the second substrate 400; the precursor solution of the second adhesive material portion 322 is dried and cured to form the second adhesive material portion 322 in the second space to be filled; the precursor solution of the second adhesive material portion 322 is dried and cured to form the second adhesive material portion 322 in the second space to be filled. The appropriate amount of precursor solution used for the second adhesive material portion 322 can be selected according to actual process requirements. If the formed second adhesive material portion 322 is higher than the second thermally conductive material portion 321, a planarization process can be used to make the two portions the same height to facilitate subsequent bonding processes.
[0100] Alternatively, after the first bonding layer 310 and the second bonding layer 320 are formed, the semiconductor device manufacturing method may further include the step of: performing plasma activation treatment on the first substrate 101 with the first bonding layer 310 formed and the second substrate 400 with the second bonding layer 320 formed, respectively, under the synergistic effect of water molecule wetting, to improve interface defects caused by the differences in physical properties between the first thermally conductive material portion 311 and the first adhesive material portion 312, and the second thermally conductive material portion 321 and the second adhesive material portion 322. The plasma gas can be O2, N2, Ar, H2, etc., or one or more of these. Preferably, it is O2. The volume fraction of O2 in the plasma gas is 1% to 10%, the activation power of the plasma activation treatment can be 100W to 600W, and the activation time can be 20s to 500s.
[0101] Next, please refer to Figure 5The second substrate 400 and the semiconductor structure 100 are bonded together by means of a one-to-one correspondence between the second thermally conductive material portion 321 of the second bonding layer 320 and the first thermally conductive material portion 311 of the first bonding layer 310, and a one-to-one correspondence between the second adhesive material portion 322 of the second bonding layer 320 and the first adhesive material portion 312 of the first bonding layer 310.
[0102] In practical applications, this application does not specifically limit the bonding method and bonding conditions of the first bonding layer 310 and the second bonding layer 320, as long as they can be applied to the semiconductor device manufacturing method provided in this application. For example, the vacuum degree of the direct bonding process can be 1×10⁻⁶. -3 Pa to 1×10 -7 Pa.
[0103] For example, the temperature can be between 150 and 300°C. In this case, the lower bonding temperature can prevent damage to chip 102 from high temperatures.
[0104] For example, the pressure can be from 100N to 100,000N.
[0105] For example, the time can be from 30 minutes to 600 minutes.
[0106] Optionally, the semiconductor device processed by the above process may be subjected to annealing and hardening treatment to further improve the structural reliability of the semiconductor device.
[0107] For example, the atmosphere of the aforementioned annealing process can be N2, Ar, or a high vacuum atmosphere, etc.
[0108] For example, the temperature can be from 200°C to 600°C.
[0109] For example, the time can be from 2 hours to 24 hours.
[0110] It should be noted that if a carrier 201 is temporarily bonded to the side of the chip 102 opposite to the first substrate 101 before the formation of the first bonding layer 310, please refer to... Figure 6 After bonding the first bonding layer 310 and the second bonding layer 320, it is necessary to debond the carrier 201 to the chip 102. Specifically, the debonding methods include, but are not limited to, thermal debonding, laser debonding, and gas debonding.
[0111] Please refer to Figures 7 to 8 The semiconductor device with a temporary bonding layer 202 attached to the surface of the chip 102 is obtained by dicing. The temporary bonding layer 202 is removed to obtain the semiconductor device.
[0112] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0113] The embodiments of this application have been described above. However, these embodiments are merely illustrative of the content of this application and are not intended to limit the scope of this application. The scope of this application is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this application, and all such substitutions and modifications should fall within the scope of this application.
Claims
1. A semiconductor device, characterized in that, include: A semiconductor structure, the semiconductor structure including a first substrate and a chip disposed on the first substrate; A first bonding layer is disposed on the side of the first substrate away from the chip; the first bonding layer includes a first thermally conductive material portion and a first adhesive material portion alternately distributed along a direction parallel to the surface of the first substrate; The second substrate has a higher thermal conductivity than the first substrate; The second substrate has a bonding surface; A second bonding layer is disposed on the bonding surface of the second substrate. The second bonding layer includes a second thermally conductive material portion and a second adhesive material portion alternately distributed along a direction parallel to the bonding surface. The second thermally conductive material portion of the second bonding layer corresponds one-to-one with the first thermally conductive material portion of the first bonding layer, and the second adhesive material portion of the second bonding layer corresponds one-to-one with the first adhesive material portion of the first bonding layer. The second substrate and the semiconductor structure are bonded together by the second bonding layer and the first bonding layer, respectively.
2. The semiconductor device according to claim 1, characterized in that, The first thermally conductive material portion and the first adhesive material portion are alternately distributed in a strip, comb, dot matrix or concentric circle manner along a direction parallel to the surface of the first substrate.
3. The semiconductor device according to claim 1, characterized in that, The thickness of the first thermally conductive material portion and the first adhesive material portion are the same; And / or, along a direction parallel to the surface of the first substrate, the ratio of the width of a single first thermally conductive material portion to the width of a single first adhesive material portion is greater than or equal to 1 / 4 and less than or equal to 2 / 3. And / or, along a direction parallel to the surface of the first substrate, the ratio of the width of a single first thermally conductive material portion to the width of the first bonding layer is greater than or equal to 1 / 4 and less than or equal to 2 / 3.
4. The semiconductor device according to claim 1, characterized in that, The first thermally conductive material part and the second thermally conductive material part are made of the same material; And / or, the material of the first thermally conductive material portion includes copper, aluminum, silver, or gold; And / or, the first adhesive material portion and the second adhesive material portion are made of the same material; And / or, the material of the first adhesive material portion includes polyimide, benzocyclobutene, or SU8 photoresist.
5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The material of the second substrate is diamond and / or silicon carbide; And / or, the thickness of the first substrate is less than the thickness of the second substrate; And / or, the thickness of the first substrate is greater than or equal to 8 μm and less than or equal to 100 μm.
6. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a first substrate and a chip disposed on the first substrate; A first bonding layer is formed on the side of the first substrate opposite to the chip. The first bonding layer includes a first thermally conductive material portion and a first adhesive material portion that are alternately distributed along a direction parallel to the surface of the first substrate. A second substrate is provided, wherein the thermal conductivity of the second substrate is greater than that of the first substrate; The second substrate has a bonding surface; A second bonding layer is formed on the bonding surface, the second bonding layer comprising a second thermally conductive material portion and a second adhesive material portion alternately distributed along a direction parallel to the bonding surface; The second substrate and the semiconductor structure are bonded together by means of a one-to-one correspondence between the second thermally conductive material portion of the second bonding layer and the first bonding layer, and a one-to-one correspondence between the second adhesive material portion of the second bonding layer and the first adhesive material portion of the first bonding layer.
7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The formation of the first bonding layer disposed on the side of the first substrate opposite to the chip includes: A first thermally conductive material portion is formed on the side of the semiconductor structure opposite to the chip; the first thermally conductive material portion is selectively etched to form a first space to be filled penetrating the first thermally conductive material portion; a first adhesive material portion is formed within the first space to be filled; and / or, The formation of the second bonding layer on the bonding surface includes: A second thermally conductive material portion is formed on the bonding surface; the second thermally conductive material portion is selectively etched to form a second space to be filled that penetrates the second thermally conductive material portion; and a second adhesive material portion is formed within the second space to be filled.
8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The formation of the first bonding layer disposed on the side of the first substrate opposite to the chip includes: A first thermally conductive material layer is formed on the side of the semiconductor structure opposite to the chip; A first mask is formed on a portion of the first thermally conductive material layer; Under the protection of the first mask, a second thermal conductive material layer is electroplated on a portion of the first thermal conductive material layer to form a second thermal conductive material layer; An etching process is used to remove the first mask and the portion of the first thermally conductive material layer not covered by the second thermally conductive material layer, forming a first space to be filled, and obtaining the first thermally conductive material portion; the first thermally conductive material portion includes the second thermally conductive material layer and the remaining first thermally conductive material layer; The precursor solution of the first adhesive material portion is spin-coated onto the side of the semiconductor structure opposite to the chip; The precursor solution of the first adhesive material portion is dried and cured to form the first adhesive material portion in the first space to be filled.
9. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The formation of the second bonding layer on the bonding surface includes: A third thermally conductive material layer is formed at the bonding surface; A second mask is formed on a portion of the third thermally conductive submaterial layer; Under the protection of the second mask, a fourth thermal conductive material layer is electroplated on a portion of the third thermal conductive material layer to form a fourth thermal conductive material layer; An etching process is used to remove the second mask and the portion of the third thermal conductive material layer not covered by the fourth thermal conductive material layer, forming a second space to be filled, and obtaining the second thermal conductive material portion; the second thermal conductive material portion includes the fourth thermal conductive material layer and the remaining third thermal conductive material layer; The precursor solution of the second adhesive material portion is spin-coated onto the side of the semiconductor structure opposite to the chip; The precursor solution of the second adhesive material portion is dried and cured to form the second adhesive material portion in the second space to be filled.
10. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The vacuum level required to bond the second substrate and the semiconductor structure together is greater than or equal to 1 × 10⁻⁶. -3 Pa, and less than or equal to 1 × 10 -7 Pa; And / or, the temperature at which the second substrate and the semiconductor structure are bonded together is greater than or equal to 150°C and less than or equal to 300°C; And / or, the pressure applied when bonding the second substrate and the semiconductor structure together is greater than or equal to 100 N and less than or equal to 100,000 N; And / or, the bonding time for bonding the second substrate and the semiconductor structure together is greater than or equal to 30 min and less than or equal to 600 min.