Semiconductor structure and preparation method thereof

Abstract

An embodiment of the present disclosure discloses a semiconductor structure and a method for preparing the same, wherein the semiconductor structure includes: a chip unit, the chip unit includes a first region and a second region located outside the first region, a plurality of first connection structures located on the first region and a plurality of second connection structures located on the second region, wherein the spacing between adjacent first connection structures is smaller than the spacing between adjacent second connection structures, and a main path located on the second region, wherein the spacing between two second connection structures oppositely arranged on both sides of the main path is larger than the spacing between two adjacent second connection structures at other positions.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In 3DS and HBM products, molded underfill technology integrates underfill and injection molding processes, offering the advantages of high throughput and low cost. However, as integration and I / O density increase, the gaps between adjacent bumps are shrinking. Especially in HBM products, the bump spacing is now less than 20μm, and the number of bumps is large, often reaching tens of thousands. The densely packed bumps increase the flow resistance of the molding compound, posing a significant challenge to the molded underfill process. This can lead to voids or flow marks, which can severely impact package reliability. Existing solutions include increasing the clamping pressure during the compression mold process to compensate for the increased flow resistance caused by the dense bump packing. However, this increased clamping pressure also increases the risk of wafer cracking, making it an ineffective and unsafe solution. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, comprising:

[0005] A chip unit, the chip unit comprising a first area and a second area located outside the first area;

[0006] a plurality of connection structures, the connection structures comprising a plurality of first connection structures located on the first region and a plurality of second connection structures located on the second region, wherein, in a first direction, a spacing between adjacent first connection structures is smaller than a spacing between adjacent second connection structures, and the first direction is parallel to a plane of the chip unit;

[0007] The main path is located on the second area, and the distance between two second connecting structures arranged opposite to each other on both sides of the main path is greater than the distance between two adjacent second connecting structures at other positions.

[0008] In some embodiments, the first region extends along the first direction, and the second region is distributed on both sides of the first region along a second direction, wherein the second direction is parallel to the plane of the chip unit, and the first direction and the second direction intersect.

[0009] In some embodiments, the chip unit includes a plurality of first regions spaced apart from each other, each of the first regions being connected to at least one main path.

[0010] A plurality of main paths are formed on the second area between two adjacent first areas, wherein each first area is connected to at least one main path located on the second area between two adjacent first areas.

[0011] In some embodiments, the main path includes a first sub-path, which extends from an edge of the chip unit toward the first region, and an angle between the first sub-path and the edge of the chip unit in contact therewith ranges from 30° to 60°.

[0012] In some embodiments, the main path further includes a second sub-path, and the second sub-path is connected to at least one of the first sub-paths.

[0013] In some embodiments, the connection structure further includes a plurality of third connection structures located on the second region, the third connection structures are arranged on the main path, and top surfaces of the third connection structures are lower than top surfaces of the second connection structures.

[0014] In some embodiments, the first connection structure and the second connection structure simultaneously have a first connection layer, a second connection layer, and a third connection layer, and the third connection structure has the first connection layer or the first connection layer and the second connection layer.

[0015] In some embodiments, the first connection structure is a conductive contact bump, and the second connection structure is a dummy bump.

[0016] According to a second aspect of an embodiment of the present disclosure, there is provided a semiconductor package structure, including:

[0017] substrate;

[0018] A chip unit, wherein the chip unit is mounted on the substrate via a connecting structure; the chip unit has a first area and a second area located outside the first area; the connecting structure includes a plurality of first connecting structures and a plurality of second connecting structures; in a first direction, a spacing between adjacent first connecting structures is smaller than a spacing between adjacent second connecting structures; the first direction is parallel to a plane of the chip unit;

[0019] A main path is located on the second area, and a distance between two second connecting structures arranged opposite to each other on both sides of the main path is greater than a distance between two adjacent second connecting structures at other positions;

[0020] A bottom filling material is filled between the first connecting structure and the second connecting structure along the main path to plastic-encapsulate the chip unit and the substrate.

[0021] In some embodiments, the connection structure further includes a plurality of third connection structures located on the second region, the third connection structures are arranged on the main path, and the third connection structures are not in contact with the substrate.

[0022] In some embodiments, the first connection structure and the second connection structure simultaneously have a first connection layer, a second connection layer, and a third connection layer, and the third connection structure has the first connection layer or the first connection layer and the second connection layer.

[0023] According to a third aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising:

[0024] Providing a chip unit, the chip unit comprising a first area and a second area located outside the first area;

[0025] forming a plurality of connection structures on the chip unit, the connection structures including a plurality of first connection structures located on the first region and a plurality of second connection structures located on the second region, wherein in a first direction, a spacing between adjacent first connection structures is controlled to be smaller than a spacing between adjacent second connection structures, and the first direction is parallel to the plane of the chip unit;

[0026] A main path is formed on the second area, and a distance between two second connection structures arranged opposite to each other on both sides of the main path is controlled to be greater than a distance between two adjacent second connection structures at other positions.

[0027] In some embodiments, it further includes:

[0028] A third connection structure is formed on the main path of the second region, and a top surface of the third connection structure is lower than a top surface of the second connection structure.

[0029] In some embodiments, the steps of forming the first connection structure, the second connection structure, and the third connection structure include:

[0030] forming a first connection layer on the chip unit, wherein the first connection layer is formed in the first region and the second region at the same time;

[0031] forming a mask layer on the chip unit, wherein the mask layer covers the main path and exposes the first connection layer in the first area and the first connection layer in other second areas outside the main path;

[0032] forming a second connection layer and a third connection layer on the exposed first connection layer to form the first connection structure and the second connection structure respectively;

[0033] The mask layer is removed to expose the first connection layer covered by the mask layer, thereby forming the third connection structure.

[0034] In some embodiments, the steps of forming the first connection structure, the second connection structure, and the third connection structure include:

[0035] forming a first connection layer on the chip unit, wherein the first connection layer is formed in the first region and the second region at the same time;

[0036] forming a mask layer on the chip unit, wherein the mask layer exposes the first connection layer;

[0037] forming a second connection layer on the first connection layer;

[0038] A third connection layer is formed on the second connection layer, and the third connection layer is not formed on the second connection layer on the main path, so as to simultaneously form the first connection structure, the second connection structure, and the third connection structure.

[0039] In the embodiment of the present disclosure, a main path is formed on the second area, and the spacing between two second connecting structures arranged opposite to each other on both sides of the main path is greater than the spacing between two adjacent second connecting structures at other positions. In this way, the bottom filling material can flow into the connection structures through the main path during filling. Because the width of the main path is large and there is no second connecting structure to hinder it, the flow resistance on the main path is reduced, thereby reducing the total flow resistance and improving the filling effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0042] Figure 2 Another example 1 of the structural schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure;

[0043] Figure 3 Another example 2 of the structural schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure;

[0044] Figure 4 for Figure 3 A schematic cross-sectional view of a semiconductor structure shown;

[0045] Figure 5 Another example three of the structural schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure;

[0046] Figure 6 Another example 4 of the structural schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure;

[0047] Figure 7 A schematic structural diagram of a semiconductor package structure provided by an embodiment of the present disclosure;

[0048] Figure 8 A flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0049] Figures 9a to 11c A schematic diagram of the structure of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure.

[0050] Description of reference numerals:

[0051] 10. Chip unit; 11. First region; 12. Second region; 101. Protective layer;

[0052] 20. Connection structure; 21. First connection structure; 22. Second connection structure; 23. Third connection structure; 201. First connection layer; 202. Second connection layer; 203. Third connection layer;

[0053] 30. Main path; 31. First sub-path; 32. Second sub-path;

[0054] 40. substrate; 41. substrate connection bump;

[0055] 50. Bottom filling material;

[0056] 60. Mask layer. DETAILED DESCRIPTION

[0057] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0058] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0059] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0060] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0061] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0062] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0064] Based on this, the present disclosure provides a semiconductor structure. Figure 1 A schematic structural diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0065] See also Figure 1 , semiconductor structures, including:

[0066] The chip unit 10 includes a first region 11 and a second region 12 located outside the first region 11;

[0067] a plurality of connection structures 20, the connection structures 20 including a plurality of first connection structures 21 located on the first region 11 and a plurality of second connection structures 22 located on the second region 12, wherein, in a first direction, a spacing between adjacent first connection structures 21 is smaller than a spacing between adjacent second connection structures 22, and the first direction is parallel to the plane of the chip unit 10;

[0068] The main path 30 is located on the second area 12 , and the distance between two second connection structures 22 oppositely arranged on both sides of the main path 30 is greater than the distance between two adjacent second connection structures 22 at other positions.

[0069] In the embodiment of the present disclosure, a main path is formed on the second area, and the spacing between two second connecting structures arranged opposite to each other on both sides of the main path is greater than the spacing between two adjacent second connecting structures at other positions. In this way, the subsequent bottom filling material can flow into the connection structures through the main path during filling. Because the width of the main path is large and there is no second connecting structure to hinder it, the flow resistance on the main path is reduced, thereby reducing the total flow resistance and improving the filling effect.

[0070] In one embodiment, if Figure 1 As shown, the first region 11 extends along a first direction, and the second region 12 is distributed on both sides of the first region 11 along a second direction, wherein the second direction is parallel to the plane of the chip unit 10, and the first direction and the second direction intersect.

[0071] Specifically, in some embodiments, Figure 1 As shown, the first direction and the second direction are perpendicular to each other.

[0072] In some other embodiments, the angle between the first direction and the second direction is greater than 0° and less than 90°.

[0073] like Figure 1 As shown, the first region 11 is located in the middle of the chip unit 10. The first connection structure on the first region includes a conductive contact bump that serves a functional purpose. Therefore, when a device structure is subsequently formed on the connection structure, because the first region is located in the middle of the chip unit, the first connection structure can provide a more comprehensive and uniform conductive function for the entire chip unit.

[0074] In one embodiment, if Figure 1 As shown, a plurality of first connection structures 21 are formed on the first region 11 , and a plurality of second connection structures 22 are formed on the second region 12 . In the first direction, the spacing between adjacent first connection structures 21 is smaller than the spacing between adjacent second connection structures 22 .

[0075] When the spacing between the first connection structures is smaller than the spacing between the second connection structures, it means that the spacing between the second connection structures is wider. In this way, the flow resistance during subsequent bottom filling material filling can be reduced, ensuring that the bottom filling material can be more smoothly filled between the second connection structures and flow to the first connection structure.

[0076] In one embodiment, the number of the first connection structures 21 is less than the number of the second connection structures 22 .

[0077] When the number of first connection structures is smaller than the number of second connection structures, a main path can be formed in the second region, reducing the flow resistance of the underfill material flowing into the first region, thereby reducing the overall flow resistance and improving the filling effect. However, if the number of first connection structures is greater than the number of second connection structures, the area of ​​the first region is too large. In this case, even if a main path is formed in the second region, the flow resistance in the first region is still too high, resulting in an excessively high overall flow resistance and affecting the filling effect.

[0078] In one embodiment, the first connection structure 21 is a conductive contact bump, and the second connection structure 22 is a dummy bump.

[0079] The first connection structure is a conductive contact bump, which can transmit signals and power. The second connection structure is a virtual bump, which plays a role in support and heat transfer. In this embodiment, since only a small number of local virtual bumps are removed and the arrangement of the conductive contact bumps is not changed, the overall performance of the semiconductor structure is not affected.

[0080] In some other embodiments, the second connection structure may also include a conductive contact bump.

[0081] In one embodiment, if Figure 3 As shown, the connection structure 20 further includes a plurality of third connection structures 23 located on the second region 12 . The third connection structures 23 are arranged on the main path 30 , and top surfaces of the third connection structures 23 are lower than top surfaces of the second connection structures 22 .

[0082] Because the top surface of the third connection structure is lower than the top surface of the second connection structure, the flow resistance encountered by the bottom filling material at the third connection structure during filling is smaller than the flow resistance encountered at the second connection structure.

[0083] like Figure 4 As shown, the first connection structure 21 and the second connection structure 22 simultaneously include the first connection layer 201 , the second connection layer 202 and the third connection layer 203 , and the third connection structure 23 includes the first connection layer 201 or the first connection layer 201 and the second connection layer 202 .

[0084] Specifically, a first connection layer 201, a second connection layer 202, and a third connection layer 203 are sequentially formed on the chip unit 10. The first connection layer is a pad; the second connection layer is a metal layer, comprising a first sub-metal layer located below and a second sub-metal layer located above the first sub-metal layer. The first sub-metal layer is made of titanium or copper, and the second sub-metal layer is made of copper. The third connection layer is a solder ball. A protective layer 101 is formed on the surface of the chip unit 10 not covered by the first connection layer 201, as well as on the sidewalls and part of the surface of the first connection layer 201. The protective layer prevents damage to the chip unit and the first connection structure during subsequent processing.

[0085] In one embodiment, if Figure 1 As shown, the main path 30 is located on the second area 12, and the distance between two second connection structures 22 arranged opposite to each other on both sides of the main path 30 is greater than the distance between two adjacent second connection structures 22 at other positions.

[0086] Because the first connection structure on the first area is a functional conductive contact bump, the first connection structure cannot be removed to avoid affecting the performance of the semiconductor structure. Therefore, the main path is set on the second area that does not affect the performance of the device. In this way, the flow resistance during the filling of the bottom filling material can be reduced while ensuring the performance of the device.

[0087] like Figure 1 As shown, the spacing between two second connection structures 22 opposite each other on either side of the main path 30 is h1, while the spacing between two adjacent second connection structures 22 at other locations is h2, where h1 is greater than h2. The larger spacing between the two second connection structures opposite each other on either side of the main path reduces the flow resistance of the underfill material through the main path during filling, improving the filling effect.

[0088] In one embodiment, the distance between two second connection structures 22 disposed opposite to each other on both sides of the main path 30 is 1.5 to 2 times the distance between two adjacent second connection structures 22 at other positions.

[0089] The width of the main path is 1.5 to 2 times the width between adjacent second connection structures. In this way, when the main path serves as the path for the flow filling of the bottom filling material, it will not be too narrow to reduce the flow resistance during the flow filling, nor will it be too wide to remove too many second connection structures, affecting the overall structural strength and heat transfer performance.

[0090] In one embodiment, if Figure 2 As shown, the chip unit 10 includes a plurality of first regions 11 spaced apart from each other, and each first region 11 is connected to at least one main path 30.

[0091] A plurality of main paths 30 are formed on the second region 12 between two adjacent first regions 11 , wherein each first region 11 is connected to at least one main path 30 located on the second region 12 between two adjacent first regions 11 .

[0092] There are multiple first regions forming the first connection structure, and each first region has at least one main path connected to it. This reduces flow resistance during underfilling in each first region, improving the filling effect. Furthermore, when multiple first regions are included, the performance of the entire device structure can be more comprehensively guaranteed. Furthermore, because underfilling is more difficult in the second region between two adjacent first regions, forming at least one main path connecting to each first region in the second region between the two first regions can reduce flow resistance during filling of the second region between the two first regions, improving the filling effect.

[0093] Specifically, if Figure 2 As shown in the figure, the area circled by the thick dashed line A is the main path connecting to the upper first area, and the area circled by the thin dashed line B is the main path connecting to the lower first area. In the figure, the main path connecting to the upper first area and the main path connecting to the lower first area partially overlap. In other embodiments, a main path connecting to the upper first area may be formed on one side, and a main path connecting to the lower first area may be formed on the other side, and the two main paths may not overlap.

[0094] In one embodiment, if Figure 5 As shown, the main path 30 includes a first sub-path 31 , which extends from the edge of the chip unit 10 toward the first region 11 . The angle between the first sub-path 31 and the edge of the chip unit 10 in contact therewith ranges from 30° to 60°.

[0095] Specifically, see Figure 5 The included angle between the first sub-path 31 and the side of the chip unit 10 in contact therewith is a, and the range of angle a is 30° to 60°.

[0096] The angle between the first sub-path and the edge of the chip unit is in the range of 30° to 60°. In this way, the length of the first sub-path can be kept moderate, so that the flow resistance during filling can be reduced without affecting the overall structural strength and heat transfer performance. Because if the length of the first sub-path is too long and more second connecting structures are removed, the overall structural strength and heat transfer performance will be affected. If the length of the first sub-path is too short, the reduction of flow resistance will be affected.

[0097] In one embodiment, if Figure 5 and Figure 6As shown, the main path 30 further includes a second sub-path 32 , and the second sub-path 32 is connected to at least one first sub-path 31 .

[0098] By setting up a second sub-path and connecting the second sub-path with the first sub-path, when filling the bottom filling material, it can flow through the first sub-path to the second sub-path and then flow between the various connection structures, thereby further reducing the flow resistance and improving the filling effect.

[0099] The first sub-path is a path for injecting the bottom filling material into the chip unit. After the bottom filling material is injected into the first sub-path, it flows to the second sub-path to wrap each connection structure.

[0100] exist Figure 5 In the embodiment shown, there are two second sub-paths 32, and each second sub-path 32 extends along the first direction and is connected to the first sub-paths 31 on both sides.

[0101] exist Figure 6 In the illustrated embodiment, there are four second sub-paths 32, two of which extend along the first direction and two extend along the second direction, and each second sub-path 32 extending along the first direction communicates with a second sub-path 32 extending along the second direction. The first sub-path 31 communicates with the second sub-path 32 extending along the second direction via the second sub-path 32 extending along the first direction.

[0102] The present disclosure also provides a semiconductor packaging structure. Figure 7 A schematic structural diagram of a semiconductor packaging structure provided in an embodiment of the present disclosure.

[0103] like Figure 1 and Figure 7 As shown, the semiconductor package structure includes:

[0104] substrate 40;

[0105] A chip unit 10 is mounted on a substrate 40 via a connecting structure 20. The chip unit 10 has a first region 11 and a second region 12 located outside the first region 11. The connecting structure 20 includes a plurality of first connecting structures 21 and a plurality of second connecting structures 22. In a first direction, the spacing between adjacent first connecting structures 21 is smaller than the spacing between adjacent second connecting structures 22. The first direction is parallel to the plane of the chip unit 10.

[0106] The main path 30 is located on the second area 12, and the distance between two second connection structures 22 arranged opposite to each other on both sides of the main path 30 is greater than the distance between two adjacent second connection structures 22 at other positions;

[0107] The bottom filling material 50 is filled between the first connection structure 21 and the second connection structure 22 along the main path 30 to encapsulate the chip unit 10 and the substrate 40 .

[0108] In the embodiment of the present disclosure, a main path is formed on the second area, and the spacing between two second connecting structures arranged opposite to each other on both sides of the main path is greater than the spacing between two adjacent second connecting structures at other positions. In this way, the bottom filling material can flow into the connection structures through the main path during filling. Because the width of the main path is large and there is no second connecting structure to hinder it, the flow resistance on the main path is reduced, thereby reducing the total flow resistance and improving the filling effect.

[0109] In one embodiment, the substrate 40 may be a printed circuit board (PCB) or a redistribution substrate.

[0110] The substrate 40 may include a substrate backing (not shown in the figure) and an upper substrate insulating dielectric layer (not shown in the figure) and a lower substrate insulating dielectric layer (not shown in the figure) respectively disposed on the upper surface and the lower surface of the substrate backing.

[0111] The substrate can be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc. It can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., and can also be other epitaxial structures, such as SGOI (Silicon Germanium on Insulator), etc.

[0112] The insulating dielectric layer on the substrate and the insulating dielectric layer under the substrate may be solder resist layers. For example, the material of the insulating dielectric layer on the substrate and the insulating dielectric layer under the substrate may be green paint.

[0113] The substrate 40 also includes a substrate connection bump 41, which can electrically connect the semiconductor package structure to an external device, and can receive at least one of a control signal, a power signal, and a ground signal for operating the chip unit from the external device, or can receive a data signal to be stored in the chip unit from the external device, and can also provide data in the chip unit to an external device.

[0114] In one embodiment, see Figure 3 and Figure 7 The connection structure 20 further includes a plurality of third connection structures 23 located on the second region 12 . The third connection structures 23 are arranged on the main path 30 , and the third connection structures 23 are not in contact with and connected to the substrate 40 .

[0115] The third connection structure is not in contact with the substrate, which means that the height of the third connection structure is smaller than that of the second connection structure. Thus, when the bottom filling material is being filled, the flow resistance encountered at the third connection structure is smaller than the flow resistance encountered at the second connection structure.

[0116] like Figure 4 and Figure 7 As shown, the first connection structure 21 and the second connection structure 22 simultaneously include the first connection layer 201 , the second connection layer 202 and the third connection layer 203 , and the third connection structure 23 includes the first connection layer 201 or the first connection layer 201 and the second connection layer 202 .

[0117] exist Figure 7 In the illustrated embodiment, the third connection structure 23 only includes the first connection layer 201 . In other embodiments, the third connection structure may further include a second connection layer.

[0118] In some embodiments, as Figure 7 As shown, the chip unit 10 is a single chip; in some other embodiments, the chip unit may also be a stack formed by stacking multiple chips.

[0119] The bottom filling material 50 flows from the main path 30 and then fills between each connection structure 20 to encapsulate the chip unit 10 and the substrate 40 .

[0120] It should be explained that the chip unit, connection structure and main path in the semiconductor packaging structure can refer to the chip unit, connection structure and main path in the semiconductor structure in any of the above embodiments, and will not be repeated here.

[0121] The present disclosure also provides a method for preparing a semiconductor structure. Figure 8 As shown in the figure, the method for preparing the semiconductor structure includes the following steps:

[0122] Step 801: providing a chip unit, the chip unit comprising a first region and a second region located outside the first region;

[0123] Step 802: forming a plurality of connection structures on the chip unit, the connection structures including a plurality of first connection structures located on a first region and a plurality of second connection structures located on a second region, wherein, in a first direction, a spacing between adjacent first connection structures is controlled to be smaller than a spacing between adjacent second connection structures, and the first direction is parallel to a plane of the chip unit;

[0124] Step 803: forming a main path on the second area, and controlling the distance between two second connection structures disposed opposite to each other on both sides of the main path to be greater than the distance between two adjacent second connection structures at other positions.

[0125] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure will be further described in detail below with reference to specific embodiments.

[0126] Figures 9a to 11c A schematic diagram of the structure of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure.

[0127] First, see Figure 9a , execute step 801 to provide a chip unit 10 , where the chip unit 10 includes a first area 11 and a second area 12 located outside the first area 11 .

[0128] In one embodiment, the first region 11 extends along a first direction, and the second region 12 is distributed on both sides of the first region 11 along a second direction, wherein the second direction is parallel to the plane of the chip unit 10 , and the first direction and the second direction intersect.

[0129] Specifically, in some embodiments, Figure 9a As shown, the first direction and the second direction are perpendicular to each other.

[0130] In some other embodiments, the angle between the first direction and the second direction is greater than 0° and less than 90°.

[0131] like Figure 9a As shown, the first region 11 is located in the middle of the chip unit 10. The first connection structure subsequently formed on the first region includes conductive contact bumps that serve a functional purpose. Therefore, when a device structure is subsequently formed on the connection structure, because the first region is located in the middle of the chip unit, the first connection structure can provide a more comprehensive and uniform conductive function for the entire chip unit.

[0132] Next, see Figure 9b , execute steps 802 and 803 to form a plurality of connection structures 20 on the chip unit 10, the connection structures 20 including a plurality of first connection structures 21 located on the first area 11 and a plurality of second connection structures 22 located on the second area 12, wherein, in a first direction, the spacing between adjacent first connection structures 21 is controlled to be smaller than the spacing between adjacent second connection structures 22, and the first direction is parallel to the plane of the chip unit 10; a main path 30 is formed on the second area 12, and the spacing between two second connection structures 22 oppositely arranged on both sides of the main path 30 is controlled to be larger than the spacing between two adjacent second connection structures 22 at other positions.

[0133] When the spacing between the first connection structures is smaller than the spacing between the second connection structures, it means that the spacing between the second connection structures is wider. In this way, the flow resistance during subsequent bottom filling material filling can be reduced, ensuring that the bottom filling material can be more smoothly filled between the second connection structures and flow to the first connection structure.

[0134] In one embodiment, the number of the first connection structures 21 is less than the number of the second connection structures 22 .

[0135] When the number of first connection structures is smaller than the number of second connection structures, a main path can be formed in the second region, reducing the flow resistance of the underfill material flowing into the first region, thereby reducing the overall flow resistance and improving the filling effect. However, if the number of first connection structures is greater than the number of second connection structures, the area of ​​the first region is too large. In this case, even if a main path is formed in the second region, the flow resistance in the first region is still too high, resulting in an excessively high overall flow resistance and affecting the filling effect.

[0136] In one embodiment, the first connection structure 21 is a conductive contact bump, and the second connection structure 22 is a dummy bump.

[0137] The first connection structure is a conductive contact bump, which can transmit signals and power. The second connection structure is a virtual bump, which plays a role in support and heat transfer. In this embodiment, since only a small number of local virtual bumps are removed and the arrangement of the conductive contact bumps is not changed, the overall performance of the semiconductor structure is not affected.

[0138] In some other embodiments, the second connection structure may also include a conductive contact bump.

[0139] In one embodiment, see Figure 3 The method further includes forming a third connection structure 23 on the main path 30 of the second region 12 , wherein a top surface of the third connection structure 23 is lower than a top surface of the second connection structure 22 .

[0140] Because the top surface of the third connection structure is lower than the top surface of the second connection structure, the flow resistance encountered by the bottom filling material at the third connection structure during filling is smaller than the flow resistance encountered at the second connection structure.

[0141] Specifically, Figures 10a to 11c The preparation process of the first connection structure, the second connection structure and the third connection structure is described in detail, wherein: Figures 10a to 10c The preparation process provided in one embodiment is: Figures 11a to 11c A preparation process is provided for another embodiment.

[0142] See first Figures 10a to 10c, a preparation process provided in one of the embodiments is described in detail.

[0143] Specifically, the steps of forming the first connection structure 21, the second connection structure 22, and the third connection structure 23 include:

[0144] A first connection layer 201 is formed on the chip unit 10 , and the first connection layer 201 is formed in the first region 11 and the second region 12 at the same time;

[0145] A mask layer 60 is formed on the chip unit 10 , the mask layer 60 covers the main path 30 and exposes the first connection layer 201 in the first area 11 and the first connection layer 201 in the second area 12 outside the main path 30 ;

[0146] forming a second connection layer 202 and a third connection layer 203 on the exposed first connection layer 201 to form a first connection structure 21 and a second connection structure 22 respectively;

[0147] The mask layer 60 is removed to expose the first connection layer 201 covered by the mask layer 60 , thereby forming the third connection structure 23 .

[0148] See also Figure 10a The method further includes: after forming the first connection layer 201, forming a protective layer 101 on the surface of the chip unit 10 not covered by the first connection layer 201 and on the sidewalls and a portion of the surface of the first connection layer 201. The protective layer can prevent the chip unit and the first connection structure from being damaged in subsequent processes.

[0149] Next, see Figures 11a to 11c , the preparation process provided in another embodiment is described in detail.

[0150] Specifically, the steps of forming the first connection structure 21, the second connection structure 22, and the third connection structure 23 include:

[0151] A first connection layer 201 is formed on the chip unit 10 , and the first connection layer 201 is formed in the first region 11 and the second region 12 at the same time;

[0152] A mask layer 60 is formed on the chip unit 10 , wherein the mask layer 60 exposes the first connection layer 201 ;

[0153] forming a second connection layer 202 on the first connection layer 201;

[0154] The third connection layer 203 is formed on the second connection layer 202 , and the third connection layer 203 is not formed on the second connection layer 202 on the main path 30 , so as to simultaneously form the first connection structure 21 , the second connection structure 22 , and the third connection structure 23 .

[0155] Continue to see Figure 9b The distance between the two second connection structures 22 arranged opposite to each other on both sides of the main path 30 is greater than the distance between two adjacent second connection structures 22 at other positions.

[0156] Because the first connection structure on the first area is a functional conductive contact bump, the first connection structure cannot be removed to avoid affecting the performance of the semiconductor structure. Therefore, the main path is set on the second area that does not affect the performance of the device. In this way, the flow resistance during the filling of the bottom filling material can be reduced while ensuring the performance of the device.

[0157] like Figure 9b As shown, the spacing between two second connection structures 22 opposite each other on either side of the main path 30 is h1, while the spacing between two adjacent second connection structures 22 at other locations is h2, where h1 is greater than h2. The larger spacing between the two second connection structures opposite each other on either side of the main path reduces the flow resistance of the underfill material through the main path during filling, improving the filling effect.

[0158] In one embodiment, the distance between two second connection structures 22 disposed opposite to each other on both sides of the main path 30 is 1.5 to 2 times the distance between two adjacent second connection structures 22 at other positions.

[0159] The width of the main path is 1.5 to 2 times the width between adjacent second connection structures. In this way, when the main path serves as the path for the flow filling of the bottom filling material, it will not be too narrow to reduce the flow resistance during the flow filling, nor will it be too wide to remove too many second connection structures, affecting the overall structural strength and heat transfer performance.

[0160] In one embodiment, if Figure 2 As shown, the chip unit 10 includes a plurality of first regions 11 spaced apart from each other, and each first region 11 is connected to at least one main path 30.

[0161] A plurality of main paths 30 are formed on the second region 12 between two adjacent first regions 11 , wherein each first region 11 is connected to at least one main path 30 located on the second region 12 between two adjacent first regions 11 .

[0162] There are multiple first regions forming the first connection structure, and each first region has at least one main path connected to it. This reduces flow resistance during underfilling in each first region, improving the filling effect. Furthermore, when multiple first regions are included, the performance of the entire device structure can be more comprehensively guaranteed. Furthermore, because underfilling is more difficult in the second region between two adjacent first regions, forming at least one main path connecting to each first region in the second region between the two first regions can reduce flow resistance during filling of the second region between the two first regions, improving the filling effect.

[0163] Specifically, if Figure 2 As shown in the figure, the area circled by the thick dashed line A is the main path connecting to the upper first area, and the area circled by the thin dashed line B is the main path connecting to the lower first area. In the figure, the main path connecting to the upper first area and the main path connecting to the lower first area partially overlap. In other embodiments, a main path connecting to the upper first area may be formed on one side, and a main path connecting to the lower first area may be formed on the other side, and the two main paths may not overlap.

[0164] In one embodiment, if Figure 5 As shown, the main path 30 includes a first sub-path 31 , which extends from the edge of the chip unit 10 toward the first region 11 . The angle between the first sub-path 31 and the edge of the chip unit 10 in contact therewith ranges from 30° to 60°.

[0165] Specifically, see Figure 5 The included angle between the first sub-path 31 and the side of the chip unit 10 in contact therewith is a, and the range of angle a is 30° to 60°.

[0166] The angle between the first sub-path and the edge of the chip unit is in the range of 30° to 60°. In this way, the length of the first sub-path can be kept moderate, so that the flow resistance during filling can be reduced without affecting the overall structural strength and heat transfer performance. Because if the length of the first sub-path is too long and more second connecting structures are removed, the overall structural strength and heat transfer performance will be affected. If the length of the first sub-path is too short, the reduction of flow resistance will be affected.

[0167] In one embodiment, if Figure 5 and Figure 6 As shown, the main path 30 further includes a second sub-path 32 , and the second sub-path 32 is connected to at least one first sub-path 31 .

[0168] By setting up a second sub-path and connecting the second sub-path with the first sub-path, when filling the bottom filling material, it can flow through the first sub-path to the second sub-path and then flow between the various connection structures, thereby further reducing the flow resistance and improving the filling effect.

[0169] The first sub-path is a path for injecting the bottom filling material into the chip unit. After the bottom filling material is injected into the first sub-path, it flows to the second sub-path to wrap each connection structure.

[0170] exist Figure 5 In the embodiment shown, there are two second sub-paths 32, and each second sub-path 32 extends along the first direction and is connected to the first sub-paths 31 on both sides.

[0171] exist Figure 6 In the illustrated embodiment, there are four second sub-paths 32, two of which extend along the first direction and two extend along the second direction, and each second sub-path 32 extending along the first direction communicates with a second sub-path 32 extending along the second direction. The first sub-path 31 communicates with the second sub-path 32 extending along the second direction via the second sub-path 32 extending along the first direction.

[0172] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: A chip unit, the chip unit comprising a first area and a second area located outside the first area; a plurality of connection structures, the connection structures comprising a plurality of first connection structures located on the first region and a plurality of second connection structures located on the second region, wherein, in a first direction, a spacing between adjacent first connection structures is smaller than a spacing between adjacent second connection structures, and the first direction is parallel to a plane of the chip unit; A main path is located on the second area, and a distance between two second connecting structures arranged opposite to each other on both sides of the main path is greater than a distance between two adjacent second connecting structures at other positions; The connection structure further includes a plurality of third connection structures located on the second area, the third connection structures are arranged on the main path, and the top surfaces of the third connection structures are lower than the top surfaces of the second connection structures.

2. The semiconductor structure according to claim 1, wherein: The first region extends along the first direction, and the second region is distributed on both sides of the first region along a second direction, wherein the second direction is parallel to the plane of the chip unit, and the first direction and the second direction intersect.

3. The semiconductor structure according to claim 1, wherein: The chip unit includes a plurality of first regions spaced apart from each other, each of the first regions being connected to at least one main path. A plurality of main paths are formed on the second area between two adjacent first areas, wherein each first area is connected to at least one main path located on the second area between two adjacent first areas.

4. The semiconductor structure according to claim 1, wherein: The main path includes a first sub-path, which extends from an edge of the chip unit toward the first region. An angle between the first sub-path and a side of the chip unit in contact with the first sub-path is in a range of 30° to 60°.

5. The semiconductor structure according to claim 4, wherein: The main path further includes a second sub-path, and the second sub-path is connected to at least one of the first sub-paths. The semiconductor structure according to claim 1 , wherein: The first connection structure and the second connection structure simultaneously include a first connection layer, a second connection layer, and a third connection layer, and the third connection structure includes a first connection layer or a first connection layer and a second connection layer.

7. The semiconductor structure according to claim 1, wherein: The first connection structure is a conductive contact bump, and the second connection structure is a dummy bump.

8. A semiconductor packaging structure, characterized in that: include: substrate; a chip unit, the chip unit being mounted on the substrate via a connecting structure; The chip unit has a first area and a second area located outside the first area, the connection structure includes a plurality of first connection structures and a plurality of second connection structures, and in a first direction, a spacing between adjacent first connection structures is smaller than a spacing between adjacent second connection structures, and the first direction is parallel to a plane of the chip unit; A main path is located on the second area, and a distance between two second connecting structures arranged opposite to each other on both sides of the main path is greater than a distance between two adjacent second connecting structures at other positions; An underfill material is filled between the first connecting structure and the second connecting structure along the main path to plastic-encapsulate the chip unit and the substrate; The connection structure further includes a plurality of third connection structures located on the second region, the third connection structures are arranged on the main path, and the third connection structures are not in contact with the substrate.

9. The structure according to claim 8, characterized in that The first connection structure and the second connection structure simultaneously include a first connection layer, a second connection layer, and a third connection layer, and the third connection structure includes a first connection layer or a first connection layer and a second connection layer.

10. A method for preparing a semiconductor structure, characterized in that: include: Providing a chip unit, the chip unit comprising a first area and a second area located outside the first area; forming a plurality of connection structures on the chip unit, the connection structures including a plurality of first connection structures located on the first region and a plurality of second connection structures located on the second region, wherein in a first direction, a spacing between adjacent first connection structures is controlled to be smaller than a spacing between adjacent second connection structures, and the first direction is parallel to the plane of the chip unit; forming a main path on the second area, and controlling the distance between two second connecting structures disposed opposite to each other on both sides of the main path to be greater than the distance between two adjacent second connecting structures at other positions; A third connection structure is formed on the main path of the second region, and a top surface of the third connection structure is lower than a top surface of the second connection structure.

11. The method according to claim 10, characterized in that The steps of forming the first connection structure, the second connection structure and the third connection structure include: forming a first connection layer on the chip unit, wherein the first connection layer is formed in the first region and the second region at the same time; forming a mask layer on the chip unit, wherein the mask layer covers the main path and exposes the first connection layer in the first area and the first connection layer in other second areas outside the main path; forming a second connection layer and a third connection layer on the exposed first connection layer to form the first connection structure and the second connection structure respectively; The mask layer is removed to expose the first connection layer covered by the mask layer, thereby forming the third connection structure.

12. The method according to claim 10, characterized in that The steps of forming the first connection structure, the second connection structure and the third connection structure include: forming a first connection layer on the chip unit, wherein the first connection layer is formed in the first region and the second region at the same time; forming a mask layer on the chip unit, wherein the mask layer exposes the first connection layer; forming a second connection layer on the first connection layer; A third connection layer is formed on the second connection layer, and the third connection layer is not formed on the second connection layer on the main path, so as to simultaneously form the first connection structure, the second connection structure, and the third connection structure.

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