Adaptive temperature compensated charge pump phase-locked loop circuit, module based on mtj

Abstract

This invention relates to the field of charge pump phase-locked loop (CPPLL) design technology, specifically to an adaptive temperature-compensated charge pump PLL circuit and module based on a magnetic tunnel junction (MTJ). The invention provides an MTJ-based adaptive temperature-compensated charge pump PLL circuit, comprising: a frequency and phase discriminator, a charge pump section, a low-pass filter section, a voltage-controlled oscillator (VCO) section, and a frequency divider section. Based on the traditional charge pump PLL, this invention connects a magnetic tunnel junction (MTJ) in series with the upper and lower charge / discharge circuits of the charge pump section, and also connects a MTJ in series with the output terminal of the dual-input, dual-output VCO section. Utilizing the MTJ for temperature compensation effectively reduces the current mismatch of the charge pump and significantly improves the frequency stability of the VCO, ensuring and enhancing the performance of the CPPLL. This invention solves the problem of CPPLLs being easily affected by on-chip system temperature changes.

Description

Technical Field

[0001] This invention relates to the field of charge pump phase-locked loop (PLL) design technology, and more specifically, to: 1. an adaptive temperature-compensated charge pump PLL circuit based on MTJ; 2. an adaptive temperature-compensated charge pump PLL module based on MTJ. Background Technology

[0002] A phase-locked loop (PLL) circuit is a closed-loop automatic control system capable of tracking the phase of an input signal. The charge-pump PLL (CPPLL) is a widely used type of PLL circuit.

[0003] Charge pumps are typically used in conjunction with phase-frequency detectors (PFDs), low-pass filters (LPFs), and voltage-controlled oscillators (VCOs). In a CPPLL, the charge pump is an electronic switch that distributes charge to the LPF under the control of the PFD. The advantage of charge pumps is their compatibility with any PFD that outputs a two-level waveform, with phase error information included in the waveform's duty cycle. This results in a significant performance improvement for the CPPLL, including reduced output phase-locking efficiency, jitter, and noise. While the CPPLL uses a passive low-pass filter, it performs the functions of an active filter, effectively reducing noise and significantly lowering manufacturing costs.

[0004] However, commercial and high-energy physics applications of CPPLLs require continuous operation over a wide temperature range, ideally without additional calibration. But on-chip systems are highly sensitive to temperature fluctuations, which can lead to current mismatch in the charge pump and VCO oscillation frequency drift: see [link to relevant documentation]. Figure 1 The mismatch rate of the charge pump increases as the temperature decreases; see also Figure 2 The oscillation frequency of the VCO decreases as temperature increases. Both of these issues affect the VCO and ultimately lead to phase loss within the phase-locked loop. This is because the primary function of the charge pump is to convert output pulses—converting the signal from the PFD into a corresponding current signal; this current signal is then converted into a voltage signal after passing through the LPF, which adjusts the output frequency; any fluctuation in this voltage signal can interfere with the VCO output, resulting in jitter and reference spurious signals within the phase-locked loop.

[0005] In conclusion, addressing the temperature issue of the CPPLL on-chip system is extremely important, as it helps to ensure and improve the performance of the CPPLL. Summary of the Invention

[0006] Therefore, it is necessary to address the issue that CPPLLs are susceptible to changes in on-chip system temperature by providing an adaptive temperature-compensated charge pump phase-locked loop circuit and module based on MTJ.

[0007] This invention is achieved using the following technical solution:

[0008] In a first aspect, the present invention provides an adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ, comprising: a frequency and phase discrimination section, a charge pump section, a low-pass filter section, a voltage-controlled oscillator section, and a frequency divider section.

[0009] The frequency and phase detector compares the phase of the reference signal FREF and the divided signal FVCODIV, and converts the phase difference into signals UP and DOWN. The charge pump charges and discharges the low-pass filter based on the signals UP and DOWN. The low-pass filter adjusts the control voltage VTCAL of the voltage-controlled oscillator (VCO). The VCO generates an oscillation signal FVCO under the control voltage VTCAL. The frequency divider divides the oscillation signal FVCO and outputs the divided signal FVCODIV.

[0010] In this section, the upper charge-discharge circuit of the charge pump unit has a magnetic tunnel junction MTJ1 connected in series, and the lower charge-discharge circuit has a magnetic tunnel junction MTJ2 connected in series, both used for temperature compensation. The charging and discharging currents of the upper and lower charge-discharge circuits of the charge pump unit are the same.

[0011] The voltage-controlled oscillator section includes: a current mirror section and three cascaded differential amplifiers S1 to S3. The current mirror section serves as the differential amplifier S1... n The current source; n∈[1,3]. Differential amplifier S n It has an input terminal VIN n1 Input terminal VIN n2 OUT output terminal n1 OUT output terminal n2 Output terminal OUT n1 A magnetic tunnel junction MTJ connected in series n1 OUT output terminal n2 A magnetic tunnel junction MTJ connected in series n2 Both are used for temperature compensation.

[0012] The implementation of this MTJ-based adaptive temperature-compensated charge pump phase-locked loop circuit is based on the method or process of an embodiment of this disclosure.

[0013] In a second aspect, the present invention discloses an adaptive temperature-compensated charge pump phase-locked loop module based on MTJ, which adopts the layout of the adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ disclosed in the first aspect.

[0014] The implementation of this MTJ-based adaptive temperature-compensated charge pump phase-locked loop module is based on the method or process of an embodiment of this disclosure.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] 1. Based on the traditional charge pump phase-locked loop, this invention connects a magnetic tunnel junction (MTJ) in series with the upper and lower charge / discharge circuits of the charge pump section, and also connects a MTJ in series with the output terminal of the voltage-controlled oscillator (VCO) section with dual input and dual output. By using the MTJ for temperature compensation, the current mismatch of the charge pump is effectively reduced, and the frequency stability of the VCO is significantly improved, thus ensuring and improving the performance of the CPPLL.

[0017] 2. By adding a magnetic tunnel junction (MTJ) to the charge pump section, the present invention reduces the current mismatch to below 0.3% over a wide temperature range of -80℃ to 150℃, thereby improving the current matching stability over a wide temperature range.

[0018] 3. By adding a magnetic tunnel junction (MTJ) to the voltage-controlled oscillator, the present invention achieves a maximum frequency shift of only 8 MHz within a wide temperature range of -80℃ to 150℃, thereby improving frequency stability. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the current mismatch mentioned in the background art;

[0021] Figure 2 This is a schematic diagram of the oscillation frequency drift mentioned in the background art;

[0022] Figure 3 The overall structure diagram of an adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ provided by the present invention;

[0023] Figure 4 for Figure 3 Circuit diagram of the first frequency and phase detector in China;

[0024] Figure 5 for Figure 3 Circuit diagram of the second type of frequency and phase detector;

[0025] Figure 6 for Figure 3 Circuit diagram of the medium charge pump section and the low-pass filter section;

[0026] Figure 7 for Figure 3 Circuit diagram of the medium-voltage controlled oscillator;

[0027] Figure 8 for Figure 3 Circuit diagram of the intermediate frequency division section;

[0028] Figure 9 Simulation results provided for Embodiment 1 of the present invention Figure 1 ;

[0029] Figure 10 Simulation results provided for Embodiment 1 of the present invention Figure 2 ;

[0030] Figure 11 Simulation results provided for Embodiment 1 of the present invention Figure 3 ;

[0031] Figure 12 Simulation results provided for Embodiment 1 of the present invention Figure 4 ;

[0032] Figure 13 Simulation results provided for Embodiment 1 of the present invention Figure 5 ;

[0033] Figure 14 This is a structural diagram of the adaptive temperature-compensated charge pump phase-locked loop module based on MTJ provided in Embodiment 2 of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] Example 1

[0038] See Figure 3 , Figure 3 The overall structure diagram of an adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ provided in Embodiment 1 is shown.

[0039] It should be noted that the adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ provided in this embodiment 1 is a type II phase-locked loop.

[0040] like Figure 3 As shown, according to the functional area division, the adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ provided in this embodiment 1 includes: a frequency and phase discrimination section, a charge pump section, a low-pass filter section, a voltage-controlled oscillator section, and a frequency divider section.

[0041] The following sections will explain each part in detail:

[0042] 1. The frequency and phase detector is used to compare the phase of the reference signal FREF and the frequency division signal FVCODIV, and convert the phase difference into the signals UP and DOWN.

[0043] The frequency and phase detector can employ, for example, Figure 4 The design can also adopt, for example Figure 5 Design:

[0044] I. See Figure 4 The frequency and phase detection unit includes: two flip-flops (i.e., flip-flop D1 and flip-flop D2), one NAND gate, and one inverter (i.e., inverter INV).

[0045] Specifically, the input D of flip-flop D1 is connected to VDD, the clock signal CLK is connected to the reference signal FREF, and the output Q is connected to the signal UP. The input D of flip-flop D2 is connected to VDD, the clock signal CLK is connected to the frequency divider signal FVCODIV, and the output Q is connected to the signal DOWN. The first input of the NAND gate is connected to the signal UP, and the second input is connected to the signal DOWN. The input of the inverter INV is connected to the output of the NAND gate, and its output is connected to the reset terminals RET of both flip-flop D1 and D2.

[0046] II. See Figure 5 The frequency and phase detection unit includes: two flip-flops (i.e., flip-flop D1 and flip-flop D2), one AND gate (i.e., AND gate), and one delay unit (i.e., delay unit Delay).

[0047] Specifically, the input D of flip-flop D1 is connected to VDD, the clock signal CLK is connected to the reference signal FREF, and the output Q is connected to the signal UP. The input D of flip-flop D2 is connected to VDD, the clock signal CLK is connected to the frequency divider signal FVCODIV, and the output Q is connected to the signal DOWN. Input one of the AND gate is connected to the signal UP, and input two is connected to the signal DOWN. The input of the delay unit Delay is connected to the output of the AND gate, and its output is connected to the reset terminals RET of flip-flop D1 and D2.

[0048] 2. The charge pump section is used to charge and discharge the low-pass filter section according to the UP and DOWN signals.

[0049] The charge pump section can adopt, for example Figure 6 Design:

[0050] See Figure 6 The charge pump section includes: 5 PMOS transistors (i.e., PMOS transistor P38, PMOS transistor P11, PMOS transistor P10, PMOS transistor P9, and PMOS transistor PM5), 5 NMOS transistors (i.e., NMOS transistor N33, NMOS transistor N32, NMOS transistor N30, NMOS transistor N31, and NMOS transistor N4), and 2 magnetic tunnel junctions (i.e., magnetic tunnel junction MTJ1 and magnetic tunnel junction MTJ2).

[0051] Specifically, the gate of PMOS transistor P38 is connected to its source, and its drain is connected to VDD. The gate of NMOS transistor N33 is connected to its drain, and its source is connected to ground (GND). The gate of NMOS transistor N32 is connected to the gate of NMOS transistor N33, and its source is connected to ground (GND). The gate of PMOS transistor P11 is connected to its drain, and its source is connected to VDD. The gate of PMOS transistor P10 is connected to the gate of PMOS transistor P11, and its source is connected to VDD. The T1 terminal of magnetic tunnel junction MTJ1 is connected to the drain of PMOS transistor P10. The gate of PMOS transistor P9 is connected to signal UP, its drain is connected to the control voltage VTCAL, and its source is connected to the T2 terminal of magnetic tunnel junction MTJ1. The gate of NMOS transistor N30 is connected to signal DOWN, and its drain is connected to the control voltage VTCAL. The T1 terminal of magnetic tunnel junction MTJ2 is connected to the source of NMOS transistor N30. The gate of NMOS transistor N31 is connected to the gate of NMOS transistor N33, its drain is connected to the T2 terminal of magnetic tunnel junction MTJ2, and its source is connected to ground (GND). The gate of NMOS transistor N4 is connected to VDD, and its source is connected to the drain of NMOS transistor N32. The gate of PMOS transistor PM5 is connected to VSS, its drain is connected to the drain of NMOS transistor N4, and its source is connected to the drain of PMOS transistor P11.

[0052] Among them, PMOS transistor P10, magnetic tunnel junction MTJ1, and PMOS transistor P9 constitute the upper charge-discharge circuit: when the upper charge-discharge circuit is turned on, VDD is charged through the upper charge-discharge circuit, thereby increasing the control voltage VTCAL.

[0053] NMOS transistor N31, magnetic tunnel junction MTJ2, and NMOS transistor N30 constitute the lower charge-discharge circuit: when the lower charge-discharge circuit is turned on, the control voltage VTCAL discharges to VSS through the lower charge-discharge circuit, thereby reducing the control voltage VTCAL.

[0054] It is important to note that:

[0055] As described in the background section, conventional charge pumps exhibit current mismatch, which becomes more pronounced as the temperature decreases.

[0056] In this embodiment 1, since PMOS transistors P38, PMOS transistor P11, NMOS transistors N33 and NMOS transistors N32 form a current mirror, the charging and discharging currents of the upper and lower charging and discharging circuits are the same, thus avoiding current differences and ensuring the current matching performance of the charge pump section.

[0057] The upper charge / discharge circuit of the charge pump section has a magnetic tunnel junction (MTJ1) connected in series, and the lower charge / discharge circuit has a magnetic tunnel junction (MTJ2) connected in series, both used for temperature compensation. This utilizes the following principle: the on-resistance of the MOSFET in the charge pump section increases with increasing temperature—that is, it has a positive temperature coefficient; in other words, without the addition of the magnetic tunnel junction, the charge pump section has a large current at low temperatures; therefore, a component that can provide a resistor with a negative temperature coefficient is used to offset temperature drift and reflect the isothermal characteristics. Furthermore, the inventors discovered through research on the magnetic tunnel junction that the antiparallel resistance of the magnetic tunnel junction increases with decreasing temperature, while the parallel resistance remains essentially unchanged with temperature; that is, the high resistance of the magnetic tunnel junction has a negative temperature coefficient, which can compensate for the temperature of the charge pump section. In addition, the magnetic tunnel junction also has the advantage of low power consumption; adding it to the charge pump section can also reduce the overall power consumption.

[0058] See Figure 6 Magnetic tunnel junctions MTJ1 and MTJ2 can be considered as resistors R with negative temperature coefficients. AP PMOS transistor P10 and NMOS transistor N31 can be regarded as resistors R0 with positive temperature coefficients. By using two types of resistors with different temperature coefficients to compensate for each other's temperature, not only can current mismatch be further suppressed, but the power of the charge pump section can also be greatly reduced.

[0059] 3. The low-pass filter section is used to adjust the control voltage VTCAL of the voltage-controlled oscillator.

[0060] The low-pass filter section can also be such as Figure 6 Design:

[0061] See Figure 6 The low-pass filter section includes: two capacitors (capacitor C1 and capacitor C2) and one resistor (resistor R2).

[0062] Specifically, one end of capacitor C1 is connected to the control voltage VTCAL, and the other end is connected to ground GND. One end of resistor R2 is connected to the control voltage VTCAL. One end of capacitor C2 is connected to the other end of resistor R2, and the other end is connected to ground GND.

[0063] Specifically,

[0064] Ⅰ. When the signal UP is high and the signal DOWN is low, the upper charge-discharge circuit is turned on and the lower charge-discharge circuit is turned off, and the charge pump section charges the low-pass filter section - the charging current is I1.

[0065] II. When the signal UP is low and the signal DOWN is high, the upper charge-discharge circuit is disconnected and the lower charge-discharge circuit is turned on, and the charge pump discharges to the low-pass filter section—the discharge current is I2.

[0066] Among them, I1 and I2 have the same size.

[0067] III. When both the UP and DOWN signals are low, the upper charge / discharge circuit is disconnected, the lower charge / discharge circuit is disconnected, and the low-pass filter does not charge or discharge—at this time, the output of the charge pump is in a high-impedance state.

[0068] IV. When both signals UP and DOWN are high, the upper charge / discharge circuit is turned on, the lower charge / discharge circuit is turned on, and the low-pass filter does not charge or discharge. At this time, a path is formed from VDD to GND, and no current flows through the low-pass filter.

[0069] 4. The voltage-controlled oscillator is used to generate an oscillation signal FVCO under the action of the control voltage VTCAL.

[0070] The voltage-controlled oscillator section includes: a current mirror section and three cascaded differential amplifiers S1 to S3. The current mirror section serves as the differential amplifier S1... n The current source; n∈[1,3]. Differential amplifier S n It has two-ended input and two-ended output, meaning it has an input terminal VIN. n1 Input terminal VIN n2 OUT output terminal n1 OUT output terminal n2 .

[0071] The voltage-controlled oscillator can be adopted as follows: Figure 7 Design:

[0072] See Figure 7 The current mirror section includes: one PMOS transistor (i.e., PMOS transistor PM10) and one NMOS transistor (NMOS transistor NM10).

[0073] Specifically, the gate of the PMOS transistor PM10 is connected to its drain, and its source is connected to VDD. The gate of the NMOS transistor NM10 is connected to its drain, its source is connected to VSS, and its drain is connected to the drain of the PMOS transistor PM10.

[0074] Differential amplifier S n Includes: 3 NMOS transistors (i.e., NMOS transistor N n NMOS transistor n1 NMOS transistor n2 ), 2 magnetic tunnel junctions (i.e., magnetic tunnel junction MTJs) n1 Magnetic Tunneling Junction (MTJ) n2 ), 2 capacitors (i.e., capacitor C) n1 Capacitor C n2 ).

[0075] Specifically, NMOS transistor N n The source of the transistor is connected to VSS, and its gate is connected to the gate of the NMOS transistor NM10. The NMOS transistor N... n1 The source of the NMOS transistor is connected to the N-terminal. n The drain and gate are connected to the input terminal VIN. n1 The drain is connected to the output terminal OUT. n1 NMOS transistor N n2 The source of the NMOS transistor is connected to the N-terminal. n The drain and gate are connected to the input terminal VIN. n2 The drain is connected to the output terminal OUT. n2 Magnetic tunnel junction MTJ n1 The T2 terminal is connected to the output terminal OUT. n1 The T1 terminal is connected to VDD. Magnetic tunnel junction (MTJ) n2 The T2 terminal is connected to the output terminal OUT. n2 Terminal T1 is connected to VDD. Capacitor C n1 One end is connected to the output terminal OUT n1 The other end is connected to the control voltage VTCAL. Capacitor C n2 One end is connected to the output terminal OUT n2 The other end is connected to the control voltage VTCAL.

[0076] Among them, the oscillation signal FVCO is positively correlated with the control voltage VTCAL—the two are almost linearly related: as the voltage of the control voltage VTCAL increases, the frequency of the oscillation signal FVCO increases; as the voltage of the control voltage VTCAL decreases, the frequency of the oscillation signal FVCO decreases.

[0077] It is important to note that:

[0078] As described in the background section, conventional VCOs exhibit oscillation frequency drift, and the oscillation frequency decreases as the temperature increases.

[0079] In this embodiment 1, the output terminal OUT n1 A magnetic tunnel junction MTJ connected in series n1 OUT output terminal n2 A magnetic tunnel junction MTJ connected in series n2 Similar to the charge pump section, the magnetic tunnel junction (MTJ) n1 Magnetic Tunneling Junction (MTJ) n2 Both are used for temperature compensation. This also utilizes a similar principle: the on-resistance of the MOSFET in a VCO increases with temperature—that is, it has a positive temperature coefficient; while the magnetic tunnel junction can be considered as a resistor R with a negative temperature coefficient. AP By using two types of resistors with different temperature coefficients to compensate for each other's temperature, not only can the oscillation frequency drift be suppressed, but the power of the voltage-controlled oscillator can also be greatly reduced.

[0080] 5. The frequency divider is used to divide the oscillation signal FVCO and output the divided signal FVCODIV.

[0081] like Figure 3 As shown, the frequency division signal FVCODIV returns to the frequency and phase detector, thus forming a closed-loop feedback.

[0082] The frequency divider can be adopted as follows: Figure 8 Design:

[0083] See Figure 8 The frequency divider section includes four flip-flops (i.e., flip-flop D3, flip-flop D4, flip-flop D5, and flip-flop D6).

[0084] Specifically, the input D of flip-flop D3 is connected to its output QB, the clock signal CLK is connected to the oscillation signal FVCO, and the reset terminal RET is connected to VSS. The input D of flip-flop D4 is connected to its output QB, the clock signal CLK is connected to the input D of flip-flop D3, and the reset terminal RET is connected to VSS. The input D of flip-flop D5 is connected to its output QB, the clock signal CLK is connected to the input D of flip-flop D4, and the reset terminal RET is connected to VSS. The input D of flip-flop D6 is connected to its output QB, the output QB is connected to the frequency divider signal FVCODIV, the clock signal CLK is connected to the input D of flip-flop D5, and the reset terminal RET is connected to VSS.

[0085] In other words, the frequency divider consists of four cascaded flip-flops, forming a 16-bit frequency divider.

[0086] The adaptive temperature-compensated charge pump phase-locked loop circuit based on the above structure can compensate for temperature, reduce the impact of on-chip system temperature changes, and ensure and improve the performance of the CPPLL.

[0087] Simulation verification

[0088] In this embodiment 1, the adaptive temperature-compensated charge pump phase-locked loop circuit based on the above structure was also simulated to verify its effectiveness:

[0089] 1. Simulation of the charge pump section with added MTJ, the results are as follows: Figure 9 , Figure 10 As shown.

[0090] Figure 9 The current mismatch curves of the charge pump section with MTJ added at different temperatures are shown. Figure 1 different, Figure 9 The high overlap of the curves at different temperatures indicates that the current matching performance of the charge pump section with added MTJ is excellent—the current mismatch is less than 0.3%, and it also shows that temperature no longer has a significant impact on the current mismatch of the charge pump section with added MTJ.

[0091] Figure 10 The curves showing the compensation effects of the MOSFET and MTJ resistors are presented. It can be seen that the on-resistance of the MOSFET increases with increasing temperature—that is, it has a positive temperature coefficient; the corresponding R of the MTJ... AP This decreases with increasing temperature—meaning it has a negative temperature coefficient. Therefore, within a temperature range of -80℃ to 125℃, the total resistance of the two resistors stacked together remains almost unaffected by temperature and remains constant. Furthermore, differentiating the total resistance with respect to temperature reveals that most of the slope is 0, indicating that the temperature effect on the total resistance is negligible, and also demonstrating that adding the charge pump section of the MTJ provides excellent temperature compensation.

[0092] 2. Simulations were performed on the voltage-controlled oscillator (VCO) with the MTJ added, and a VCO without the MTJ was introduced for comparison. The results are as follows: Figure 11 , Figure 12 , Figure 13 .

[0093] Figure 11 The changes in control voltage VTCAL and oscillation signal FVCO without the addition of MTJ are shown. It can be seen that without MTJ, the control voltage VTCAL ranges from 0.32V to 0.6V—a variation of 280mV; the frequency fluctuation of the oscillation signal FVCO ranges from 2.54GHz to 2.638GHz—a fluctuation of 98MHz. Figure 12The changes in control voltage VTCAL and oscillation signal FVCO after adding the MTJ are shown. It can be seen that after adding the MTJ, the control voltage VTCAL ranges from 0.42V to 0.47V—a change of 50mV; the frequency fluctuation of the oscillation signal FVCO also decreases to only 8MHz. This indicates that the voltage-controlled oscillator with the MTJ added can effectively compensate for temperature and suppress oscillation frequency drift.

[0094] In addition, the output noise gain of the voltage-controlled oscillator is an important factor affecting the entire CPPLL and should also be considered. Figure 13 The output noise of the voltage-controlled oscillator (VCO) with and without an MTJ is compared. It can be seen that the output noise curves of the two are not significantly different, and the addition or absence of an MTJ has a negligible impact on the output noise of the VCO.

[0095] Example 2

[0096] This embodiment 2 discloses an adaptive temperature-compensated charge pump phase-locked loop module based on MTJ, which adopts the layout of the adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ disclosed in Embodiment 1. The modular packaging facilitates the promotion and application of the aforementioned circuit.

[0097] See Figure 14 According to function, the MTJ-based adaptive temperature-compensated charge pump phase-locked loop module includes: a frequency and phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider.

[0098] Among them, the frequency and phase detector corresponds to the frequency and phase detection section; the charge pump corresponds to the charge pump section; the low-pass filter corresponds to the low-pass filter section; the voltage-controlled oscillator corresponds to the voltage-controlled oscillator section; and the frequency divider corresponds to the frequency divider section. For the specific circuit distribution, please refer to Example 1, which will not be repeated here.

[0099] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ, characterized in that, include: Frequency and phase detector, charge pump, low-pass filter, voltage-controlled oscillator, frequency divider; The frequency and phase detector is used to compare the phase of the reference signal FREF and the frequency-divided signal FVCODIV, and convert the phase difference into signals UP and DOWN; the charge pump is used to charge and discharge the low-pass filter according to the signals UP and DOWN; the low-pass filter is used to adjust the control voltage VTCAL of the voltage-controlled oscillator; the voltage-controlled oscillator is used to generate an oscillation signal FVCO under the action of the control voltage VTCAL; the frequency divider is used to divide the oscillation signal FVCO and output the frequency-divided signal FVCODIV. The upper charge-discharge circuit of the charge pump section is connected in series with a magnetic tunnel junction MTJ1, and the lower charge-discharge circuit is connected in series with a magnetic tunnel junction MTJ2, both of which are used for temperature compensation; the charging and discharging currents of the upper charge-discharge circuit and the lower charge-discharge circuit of the charge pump section are the same. The charge pump unit includes: PMOS transistor P38 has its gate connected to its source and its drain connected to VDD. NMOS transistor N33 has its gate connected to its drain and its source connected to ground (GND). NMOS transistor N32 has its gate connected to the gate of NMOS transistor N33, and its source connected to ground (GND). PMOS transistor P11 has its gate connected to its drain and its source connected to VDD. PMOS transistor P10 has its gate connected to the gate of PMOS transistor P11, and its source connected to VDD. The magnetic tunnel junction MTJ1 has its T1 terminal connected to the drain of the PMOS transistor P10; PMOS transistor P9 has its gate connected to signal UP, its drain connected to control voltage VTCAL, and its source connected to T2 terminal of magnetic tunnel junction MTJ1. NMOS transistor N30 has its gate connected to the signal DOWN and its drain connected to the control voltage VTCAL. The magnetic tunnel junction MTJ2 has its T1 terminal connected to the source of the NMOS transistor N30; NMOS transistor N31 has its gate connected to the gate of NMOS transistor N33, its drain connected to the T2 terminal of magnetic tunnel junction MTJ2, and its source connected to ground GND. NMOS transistor N4 has its gate connected to VDD and its source connected to the drain of NMOS transistor N32; and PMOS transistor PM5 has its gate connected to VSS, its drain connected to the drain of NMOS transistor N4, and its source connected to the drain of PMOS transistor P11. Among them, PMOS transistor P10, magnetic tunnel junction MTJ1, PMOS transistor P9, and magnetic tunnel junction MTJ1 constitute the upper charge-discharge circuit; NMOS transistor N31, magnetic tunnel junction MTJ2, NMOS transistor N30, and magnetic tunnel junction MTJ2 constitute the lower charge-discharge circuit; The voltage-controlled oscillator section includes: a current mirror section and three cascaded differential amplifiers S1 to S3; the current mirror section serves as the differential amplifier S1. n The current source; n∈[1,3]; differential amplifier S n It has an input terminal VIN n1 Input terminal VIN n2 OUT output terminal n1 OUT output terminal n2 ; Output terminal OUT n1 A magnetic tunnel junction MTJ connected in series n1 OUT output terminal n2 A magnetic tunnel junction MTJ connected in series n2 Both are used for temperature compensation and to make the introduced noise effect negligible; The differential amplifier S n include: NMOS transistor N n Its source is connected to VSS, and its gate is connected to the gate of NMOS transistor NM10; NMOS transistor N n1 Its source is connected to NMOS transistor N n The drain and gate are connected to the input terminal VIN. n1 The drain is connected to the output terminal OUT. n1 ; NMOS transistor N n2 Its source is connected to NMOS transistor N n The drain and gate are connected to the input terminal VIN. n2 The drain is connected to the output terminal OUT. n2 ; Magnetic Tunnel Junction (MTJ) n1 Its T2 terminal is connected to the output terminal OUT. n1 The T1 terminal is connected to VDD; Magnetic Tunnel Junction (MTJ) n2 Its T2 terminal is connected to the output terminal OUT. n2 The T1 terminal is connected to VDD; Capacitor C n1 One end of it is connected to the output terminal OUT. n1 The other end is connected to the control voltage VTCAL; as well as Capacitor C n2 One end of it is connected to the output terminal OUT. n2 The other end is connected to the control voltage VTCAL.

2. The adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ according to claim 1, characterized in that, The frequency and phase detector section includes: flip-flop D1, flip-flop D2, NAND gate, and inverter INV; the input terminal D of flip-flop D1 is connected to VDD, the clock signal terminal CLK is connected to the reference signal FREF, and the output terminal Q is connected to the signal UP; the input terminal D of flip-flop D2 is connected to VDD, the clock signal terminal CLK is connected to the frequency divider signal FVCODIV, and the output terminal Q is connected to the signal DOWN; one input terminal of the NAND gate is connected to the signal UP, and the other input terminal is connected to the signal DOWN; the input terminal of the inverter INV is connected to the output terminal of the NAND gate, and the output terminal is connected together with the reset terminal RET of flip-flop D1 and the reset terminal RET of flip-flop D2. Alternatively, the frequency and phase discrimination section includes: flip-flop D1, flip-flop D2, AND gate, and delay unit Delay; the input terminal D of flip-flop D1 is connected to VDD, the clock signal terminal CLK is connected to the reference signal FREF, and the output terminal Q is connected to the signal UP; the input terminal D of flip-flop D2 is connected to VDD, the clock signal terminal CLK is connected to the frequency divider signal FVCODIV, and the output terminal Q is connected to the signal DOWN; one input terminal of AND gate is connected to the signal UP, and the other input terminal is connected to the signal DOWN; the input terminal of delay unit Delay is connected to the output terminal of AND gate, and the output terminal is connected together with the reset terminal RET of flip-flop D1 and the reset terminal RET of flip-flop D2.

3. The adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ according to claim 1, characterized in that, When the UP signal is high and the DOWN signal is low, the upper charge-discharge circuit is turned on and the lower charge-discharge circuit is turned off, and the charge pump section charges the low-pass filter section. When the UP signal is low and the DOWN signal is high, the upper charge-discharge circuit is disconnected and the lower charge-discharge circuit is turned on, and the charge pump discharges to the low-pass filter. When both signals UP and DOWN are low, the upper charge / discharge circuit is disconnected, the lower charge / discharge circuit is disconnected, and the low-pass filter does not charge or discharge. When both signals UP and DOWN are high, the upper charge / discharge circuit is turned on, the lower charge / discharge circuit is turned on, and the low-pass filter does not charge or discharge.

4. The adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ according to claim 1, characterized in that, The low-pass filter section includes: Capacitor C1, one end of which is connected to the control voltage VTCAL, and the other end is connected to ground GND; Resistor R2, one end of which is connected to the control voltage VTCAL; Capacitor C2 has one end connected to the other end of resistor R2, and the other end connected to ground GND.

5. The adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ according to claim 1, characterized in that, The current mirror includes: The PMOS transistor PM10 has its gate connected to its drain and its source connected to VDD. as well as The gate of the NMOS transistor NM10 is connected to its drain, the source is connected to VSS, and the drain is connected to the drain of the PMOS transistor PM10.

6. The adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ according to claim 1, characterized in that, The oscillation signal FVCO is positively correlated with the control voltage VTCAL.

7. The adaptive temperature-compensated charge pump phase-locked loop circuit based on MTJ according to claim 1, characterized in that, The frequency division unit includes: Flip-flop D3 has its input terminal D connected to its output terminal QB, its clock signal terminal CLK connected to the oscillation signal FVCO, and its reset terminal RET connected to VSS. Flip-flop D4 has its input terminal D connected to its output terminal QB, its clock signal terminal CLK connected to the input terminal D of flip-flop D3, and its reset terminal RET connected to VSS. Flip-flop D5 has its input terminal D connected to its output terminal QB, its clock signal terminal CLK connected to the input terminal D of flip-flop D4, and its reset terminal RET connected to VSS. as well as Flip-flop D6 has its input D connected to its output QB, which is connected to the frequency divider signal FVCODIV. The clock signal CLK is connected to the input D of flip-flop D5, and the reset signal RET is connected to VSS.

8. An adaptive temperature-compensated charge pump phase-locked loop module based on MTJ, characterized in that, It adopts the layout of the MTJ-based adaptive temperature-compensated charge pump phase-locked loop circuit as described in any one of claims 1-7.

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