Drive circuit, CAN transceiver, CAN system and chip

Abstract

The present application provides a drive circuit, a CAN transceiver, a CAN system, and a chip. In the drive circuit, a pre-stage drive circuit is respectively connected to a controller, a high-side drive switch group, and a low-side drive switch group. The high-side drive switch group is also connected to a common-mode circuit at a high-side port, and the low-side drive switch group is also connected to a common-mode circuit at a low-side port. The first switch tube connected to the high-side port in the high-side drive switch group is an NMOS, and the second switch tube connected to the low-side port in the low-side drive switch group is an NMOS. When a data signal indicates that the drive circuit changes from outputting a common-mode voltage to outputting a non-common-mode voltage, the pre-stage drive circuit generates a first control signal and a second control signal. The first control signal controls the high-side drive switch group to operate and the first switch tube is in a linear region, and the second control signal controls the low-side drive switch group to operate and the second switch tube is in a linear region. Thus, the impact on the electromagnetic compatibility of the CAN bus is reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a drive circuit, a CAN transceiver, a CAN system and a chip. Background Art

[0002] The controller area network (CAN) bus has the advantages of high speed, high reliability, and high real-time performance. It solves the problem of data exchange between many electronic control devices and is widely used in industries such as industry, transportation, medical care, education, and automobiles.

[0003] In related CAN interface communication systems, data exchange between the CAN bus and the controller relies on the CAN transceiver within the CAN interface communication system, which in turn relies on the driver circuit within it. Existing driver circuits typically include a high-side driver circuit and a low-side driver circuit. The high-side driver circuit provides the CANH voltage to the high-side port of the driver circuit, while the low-side driver circuit provides the CANL voltage to the low-side port of the driver circuit. When the CANH voltage and CANL voltage are dominant, data exchange occurs between the CAN bus and the controller. When the CANH voltage and CANL voltage are recessive, data exchange between the CAN bus and the controller ends.

[0004] However, in the relevant drive circuit, since the conduction capability of the switch tube connected to the high-side port and the switch tube connected to the low-side port is relatively poor, it will affect the electromagnetic compatibility (EMC) of the CAN bus and affect the communication distance of the CAN bus. Therefore, a new drive circuit is urgently needed to reduce the impact on the EMC of the CAN bus and increase the communication distance of the CAN bus. Summary of the Invention

[0005] In view of this, the present application provides a driving circuit, a CAN transceiver, a CAN system and a chip, which are used to reduce the impact on the EMC of the CAN bus and increase the communication distance of the CAN bus.

[0006] To achieve the above objectives, in a first aspect, an embodiment of the present application provides a driving circuit for use in a CAN transceiver; the driving circuit comprises: a pre-stage driving circuit, a high-side driving switch group, a common-mode supply circuit, and a low-side driving switch group;

[0007] A first end of the pre-stage driver circuit is electrically connected to the controller, a second end of the pre-stage driver circuit is electrically connected to a first end of the high-side driver switch group, and a third end of the pre-stage driver circuit is electrically connected to a first end of the low-side driver switch group; a first end of the common-mode supply circuit is electrically connected to the second end of the high-side driver switch group and the high-side port of the driver circuit, and a second end of the common-mode supply circuit is electrically connected to the second end of the low-side driver switch group and the low-side port of the driver circuit;

[0008] The first switch tube electrically connected to the high-side port in the high-side drive switch group is an NMOS, and the second switch tube electrically connected to the low-side port in the low-side drive switch group is an NMOS;

[0009] The common mode supply circuit is used to provide a common mode voltage to the high-side port and the low-side port respectively when both the high-side drive switch group and the low-side drive switch group are not working;

[0010] a pre-stage driving circuit, configured to receive a data signal sent by the controller and, when the data signal is used to instruct the driving circuit to change from outputting a common-mode voltage to outputting a non-common-mode voltage, generate a first control signal and a second control signal according to the data signal, wherein the non-common-mode voltage includes the first voltage and the second voltage;

[0011] The front-stage driver circuit is further configured to send a first control signal to the high-side driver switch group to control the high-side driver switch group to operate and the first switch tube to be in the linear region, and to send a second control signal to the low-side driver switch group to control the low-side driver switch group to operate and the second switch tube to be in the linear region;

[0012] When both the high-side drive switch group and the low-side drive switch group are working, the voltage of the high-side port changes from the common mode voltage to the first voltage, and the voltage of the low-side port changes from the common mode voltage to the second voltage.

[0013] In a second aspect, an embodiment of the present application provides a CAN transceiver, comprising: a driving circuit and a receiver as described in any one of the first aspects, wherein the receiver is electrically connected to the driving circuit;

[0014] The receiver is used to receive the signal sent by the driving circuit.

[0015] In a third aspect, an embodiment of the present application provides a CAN communication system, including a controller, a CAN bus, and a CAN transceiver as in the second aspect;

[0016] The CAN bus includes: a first terminal and a second terminal; the CAN transceiver includes a third terminal and a fourth terminal;

[0017] The controller is electrically connected to the CAN transceiver;

[0018] The third end of the CAN transceiver is electrically connected to the first end of the CAN bus, and the fourth end of the CAN transceiver is electrically connected to the second end of the CAN bus.

[0019] In a fourth aspect, an embodiment of the present application provides an automotive-grade chip, comprising: a driving circuit as in any one of the first aspect; and / or a CAN transceiver as in the second aspect.

[0020] The embodiment of the present application provides a driving circuit, a CAN transceiver, a CAN system and a chip, wherein the driving circuit includes: a pre-stage driving circuit, a high-side driving switch group, a common-mode supply circuit and a low-side driving switch group. When the data signal indicates that the driving circuit changes from outputting a common-mode voltage to outputting a non-common-mode voltage, the pre-stage driving circuit generates a first control signal and a second control signal according to the data signal, the first control signal controls the high-side driving switch group to operate and the first switch tube is in a linear region, and the second control signal controls the low-side driving switch group to operate and the second switch tube is in a linear region. Since the first switch tube and the second switch tube are of NMOS type and operate in the linear region, compared with the prior art, in which the switch tube connected to the high-side port is PMOS and the switch tube connected to the low-side port is PMOS, the conduction capability of the switch tube connected to the high-side port and the switch tube connected to the low-side port in the present application is improved, which can reduce the impact on the EMC of the CAN bus and further increase the communication distance of the CAN bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of a CAN system provided in one embodiment of the present application;

[0022] Figure 2 1 is a structural diagram of a related driving circuit;

[0023] Figure 3 A timing diagram for the operation of a related control drive circuit;

[0024] Figure 4 A schematic structural diagram of a driving circuit provided in one embodiment of the present application;

[0025] Figure 5 A timing diagram for controlling the operation of a driving circuit provided in one embodiment of the present application;

[0026] Figure 6 A schematic structural diagram of a driving circuit provided in one embodiment of the present application;

[0027] Figure 7 A schematic structural diagram of a driving circuit provided in one embodiment of the present application;

[0028] Figure 8 A schematic structural diagram of a driving circuit provided in one embodiment of the present application;

[0029] Figure 9A schematic structural diagram of a driving circuit provided in one embodiment of the present application;

[0030] Figure 10 A schematic structural diagram of a driving circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0031] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] Figure 1 A schematic diagram of the structure of a CAN system provided in one embodiment of the present application is shown in FIG. Figure 1 As shown, the CAN system may include N controllers and N CAN transceivers, where N is a positive integer. In addition, the CAN system may also include a controller and multiple CAN transceivers (not shown).

[0033] In a CAN system, each transceiver corresponds to a controller, and each controller corresponds to one or more transceivers.

[0034] The controller may be a CAN controller or a microcontroller unit (MCU) controller, which is not particularly limited in the embodiment of the present application.

[0035] Taking the first controller and the first CAN transceiver as an example, the first end of the first controller is electrically connected to the first end of the first CAN transceiver, the second end of the first controller is electrically connected to the second end of the first CAN transceiver, the high-side port of the first CAN transceiver is electrically connected to the CANH line, the low-side port of the first CAN transceiver is electrically connected to the CANL line, and the first end of the CANH line is electrically connected to the first loop resistor R f1 The first end of the CANH line is electrically connected to the second loop resistor R f2 The first end of the CANL line is electrically connected to the first loop resistor R f1 The second end of the CANL line is electrically connected to the second loop resistor R f2 For ease of description, the high-side port is represented by CANH, and the low-side port is represented by CANL.

[0036] If the first CAN transceiver is used as a reference, the first CAN transceiver is used to receive the data signal CAN sent by the first controller.TX and sends data signal CAN to the first controller RX .

[0037] If the first controller is used as a reference, the first controller is used to send data signals CAN to the first CAN transceiver TX , and receives the data signal CAN sent by the first CAN transceiver RX .

[0038] The first CAN transceiver will receive the data signal CAN TX After that, according to the data signal CAN TX Then the CANH voltage and CANL voltage are generated, and the CANH voltage is sent to the CANH line and the CANL voltage is sent to the CANL line respectively to carry out data exchange.

[0039] In the process of data interaction, it usually depends on the driving circuit in the CAN transceiver. The relevant driving circuit usually includes a high-side driving circuit and a low-side driving circuit. The high-side driving circuit provides a CANH voltage to the CANH end of the driving circuit and outputs the CANH voltage to the CANH line. The low-side driving circuit provides a CANL voltage to the CANL end of the driving circuit and outputs the CANL voltage to the CANL line.

[0040] When both the CANH voltage and the CANL voltage are dominant, data is exchanged between the CAN bus and the controller. When both the CANH voltage and the CANL voltage are recessive, data exchange between the CAN bus and the controller is terminated. It is understood that for those skilled in the art, "dominant" and "recessive" are common technical terms and therefore require no explanation.

[0041] However, in the relevant driving circuit, the switch tube connected to the CANH end and the switch tube connected to the CANL end are both PMOS tubes, which have relatively poor conduction capabilities and will affect the EMC of the CAN bus and the communication distance of the CAN bus.

[0042] The following combination Figure 2 and Figure 3 , explaining the connection relationship and working principle of the existing driving circuit.

[0043] Figure 2 It is a structural diagram of an existing driving circuit, such as Figure 2As shown, the drive circuit includes: a first pre-stage drive circuit 201, a power supply Vcc, a resistor R, a high-side switch group, and a low-side switch group. The high-side switch group includes: a first high-side switch transistor M1, a second high-side switch transistor M2, a third high-side switch transistor M3, a first diode D1, and a second diode D2; the low-side switch group includes: a first low-side switch transistor M4, a second low-side switch transistor M5, a third low-side switch transistor M6, a third diode D3, and a fourth diode D4.

[0044] The first controller 101 may be a CAN controller or an MCU controller, etc., and this embodiment of the present application does not specifically limit this.

[0045] The first pre-stage driver circuit 201 uses a first pre-stage driver GD1, the first diode D1 is the body diode of the second high-side switch tube M2, the second diode D2 is the body diode of the third high-side switch tube M3, the third diode D3 is the body diode of the third low-side switch tube M6, and the fourth diode D4 is the body diode of the second low-side switch tube M5; the first high-side switch tube M1, the second high-side switch tube M2, the third high-side switch tube M3, the first low-side switch tube M4, the second low-side switch tube M5 and the third low-side switch tube M6 all use metal oxide semiconductor field effect transistors (MOS).

[0046] Among them, MOS tubes can be divided into P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOS) and N-channel Metal Oxide Semiconductor Field Effect Transistor (NMOS). PMOS has the characteristics of low level closed and high level cut off, while NMOS has the characteristics of high level closed and low level cut off.

[0047] According to the characteristics of PMOS and NMOS, as well as the requirements of the circuit, such as Figure 2 As shown, the first high-side switch tube M1 is a PMOS tube, the second high-side switch tube M2 is an NMOS tube, the third high-side switch tube M3 is a PMOS tube, the first low-side switch tube M4 is an NMOS tube, the second low-side switch tube M5 is an NMOS tube, and the third low-side switch tube M6 is a PMOS tube.

[0048] In the case where the first high-side switch tube M1 is a PMOS tube, the second high-side switch tube M2 is an NMOS tube, the third high-side switch tube M3 is a PMOS tube, the first low-side switch tube M4 is an NMOS tube, the second low-side switch tube M5 is an NMOS tube, and the third low-side switch tube M6 is a PMOS tube, Figure 2The specific connection relationship of an existing driving circuit provided is as follows: the gate (i.e., the control end) of the first high-side switch tube M1 is electrically connected to the second end of the first pre-driver GD1, the drain (i.e., the input end) of the first high-side switch tube M1 is electrically connected to the power supply Vcc, and the source (i.e., the output end) of the first high-side switch tube M1 is electrically connected to the source (i.e., the output end) of the second high-side switch tube M2.

[0049] The gate (i.e., the control end) of the second high-side switch tube M2 is electrically connected to the power supply Vcc, the source (i.e., the input end) of the second high-side switch tube M2 is also electrically connected to the anode of the first diode D1, and the drain (i.e., the output end) of the second high-side switch tube M2 is electrically connected to the cathode of the first diode D1 and the input end of the third high-side switch tube M3.

[0050] The gate (i.e., the control end) of the third high-side switch tube M3 is grounded GND, the drain (i.e., the input end) of the third high-side switch tube M3 is also electrically connected to the cathode of the second diode D2, and the source (i.e., the output end) of the third high-side switch tube M3 is electrically connected to the anode of the second diode D2 and the first end of the resistor R to the CANH end of the drive circuit.

[0051] The gate (i.e., the control terminal) of the first low-side switch tube M4 is electrically connected to the third terminal of the first pre-driver GD1. The drain (i.e., the input terminal) of the first low-side switch tube M4 is electrically connected to the source (i.e., the output terminal) of the second low-side switch tube M5 and the anode of the fourth diode D4. The source (i.e., the output terminal) of the first low-side switch tube M4 is grounded GND.

[0052] The gate (i.e., the control terminal) of the second low-side switch tube M5 is electrically connected to the power supply Vcc, and the drain (i.e., the input terminal) of the second low-side switch tube M5 is electrically connected to the cathode of the fourth diode D4 and the drain (i.e., the input terminal) of the third low-side switch tube M6.

[0053] The gate (i.e., control terminal) of the third low-side switch M6 is grounded GND. The source (i.e., input terminal) of the third low-side switch M6 is also electrically connected to the cathode of the third diode D3. The drain (i.e., output terminal) of the third low-side switch M6 is electrically connected to the anode of the third diode D3 and the second end of the resistor R, respectively, and is connected to the CANL terminal of the driver circuit. The first terminal of the first pre-stage driver circuit 201 is electrically connected to the first terminal of the first controller 101.

[0054] Among them, the first pre-driver GD1 is used to receive the first data signal TXD1 sent by the first controller 101, and can generate a control signal CTL1 and a control signal CTL2 according to the first data signal TXD1; it is also used to send the control signal CTL1 to the first high-side switch tube M1 to control the conduction or cut-off of the first high-side switch tube M1, and send the control signal CTL2 to the first low-side switch tube M4 to control the conduction or cut-off of the first low-side switch tube M4.

[0055] The control signal CTL1 follows the first data signal TXD1, and the phase of the control signal CTL2 is opposite to that of the first data signal TXD1. It will be understood that the first data signal TXD1 includes a high level (hereinafter referred to as "1") and a low level (hereinafter referred to as "0"). Therefore, the control signals CTL1 and CTL2 also have a high level (hereinafter referred to as "1") and a low level (hereinafter referred to as "0").

[0056] When the first data signal TXD1 is output as 1, the control signal CTL1 is output as 1 and the control signal CTL2 is output as 0; when the first data signal TXD1 is output as 0, the control signal CTL1 is output as 0 and the control signal CTL2 is output as 1.

[0057] When the first data signal TXD1 is output as 0, the drive circuit is turned on as a whole, the CANH terminal of the drive circuit outputs the first dominant voltage VH1, and the CANL terminal of the drive circuit outputs the second dominant voltage VL1; when the first data signal TXD1 is output as 1, the drive circuit is turned off as a whole, the CANH terminal of the drive circuit outputs the first common-mode voltage Vcm1, and the CANL terminal of the drive circuit outputs the first common-mode voltage Vcm1.

[0058] The first common-mode voltage Vcm1 represents a dominant voltage. When the voltage outputted by the CANH and CANL terminals of the driver circuit is a dominant voltage, data transmission is occurring. When the voltage outputted by the CANH and CANL terminals of the driver circuit is a recessive voltage, data transmission is not occurring.

[0059] The following combination Figure 3 Explain the working principle of the relevant driving circuit.

[0060] Figure 3 This is a timing diagram of a related control drive circuit, such as Figure 3 As shown, during the time period t1, the first data signal TXD1 output by the first controller 101 to the first pre-driver GD1 is 0; the control signal CTL1 output by the first pre-driver GD1 to the first high-side switch tube M1 is 0. Since the first high-side switch tube M1 is a PMOS tube, it has the characteristics of being closed at a low level and cut off at a high level. Therefore, the first pre-driver GD1 can control the first high-side switch tube M1 to be turned on; the control signal CTL2 output by the first pre-driver GD1 to the first low-side switch tube M4 is 1. Since the first low-side switch tube M4 is an NMOS tube, it has the characteristics of being closed at a high level and cut off at a low level. Therefore, the first pre-driver GD1 can control the first low-side switch tube M4 to be turned on.

[0061] The second high-side switch tube M2 is controlled to be turned on by the power supply Vcc. Since the first high-side switch tube M1 is turned on, the anode potential of the first diode D1 is higher than the cathode potential, so the first diode D1 is turned on; the third high-side switch tube M3 is controlled to be turned on by the ground voltage. Since the second diode D2 is in reverse, the anode potential of the second diode D2 is lower than the cathode potential, so the second diode D2 is turned off.

[0062] The second low-side switch tube M5 is controlled to be turned on by the power supply Vcc. Since the fourth diode D4 is in reverse, the anode potential of the fourth diode D4 is lower than the cathode potential, so the fourth diode D4 is turned off. The third low-side switch tube M6 is controlled to be turned on by the ground voltage. Since the third high-side switch tube M3 is turned on, the anode potential of the third diode D3 is higher than the cathode potential, and therefore, the third diode D3 is turned on.

[0063] Therefore, for the entire drive circuit, the current flows from the power supply Vcc, through the first high-side switch M1, the first diode D1, the third high-side switch M3, the resistor R, the third diode D3, the second low-side switch M5, and the first low-side switch M4 to the ground GND.

[0064] Therefore, during the time period t1 , the CANH terminal of the driving circuit outputs the first dominant voltage VH1 , and the CANL terminal of the driving circuit outputs the second dominant voltage VL1 .

[0065] During the time period t2, the first data signal TXD1 output by the first controller 101 to the first pre-driver GD1 is 1; the control signal CTL1 output by the first pre-driver GD1 to the first high-side switch tube M1 is 1. Since the first high-side switch tube M1 is a PMOS tube and has the characteristics of low-level closing and high-level cutting, the first pre-driver GD1 can control the first high-side switch tube M1 to be cut off; the control signal CTL2 output by the first pre-driver GD1 to the first low-side switch tube M4 is 0. Since the first low-side switch tube M4 is an NMOS tube and has the characteristics of high-level closing and low-level cutting, the first pre-driver GD1 can control the first low-side switch tube M4 to be cut off.

[0066] Since the first high-side switch M1 and the first low-side switch M4 are both turned off, this means that there is no path between the power supply Vcc electrically connected to the first high-side switch M1 and the ground GND electrically connected to the first low-side switch M4. Therefore, the second high-side switch M2, the first diode D1, the third high-side switch M3, the second diode D2, the second low-side switch M5, the fourth diode D4, the third low-side switch M6 and the third diode D3 are all turned off. The first end of the resistor R outputs the first common-mode voltage Vcm1 to the CANH terminal of the drive circuit, and the second end of the resistor R outputs the first common-mode voltage Vcm1 to the CANL terminal of the drive circuit.

[0067] From the above description of the existing drive circuit, it can be seen that, first, during time period t1, the current flows through the body diode of the second high-side switch M2 (i.e., the first diode D1) and the body diode of the third low-side switch M6 (i.e., the third diode D3). This means that the conduction of the second high-side switch M2 and the third low-side switch M6 depends on their body diodes. For MOS transistors, this conduction mode results in a PNP junction, which generates leakage current in the P-type substrate. This leakage current cannot be eliminated, further affecting the output voltages of the CANH and CANL terminals of the drive circuit, further affecting the accuracy of data exchange.

[0068] Secondly, the third high-side switch tube M3 electrically connected to the first end of the resistor R is a PMOS, and the third low-side switch tube M6 electrically connected to the second end of the resistor R is also a PMOS. Due to the weak conduction capability of the PMOS, the working area of ​​the third high-side switch tube M3 and the third low-side switch tube M6 will be limited, and a relatively large parasitic capacitance will be generated inside the third high-side switch tube M3 and the third low-side switch tube M6. The large parasitic capacitance will further have a greater impact on the EMC of the CAN bus, and further, will have an adverse effect on the long-distance communication of the CAN bus.

[0069] In order to solve the above technical problems, the embodiments of the present application provide a drive circuit, a CAN transceiver, a CAN system and a chip. The technical solution provided by the present application, first, since the first switch tube and the second switch tube operate in the linear region, the negative impact of the PNP junction is eliminated, and the output voltage of the CANH end and the CANL end of the drive circuit can be made more stable, which can improve the accuracy of data interaction. Second, since the type of the first switch tube and the second switch tube is NMOS, compared with the related art, the switch tube connected to the CANH end and the switch tube connected to the CANL end are PMOS type switch tubes, the conduction capability is improved, the parasitic capacitance is reduced, the impact on the EMC of the CAN bus is further reduced, and the communication distance of the CAN bus is further improved.

[0070] The technical solution of the present application is described in detail below with reference to the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to be used to explain the present application, but should not be understood as limiting the present application.

[0071] Figure 4 A schematic diagram of a driving circuit according to an embodiment of the present invention is shown in FIG. Figure 4 As shown, the driving circuit includes: a pre-stage driving circuit 20 , a high-side driving switch group 30 , a common-mode supply circuit 40 and a low-side driving switch group 50 .

[0072] A first end of the pre-stage driver circuit 20 is electrically connected to the controller 102, a second end of the pre-stage driver circuit 20 is electrically connected to a first end of the high-side driver switch group 30, and a third end of the pre-stage driver circuit 20 is electrically connected to a first end of the low-side driver switch group 50; a first end of the common-mode supply circuit 40 is electrically connected to the second end of the high-side driver switch group 30 and the CANH end of the driver circuit, and a second end of the common-mode supply circuit 40 is electrically connected to the second end of the low-side driver switch group 50 and the CANL end of the driver circuit; wherein, the first switch tube (not shown) in the high-side driver switch group 30 electrically connected to the CANH end is an NMOS, and the second switch tube (not shown) in the low-side driver switch group 50 electrically connected to the CANL end is an NMOS.

[0073] When both the high-side driver switch group 30 and the low-side driver switch group 50 are not operating, the common mode supply circuit 40 provides a common mode voltage Vcm2 to the CANH terminal and the CANL terminal, respectively.

[0074] Among them, the non-operation of the high-side drive switch group 30 means that all circuits (not shown) inside the high-side drive switch group 30 are in the off state; the non-operation of the low-side drive switch group 50 means that all circuits (not shown) inside the low-side drive switch group 50 are in the off state.

[0075] The controller 102 may be a CAN controller or an MCU controller, etc., and this embodiment of the present application does not impose any special limitation on this.

[0076] The voltage value of the common-mode voltage Vcm2 can be greater than the voltage value of the common-mode voltage Vcm1, or less than the voltage value of the common-mode voltage Vcm1, or can be equal to the voltage value of the common-mode voltage Vcm1, and this is not particularly limited in the embodiments of the present application. It is understood that errors will exist in actual applications. Therefore, within the allowable range of errors, the embodiments of the present application do not particularly limit the voltage values ​​of the common-mode voltage Vcm2 and the common-mode voltage Vcm1.

[0077] The pre-stage driving circuit 20 receives the data signal TXD sent by the controller 102, and generates a first control signal CTL according to the data signal TXD when the data signal TXD indicates that the driving circuit changes from outputting the common mode voltage Vcm2 to outputting the non-common mode voltage. 111 and the second control signal CTL 121 .

[0078] The non-common mode voltage includes a first voltage VH2 and a second voltage VL2.

[0079] The voltage value of the first voltage VH1 is greater than the voltage value of the second voltage VL2.

[0080] The pre-stage driving circuit 20 sends a first control signal CTL to the high-side driving switch group 30 111 , to control the high-side drive switch group 30 to work and the first switch tube is in the linear region, and send the second control signal CTL to the low-side drive switch group 50 121 , to control the low-side drive switch group 50 to work and the second switch tube is in the linear region.

[0081] The operation of the high-side drive switch group 30 indicates that part or all of the circuit inside the high-side drive switch group 30 is in a conducting state; the operation of the low-side drive switch group 50 indicates that part or all of the circuit inside the low-side drive switch group 50 is in a conducting state.

[0082] When both the high-side driver switch group 30 and the low-side driver switch group 50 are working, the voltage at the CANH terminal changes from the common mode voltage Vcm2 to the first voltage VH2, and the voltage at the CANL terminal changes from the common mode voltage Vcm2 to the second voltage VL2.

[0083] When the data signal TXD indicates that the driving circuit changes from outputting the non-common mode voltage to outputting the common mode voltage Vcm2, the pre-stage driving circuit 20 generates the third control signal CTL according to the data signal TXD. 112 and the fourth control signal CTL 122 .

[0084] The pre-stage driving circuit 20 sends a third control signal CTL to the high-side driving switch group 30 112 , to control the high-side drive switch group 30 not to work, and send the fourth control signal CTL to the low-side drive switch group 50 122 , to control the low-side drive switch group 50 to not work.

[0085] When the high-side driver switch group 30 is working and the low-side driver switch group 50 is not working, the voltage at the CANH terminal changes from the first voltage VH2 to the common mode voltage Vcm2, and the voltage at the CANL terminal changes from the second voltage VL2 to the common mode voltage Vcm2.

[0086] Among them, the first control signal CTL 111 Control signal CTL 11 The third control signal CTL is low level. 112 Control signal CTL 11 High level; second control signal CTL 121 Control signal CTL 12 The high level of the fourth control signal CTL 122 Control signal CTL 12 Low level; control signal CTL 11 Follow the data signal TXD, control signal CTL 12The phase of the data signal TXD is opposite to that of the data signal TXD.

[0087] It is understood that the data signal TXD includes a high level (hereinafter referred to as "1" to represent a high level) and a low level (hereinafter referred to as "0" to represent a low level). When the first data signal TXD1 is output as 0, the control signal CTL1 is output as the first control signal CTL 111 , the control signal CTL2 is output as the second control signal CTL 121 ; When the data signal TXD is output as 1, the control signal CTL 11 Output is the third control signal CTL 112 , the control signal CTL2 is output as the fourth control signal CTL 122 .

[0088] Among them, the first voltage VH2 is the dominant voltage of the CANH voltage output by the CANH terminal, and the second voltage VL2 is the dominant voltage of the CANL voltage output by the CANL terminal. When the dominant voltage is output at the CANH terminal and the CANL terminal, it indicates that data interaction is in progress; the common mode voltage Vcm2 represents the invisible voltage of the CANH voltage and the invisible voltage of the CANL voltage. When the recessive voltage is output at the CANH terminal and the CANL terminal, it indicates that the data interaction is completed.

[0089] The following combination Figure 5 ,illustrate Figure 4 The working principle of the driving circuit is provided.

[0090] Figure 5 A timing diagram of a control driving circuit according to an embodiment of the present application is provided, such as Figure 5 As shown, during the time period t1, the data signal TXD output by the controller 102 to the front-stage driving circuit 20 is 0, and the front-stage driving circuit 20 generates the first control signal CTL according to the data signal TXD. 111 and the second control signal CTL 121 , and output the first control signal CTL to the high-side drive switch group 30 respectively 111 , to control the high-side drive switch group 30 to work, and the first switch tube works in the linear region; output the second control signal CTL to the low-side drive switch group 50 121 , to control the low-side drive switch group 50 to work, and the second switch tube works in the linear region.

[0091] Therefore, for the entire driving circuit, the current flows from the high-side driving switch group 30 , the common-mode supply circuit 40 to the low-side driving switch group 50 .

[0092] Therefore, during the time period t1, the voltage outputted by the CANH terminal of the driving circuit changes from the common mode voltage Vcm2 of the previous time period to the first voltage VH2, and the voltage outputted by the CANL terminal of the driving circuit changes from the common mode voltage Vcm2 of the previous time period to the second voltage VL2.

[0093] When the CANH terminal outputs the first voltage VH2 and the CANL terminal outputs the second voltage VL2, data is exchanged between the CAN bus and the controller 102.

[0094] During the time period t2, the data signal TXD output by the controller 102 to the front-stage driving circuit 20 is 1, and the front-stage driving circuit 20 generates the third control signal CTL according to the data signal TXD. 112 and the fourth control signal CTL 122 , and output the third control signal CTL to the high-side drive switch group 30 respectively 112 , to control the high-side drive switch group 30 not to work; output the fourth control signal CTL to the low-side drive switch group 50 122 , to control the low-side drive switch group 50 to not work.

[0095] When both the high-side drive switch group 30 and the low-side drive switch group 50 are not working, the common-mode supply circuit 40 provides a common-mode voltage Vcm2 to the CANH terminal and the CANL terminal, respectively. That is, the voltage output by the CANH terminal changes from the first voltage VH2 in the time period t1 to the common-mode voltage Vcm2, and the voltage output by the CANL terminal changes from the second voltage VL2 in the time period t1 to the common-mode voltage Vcm2.

[0096] When both the CANH terminal and the CANL terminal output the common mode voltage Vcm2, the data exchange between the CAN bus and the controller 102 ends.

[0097] Based on the above description of the connection relationship and operation of the drive circuit provided in one embodiment of the present application, it can be understood that the drive circuit provided in the present application, first, because the first switch tube and the second switch tube operate in the linear region, the negative impact of the PNP junction is eliminated, and the output voltage of the CANH terminal and the CANL terminal of the drive circuit can be made more stable, which can improve the accuracy of data exchange. Second, because the first switch tube and the second switch tube are of NMOS type, compared with the related art, in which the switch tube connected to the CANH terminal and the switch tube connected to the CANL terminal are PMOS type switch tubes, the conduction capability is improved, the parasitic capacitance is reduced, the impact on the EMC of the CAN bus is further reduced, and the communication distance of the CAN bus is further improved.

[0098] Based on the description of the above embodiment, the pre-stage driving circuit 20 adopts the second pre-stage driver GD2.

[0099] As an optional implementation, the second pre-stage driver GD2 can be a complex circuit or an integrated chip, etc. The embodiment of the present application does not specifically limit this. In order to reduce the circuit volume and reduce production costs, the second pre-stage driver GD2 is an integrated chip as an example for exemplary description.

[0100] Figure 6 A schematic diagram of a driving circuit according to an embodiment of the present invention is shown in FIG. Figure 6 As shown, the driving circuit includes: a pre-stage driving circuit 20, a high-side driving switch group 30, a common mode supply circuit 40 and a low-side driving switch group 50. The pre-stage driving circuit 20 includes a second pre-stage driver GD2.

[0101] It should be noted that, only the connection relationship between the second pre-stage driver GD2 and the high-side driver switch group 30, the connection relationship between the second pre-stage driver GD2 and the low-side driver switch group 50, and the connection relationship between the second pre-stage driver GD2 and the controller 102 are described here when the pre-stage driver circuit 20 includes the second pre-stage driver GD2. The connection relationship of the remaining circuits can be referred to. Figure 4 The relevant description of the driving circuit provided will not be repeated here.

[0102] Specifically, the first end of the second pre-stage driver GD2 (i.e., the first end of the pre-stage driver circuit 20) is electrically connected to the controller 102, the second end of the second pre-stage driver GD2 (i.e., the second end of the pre-stage driver circuit 20) is electrically connected to the first end of the high-side drive switch group 30, and the third end of the second pre-stage driver GD2 (i.e., the third end of the pre-stage driver circuit 20) is electrically connected to the first end of the low-side drive switch group 50.

[0103] The first switch tube (not shown) electrically connected to the CANH terminal in the high-side driver switch group 30 is an NMOS, and the second switch tube (not shown) electrically connected to the CANL terminal in the low-side driver switch group 50 is an NMOS.

[0104] The common mode supply circuit 40 provides a common mode voltage Vcm2 to the CANH terminal and the CANL terminal respectively when both the high-side driver switch group 30 and the low-side driver switch group 50 are not in operation.

[0105] The second pre-stage driver GD2 receives the data signal TXD sent by the controller 102, and generates a first control signal CTL according to the data signal TXD when the data signal TXD indicates that the driving circuit changes from outputting the common mode voltage Vcm2 to outputting the non-common mode voltage. 111 and the second control signal CTL 121 .

[0106] The second pre-stage driver GD2 sends a first control signal CTL to the high-side driver switch group 30111 , to control the high-side drive switch group 30 to work and the first switch tube is in the linear region, and send the second control signal CTL to the low-side drive switch group 50 121 , to control the low-side drive switch group 50 to work and the second switch tube is in the linear region.

[0107] When the data signal TXD is used to instruct the driving circuit to change from outputting the non-common mode voltage to outputting the common mode voltage Vcm2, the second pre-stage driver GD2 generates a third control signal CTL according to the data signal TXD. 112 and the fourth control signal CTL 122 .

[0108] The second pre-stage driver GD2 sends a third control signal CTL to the high-side driver switch group 30 112 , to control the high-side drive switch group 30 not to work, and send the fourth control signal CTL to the low-side drive switch group 50 122 , to control the low-side drive switch group 50 to not work.

[0109] The following combination Figure 5 ,illustrate Figure 6 The working principle of the driving circuit is provided.

[0110] like Figure 5 As shown, during the time period t1, the data signal TXD output by the controller 102 to the second pre-stage driver GD2 is 0, and the second pre-stage driver GD2 generates the first control signal CTL according to the data signal TXD. 111 and the second control signal CTL 121 , and output the first control signal CTL to the high-side drive switch group 30 respectively 111 , to control the high-side drive switch group 30 to work, and the first switch tube works in the linear region, outputting the second control signal CTL to the low-side drive switch group 50 121 , to control the low-side drive switch group 50 to work, and the second switch tube works in the linear region.

[0111] Therefore, for the entire driving circuit, the current flows from the high-side driving switch group 30 , the common-mode supply circuit 40 to the low-side driving switch group 50 .

[0112] Therefore, during the time period t1, the voltage outputted by the CANH terminal of the driving circuit changes from the common mode voltage Vcm2 of the previous time period to the first voltage VH2, and the voltage outputted by the CANL terminal of the driving circuit changes from the common mode voltage Vcm2 of the previous time period to the second voltage VL2.

[0113] When the CANH terminal outputs the first voltage VH2 and the CANL terminal outputs the second voltage VL2, data is exchanged between the CAN bus and the controller 102.

[0114] During the time period t2, the data signal TXD output by the controller 102 to the second pre-driver GD2 is 1, and the second pre-driver GD2 generates a third control signal CTL according to the data signal TXD. 112 and the fourth control signal CTL 122 , and output the third control signal CTL to the high-side drive switch group 30 respectively 112 , to control the high-side drive switch group 30 not to work; output the fourth control signal CTL to the low-side drive switch group 50 122 , to control the low-side drive switch group 50 to not work.

[0115] When both the high-side drive switch group 30 and the low-side drive switch group 50 are not working, the common-mode supply circuit 40 provides a common-mode voltage Vcm2 to the CANH terminal and the CANL terminal, respectively. That is, the voltage output by the CANH terminal changes from the first voltage VH2 in the time period t1 to the common-mode voltage Vcm2, and the voltage output by the CANL terminal changes from the second voltage VL2 in the time period t1 to the common-mode voltage Vcm2.

[0116] When both the CANH terminal and the CANL terminal output the common mode voltage Vcm2, the data exchange between the CAN bus and the controller 102 ends.

[0117] Based on the above description of the connection relationship and working principle of the drive circuit provided in one embodiment of the present application, it can be understood that the drive circuit provided in the present application, first, because the first switch tube and the second switch tube operate in the linear region, the negative impact of the PNP junction is eliminated, and the output voltage of the CANH terminal and the CANL terminal of the drive circuit can be made more stable, which can improve the accuracy of data exchange. Second, because the first switch tube and the second switch tube are of NMOS type, compared with the related art, in which the switch tube connected to the CANH terminal and the switch tube connected to the CANL terminal are PMOS type switch tubes, the conduction capability is improved, the parasitic capacitance is reduced, the impact on the EMC of the CAN bus is further reduced, and the communication distance of the CAN bus is further improved.

[0118] Based on the description of the above embodiment, the structure of the high-side driver switch group 30 is described in detail below.

[0119] Figure 7 A schematic diagram of a driving circuit according to an embodiment of the present invention is shown in FIG. Figure 7As shown, the driving circuit includes: a pre-stage driving circuit 20, a high-side driving switch group 30, a common-mode supply circuit 40 and a low-side driving switch group 50; the pre-stage driving circuit 20 includes a second pre-stage driver GD2; the high-side driving switch group 30 includes a first control switch circuit 301, a first high-voltage resistant circuit 302 and a second high-voltage resistant circuit 303; the second high-voltage resistant circuit 303 includes a first switch tube (not shown) and a charge pump circuit (not shown).

[0120] It should be noted that, here only describes the connection relationship between the first control switch circuit 301, the first high-voltage resistant circuit 302 and the second high-voltage resistant circuit 303 when the high-side drive switch group 30 includes the first control switch circuit 301, the first high-voltage resistant circuit 302 and the second high-voltage resistant circuit 303, and the second high-voltage resistant circuit 303 includes the first switch tube (not shown) and the charge pump circuit (not shown). The connection relationship of the remaining circuits can refer to Figure 6 The relevant description of the driving circuit provided will not be repeated here.

[0121] The first end of the charge pump circuit is electrically connected to the control end of the first switching tube; the input end of the first switching tube (i.e., the first end of the second high-voltage resistant circuit 303) is electrically connected to the second end of the first high-voltage resistant circuit 302, and the output end of the first switching tube (i.e., the second end of the second high-voltage resistant circuit 303, i.e., the second end of the high-side drive switch group 30) is electrically connected to the first end of the common-mode supply circuit 40 at the CANH end; the first end of the first high-voltage resistant circuit 302 is electrically connected to the second end of the first control switch circuit 301, and the first end of the first control switch circuit 301 (i.e., the first end of the high-side drive switch group 30) is electrically connected to the second end of the second pre-stage driver GD2 (i.e., the second end of the pre-stage driver circuit 20).

[0122] The first switch tube (not shown) electrically connected to the CANH terminal in the high-side driver switch group 30 is an NMOS, and the second switch tube (not shown) electrically connected to the CANL terminal in the low-side driver switch group 50 is an NMOS.

[0123] When both the high-side driver switch group 30 and the low-side driver switch group 50 are not operating, the common mode supply circuit 40 provides a common mode voltage Vcm2 to the high-side port and the low-side port, respectively.

[0124] The second pre-stage driver GD2 receives the data signal TXD sent by the controller 102, and generates a first control signal CTL according to the data signal TXD when the data signal TXD is used to instruct the driving circuit to change from outputting the common mode voltage Vcm2 to outputting the non-common mode voltage. 111 and the second control signal CTL 121 .

[0125] The second pre-stage driver GD2 sends a first control signal CTL to the first control switch circuit 301 in the high-side driver switch group 30 111 , to control the first control switch circuit 301 to be turned on. The first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 are both turned on, and the first high-voltage withstand circuit 302 operates in the linear region. The first switch transistor in the second high-voltage withstand circuit 303 also operates in the linear region. The first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 can both suppress the reverse current at the CANH terminal.

[0126] The second pre-stage driver GD2 can also send a second control signal CTL to the low-side driver switch group 50 121 , to control the low-side drive switch group 50 to work and the second switch tube is in the linear region.

[0127] The second pre-stage driver GD2 can also generate a third control signal CTL according to the data signal TXD when the data signal TXD indicates that the driving circuit changes from outputting a non-common mode voltage to outputting a common mode voltage Vcm2. 112 and the fourth control signal CTL 122 .

[0128] The second pre-driver GD2 may also send a third control signal CTL to the first control switch circuit 301 112 , to control the first control switch circuit 301 to be turned off. When the first control switch circuit 301 is turned off, the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 are both turned off, which is equivalent to the high-side drive switch group 30 not working; at the same time, the second pre-stage driver GD2 also sends a fourth control signal CTL to the low-side drive switch group 50 122 , to control the low-side drive switch group 50 to not work.

[0129] Specifically, the first high-voltage-resistant circuit 302 and the second high-voltage-resistant circuit 303 can both suppress the reverse current at the CANH terminal. Specifically, the first high-voltage-resistant circuit 302 can suppress the reverse current when the CANH terminal is at a high positive voltage, and the second high-voltage-resistant circuit 303 can suppress the reverse current when the CANH terminal is at a high negative voltage. It is understood that for those skilled in the art, "high positive voltage" and "high negative voltage" are commonly used technical terms in this field, and therefore, this application will not elaborate on them.

[0130] The following combination Figure 5 ,illustrate Figure 7 The working principle of the driving circuit is provided.

[0131] like Figure 5As shown, during the time period t1, the data signal TXD output by the controller 102 to the second pre-stage driver GD2 is 0, and the second pre-stage driver GD2 generates the first control signal CTL according to the data signal TXD. 111 and the second control signal CTL 121 , and output the first control signal CTL to the first control switch circuit 301 in the high-side drive switch group 30 respectively. 111 , to control the first control switch circuit 301 to be turned on, and output the second control signal CTL to the low-side drive switch group 50 121 , to control the low-side drive switch group 50 to work, and the second switch tube works in the linear region.

[0132] When the first control switch circuit 301 is turned on, the first high voltage circuit 302 and the second high voltage circuit 303 are also turned on (i.e., the high side driver switch group 30 is working). The first switches in the first high voltage circuit 302 and the second high voltage circuit 303 both operate in the linear region.

[0133] Therefore, for the entire driving circuit, the current flows through the first control switch circuit 301 , the first high-voltage withstand circuit 302 , the second high-voltage withstand circuit 303 , the common-mode supply circuit 40 and the low-side driving switch group 50 .

[0134] Therefore, during the time period t1, the voltage outputted by the CANH terminal of the driving circuit changes from the common mode voltage Vcm2 of the previous time period to the first voltage VH2, and the voltage outputted by the CANL terminal of the driving circuit changes from the common mode voltage Vcm2 of the previous time period to the second voltage VL2.

[0135] When the CANH terminal outputs the first voltage VH2 and the CANL terminal outputs the second voltage VL2, data is exchanged between the CAN bus and the controller 102.

[0136] During the time period t2, the data signal TXD output by the controller 102 to the second pre-driver GD2 is 1, and the second pre-driver GD2 generates a third control signal CTL according to the data signal TXD. 112 and the fourth control signal CTL 122 , and output the third control signal CTL to the first control switch circuit 301 in the high-side drive switch group 30 respectively. 112 , to control the first control switch circuit 301 to be turned off, and output the fourth control signal CTL to the low-side drive switch group 50 122 , to control the low-side drive switch group 50 to not work.

[0137] Since the first control switch circuit 301 is turned off and the low-side drive switch group 50 is not working, there is no path in the drive circuit. Therefore, the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 are both turned off, that is, the high-side drive switch group 30 is not working. This is equivalent to, when the first control switch circuit 301 is turned off, the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 are both turned off.

[0138] When both the high-side drive switch group 30 and the low-side drive switch group 50 are not working, the common-mode supply circuit 40 provides a common-mode voltage Vcm2 to the CANH terminal and the CANL terminal, respectively. That is, the voltage output by the CANH terminal changes from the first voltage VH2 in the time period t1 to the common-mode voltage Vcm2, and the voltage output by the CANL terminal changes from the second voltage VL2 in the time period t1 to the common-mode voltage Vcm2.

[0139] When both the CANH terminal and the CANL terminal output the common mode voltage Vcm2, the data exchange between the CAN bus and the controller 102 ends.

[0140] Based on the above description of the connection relationship and working principle of the drive circuit provided in one embodiment of the present application, it can be understood that the drive circuit provided in the present application, first, because the first switch tube and the second switch tube operate in the linear region, the negative impact of the PNP junction is eliminated, and the output voltage of the CANH terminal and the CANL terminal of the drive circuit can be made more stable, which can improve the accuracy of data exchange. Second, because the first switch tube and the second switch tube are of NMOS type, compared with the prior art, in which the switch tube connected to the CANH terminal and the switch tube connected to the CANL terminal are PMOS type switch tubes, the conduction capability is improved, the parasitic capacitance is reduced, the impact on the EMC of the CAN bus is further reduced, and the communication distance of the CAN bus is further improved.

[0141] Based on the description of the above embodiment, the structure of the low-side driver switch group 50 is described in detail below.

[0142] Figure 8 A schematic diagram of a driving circuit according to an embodiment of the present invention is shown in FIG. Figure 8As shown, the drive circuit includes: a pre-stage drive circuit 20, a high-side drive switch group 30, a common-mode supply circuit 40 and a low-side drive switch group 50; the pre-stage drive circuit 20 includes a second pre-stage driver GD2; the high-side drive switch group 30 includes a first control switch circuit 301, a first high-voltage resistant circuit 302 and a second high-voltage resistant circuit 303; the second high-voltage resistant circuit 303 includes a first switch tube (not shown) and a charge pump circuit (not shown); the low-side drive switch group 50 includes a second control switch 501, a third high-voltage resistant circuit 502 and a fourth high-voltage resistant circuit 503; the fourth high-voltage resistant circuit includes a first power supply (not shown) and a second switch tube (not shown).

[0143] It should be noted that, here only describes the connection relationship between the second control switch circuit 501, the third high-voltage resistant circuit 502 and the fourth high-voltage resistant circuit 503 when the low-side drive switch group 50 includes the second control switch circuit 501, the third high-voltage resistant circuit 502 and the fourth high-voltage resistant circuit 503, and the fourth high-voltage resistant circuit 503 includes the first power supply (not shown) and the second switch tube (not shown). The connection relationship of the remaining circuits can refer to Figure 7 The relevant description of the driving circuit provided will not be repeated here.

[0144] The third end of the second pre-stage driver GD2 (i.e., the third end of the pre-stage driver circuit 20) is electrically connected to the first end of the second control switch circuit 501; the second end of the second control switch circuit 501 is electrically connected to the first end of the third high-voltage resistant circuit 502; the second end of the third high-voltage resistant circuit 502 is electrically connected to the input end of the second switch tube (i.e., the first end of the fourth high-voltage resistant circuit 503); the control end of the second switch tube is electrically connected to the first power supply (not shown), and the output end of the second switch tube (i.e., the second end of the fourth high-voltage resistant circuit 503) is electrically connected to the second end of the common-mode supply circuit 40 and the CANL end.

[0145] The first switch tube (not shown) electrically connected to the CANH terminal in the high-side driver switch group 30 is an NMOS, and the second switch tube (not shown) electrically connected to the CANL terminal in the low-side driver switch group 50 is an NMOS.

[0146] When both the high-side driver switch group 30 and the low-side driver switch group 50 are not operating, the common mode supply circuit 40 provides a common mode voltage Vcm2 to the high-side port and the low-side port, respectively.

[0147] The second pre-stage driver GD2 receives the data signal TXD sent by the controller 102, and generates a first control signal CTL according to the data signal TXD when the data signal TXD is used to instruct the driving circuit to change from outputting the common mode voltage Vcm2 to outputting the non-common mode voltage. 111 and the second control signal CTL 121, the non-common mode voltage includes a first voltage VH2 and a second voltage VL2.

[0148] The second pre-stage driver GD2 sends a first control signal CTL to the first control switch circuit 301 in the high-side driver switch group 30 111 , to control the first control switch circuit 301 to conduct. The charge pump circuit provides a first drive voltage to the first switch transistor, controlling the first switch transistor to conduct and operate in the linear region (i.e., the second high-voltage withstand circuit 303 is on and in the linear region). The first high-voltage withstand circuit 302 is also on and operates in the linear region. Both the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 are used to suppress reverse current at the CANH terminal.

[0149] The second pre-stage driver GD2 sends a second control signal CTL to the second control switch circuit 501 in the low-side driver switch group 50 121 , to control the second control switch circuit 501 to be turned on. The first power supply provides a second driving voltage to the second switch tube to control the second switch tube to be turned on and the second switch tube to be in the linear region (that is, the fourth high-voltage withstand circuit 503 is turned on and in the linear region, and the third high-voltage withstand circuit 502 is also turned on and operates in the linear region). The third high-voltage withstand circuit 502 and the fourth high-voltage withstand circuit 503 are both used to suppress reverse current at the CANL terminal.

[0150] The voltage value of the first driving voltage is greater than the voltage value of the second driving voltage.

[0151] The second pre-stage driver GD2 can also generate a third control signal CTL according to the data signal TXD when the data signal TXD is used to instruct the driving circuit to change from outputting a non-common mode voltage to outputting a common mode voltage Vcm2. 112 and the fourth control signal CTL 122 .

[0152] The second pre-stage driver GD2 can also send a third control signal CTL to the first control switch circuit 301 112 , to control the first control switch circuit 301 to be turned off. When the first control switch circuit 301 is turned off, the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 are both turned off, which is equivalent to the high-side drive switch group 30 not working.

[0153] At the same time, the second pre-stage driver GD2 can also send a fourth control signal CTL to the second control switch circuit 501. 122 , to control the second control switch circuit 501 to be turned off. When the second control switch circuit 501 is turned off, the third high-voltage withstand circuit 502 and the fourth high-voltage withstand circuit 503 are both turned off, which is equivalent to the low-side drive switch group 50 not working.

[0154] Among them, the third high-voltage resistant circuit 502 and the fourth high-voltage resistant circuit 503 are both used to suppress the reverse current of the CANL end. Specifically, the third high-voltage resistant circuit 502 can suppress the reverse current when the CANL end is a high positive voltage, and the fourth high-voltage resistant circuit 503 can suppress the reverse current when the CANL end is a high negative voltage.

[0155] The following combination Figure 5 ,illustrate Figure 8 The working principle of the driving circuit is provided.

[0156] like Figure 5 As shown, during the time period t1, the data signal TXD output by the controller 102 to the second pre-stage driver GD2 is 0, and the second pre-stage driver GD2 generates the first control signal CTL according to the data signal TXD. 111 and the second control signal CTL 121 , and output the first control signal CTL to the first control switch circuit 301 in the high-side drive switch group 30 respectively. 111 , to control the first control switch circuit 301 to be turned on, and output the second control signal CTL to the second control switch circuit 501 in the low-side drive switch group 50 121 , to control the second control switch circuit 501 to be turned on.

[0157] When the first control switch circuit 301 is turned on, the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 are also turned on (i.e., the high-side driver switch group 30 is in operation). The first switches in the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 both operate in the linear region. When the second control switch circuit 501 is turned on, the third high-voltage withstand circuit 502 and the fourth high-voltage withstand circuit 503 are also turned on (i.e., the low-side driver switch group 50 is in operation). The second switches in the third high-voltage withstand circuit 502 and the fourth high-voltage withstand circuit 503 both operate in the linear region.

[0158] Therefore, for the entire driving circuit, the current flows through the first control switch circuit 301, the first high-voltage resistant circuit 302, the second high-voltage resistant circuit 303, the common-mode supply circuit 40, the fourth high-voltage resistant circuit 503, the third high-voltage resistant circuit 502 to the second control switch 501.

[0159] Therefore, during the time period t1, the voltage outputted by the CANH terminal of the driving circuit changes from the common mode voltage Vcm2 of the previous time period to the first voltage VH2, and the voltage outputted by the CANL terminal of the driving circuit changes from the common mode voltage Vcm2 of the previous time period to the second voltage VL2.

[0160] When the CANH terminal outputs the first voltage VH2 and the CANL terminal outputs the second voltage VL2, data is exchanged between the CAN bus and the controller 102.

[0161] During the time period t2, the data signal TXD output by the controller 102 to the second pre-driver GD2 is 1, and the second pre-driver GD2 generates a third control signal CTL according to the data signal TXD. 112 and the fourth control signal CTL 122 , and output the third control signal CTL to the first control switch circuit 301 in the high-side drive switch group 30 respectively. 112 , to control the first control switch circuit 301 to be turned off, and output the fourth control signal CTL to the second control switch circuit 501 in the low-side drive switch group 50 122 , to control the second control switch circuit 501 to be turned off.

[0162] Since the first control switch circuit 301 is turned off and the second control switch circuit 501 is turned off, there is no path in the drive circuit. Therefore, the first high-voltage resistant circuit 302 and the second high-voltage resistant circuit 303 are both turned off, that is, the high-side drive switch group 30 does not work (equivalent to, under the action of the first control switch circuit 301, the first high-voltage resistant circuit 302 and the second high-voltage resistant circuit 303 are both turned off); therefore, the third high-voltage resistant circuit 502 and the fourth high-voltage resistant circuit 503 are both turned off, that is, the low-side drive switch group does not work (equivalent to, under the action of the second control switch circuit 501, the third high-voltage resistant circuit 502 and the fourth high-voltage resistant circuit 503 are both turned off).

[0163] When both the high-side drive switch group 30 and the low-side drive switch group 50 are not working, the common-mode supply circuit 40 provides a common-mode voltage Vcm2 to the CANH terminal and the CANL terminal, respectively. That is, the voltage output by the CANH terminal changes from the first voltage VH2 in the time period t1 to the common-mode voltage Vcm2, and the voltage output by the CANL terminal changes from the second voltage VL2 in the time period t1 to the common-mode voltage Vcm2.

[0164] When both the CANH terminal and the CANL terminal output the common mode voltage Vcm2, the data exchange between the CAN bus and the controller 102 ends.

[0165] Based on the above description of the connection relationship and working principle of the drive circuit provided in one embodiment of the present application, it can be understood that the drive circuit provided in the present application, first, because the first switch tube and the second switch tube operate in the linear region, the negative impact of the PNP junction is eliminated, and the output voltage of the CANH terminal and the CANL terminal of the drive circuit can be made more stable, which can improve the accuracy of data exchange. Second, because the first switch tube and the second switch tube are of NMOS type, compared with the prior art, in which the switch tube connected to the CANH terminal and the switch tube connected to the CANL terminal are PMOS type switch tubes, the conduction capability is improved, the parasitic capacitance is reduced, the impact on the EMC of the CAN bus is further reduced, and the communication distance of the CAN bus is further improved.

[0166] Based on the description of the above embodiment, the structure of the common mode supply circuit 40 is introduced in detail below.

[0167] As an optional embodiment, the common-mode supply circuit 40 may include a bleeder circuit. As another optional embodiment, the common-mode supply circuit 40 may include two bleeder circuits and a common-mode voltage source, etc., which are not particularly limited in this embodiment of the present application. To improve the accuracy of the driver circuit interaction data, the following exemplary description uses the example of the common-mode supply circuit 40 including two bleeder circuits and a common-mode voltage source as an example.

[0168] Figure 9 A schematic diagram of a driving circuit according to an embodiment of the present invention is shown in FIG. Figure 9 As shown, the drive circuit includes: a pre-stage drive circuit 20, a high-side drive switch group 30, a common-mode supply circuit 40 and a low-side drive switch group 50; the pre-stage drive circuit 20 includes a second pre-stage driver GD2; the high-side drive switch group 30 includes a first control switch circuit 301, a first high-voltage resistant circuit 302 and a second high-voltage resistant circuit 303; the second high-voltage resistant circuit 303 includes a first switch tube (not shown) and a charge pump circuit (not shown); the low-side drive switch group 50 includes a second control switch 501, a third high-voltage resistant circuit 502 and a fourth high-voltage resistant circuit 503; the fourth high-voltage resistant circuit 503 includes a first power supply (not shown) and a second switch tube (not shown); the common-mode supply circuit 40 includes a first discharge circuit 401, a second discharge circuit 402 and a common-mode voltage power supply 403.

[0169] It should be noted that, here only describes the connection relationship between the first bleeder circuit 401, the second bleeder circuit 402 and the common mode voltage power supply 403 when the common mode supply circuit 40 includes the first bleeder circuit 401, the second bleeder circuit 402 and the common mode voltage power supply 403. The connection relationship of the remaining circuits can refer to Figure 8The relevant description of the driving circuit provided will not be repeated here.

[0170] A first end of the first discharge circuit 401 (i.e., a first end of the common-mode supply circuit 40) is electrically connected to an output end of the first switching tube (not shown) (i.e., a second end of the second high-voltage withstand circuit 303) at the CANH terminal. A second end of the first discharge circuit 401 is electrically connected to a first end of the second discharge circuit 402 and a first end of the common-mode voltage power supply 403, respectively. A second end of the common-mode voltage power supply 403 is grounded GND. A second end of the second discharge circuit 402 (i.e., a second end of the common-mode supply circuit 40) is electrically connected to an input end of the second switching tube (not shown) (i.e., a second end of the fourth high-voltage withstand circuit 503) at the CANL terminal.

[0171] The first switch tube (not shown) electrically connected to the CANH terminal in the high-side driver switch group 30 is an NMOS, and the second switch tube (not shown) electrically connected to the CANL terminal in the low-side driver switch group 50 is an NMOS.

[0172] When both the high-side driver switch group 30 and the low-side driver switch group 50 are not operating, the first bleeder circuit 401 provides the common-mode voltage Vcm2 to the CANH terminal, and the second bleeder circuit 402 provides the common-mode voltage Vcm2 to the CANL terminal.

[0173] The common mode voltage Vcm2 is provided by the common mode voltage power supply 403 .

[0174] The second pre-stage driver GD2 receives the data signal TXD sent by the controller 102, and generates a first control signal CTL according to the data signal TXD when the data signal TXD is used to instruct the driving circuit to change from outputting the common mode voltage Vcm2 to outputting the non-common mode voltage. 111 and the second control signal CTL 121 , the non-common mode voltage includes a first voltage VH2 and a second voltage VL2.

[0175] The second pre-stage driver GD2 sends a first control signal CTL to the first control switch circuit 301 in the high-side driver switch group 30 111 , to control the first control switch circuit 301 to conduct. The charge pump circuit provides a first drive voltage to the first switch transistor, controlling the first switch transistor to conduct and operate in the linear region (i.e., the second high-voltage withstand circuit 303 is on and in the linear region). The first high-voltage withstand circuit 302 is also on and operates in the linear region. Both the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 are used to suppress reverse current at the CANH terminal.

[0176] The second pre-stage driver GD2 sends a second control signal CTL to the second control switch circuit 501 in the low-side driver switch group 50 121, to control the second control switch circuit 501 to conduct. The first power supply provides a second drive voltage to the second switch tube, controlling the second switch tube to conduct and operate in the linear region (i.e., the fourth high-voltage withstand circuit 503 is on and in the linear region). The third high-voltage withstand circuit 502 is also on and operates in the linear region. Both the third high-voltage withstand circuit 502 and the fourth high-voltage withstand circuit 503 are used to suppress reverse current at the CANL terminal.

[0177] The second pre-stage driver GD2 can also generate a third control signal CTL according to the data signal TXD when the data signal TXD is used to instruct the driving circuit to change from outputting a non-common mode voltage to outputting a common mode voltage Vcm2. 112 and the fourth control signal CTL 122 .

[0178] The second pre-stage driver GD2 can also send a third control signal CTL to the first control switch circuit 301 112 , to control the first control switch circuit 301 to be turned off. Under the action of the first control switch circuit 301, the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 are both turned off, which is equivalent to the high-side drive switch group 30 not working.

[0179] The second pre-driver GD2 can also send a fourth control signal CTL to the second control switch circuit 501. 122 , to control the second control switch circuit 501 to be turned off. When the second control switch 501 is turned off, the third high-voltage withstand circuit 502 and the fourth high-voltage withstand circuit 503 are both turned off, which is equivalent to the low-side drive switch group 50 not working.

[0180] The following combination Figure 5 ,illustrate Figure 9 The working principle of the driving circuit is provided.

[0181] like Figure 5 As shown, during the time period t1, the data signal TXD output by the controller 102 to the second pre-stage driver GD2 is 0, and the second pre-stage driver GD2 generates the first control signal CTL according to the data signal TXD. 111 and the second control signal CTL 121 , and output the first control signal CTL to the first control switch circuit 301 in the high-side drive switch group 30 respectively. 111 , to control the first control switch circuit 301 to be turned on, and output the second control signal CTL to the second control switch circuit 501 in the low-side drive switch group 50 121 , to control the second control switch circuit 501 to be turned on.

[0182] When the first control switch circuit 301 is turned on, the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 are also turned on (i.e., the high-side drive switch group 30 is working), wherein the first switch tubes in the first high-voltage withstand circuit 302 and the second high-voltage withstand circuit 303 both work in the linear region.

[0183] When the second control switch circuit 501 is turned on, the third high-voltage-resistant circuit 502 and the fourth high-voltage-resistant circuit 503 are also turned on (i.e., the low-side drive switch group 50 is working), wherein the second switch tubes in the third high-voltage-resistant circuit 502 and the fourth high-voltage-resistant circuit 503 both operate in the linear region.

[0184] Therefore, for the entire driving circuit, the direction of current flow is: flowing through the first control switch circuit 301, the first high-voltage resistant circuit 302, the second high-voltage resistant circuit 303, the first discharge circuit 401, the second discharge circuit 402, the fourth high-voltage resistant circuit 503, the third high-voltage resistant circuit 502 to the second control switch circuit 501.

[0185] Therefore, during the time period t1, the voltage outputted by the CANH terminal of the driving circuit changes from the common mode voltage Vcm2 of the previous time period to the first voltage VH2, and the voltage outputted by the CANL terminal of the driving circuit changes from the common mode voltage Vcm2 of the previous time period to the second voltage VL2.

[0186] When the CANH terminal outputs the first voltage VH2 and the CANL terminal outputs the second voltage VL2, data is exchanged between the CAN bus and the controller 102.

[0187] During the time period t2, the data signal TXD output by the controller 102 to the second pre-driver GD2 is 1, and the second pre-driver GD2 generates a third control signal CTL according to the data signal TXD. 112 and the fourth control signal CTL 122 , and output the third control signal CTL to the first control switch circuit 301 in the high-side drive switch group 30 respectively. 112 , to control the first control switch circuit 301 to be turned off, and output the fourth control signal CTL to the second control switch circuit 501 in the low-side drive switch group 50 122 , to control the second control switch circuit 501 to be turned off.

[0188] Since the first control switch circuit 301 is turned off and the second control switch circuit 501 is turned off, there is no path in the drive circuit. Therefore, the first high-voltage resistant circuit 302 and the second high-voltage resistant circuit 303 are both turned off, that is, the high-side drive switch group 30 does not work (equivalent to, under the action of the first control switch circuit 301, the first high-voltage resistant circuit 302 and the second high-voltage resistant circuit 303 are both turned off); therefore, the third high-voltage resistant circuit 502 and the fourth high-voltage resistant circuit 503 are both turned off, that is, the low-side drive switch group does not work (equivalent to, under the action of the second control switch circuit 501, the third high-voltage resistant circuit 502 and the fourth high-voltage resistant circuit 503 are both turned off).

[0189] When both the high-side drive switch group 30 and the low-side drive switch group 50 are not working, the common-mode voltage power supply 403 provides the common-mode voltage Vcm2 to the CANH terminal through the first end of the first discharge circuit 401, that is, the voltage output by the CANH terminal changes from the first voltage VH2 in the time period t1 to the common-mode voltage Vcm2; the common-mode voltage power supply 403 provides the common-mode voltage Vcm2 to the CANL terminal through the second end of the second discharge circuit 402, that is, the voltage at the CANL terminal changes from the second voltage VL2 in the time period t1 to the common-mode voltage Vcm2.

[0190] When both the CANH terminal and the CANL terminal output the common mode voltage Vcm2, the data exchange between the CAN bus and the controller 102 ends.

[0191] Based on the above description of the connection relationship and working principle of the drive circuit provided in one embodiment of the present application, it can be understood that the drive circuit provided in the present application, first, because the first switch tube and the second switch tube operate in the linear region, the negative impact of the PNP junction is eliminated, and the output voltage of the CANH terminal and the CANL terminal of the drive circuit can be made more stable, which can improve the accuracy of data exchange. Second, because the type of the first switch tube and the second switch tube is NMOS, compared with the prior art, in which the switch tube connected to the CANH terminal and the switch tube connected to the CANL terminal are PMOS type switch tubes, the conduction capability is improved, the parasitic capacitance is reduced, the impact on the EMC of the CAN bus is further reduced, and the communication distance of the CAN bus is further improved.

[0192] Based on the description of the above embodiments, the structures of the first control switch circuit 301, the first high-voltage resistant circuit 302, the second high-voltage resistant circuit 303, the second control switch circuit 501, the third high-voltage resistant circuit 502, the fourth high-voltage resistant circuit 503, the first discharge circuit 401, the second discharge circuit 402 and the common-mode voltage power supply 403 are specifically introduced below.

[0193] Figure 10A schematic diagram of a driving circuit according to an embodiment of the present invention is shown in FIG. Figure 10 As shown, the drive circuit includes: a pre-stage drive circuit 20, a high-side drive switch group 30, a common-mode supply circuit 40 and a low-side drive switch group 50; the pre-stage drive circuit 20 includes a second pre-stage driver GD2; the high-side drive switch group 30 includes a first control switch circuit 301, a first high-voltage resistant circuit 302 and a second high-voltage resistant circuit 303; the second high-voltage resistant circuit 303 includes a second high-voltage resistant tube 303A and a charge pump circuit 303B; the low-side drive switch group 50 includes a second control switch circuit 501, a third high-voltage resistant circuit 502 and a fourth high-voltage resistant circuit 503; the fourth high-voltage resistant circuit 503 includes a first power supply V1 and a fourth high-voltage resistant tube 503A; the common-mode supply circuit 40 includes a first discharge circuit 401, a second discharge circuit 402 and a common-mode voltage power supply 403.

[0194] The first control switch circuit 301 includes: a second power supply V2 and a first control switch 301A; the first high-voltage circuit 302 includes: a first high-voltage tube 302A and a first protection circuit 302B; the second high-voltage circuit 303 includes: a second high-voltage tube 303A and a charge pump circuit 303B.

[0195] The second control switch circuit 501 includes: a second control switch 501A; the third high-voltage circuit 502 includes: a third power supply V3 and a third high-voltage tube 502A; the fourth high-voltage circuit 503 includes: a fourth high-voltage tube 503A and a second protection circuit 503B.

[0196] The first discharge circuit 401 may include a second resistor R2, and may also include other circuits. This embodiment of the present application does not specifically limit this. In order to save manufacturing costs and reduce circuit volume, the following explanation is given by taking the first discharge circuit 401 including the second resistor R2 as an example.

[0197] The second discharge circuit 402 may include a third resistor R3, and may also include other circuits. This embodiment of the present application does not specifically limit this. In order to save manufacturing costs and reduce circuit volume, the second discharge circuit 402 including the third resistor R3 is used as an example for exemplary description.

[0198] The resistance values ​​of the second resistor R2 and the third resistor R3 can be selected according to actual conditions, and are not particularly limited in this embodiment of the present application.

[0199] The common mode supply voltage 403 includes a fourth power supply V4.

[0200] The voltage value of the fourth power source V4 is smaller than the voltage values ​​of the first power source V1 , the second power source V2 and the third power source V3 .

[0201] The voltage values ​​of the first power source V1 , the second power source V2 and the third power source V3 may be the same or different, and this embodiment of the present application does not impose any special limitation on this.

[0202] Among them, the first protection circuit 302B can be a Zener diode Z1, or it can be other protection circuits, etc. The embodiment of the present application does not specifically limit this. In order to reduce the volume of the circuit and reduce production costs, the following explanation will be given by taking the first protection circuit 302B as a Zener diode Z1 as an example. The Zener diode Z1 is used to protect the gate-source voltage of the first high-voltage tube 302A.

[0203] The second protection circuit 503B can be the first resistor R1 or other protection circuits, and this embodiment of the present application does not specifically limit this. To reduce the circuit size and production costs, the following description uses the second protection circuit 503B as the first resistor R1 as an example. The first resistor R1 is used to protect the gate-source voltage of the fourth high-voltage transistor 503A. The resistance value of the first resistor R1 can be selected based on actual conditions and is not specifically limited in this embodiment of the present application.

[0204] Among them, the first control switch 301A includes a third switch tube P1; the first high-voltage resistant tube 302A includes a fourth switch tube P2; the second high-voltage resistant tube 303A includes a first switch tube N1; the second control switch 501A includes a fifth switch tube N4; the third high-voltage resistant tube 502A includes a sixth switch tube N3; and the fourth high-voltage resistant tube 503A includes a second switch tube N2.

[0205] The first switch N1, the second switch N2, the third switch P1, the fourth switch P2, the fifth switch N4, and the sixth switch N3 may be MOS transistors, bipolar junction transistors (BJTs), or electronic switches such as relays, which are not particularly limited in the present embodiment. To reduce power consumption and cost of the drive circuit, MOS transistors are used as an example for the following explanation.

[0206] Among them, the fourth switch tube P2 is a MOS tube including a body diode (not shown), the first switch tube N1 is a MOS tube including a body diode (not shown), the second switch tube N2 is a MOS tube including a body diode (not shown), and the sixth switch tube N3 is a MOS tube including a body diode (not shown).

[0207] According to the characteristics of PMOS and NMOS, as well as circuit requirements, the following explanation is given by taking as an example that the first switch tube N1 is NMOS, the second switch tube N2 is NMOS, the third switch tube P1 is PMOS, the fourth switch tube P2 is PMOS, the fifth switch tube N4 is NMOS, and the sixth switch tube N3 is NMOS.

[0208] When the first switch transistor N1 is an NMOS, the second switch transistor N2 is an NMOS, the third switch transistor P1 is a PMOS, the fourth switch transistor P2 is a PMOS, the fifth switch transistor N4 is an NMOS, and the sixth switch transistor N3 is an NMOS, the specific connection of the drive circuit is as follows: the first end of the second pre-stage driver GD2 (i.e., the first end of the pre-stage driver circuit 20) is electrically connected to the controller 102, the second end of the second pre-stage driver GD2 (i.e., the second end of the pre-stage driver circuit 20) is electrically connected to the gate of the third switch transistor P1 (i.e., the first end of the first control switch circuit, i.e., the first end of the high-side driver switch group 30), and the third end of the second pre-stage driver GD2 (i.e., the third end of the pre-stage driver circuit 20) is electrically connected to the gate of the fifth switch transistor N4 (i.e., the first end of the second control switch circuit 501, i.e., the first end of the low-side driver switch group 50).

[0209] A first terminal of the charge pump circuit 303B is electrically connected to the gate (i.e., the control terminal) of the first switching transistor N1. The drain (i.e., the input terminal) of the first switching transistor N1 is electrically connected to the source (i.e., the second terminal of the first high-voltage withstand circuit 302) of the fourth switching transistor P2. The source (i.e., the output terminal) of the first switching transistor N1 is electrically connected to the first terminal of the second resistor R2 (i.e., the first terminal of the first bleeder circuit 401) at the CANH terminal. The second terminal of the second resistor R2 (i.e., the second terminal of the first bleeder circuit 401) is electrically connected to the first terminal of the third resistor R3 (i.e., the first terminal of the second bleeder circuit 402) and the first terminal of the fourth power supply V4 (i.e., the first terminal of the common-mode voltage power supply 403), respectively. The second terminal of the fourth power supply V4 (i.e., the second terminal of the common-mode voltage power supply 403) is grounded GND. The second terminal of the third resistor R3 (i.e., the second terminal of the second bleeder circuit 402) is electrically connected to the source (i.e., the output terminal) of the second switching transistor N2 at the CANL terminal.

[0210] The drain of the fourth switch transistor P2 (i.e., the first end of the first high-voltage withstand circuit 302) is electrically connected to the drain of the third switch transistor P1 (i.e., the second end of the first control switch circuit 301). The gate of the fourth switch transistor P2 is electrically connected to the anode of the Zener diode Z1 and the ground GND, respectively. The source of the fourth switch transistor P2 is also electrically connected to the cathode of the Zener diode Z1. The source of the third switch transistor P1 is electrically connected to the second power supply V2.

[0211] The drain of the fifth switch transistor N4 (i.e., the second end of the second control switch circuit 501) is electrically connected to the source of the sixth switch transistor N3 (i.e., the first end of the third high-voltage withstand circuit 502), and the source of the fifth switch transistor N4 is grounded GND. The gate of the sixth switch transistor N3 is electrically connected to the third power supply V3, and the drain of the sixth switch transistor N3 (i.e., the second end of the third high-voltage withstand circuit 502) is electrically connected to the drain (i.e., the input end) of the second switch transistor N2. The gate (i.e., the control end) of the second switch transistor N2 is electrically connected to the first power supply V1 and the first end of the first resistor R1, respectively. The source (i.e., the output end) of the second switch transistor N2 is also electrically connected to the second end of the first resistor R1.

[0212] When both the high-side driver switch group 30 and the low-side driver switch group 50 are not operating, the second resistor R2 provides a common-mode voltage Vcm2 to the CANH terminal, and the third resistor R3 provides a common-mode voltage Vcm2 to the CANL terminal.

[0213] The common mode voltage Vcm2 is provided by the common mode voltage power supply 403 .

[0214] The second pre-stage driver GD2 receives the data signal TXD sent by the controller 102, and generates a first control signal CTL according to the data signal TXD when the data signal TXD is used to instruct the driving circuit to change from outputting the common mode voltage Vcm2 to outputting the non-common mode voltage. 111 and the second control signal CTL 121 , the non-common mode voltage includes a first voltage VH2 and a second voltage VL2.

[0215] The second pre-driver GD2 sends a first control signal CTL to the third switch transistor P1 111 , to control the third switch P1 to turn on. The charge pump circuit 303B provides a first driving voltage to the first switch N1 to control the first switch N1 to turn on and operate in the linear region (i.e., the second high-voltage circuit 303 is turned on and in the linear region). The ground voltage controls the fourth switch P2 to also turn on and operate in the linear region (i.e., the first high-voltage circuit 302 is turned on and in the linear region). Both the first switch N1 and the fourth switch P2 are used to suppress reverse current at the CANH terminal.

[0216] The second pre-driver GD2 sends a second control signal CTL to the fifth switch N4 121, to control the fifth switch N4 to turn on. The first power supply V1 provides a second driving voltage to the second switch N2 to control the second switch N2 to turn on and operate in the linear region (i.e., the fourth high-voltage withstand circuit 503 is turned on and operates in the linear region). The third power supply V3 provides a third driving voltage to the sixth switch N3 to control the sixth switch N3 to turn on and operate in the linear region (i.e., the third high-voltage withstand circuit 502 is also turned on and operates in the linear region). The second switch N2 and the sixth switch N3 are both used to suppress reverse current at the CANL terminal.

[0217] The embodiment of the present application does not specifically limit the voltage value of the third driving voltage.

[0218] When both the high-side driver switch group 30 and the low-side driver switch group 50 are working, the voltage at the CANH terminal changes from the common mode voltage Vcm2 to the first voltage VH2, and the voltage at the CANL terminal changes from the common mode voltage Vcm2 to the second voltage VL2.

[0219] The second pre-stage driver GD2 can also generate a third control signal CTL according to the data signal TXD when the data signal TXD is used to instruct the driving circuit to change from outputting a non-common mode voltage to outputting a common mode voltage Vcm2. 112 and the fourth control signal CTL 122 .

[0220] The second pre-stage driver GD2 can also send a third control signal CTL to the third switch tube P1 112 When the third switch tube P1 is turned off, the fourth switch tube P2 and the first switch tube N1 are both turned off, which is equivalent to the high-side drive switch group 30 not working.

[0221] The second pre-stage driver GD2 can also send a fourth control signal CTL to the fifth switch tube N4. 122 When the fifth switch tube N4 is turned off, the sixth switch tube N3 and the second switch tube N2 are both turned off, which is equivalent to the low-side drive switch group 50 not working.

[0222] When the high-side driver switch group 30 is working and the low-side driver switch group 50 is not working, the voltage at the CANH terminal changes from the first voltage VH2 to the common mode voltage Vcm2, and the voltage at the CANL terminal changes from the second voltage VL2 to the common mode voltage Vcm2.

[0223] The following combination Figure 5 ,illustrate Figure 10 The working principle of the driving circuit is provided.

[0224] like Figure 5As shown, during the time period t1, the data signal TXD output by the controller 102 to the second pre-stage driver GD2 is 0, and the second pre-stage driver GD2 generates the first control signal CTL according to the data signal TXD. 111 and the second control signal CTL 121 , and the third switch tube P1 outputs the first control signal CTL 111 , to control the third switch tube P1 to be turned on, and output the second control signal CTL to the fifth switch tube N4 121 , to control the fifth switch tube N4 to be turned on.

[0225] The ground voltage controls the fourth switch transistor P2 to also turn on and operate in the linear region (i.e., the first high-voltage withstand circuit 302 is turned on and in the linear region). Since the third switch transistor P1 is turned on, the anode potential of the body diode of the fourth switch transistor P2 is higher than the cathode potential, so the body diode of the fourth switch transistor P2 is turned on.

[0226] The charge pump circuit 303B provides a first driving voltage to the first switch tube N1 to control the first switch tube N1 to be turned on and the first switch tube N1 is in the linear region (that is, the second high-voltage withstand circuit 303 is turned on and is in the linear region). For the body diode of the first switch tube N1, the anode potential is lower than the cathode potential, so the body diode of the first switch tube N1 is turned off.

[0227] The first power supply V1 provides a second driving voltage to the second switch N2 to control the second switch N2 to be turned on and to place the second switch N2 in the linear region (i.e., the fourth high-voltage withstand circuit 503 is turned on and in the linear region). Since the first switch N1 is turned on, the anode potential of the body diode of the second switch N2 is higher than the cathode potential, so the body diode of the second switch N2 is turned on.

[0228] The third power supply V3 provides a third driving voltage to the sixth switch N3 to control the sixth switch N3 to be turned on and to operate in the linear region (i.e., the third high-voltage withstand circuit 502 is also turned on and operates in the linear region). For the body diode of the sixth switch N3, the anode potential is lower than the cathode potential, so the body diode of the sixth switch N3 is turned off.

[0229] Therefore, for the entire drive circuit, the current flows from the second power supply V2, through the third switch tube P1, the body diode of the fourth switch tube P2, the first switch tube N1, the second resistor R2, the third resistor R3, the body diode of the second switch tube N2, the sixth switch tube N3, the fifth switch tube N4, and finally to the ground GND.

[0230] Therefore, during the time period t1, the voltage outputted by the CANH terminal of the driving circuit changes from the common-mode voltage Vcm2 of the previous time period to the first voltage VH2, and the voltage outputted by the CANL terminal of the driving circuit changes from the common-mode voltage Vcm2 of the previous time period to the second voltage VL2. When the CANH terminal outputs the first voltage VH2 and the CANL terminal outputs the second voltage VL2, data is exchanged between the CAN bus and the controller 102.

[0231] During the time period t2, the data signal TXD output by the controller 102 to the second pre-driver GD2 is 1, and the second pre-driver GD2 generates a third control signal CTL according to the data signal TXD. 112 and the fourth control signal CTL 122 , and output the third control signal CTL to the third switch tube P1 respectively 112 , to control the third switch tube P1 to be turned off, and output the fourth control signal CTL to the fifth switch tube N4 122 , to control the fifth switch tube N4 to be turned off.

[0232] Because the third switch P1 and the fifth switch N4 are turned off, no path exists in the drive circuit. Consequently, the fourth switch P2 and its body diode, as well as the first switch N1 and its body diode, are all turned off. This means that the high-side driver switch group 30 is inoperative (equivalent to the fourth switch P2 and the first switch N1 being turned off due to the third switch P1). Consequently, the sixth switch N3 and its body diode, as well as the second switch N2 and its body diode, are all turned off. This means that the low-side driver switch group is inoperative (equivalent to the sixth switch N3 and the second switch N2 being turned off due to the fifth switch N4).

[0233] When both the high-side drive switch group 30 and the low-side drive switch group 50 are not working, the common-mode voltage power supply 403 provides the common-mode voltage Vcm2 to the CANH terminal through the first end of the second resistor R2, that is, the voltage output by the CANH terminal changes from the first voltage VH2 in the time period t1 to the common-mode voltage Vcm2; the common-mode voltage power supply 403 provides the common-mode voltage Vcm2 to the CANL terminal through the second end of the third resistor R3, that is, the voltage at the CANL terminal changes from the second voltage VL2 in the time period t1 to the common-mode voltage Vcm2.

[0234] When both the CANH terminal and the CANL terminal output the common mode voltage Vcm2, the data exchange between the CAN bus and the controller 102 ends.

[0235] According to the above description of the connection relationship and working principle of the driving circuit provided in one embodiment of the present application, it can be known that the driving circuit provided in the present application has the following characteristics: first, since the first switch tube and the second switch tube operate in the linear region, the negative impact of the PNP junction is eliminated, and the output voltage of the CANH terminal and the CANL terminal of the driving circuit can be made more stable. Similarly, since the third switch tube and the fifth switch tube are low-voltage tubes, the control signal CTL can be used to control the output voltage of the CANH terminal and the CANL terminal. 11 and control signal CTL 12 This controls the slope of the voltage change at the CANL and CANH terminals, ensuring that the CANL and CANH terminals can output relatively stable voltages, further improving the accuracy of data exchange. Secondly, since the first and second switching transistors are NMOS, compared to the prior art where the switching transistors connected to the CANH terminal and the switching transistors connected to the CANL terminal are PMOS type switching transistors, the conduction capability is improved, the parasitic capacitance is reduced, and the impact on the EMC of the CAN bus is further reduced, further increasing the communication distance of the CAN bus.

[0236] An embodiment of the present application further provides a CAN transceiver, comprising: the driving circuit of any one of the above embodiments and a receiver, the receiver being electrically connected to the driving circuit;

[0237] The receiver is used to receive the signal sent by the driving circuit.

[0238] The CAN transceiver provided in the embodiment of the present application can achieve the same technical effect as the driving circuit of any one of the above embodiments. For the specific technical effects, please refer to the above related descriptions and will not be repeated here.

[0239] The embodiment of the present application further provides a CAN communication system, including:

[0240] At least one communication node and a CAN bus, the communication node including a controller and a CAN transceiver as described above;

[0241] The CAN bus includes: a first terminal and a second terminal; the CAN transceiver includes a third terminal and a fourth terminal;

[0242] The controller is electrically connected to the CAN transceiver;

[0243] The third end of the CAN transceiver is electrically connected to the first end of the CAN bus, and the fourth end of the CAN transceiver is electrically connected to the second end of the CAN bus.

[0244] Another embodiment of the present application provides a CAN communication system. A CAN bus includes a CANH line and a CANL line. In this CAN communication system, a first end of the CAN bus is a high-voltage port of the CANH line. A second end of the CAN bus is a low-voltage port of the CANL line. A third end of the CAN transceiver is a high-side port of the CAN transceiver. A fourth end of the CAN transceiver is a low-side port of the CAN transceiver.

[0245] In a fourth aspect, an embodiment of the present application provides an automotive-grade chip, comprising: a driving circuit as in any one of the first aspect; and / or a CAN transceiver as in the second aspect.

[0246] A fourth aspect of the present application provides an automotive-grade chip. This automotive-grade chip includes any of the aforementioned drive circuits and / or the CAN transceiver according to the second aspect. This automotive-grade chip is a type of MCU chip. An automotive-grade chip is a chip that meets automotive-grade technical standards and can be used in automotive control systems. Automotive-grade refers to a standard level of specifications applicable to automotive electronic components.

[0247] The chip provided in the embodiment of the present application can achieve the same technical effect as the driving circuit in any of the above embodiments. For the specific technical effects, please refer to the above related descriptions and will not be repeated here.

[0248] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include at least one of such features.

[0249] In addition, in the description of the present application, it should be understood that the terms "longitudinal", "horizontal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "vertical", "top", "bottom", "inside", "outside", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0250] In addition, in this application, unless otherwise clearly specified and limited, the terms "connection", "connected", etc. should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection between two elements or the interaction relationship between two elements. Unless otherwise clearly specified, ordinary technicians in this field can understand the specific meanings of the above terms in this application according to specific circumstances.

[0251] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving circuit, characterized in that: Applied to CAN transceiver; The driving circuit includes: a front-stage driving circuit, a high-side driving switch group, a common-mode supply circuit and a low-side driving switch group; A first end of the pre-stage driver circuit is electrically connected to a controller, a second end of the pre-stage driver circuit is electrically connected to a first end of the high-side driver switch group, and a third end of the pre-stage driver circuit is electrically connected to a first end of the low-side driver switch group; a first end of the common-mode supply circuit is electrically connected to a second end of the high-side driver switch group and a high-side port of the driver circuit, and a second end of the common-mode supply circuit is electrically connected to a second end of the low-side driver switch group and a low-side port of the driver circuit; The first switch tube in the high-side drive switch group electrically connected to the high-side port is an NMOS, and the second switch tube in the low-side drive switch group electrically connected to the low-side port is an NMOS; The common-mode supply circuit is configured to provide a common-mode voltage to the high-side port and the low-side port respectively when both the high-side drive switch group and the low-side drive switch group are not in operation; The pre-stage driving circuit is configured to receive a data signal sent by the controller and, when the data signal is used to instruct the driving circuit to change from outputting the common-mode voltage to outputting a non-common-mode voltage, generate a first control signal and a second control signal according to the data signal, wherein the non-common-mode voltage includes a first voltage and a second voltage; The pre-stage driver circuit is further configured to send the first control signal to the high-side driver switch group to control the high-side driver switch group to operate and the first switch transistor to be in the linear region, and send the second control signal to the low-side driver switch group to control the low-side driver switch group to operate and the second switch transistor to be in the linear region; When both the high-side drive switch group and the low-side drive switch group are working, the voltage of the high-side port changes from the common-mode voltage to the first voltage, and the voltage on the low-side port changes from the common-mode voltage to the second voltage.

2. The driving circuit according to claim 1, wherein: The pre-stage driving circuit is further configured to generate a third control signal and a fourth control signal according to the data signal when the data signal is used to instruct the driving circuit to change from outputting the non-common mode voltage to outputting the common mode voltage; The pre-stage driver circuit is further configured to send the third control signal to the high-side driver switch group to control the high-side driver switch group to not operate, and send the fourth control signal to the low-side driver switch group to control the low-side driver switch group to not operate; When the high-side drive switch group is working and the low-side drive switch group is not working, the voltage of the high-side port changes from the first voltage to the common-mode voltage, and the voltage on the low-side port changes from the second voltage to the common-mode voltage.

3. The driving circuit according to claim 1 or 2, characterized in that: The first switch tube is further electrically connected to a charge pump circuit, and the charge pump circuit is used to provide a first driving voltage to the first switch tube to control the first switch tube to be turned on and the first switch tube to be in a linear region; The second switch tube is also electrically connected to a first power supply, and the first power supply is used to provide a second driving voltage to the second switch tube to control the second switch tube to be turned on and the second switch tube is in a linear region; Wherein, a voltage value of the first driving voltage is greater than a voltage value of the second driving voltage.

4. The driving circuit according to claim 3, wherein: The high-side drive switch group includes: a first control switch circuit, a first high-voltage resistant circuit and a second high-voltage resistant circuit; the second high-voltage resistant circuit includes the first switch tube and the charge pump circuit; The first end of the charge pump circuit is electrically connected to the control end of the first switching tube; the input end of the first switching tube is electrically connected to the second end of the first high-voltage resistant circuit, and the output end of the first switching tube is electrically connected to the first end of the common-mode supply circuit at the high-side port; the first end of the first high-voltage resistant circuit is electrically connected to the second end of the first control switching circuit, and the first end of the first control switching circuit is electrically connected to the second end of the pre-stage driver circuit; The first control switch circuit is configured to receive a first control signal sent by the pre-stage driver circuit, wherein the first control switch circuit is turned on under the action of the first control signal; when the first control switch circuit is turned on, the first high-voltage withstand circuit and the first switch tube are both turned on to suppress the reverse current of the high-side port; The first control switch circuit is also used to receive a third control signal sent by the pre-stage driving circuit, wherein, under the action of the third control signal, the first control switch circuit is turned off; when the first control switch circuit is turned off, the first high-voltage resistant circuit and the first switch tube are both turned off.

5. The driving circuit according to claim 3, wherein: The low-side drive switch group includes: a second control switch circuit, a third high-voltage resistant circuit and a fourth high-voltage resistant circuit; the fourth high-voltage resistant circuit includes a first resistor, the second switch tube and the first power supply; The control end of the second switching tube is electrically connected to the first end of the first power supply and the first end of the first resistor, respectively; the input end of the second switching tube is electrically connected to the second end of the third high-voltage-resistant circuit; the output end of the second switching tube is electrically connected to the second end of the first resistor and the second end of the common-mode supply circuit at the low-side port, respectively; the first end of the third high-voltage-resistant circuit is electrically connected to the second end of the second control switching circuit; and the first end of the second control switching circuit is electrically connected to the third end of the pre-stage driver circuit. The second control switch circuit is configured to receive a second control signal sent by the pre-stage driver circuit, wherein the second control switch circuit is turned on under the action of the second control signal; when the second control switch circuit is turned on, the third high-voltage withstand circuit and the second switch tube are both turned on to suppress the reverse current of the low-side port; The second control switch circuit is also used to receive a fourth control signal sent by the pre-stage driving circuit, wherein, under the action of the fourth control signal, the second control switch circuit is turned off; when the second control switch circuit is turned off, the third high-voltage resistant circuit and the second switch tube are both turned off.

6. The driving circuit according to claim 4 or 5, characterized in that: The common mode supply circuit includes: a first bleeder circuit, a second bleeder circuit and a common mode voltage power supply; A first end of the first bleeder circuit is electrically connected to the output end of the first switch tube at the high-side port, a second end of the first bleeder circuit is electrically connected to the first end of the common-mode voltage power supply and the first end of the second bleeder circuit respectively; a second end of the second bleeder circuit is electrically connected to the second switch tube at the low-side port; a second end of the common-mode voltage power supply is grounded; When both the high-side drive switch group and the low-side drive switch group are not working, the common-mode voltage power supply provides the common-mode voltage to the high-side port through the first bleeder circuit, and provides the common-mode voltage to the low-side port through the second bleeder circuit.

7. A CAN transceiver, characterized in that: include: The driving circuit and receiver according to any one of claims 1 to 6, wherein the receiver is electrically connected to the driving circuit; The receiver is used to receive the signal sent by the driving circuit.

8. A CAN communication system, characterized in that: comprising at least one communication node and a CAN bus, wherein the communication node comprises a controller and the CAN transceiver according to claim 7; The CAN bus includes: a first end and a second end; the CAN transceiver includes a third end and a fourth end; The controller is electrically connected to the CAN transceiver; The third end of the CAN transceiver is electrically connected to the first end of the CAN bus, and the fourth end of the CAN transceiver is electrically connected to the second end of the CAN bus.

9. The CAN communication system according to claim 8, characterized in that: The controller includes a CAN controller or an MCU controller.

10. An automotive-grade chip, characterized in that: include: The driving circuit according to any one of claims 1 to 6; and / or the CAN transceiver according to claim 7.

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