IO sampling methods and devices, electronic equipment

Abstract

This disclosure provides an I / O sampling method, apparatus, and electronic device. The I / O sampling method includes: receiving an I / O input signal; sampling the I / O input signal on the rising edge and falling edge according to a clock cycle signal to obtain a rising edge sampled signal and a falling edge sampled signal; comparing the rising edge sampled signal and the falling edge sampled signal to obtain a comparison result; selecting a signal to be output from a previously output sampled signal and a current sampled signal based on the comparison result, wherein the current sampled signal is either the rising edge sampled signal or the falling edge sampled signal; and outputting the signal to be output as a sampled signal corresponding to the I / O input signal. This technical solution can improve the I / O sampling accuracy in scenarios with numerous glitches and jitter.

Description

Technical Field

[0001] This disclosure belongs to the field of integrated circuit technology and relates to I / O sampling methods and apparatus, and electronic equipment. Background Technology

[0002] In signal transmission, GPIO (General Purpose Input / Output) debouncing and filtering are necessary to ensure accuracy. For example, in industrial control applications, signal jitter is often caused by factors such as electromagnetic radiation, thus placing higher demands on the chip's IO (Input / Output) debouncing and glitching capabilities. Figure 1 The debouncing shown targets the bounce of mechanical buttons, such as a low level bouncing to a high level, where the bounce must return to a stable value within the expected time. Figure 2 The filter shown is designed to address signal abrupt changes and glitches caused by electromagnetic radiation interference in industrial control applications. These abrupt changes are unpredictable and may occur at any time or persist indefinitely.

[0003] To address the aforementioned jitter, typical circuit designs can debouncing signal changes within a single clock cycle. However, this logic overlooks the issue of register metastability. When a glitch signal from the I / O input occurs during this metastability, the glitch may be input to the GPIO input. This can lead to incorrect pulse input from the I / O. This problem is particularly pronounced in industrial control scenarios with high signal noise. Summary of the Invention

[0004] This disclosure provides an IO sampling method, apparatus, and electronic device for debouncing and de-glitching IO input signals to avoid erroneous sampling of IO input signals and to achieve filtering of IO input signals.

[0005] In a first aspect, embodiments of this disclosure provide an I / O sampling method. The I / O sampling method includes: receiving an I / O input signal; performing rising edge sampling and falling edge sampling on the I / O input signal according to a clock cycle signal to obtain a rising edge sampled signal and a falling edge sampled signal; comparing the rising edge sampled signal and the falling edge sampled signal to obtain a comparison result; selecting a signal to be output from a previously output sampled signal and a current sampled signal based on the comparison result, wherein the current sampled signal is either the rising edge sampled signal or the falling edge sampled signal; and outputting the signal to be output as a sampled signal corresponding to the I / O input signal.

[0006] In one implementation of the first aspect, sampling the IO input signal for rising edge and falling edge according to the clock cycle signal to obtain the rising edge sample signal and the falling edge sample signal includes: sampling the IO input signal according to the rising edge and falling edge of one clock cycle of the clock cycle signal, or according to the falling edge of one clock cycle of the clock cycle signal and the rising edge of the next clock cycle to obtain the rising edge sample signal and the falling edge sample signal.

[0007] In one implementation of the first aspect, sampling the IO input signal on the rising edge and the falling edge according to the clock cycle signal to obtain the rising edge sample signal and the falling edge sample signal includes: sampling the IO input signal on the rising edge and the falling edge according to the clock cycle signal, such that when the IO input signal contains jitter or glitches, the rising edge sample signal is different from the falling edge sample signal.

[0008] In one implementation of the first aspect, comparing the rising edge sampling signal and the falling edge sampling signal to obtain a comparison result includes: if the rising edge sampling signal is the same as the falling edge sampling signal, then outputting a first comparison signal having a first level; and if the rising edge sampling signal is not the same as the falling edge sampling signal, then outputting a second comparison signal having a second level opposite to the first level.

[0009] In one implementation of the first aspect, selecting a signal to be output from the previously output sampled signal and the current sampled signal based on the comparison result includes: selecting the current sampled signal according to the first comparison signal during the current clock cycle of the clock cycle signal; and selecting the previously output sampled signal according to the second comparison signal during the current clock cycle, wherein the previously output sampled signal has been output during the current clock cycle.

[0010] In one implementation of the first aspect, outputting the signal to be output as a sampled signal corresponding to the IO input signal includes: temporarily storing the selected signal to be output during the current clock cycle of the clock cycle signal; and outputting the signal to be output as the sampled signal during the next clock cycle of the clock cycle signal.

[0011] In one implementation of the first aspect, sampling the IO input signal on the rising edge and on the falling edge according to the clock cycle signal to obtain the rising edge sampled signal and the falling edge sampled signal includes: sampling the IO input signal using a rising edge sampling D flip-flop according to the clock cycle signal to obtain the rising edge sampled signal; and sampling the IO input signal using a falling edge sampling D flip-flop according to the clock cycle signal to obtain the falling edge sampled signal.

[0012] In one implementation of the first aspect, comparing the rising edge sampled signal and the falling edge sampled signal to obtain a comparison result includes performing an XOR operation on the rising edge sampled signal and the falling edge sampled signal.

[0013] In one implementation of the first aspect, the IO sampling method further includes: receiving a selection signal; and selecting a sampling signal from the rising edge sampling signal and the falling edge sampling signal as the current sampling signal according to the selection signal.

[0014] In one implementation of the first aspect, the IO sampling method further includes: down-converting or dividing the clock cycle signal so that half of the clock cycle length is greater than the width of the jitter or glitches contained in the IO input signal.

[0015] Secondly, embodiments of this disclosure provide an I / O sampling device. The I / O sampling device includes: an input terminal configured to receive an I / O input signal; a sampling circuit configured to sample the I / O input signal on the rising edge and on the falling edge according to a clock cycle signal to output a rising edge sampled signal and a falling edge sampled signal; an arithmetic circuit configured to compare the rising edge sampled signal and the falling edge sampled signal to output a comparison result; a signal selection circuit configured to select and output a signal to be output from a previously output sampled signal and a current sampled signal based on the comparison result, wherein the current sampled signal is either the rising edge sampled signal or the falling edge sampled signal; and an output circuit configured to output the signal to be output as a sampled signal corresponding to the I / O input signal.

[0016] In one implementation of the second aspect, the sampling circuit includes: a first D flip-flop configured to receive the IO input signal and the clock cycle signal, and to sample the IO input signal according to the rising edge of the clock cycle signal to output the rising edge sampled signal; and a second D flip-flop configured to receive the IO input signal and the clock cycle signal, and to sample the IO input signal according to the falling edge of the clock cycle signal to output the falling edge sampled signal.

[0017] In one implementation of the second aspect, the arithmetic circuit includes an XNOR gate configured to receive the rising edge sampling signal and the falling edge sampling signal, and to perform an XNOR operation on the rising edge sampling signal and the falling edge sampling signal to output a first comparison signal having a first level or a second comparison signal having a second level opposite to the first level as the comparison result.

[0018] In one implementation of the second aspect, the signal selection circuit includes: a first selector configured to receive the comparison result, the current sampled signal, and the previously output sampled signal; select and output the current sampled signal as the signal to be output when the comparison result is the first comparison signal; and select and output the previously output sampled signal as the signal to be output when the comparison result is the second comparison signal.

[0019] In one implementation of the second aspect, the output circuit includes: a register configured to receive the clock cycle signal and the signal to be output, to temporarily store the signal to be output in the current clock cycle of the clock cycle signal, and to output the signal to be output as the sampling signal in the next clock cycle of the clock cycle signal.

[0020] In one implementation of the second aspect, the IO sampling device further includes: a second selector configured to receive a selection signal, the rising edge sampling signal, and the falling edge sampling signal, and to select one of the rising edge sampling signal and the falling edge sampling signal as the current sampling signal according to the selection signal.

[0021] Thirdly, embodiments of this disclosure provide an electronic device. The electronic device includes: an I / O sampling device as described above; and at least one sensor interface, a communication interface, and a touchscreen interface, configured to receive the sampling signal from the I / O sampling device.

[0022] This disclosure improves the accuracy of I / O sampling in scenarios with numerous glitches and jitter. After a first-stage sampling along both rising and falling edges, signal glitches are filtered out, preventing incorrect pulse judgments caused by glitches. Register sampling of the selected output signal ensures that the second-stage output signal does not exhibit metastability. Attached Figure Description

[0023] Figure 1 The diagram shows a first application scenario of the IO sampling method described in this embodiment.

[0024] Figure 2This diagram illustrates a second application scenario of the IO sampling method described in this embodiment.

[0025] Figure 3 The flowchart shown is an example of the IO sampling method described in this disclosure.

[0026] Figure 4 The diagram shown is a schematic diagram of the IO sampling device according to an embodiment of this disclosure.

[0027] Figure 5 The diagram shown is a first circuit schematic of the IO sampling device according to an embodiment of this disclosure.

[0028] Figure 6 The diagram shown is a second circuit schematic of the IO sampling device according to an embodiment of this disclosure.

[0029] Figure 7 The diagram shown is a signal timing diagram of the IO sampling device described in an embodiment of this disclosure.

[0030] Figure 8 The diagram shown is a third circuit schematic of the IO sampling device according to an embodiment of this disclosure.

[0031] Figure 9 The diagram shown is a fourth circuit schematic of the IO sampling device according to an embodiment of this disclosure.

[0032] Figure 10 The diagram shown is a structural schematic of the electronic device described in an embodiment of this disclosure. Detailed Implementation

[0033] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0034] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. Therefore, the illustrations only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0035] In existing technologies, D flip-flops or registers used to sample I / O input signals exhibit metastability. When jitter or glitches in the I / O input signal happen to occur within this metastability state, these jitters or glitches may be input to the GPIO. This can lead to incorrect pulse inputs from the I / O. This problem is particularly prominent in industrial control scenarios with high signal noise.

[0036] To address at least the aforementioned problems, embodiments of this disclosure provide an I / O sampling scheme that achieves debouncing and glitching of the I / O input signal by simultaneously sampling the rising and falling edges according to a clock cycle signal. The clock cycle signal is configured such that half the length of the clock cycle is greater than the width of the jitter or glitches contained in the I / O input signal. Sampling the I / O input signal on both the rising and falling edges according to the clock cycle signal ensures that when jitter or glitches are present in the I / O input signal, the rising edge sampled signal differs from the falling edge sampled signal; in this case, the previously output sampled signal is used instead of the current sampled signal. When the rising edge sampled signal and the falling edge sampled signal are the same, it indicates that the I / O input signal does not contain jitter or glitches; in this case, either the rising edge sampled signal or the falling edge sampled signal is output as the sampling signal for the I / O input signal. In this way, debouncing and glitching of the I / O input signal are achieved.

[0037] Please see Figure 1 and Figure 2 , Figure 1 The diagram shown is a first application scenario of the IO sampling method described in this embodiment of the present disclosure. Figure 2 This diagram illustrates a second application scenario of the IO sampling method described in an embodiment of this disclosure. The following embodiments of this disclosure provide IO sampling methods, apparatuses, and electronic devices, including but not limited to those addressing various signal jitter issues during signal transmission. On one hand, this disclosure can be applied to… Figure 1 The bouncing of the mechanical button shown, for example, from a low level to a high level after bouncing, will definitely return to a stable value within the expected time. On the other hand, this disclosure can be applied to... Figure 2 The signal abrupt changes and glitches caused by electromagnetic radiation interference in industrial control applications are shown. These abrupt changes are unpredictable and may occur at any time or persist indefinitely.

[0038] The technical solutions in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0039] Figure 3 The diagram shows a flowchart of the IO sampling method described in an embodiment of this disclosure. Figure 3 As shown, this embodiment provides an IO sampling method including the following steps S31 to S35.

[0040] In step S31, the IO input signal is received.

[0041] Specifically, depending on the application scenario, the IO input signal can be the input signal of a temperature sensor, pressure sensor or motion sensor, or the input signal of a communication line, or the input signal of a touch screen and touch screen controller.

[0042] In step S32, the IO input signal is sampled on the rising edge and the falling edge according to the clock cycle signal to obtain the rising edge sampled signal and the falling edge sampled signal.

[0043] In one embodiment, the IO input signal is sampled based on the rising edge and falling edge of one clock cycle of the clock cycle signal, or based on the falling edge of one clock cycle of the clock cycle signal and the rising edge of the next clock cycle, to obtain the rising edge sample signal and the falling edge sample signal.

[0044] Furthermore, in one embodiment, a rising-edge sampling D flip-flop is used to sample the IO input signal according to the clock cycle signal to obtain the rising-edge sampling signal, and a falling-edge sampling D flip-flop is used to sample the IO input signal according to the clock cycle signal to obtain the falling-edge sampling signal.

[0045] In one embodiment, the IO input signal is sampled on the rising edge and the falling edge according to the clock cycle signal, such that when the IO input signal contains jitter or glitches, the rising edge sampled signal is different from the falling edge sampled signal.

[0046] In step S33, the rising edge sampling signal and the falling edge sampling signal are compared to obtain a comparison result.

[0047] In one embodiment, if the rising edge sampling signal is the same as the falling edge sampling signal, a first comparison signal with a first level is output. If the rising edge sampling signal is not the same as the falling edge sampling signal, a second comparison signal with a second level opposite to the first level is output.

[0048] In one embodiment, comparing the rising edge sampled signal and the falling edge sampled signal to obtain a comparison result includes performing an XOR operation on the rising edge sampled signal and the falling edge sampled signal.

[0049] It should be noted that when obtaining the comparison result, it can be an XOR operation or a circuit implementation that achieves the same effect as an XOR operation. The same effect means that abnormal glitch pulses can be isolated.

[0050] In step S34, a signal to be output is selected from the previously output sampled signal and the current sampled signal based on the comparison result. The current sampled signal is either the rising edge sampled signal or the falling edge sampled signal.

[0051] In one embodiment, the current clock cycle in the clock cycle signal selects the current sampled signal according to the first comparison signal, and the previously output sampled signal is selected according to the second comparison signal in the current clock cycle, wherein the previously output sampled signal has been output in the current clock cycle.

[0052] Specifically, the function of the input unit for the output signal of the XNOR gate is to select either the 0-port signal or the 1-port signal based on the output signal of the XNOR gate. When the XNOR gate outputs 1, the 1-port input is selected; when the XNOR gate outputs 0, the 0-port input is selected. In practical applications, the device that implements the output selection function can be a selector in an electronic circuit.

[0053] An XNOR gate is used to isolate abnormal glitch pulses. Only when the XNOR gate result is 1 will the sampled rising edge or falling edge signal be input; otherwise, the original state is maintained, i.e., the output signal of the previous clock is selected for output. A XNOR gate output signal of 1 indicates that the input result is relatively stable and not an abnormal glitch.

[0054] In step S35, the signal to be output is output as a sampling signal corresponding to the IO input signal.

[0055] In one embodiment, the selected output signal is temporarily stored in the current clock cycle of the clock cycle signal, and the output signal is output as the sampling signal in the next clock cycle of the clock cycle signal.

[0056] In one embodiment, the IO sampling method may further include: receiving a selection signal, and selecting a sampling signal from the rising edge sampling signal and the falling edge sampling signal as the current sampling signal according to the selection signal.

[0057] In one embodiment, the IO sampling method may further include: down-converting or dividing the clock cycle signal so that half of the clock cycle length is greater than the width of the jitter or glitches contained in the IO input signal.

[0058] The scope of protection of the IO sampling method described in this disclosure is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this disclosure is included within the scope of protection of this disclosure.

[0059] This disclosure also provides an IO sampling device that can implement the IO sampling method described in this disclosure. However, the implementation device for the IO sampling method described in this disclosure includes, but is not limited to, the structure of the IO sampling device listed in this embodiment. Any structural modifications and substitutions of the prior art made based on the principles of this disclosure are included within the protection scope of this disclosure.

[0060] Figure 4 The diagram shown is a structural schematic of the IO sampling device according to an embodiment of this disclosure. Figure 4 As shown, this embodiment provides an IO sampling device 5, which includes an input terminal 51, a sampling circuit 52, an arithmetic circuit 53, a signal selection circuit 54, and an output circuit 55.

[0061] The input terminal 51 is configured to receive I / O input signals.

[0062] The sampling circuit 52 is configured to sample the IO input signal on the rising edge and on the falling edge according to the clock cycle signal to output a rising edge sampled signal and a falling edge sampled signal.

[0063] The arithmetic circuit 53 is configured to compare the rising edge sampled signal and the falling edge sampled signal to output a comparison result.

[0064] The signal selection circuit 54 is configured to select and output a signal to be output from the previously output sampled signal and the current sampled signal based on the comparison result, wherein the current sampled signal is the rising edge sampled signal or the falling edge sampled signal.

[0065] The output circuit 55 is configured to output the signal to be output as a sampled signal corresponding to the IO input signal.

[0066] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus or method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of circuit modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0067] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this disclosure, depending on actual needs. For example, the functional modules / units in the various embodiments of this disclosure may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0068] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0069] Figure 5 The diagram shown is a first circuit schematic of the IO sampling circuit according to an embodiment of this disclosure. Figure 5 As shown, this embodiment of the present disclosure provides an IO sampling device 5, which includes: an input terminal 51, a sampling circuit 52, an arithmetic circuit 53, a signal selection circuit 54, and an output circuit 55.

[0070] The input terminal 51 is configured to receive the IO input signal gpio_in.

[0071] The sampling circuit 52 is configured to sample the IO input signal gpio_in on the rising edge and the falling edge according to the clock cycle signal db_clk, so as to output the rising edge sampled signal gpio_in_pos and the falling edge sampled signal gpio_in_neg.

[0072] The arithmetic circuit 53 is configured to compare the rising edge sampling signal gpio_in_pos and the falling edge sampling signal gpio_in_neg to output a comparison result.

[0073] The signal selection circuit 54 is configured to select and output a signal to be output from the previously output sampled signal db_gpio_in and the current sampled signal gpio_in_pos, based on the comparison result xnor_vld, wherein the current sampled signal is either the rising edge sampled signal or the falling edge sampled signal.

[0074] The output circuit 55 is configured to output the signal to be output, db_gpio_in_D, as a sampling signal corresponding to the IO input signal.

[0075] In one embodiment, the output circuit 55 includes a register. The register is configured to receive the clock cycle signal and the signal to be output, temporarily store the signal to be output in the current clock cycle of the clock cycle signal, and output the signal to be output as the sampled signal in the next clock cycle of the clock cycle signal.

[0076] Specifically, the signal to be output is sampled by a register to obtain db_gpio_in, and the output signal db_gpio_in_D is used as the sampling signal corresponding to the IO input signal. In practical applications, a D flip-flop is used to implement the register function. In practical applications, such as... Figure 5 As shown, the input signal of the current clock (i.e., the input at terminal 1 of the signal selection circuit 54) uses a fixed rising edge sampling signal gpio_in_pos as the input. In another practical application, the input signal of the current clock (i.e., the input at terminal 1 of the signal selection circuit 54) can also use a fixed falling edge sampling signal gpio_in_neg as the input.

[0077] like Figure 5 As shown, the sampling circuit 52 includes a first D flip-flop and a second D flip-flop.

[0078] The first D flip-flop is configured such that the first clk terminal (the clk terminal without a circle) receives the clock cycle signal, the first D input terminal receives the IO input signal, and the IO input signal is sampled according to the rising edge of the clock cycle signal to output the rising edge sampled signal.

[0079] The second D flip-flop is configured such that the second clk terminal (the clk terminal with a circle) receives the clock cycle signal, the second D input terminal receives the IO input signal, and the IO input signal is sampled according to the falling edge of the clock cycle signal to output the falling edge sampled signal.

[0080] like Figure 5 As shown, the arithmetic circuit 53 is configured to compare the rising edge sampled signal and the falling edge sampled signal to output a comparison result.

[0081] In one embodiment, the arithmetic circuit includes an XNOR gate. The XNOR gate is configured to receive the rising edge sampled signal and the falling edge sampled signal, and to perform an XNOR operation on the rising edge sampled signal and the falling edge sampled signal to output a first comparison signal having a first level or a second comparison signal having a second level opposite to the first level as the comparison result.

[0082] In one embodiment, the signal selection circuit includes a first selector. The first selector is configured to receive the comparison result, the current sampled signal, and the previously output sampled signal; select and output the current sampled signal as the signal to be output when the comparison result is the first comparison signal; and select and output the previously output sampled signal as the signal to be output when the comparison result is the second comparison signal.

[0083] Specifically, in response to the output signal xnor_vld of the XOR operation being 1, the signal selection circuit 54 is configured to select the input signal gpio_in_pos of the current clock for output; in response to the output signal xnor_vld of the XOR operation being 0, the first selector is configured to select the output signal db_gpio_in of the previous clock for output.

[0084] In this disclosure, the IO input signal is first sampled on both the rising and falling edges. Then, the sampled data from the two different edges are XORed. When the XOR result is 1, the input signal is selected by the edge selection signal (edge_sel), and then output to the signal (db_gpio_in) by the register, and finally given to the GPIO circuit.

[0085] In this scheme, glitches are filtered out after the first stage of sampling via both rising and falling edges. The second-stage output signal db_gpio_in does not exhibit metastability. Therefore, this circuit avoids erroneous sampling of the IO input signal, effectively achieving debouncing and filtering.

[0086] Figure 6 The diagram shown is a second circuit schematic of the IO sampling circuit according to an embodiment of this disclosure. Figure 6 As shown, in addition to the input terminal 51, sampling circuit 52, arithmetic circuit 53, signal selection circuit 54 and output circuit 55, the circuit also includes a second selector 56.

[0087] Figure 6 The input terminal 51, the sampling circuit 52, the arithmetic circuit 53, the signal selection circuit 54, the output circuit 55, and the reference circuit shown are illustrated in the figure. Figure 5The corresponding modules or units in the described embodiments are the same, and will not be repeated here.

[0088] Furthermore, the second selector 56 is configured to receive a selection signal, the rising edge sampling signal, and the falling edge sampling signal, and to select one of the rising edge sampling signal and the falling edge sampling signal as the current sampling signal according to the selection signal.

[0089] like Figure 6 As shown, the function of the unit (second selector 56) to which the edge_sel signal is input is to select either the 0 port signal or the 1 port signal based on the edge_sel signal. The edge_sel signal is configured through a system register, which improves the flexibility of application scenarios. When edge_sel outputs 1, the 1 input (rising edge sampling signal gpio_in_pos) is selected; when edge_sel outputs 0, the 0 input (falling edge sampling signal gpio_in_neg) is selected. This device is a selector in electronic circuits.

[0090] The timing implementation differs depending on the scenario. Rising-edge sampling can be chosen when it's difficult to meet the setup time requirements of the subsequent register db_gpio_in, while falling-edge sampling can be chosen when it's difficult to meet its hold time requirements. For example, rising-edge sampling can be chosen in rising-edge critical scenarios such as key detection, pulse counting, and signal presence detection; falling-edge sampling can be chosen in falling-edge scenarios such as key release, pulse end, communication end, and timer control.

[0091] Figure 7 The diagram shown is a signal timing diagram of the IO sampling circuit described in an embodiment of this disclosure. Figure 7 As shown, combined with Figure 6 In the circuit shown, db_clk represents the debouncing clock, i.e., the clock cycle signal (clk clock of the first and second D flip-flops), gpio_in represents the IO input signal, gpio_in_pos represents the sampling result of the D flip-flop sampled on the rising edge, gpio_in_neg represents the sampling result of the D flip-flop sampled on the falling edge, xnor_vld represents the valid result of the XOR operation, edge_sel represents the edge selection signal of the second selector 56, db_gpio_in_D represents the D input signal of the register, and the final input signal after debouncing is db_gpio_in.

[0092] At time 5, gpio_in experiences a signal glitch due to external interference near the rising edge of db_clk, which is sampled by gpio_in_pos. If this signal were directly output to db_gpio_in, it would lead to an incorrect pulse judgment. By sampling simultaneously at the falling edge of the clock, this signal is not sampled. At this time, xnor_vld is pulled low, and the erroneous pulse sampled by gpio_in_pos is isolated and filtered, preventing it from reaching db_gpio_in_D and ensuring correct sampling.

[0093] Furthermore, this circuit also filters out metastabilities. At time 5, if the spike does not meet the setup and hold time of the rising edge sampling, a metastability may occur. When the metastability stabilizes to 0 after a period of time, it does not affect the output of db_gpio_in. When the metastability stabilizes to 1, it also does not affect the output of db_gpio_in due to the isolation of the XOR logic.

[0094] At time 14, gpio_in outputs a stable signal, and when there are no glitches, both gpio_in_pos and gpio_in_neg are sampled to a high level, and xnor_vld is pulled high before the signal can be transmitted to db_gpio_in_D.

[0095] Figure 8 The diagram shown is a third circuit schematic of the IO sampling circuit according to an embodiment of this disclosure. Figure 8 As shown, the circuit structure is similar to... Figure 6 Compared to the circuit shown, in the sampling circuit 52, the positions of the first D flip-flop and the second D flip-flop are interchanged. The first D flip-flop is on top, outputting gpio_in_pos, and the second D flip-flop is on the bottom, outputting gpio_in_neg.

[0096] Figure 9 The diagram shown is the fourth circuit schematic of the IO sampling circuit described in an embodiment of this disclosure. Figure 9 As shown, the circuit structure is similar to... Figure 6 Compared to the circuit shown, a modified output circuit 55 is provided, which uses two or more D flip-flops to achieve the function of register sampling. Although this implementation increases the area and data transmission delay, the probability of metastability when the frequency is increased is smaller.

[0097] The technical solution disclosed herein limits the debouncing time to half a clock cycle by performing an XOR operation on the sampled values ​​of the rising and falling edges. If the jitter time in the actual scenario is longer, the debouncing time can be increased by reducing or dividing the frequency of the debouncing clock. Here, "longer jitter time" refers to the width of the abnormal pulse, which exceeds half a clock cycle; if it exceeds half a debouncing clock cycle, the debouncing effect cannot be guaranteed. By dividing or reducing the frequency of the debouncing clock, the frequency of the debouncing clock decreases, the clock cycle becomes longer, and the time corresponding to half a clock cycle also increases. Therefore, the debouncing time can be increased.

[0098] refer to Figure 7 The timing diagram shown illustrates that this circuit works by sampling simultaneously on both the rising and falling edges of db_clk. The input signal is only valid if the XOR operation of the sampled signals yields the same result. If a jitter or pulse lasts longer than half a clock cycle, it's possible that both the rising and falling edges will sample the jitter pulse, resulting in the pulse being input. Therefore, the debouncing time is half a clock cycle.

[0099] The purpose of frequency reduction and division is to lower the frequency of the debouncing clock, increase the clock cycle, and thus extend the debouncing time. For example, when the debouncing clock is 20MHz, the length of one clock cycle is 50ns, so the length of the glitches that can be filtered out is half a clock cycle, 25ns. If the jitter length in the application scenario is greater than 25ns, then by reducing the frequency of db_clk to 10MHz, the length of half a clock cycle is 50ns, which can filter out jitter or glitches with a width of less than 50ns.

[0100] Figure 10 The diagram shown is a structural schematic of the electronic device described in an embodiment of this disclosure. Figure 10 As shown, this disclosure provides an electronic device including: an I / O sampling device as described above, and at least one of a sensor interface, a communication interface, and a touch screen interface, configured to receive the sampling signal from the I / O sampling device.

[0101] The IO sampling device is the device or IO sampling device corresponding to the IO sampling method described in the above embodiments, and will not be described again here.

[0102] The practical application scenarios of this disclosure are as follows:

[0103] For sensor interfaces: The system includes many sensors, such as temperature sensors, pressure sensors or motion sensors, which may generate noise during initial startup or environmental changes. The IO sampling method and apparatus and the IO debouncing function of electronic devices provided in this disclosure help to filter out these transient noises.

[0104] Regarding communication interfaces: In data communication, jitter on signal lines may cause data errors. The IO sampling method and apparatus and the IO debouncing function of electronic devices provided in this disclosure can improve the accuracy of data and the reliability of communication.

[0105] For touch screens and touch screen controllers: Touch screens may be subject to external interference when detecting touch events. The IO sampling method and apparatus and the IO debouncing function of electronic devices provided in this disclosure can reduce accidental touches and improve touch accuracy.

[0106] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0107] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.

Claims

1. An IO sampling method, comprising: comprising: receiving an IO input signal; sampling the IO input signal according to a clock period signal to obtain a rising edge sampled signal and a falling edge sampled signal, such that the rising edge sampled signal is different from the falling edge sampled signal when the IO input signal contains a jitter or a glitch, a half of a clock period length of the clock period signal being greater than a width of the jitter or the glitch contained in the IO input signal; comparing the rising edge sampled signal and the falling edge sampled signal to obtain a comparison result; selecting one of a previously output sampled signal and a current sampled signal as a to-be-output signal according to the comparison result, the current sampled signal being the rising edge sampled signal or the falling edge sampled signal; and outputting the to-be-output signal as a sampled signal corresponding to the IO input signal. The sampling the IO input signal according to a clock period signal to obtain a rising edge sampled signal and a falling edge sampled signal comprises:

2. The method of claim 1, wherein, sampling the IO input signal according to a rising edge and a falling edge of one clock period in the clock period signal, or according to a falling edge of one clock period and a rising edge of a next clock period in the clock period signal to obtain the rising edge sampled signal and the falling edge sampled signal. The comparing the rising edge sampled signal and the falling edge sampled signal to obtain a comparison result comprises:

3. The method of claim 1, wherein, outputting a first comparison signal having a first level if the rising edge sampled signal is identical to the falling edge sampled signal; and outputting a second comparison signal having a second level opposite to the first level if the rising edge sampled signal is not identical to the falling edge sampled signal. The selecting one of a previously output sampled signal and a current sampled signal as a to-be-output signal according to the comparison result comprises:

4. The method of claim 3, wherein, selecting the current sampled signal according to the first comparison signal in a current clock period in the clock period signal; and selecting the previously output sampled signal according to the second comparison signal in the current clock period, the previously output sampled signal having been output in the current clock period. The outputting the to-be-output signal as a sampled signal corresponding to the IO input signal comprises:

5. The method of claim 1, wherein, storing the selected to-be-output signal in a current clock period in the clock period signal; and outputting the to-be-output signal as the sampled signal in a next clock period in the clock period signal. The sampling the IO input signal according to a clock period signal to obtain a rising edge sampled signal and a falling edge sampled signal comprises:

6. The method of claim 1, wherein, sampling the IO input signal according to the clock period signal by using a rising edge sampling D flip-flop to obtain the rising edge sampled signal; and sampling the IO input signal according to the clock period signal by using a falling edge sampling D flip-flop to obtain the falling edge sampled signal. The comparing the rising edge sampled signal and the falling edge sampled signal to obtain a comparison result comprises:

7. The method of claim 1, wherein, ​ performing an exclusive-OR operation on the rising edge sampling signal and the falling edge sampling signal.

8. The method of claim 1, wherein, Further comprising: receiving a selection signal; and selecting one of the rising edge sampling signal and the falling edge sampling signal as the current sampling signal according to the selection signal.

9. The method of claim 1, wherein, Further comprising: down-clocking or dividing the clock period signal such that half of a clock period length is greater than a width of a jitter or glitch contained in the IO input signal.

10. An IO sampling device, comprising: Comprising: an input terminal configured to receive an IO input signal; a sampling circuit configured to perform rising edge sampling and falling edge sampling on the IO input signal according to a clock period signal to output a rising edge sampling signal and a falling edge sampling signal, such that the rising edge sampling signal is different from the falling edge sampling signal when a jitter or glitch is contained in the IO input signal, half of a clock period length of the clock period signal being greater than a width of the jitter or glitch contained in the IO input signal; an operation circuit configured to compare the rising edge sampling signal and the falling edge sampling signal to output a comparison result; a signal selection circuit configured to select and output one of a last output sampling signal and a current sampling signal as a to-be-output signal according to the comparison result, the current sampling signal being the rising edge sampling signal or the falling edge sampling signal; and an output circuit configured to output the to-be-output signal as a sampling signal corresponding to the IO input signal.

11. The IO sampling apparatus of claim 10, wherein, The sampling circuit comprises: a first D flip-flop configured to receive the IO input signal and the clock period signal, and sample the IO input signal according to a rising edge of the clock period signal to output the rising edge sampling signal; and a second D flip-flop configured to receive the IO input signal and the clock period signal, and sample the IO input signal according to a falling edge of the clock period signal to output the falling edge sampling signal.

12. The IO sampling apparatus of claim 10, wherein, The operation circuit comprises: an exclusive-OR gate configured to receive the rising edge sampling signal and the falling edge sampling signal, and perform an exclusive-OR operation on the rising edge sampling signal and the falling edge sampling signal to output a first comparison signal having a first level or a second comparison signal having a second level opposite to the first level as the comparison result.

13. The IO sampling apparatus of claim 12, wherein, The signal selection circuit comprises: a first selector configured to receive the comparison result, the current sampling signal and the last output sampling signal, select and output the current sampling signal as the to-be-output signal when the comparison result is the first comparison signal, and select and output the last output sampling signal as the to-be-output signal when the comparison result is the second comparison signal.

14. The IO sampling apparatus of claim 10, wherein, The output circuit comprises: a register configured to receive the clock period signal and the to-be-output signal, temporarily store the to-be-output signal in a current clock period of the clock period signal, and output the to-be-output signal as the sampling signal in a next clock period of the clock period signal.

15. The IO sampling apparatus of claim 10, wherein, Further comprising: a second selector configured to receive the selection signal, the rising edge sample signal and the falling edge sample signal, and select one of the rising edge sample signal and the falling edge sample signal as the current sample signal according to the selection signal.

16. An electronic device, comprising: comprising: the IO sampling device according to any one of claims 10 to 15; and at least one of a sensor interface, a communication interface and a touch screen interface configured to receive the sample signal from the IO sampling device.

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