Storage device

Abstract

The present application discloses a storage device comprising: a plurality of storage modules; a plurality of interface control modules, each interface control module being coupled to at least two storage modules; and a communication interface coupled to the interface control modules and configured to exchange data with an external device. Each interface control module, in response to a read instruction, reads at least one target data item from each of the at least two storage modules using a first clock signal as a reference, sorts the at least two target data items based on the positional relationship of the storage modules, and outputs the data items to the communication interface using a second clock signal as a reference, wherein the frequency of the second clock signal is an integer multiple of the frequency of the first clock signal. The present application can increase the storage bandwidth of the storage device.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a storage device. Background Art

[0002] Storage devices usually cooperate with external devices to complete data reading and data writing operations. Generally speaking, the relevant storage devices transmit data of a single storage module through a communication interface and output it to the external device.

[0003] However, as data increases, the demand for data calculation becomes greater and greater, and thus the demand for storage bandwidth also becomes greater and greater, resulting in insufficient storage bandwidth of related storage devices. Summary of the Invention

[0004] The present application provides a storage device capable of increasing the storage bandwidth of the storage device.

[0005] A technical solution adopted in the present application is to provide a storage device, which includes: multiple storage modules; multiple interface control modules, each interface control module is coupled to at least two storage modules respectively; a communication interface, coupled to the interface control module, and used to interact with external devices for data; wherein, each interface control module responds to a read instruction, reads at least one target data from at least two storage modules respectively based on a first clock signal, sorts the at least two target data according to the positional relationship of the storage modules, and outputs them to the communication interface based on a second clock signal, wherein the frequency of the second clock signal is an integer multiple of the frequency of the first clock.

[0006] Each interface control module includes: an interface control unit, coupled to the storage module and the communication interface, respectively, for converting an input first clock signal into a second clock signal and a third clock signal; wherein the second clock signal is used as an enable signal; the frequency of the third clock signal is an integer multiple of the frequency of the second clock signal; at least two temporary storage units, each of which is coupled to a storage module and is used to temporarily store at least one target data read from the storage module; a selection unit, coupled to the at least two temporary storage units, and in response to the enable signal, controlling the corresponding temporary storage unit to output at least one target data; wherein the phase of the enable signal corresponding to each selection unit is different; and a multiplexer, coupled to the selection unit, outputting the at least two target data to the communication interface according to the third clock signal.

[0007] Among them, at least two storage modules include a first type storage module and a second type storage module; the first type storage module and the interface control module are arranged close to the communication interface, and the second type storage module is arranged away from the communication interface; the interface control module responds to the read instruction, takes the first clock signal as the reference, reads at least one target data from a first type storage module and a second type storage module respectively, and controls the output of each target data according to the first enable signal and the second enable signal respectively, wherein the phase of the first enable signal is earlier than the phase of the second enable signal.

[0008] The frequency of the second clock signal is twice the frequency of the first clock signal, and the frequency of the third clock signal is four times the frequency of the first clock signal.

[0009] Among them, the temporary storage unit includes: a first type of temporary storage unit, coupled to the first type of storage module, and a second type of temporary storage unit, coupled to the second type of storage module. The selection unit includes: a first selection circuit, coupled to the first type of temporary storage unit; a second selection circuit, coupled to the second type of temporary storage unit; the first selection circuit obtains target data from the first type of storage module according to a first enable signal; the second selection circuit obtains target data from the second type of storage module according to a second enable signal, wherein the logic level of the first enable signal is opposite to the logic level of the second enable signal.

[0010] In which, the interface control unit includes a phase-locked loop circuit, an input end of the phase-locked loop circuit is used to receive a first clock signal, a first output end of the phase-locked loop circuit is coupled to a first selection circuit, a second output end of the phase-locked loop circuit is coupled to a second selection circuit, and a third output end of the phase-locked loop circuit is coupled to a multiplexer; in which, in response to receiving the first clock signal, the first output end of the phase-locked loop circuit outputs a first enable signal, the second output end of the phase-locked loop circuit outputs a second enable signal, and the third output end of the phase-locked loop circuit outputs a third clock signal.

[0011] The storage device further includes: a power supply module, which is coupled to the interface control module and the plurality of storage modules respectively and is used to provide a DC power supply.

[0012] The storage device further includes: a command address output module, which is coupled to the plurality of storage modules and the interface control module respectively, and is used to output a first clock signal to the plurality of storage modules and the interface control module, as well as output corresponding commands and addresses.

[0013] Each interface control module is coupled to two storage modules, and the wiring lengths between the two storage modules and the interface control module are different.

[0014] Wherein, the storage device is a memory stick.

[0015] The beneficial effects of the present application are as follows: different from the prior art, the present application sets multiple storage modules and multiple interface control modules in the storage device, so that each interface control module is coupled to at least two storage modules respectively, and each interface control module responds to the read instruction, outputs the target data read from the at least two storage modules respectively based on the first clock signal to the communication interface according to the second clock signal whose frequency is an integer multiple of the first clock signal, and synchronously reads the data of at least two storage modules and increases the frequency of the data output by the interface control module. When the bus remains unchanged, the high-frequency clock signal is used to output more data of the storage modules to the communication interface, thereby increasing the storage bandwidth of the storage device and improving the data interaction efficiency between the storage device and the external device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0017] Figure 1 It is a structural diagram of the storage device provided by this application;

[0018] Figure 2 is a connection diagram of the storage device provided by this application;

[0019] Figure 3 It is a structural diagram of the interface control module provided by this application;

[0020] Figure 4 is a circuit control schematic diagram of the storage device provided by this application;

[0021] Figure 5 This is another circuit control schematic diagram of the storage device provided in this application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0023] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0024] Storage devices usually cooperate with external devices to complete data reading and data writing operations. Generally speaking, the relevant storage devices transmit data of a single storage module through a communication interface and output it to the external device.

[0025] However, due to the increase in data, the requirements for data calculation are getting higher and higher, and thus the requirements for the storage bandwidth of the storage device are also getting higher and higher, resulting in insufficient storage bandwidth of the related storage devices.

[0026] While some technical solutions can increase bandwidth by increasing the operating frequency of the memory modules in storage devices, such as HBM (high bandwidth memory), 3D packaging is expensive, necessitating a low-cost bandwidth improvement solution. However, the memory module packaging design limits bandwidth adjustment, and the process performance of these memory modules is relatively poor, inferior to that of logic processes.

[0027] Therefore, a low-cost bandwidth improvement solution is needed that can utilize advanced technology to achieve high bandwidth performance.

[0028] The storage device provided by this application can avoid the occurrence of the above problems. The storage device provided by this application is introduced in detail below. Figure 1The storage device 10 includes: multiple storage modules 100; multiple interface control modules 200 and a communication interface 300. Each interface control module 200 is coupled to at least two storage modules 100; the communication interface 300 is coupled to the interface control module 200 and is used to exchange data with an external device; each interface control module 200, in response to a read instruction, reads at least one target data from at least two storage modules 100 based on a first clock signal, sorts the at least two target data according to the positional relationship of the storage modules 100, and outputs the data to the communication interface 300 based on a second clock signal, wherein the frequency of the second clock signal is an integer multiple of the frequency of the first clock. Specifically, the frequency multiple relationship between different clock signals is related to the number of storage modules 100 coupled to the interface control module 200. For example, in this embodiment, if the number of storage modules 100 coupled to the interface control module 200 is 2, then the frequency of the second clock signal is twice the frequency of the first clock signal. It can be understood that each storage module 100 stores corresponding data. When reading data, the logical address of the data is determined according to the corresponding read instruction, and the corresponding storage module is determined according to the logical address, and then the corresponding data is read from the storage module.

[0029] In some embodiments, the storage device may be a storage device such as a memory stick or a solid-state drive, and the plurality of storage modules 100 may be semiconductor storage modules.

[0030] The interface control module 200 can be a bidirectional interface module. One side of the interface control module 200 is connected to multiple storage modules 100 through data I / O channels and handshake I / O signals. The frequency of the data I / O channel corresponding to the other side of the interface control module 200 is at least an integer multiple of the frequency corresponding to the side of the storage module 100. The other side of the interface control module 200 is electrically connected to the communication interface 300. Figure 2 As shown, one side of the interface control module 200 is connected to two storage modules 100, the channel frequency of each storage module 100 is f, and the output frequency of the other side of the interface control module 200 is 2f, that is, the frequency of the data I / O channel on the other side of the interface control module 200 is twice the frequency of the storage module 100 side.

[0031] In some embodiments, the first clock signal and the second clock signal may be periodic pulse signals generated by a circuit. The frequency of the second clock signal is an integer multiple of the frequency of the first clock signal. For example, if the frequency of the first clock signal is f, the frequency of the second clock signal may be 2f, 3f, 4f, 5f, etc.

[0032] In some embodiments, the sorting of the at least two target data according to the positional relationship of the storage modules 100 may be determined according to the distance between the storage modules 100 and the communication interface 300. For example, the target data read from a storage module 100 closer to the communication interface 300 may be sorted before the target data read from a storage module 100 farther from the communication interface 300, so that the target data is output to the communication interface 300 first.

[0033] Optionally, in some embodiments, the storage device 10 further includes: a power supply module 400 , respectively coupled to the interface control module 200 and the plurality of storage modules 100 , for providing a DC power supply.

[0034] Optionally, in some embodiments, the storage device 10 further includes: a command address output module 500, which is respectively coupled to multiple storage modules 100 and the interface control module 200, and is used to output a first clock signal to the multiple storage modules 100 and the interface control module 200, as well as output corresponding commands and addresses.

[0035] The power supply module 400 provides at least one dedicated DC power supply to each storage module 100 , provides at least one dedicated DC power supply to the command address output module 500 , and provides at least one dedicated DC power supply to the interface control module 200 .

[0036] This embodiment arranges multiple storage modules and multiple interface control modules in the storage device, so that each interface control module is coupled to at least two storage modules respectively, and each interface control module responds to a read instruction, outputs the target data read from the at least two storage modules respectively based on the first clock signal to the communication interface according to a second clock signal whose frequency is an integer multiple of the first clock signal. By synchronously reading the data of the at least two storage modules and increasing the frequency of the data output by the interface control module, more data of the storage modules is output to the communication interface using a high-frequency clock signal when the bus remains unchanged, thereby increasing the storage bandwidth of the storage device and improving the data interaction efficiency between the storage device and external devices.

[0037] Optionally, in some embodiments, at least two storage modules 100 may include a first-type storage module 101 and a second-type storage module 102; the first-type storage module 101 and the interface control module 200 are arranged close to the communication interface 300, and the second-type storage module 102 is arranged away from the communication interface 300; the interface control module 200 responds to a read instruction, takes the first clock signal as a reference, reads at least one target data from a first-type storage module 101 and a second-type storage module 102 respectively, and controls the output of each target data according to the first enable signal and the second enable signal, respectively, wherein the phase of the first enable signal is earlier than the phase of the second enable signal.

[0038] Combine Figure 1 and Figure 4 The first clock signal, such as 1*f CLK, is input to the first type storage module 101 and the second type storage module 102 respectively. The first type storage module 101 is arranged close to the communication interface 300 (i.e., the gold finger), and the second type storage module 102 is arranged far away from the communication interface 300 (i.e., the gold finger).

[0039] The interface control module 200, such as a bidirectional interface module, responds to a read instruction and reads at least one target data from a first type storage module 101 and a second type storage module 102 respectively based on the first clock signal 1*f CLK, and controls the output of each target data according to the first enable signal (i.e., the enable signal corresponding to the first type storage module 101) and the second enable signal (i.e., the enable signal corresponding to the second type storage module 102).

[0040] Among them, since the first type storage module 101 is arranged close to the communication interface 300 (i.e., the gold finger) and the second type storage module 102 is arranged away from the communication interface 300 (i.e., the gold finger), the data in the first type storage module 101 can reach the interface control module 200 more quickly, and the data in the second type storage module 102 will arrive at the interface control module 200 a little later than the data in the first type storage module 101.

[0041] Because the data in the first type storage module 101 can reach the interface control module 200 more quickly, the first enable signal, whose phase is earlier than the second enable signal, can be used to output the data obtained from the first type storage module 101 from the interface control module 200 first, and then the second enable signal can be used to output the data obtained from the second type storage module 102 from the interface control module 200. By alternately enabling the first enable signal and the second enable signal, all data is output at the frequency of the second clock signal.

[0042] This embodiment arranges multiple storage modules and multiple interface control modules in the storage device, so that each interface control module is coupled to at least two storage modules respectively, and each interface control module responds to a read instruction, outputs the target data read from the at least two storage modules respectively based on the first clock signal to the communication interface according to a second clock signal whose frequency is an integer multiple of the first clock signal. By synchronously reading the data of the at least two storage modules and increasing the frequency of the data output by the interface control module, more data of the storage modules is output to the communication interface using a high-frequency clock signal when the bus remains unchanged, thereby increasing the storage bandwidth of the storage device and improving the data interaction efficiency between the storage device and external devices.

[0043] Alternatively, as Figure 3 As shown, in some embodiments, each interface control module 200 may include: an interface control unit 201, at least two temporary storage units 202, a selection unit 203, and a multiplexer 204. Specifically, the interface control unit 201 is coupled to the storage module 100 and the communication interface 300, respectively, and is configured to convert an input first clock signal into a second clock signal and a third clock signal, wherein the second clock signal is used as an enable signal, and the frequency of the third clock signal is an integer multiple of the frequency of the second clock signal; at least two temporary storage units 202, each of which is coupled to a storage module 100 and is configured to temporarily store at least one target data read from the storage module 100; a selection unit 203 is coupled to the at least two temporary storage units 202, and in response to the enable signal, controls the corresponding temporary storage unit 202 to output the at least one target data; wherein the phase of the enable signal corresponding to each selection unit 203 is different; and a multiplexer 204 is coupled to the selection unit 203, and outputs the at least two target data to the communication interface 300 according to the third clock signal.

[0044] The multiplexer 204 is coupled to the selection unit 203 and outputs at least two target data to the communication interface 300 according to the third clock signal, so as to achieve the purpose of increasing bandwidth by switching the multiplexer 204 at high speed.

[0045] Optionally, in some embodiments, the temporary storage unit 202 may include: a first-type temporary storage unit 202a and a second-type temporary storage unit 202b, wherein the first-type temporary storage unit 202a is coupled to the first-type storage module 101, and the second-type temporary storage unit 202b is coupled to the second-type storage module 102; the selection unit 203 may include: a first selection circuit 203a and a second selection circuit 203b, wherein the first selection circuit 203a is coupled to the first-type temporary storage unit 202a; and the second selection circuit 203b is coupled to the second-type temporary storage unit 202b; the first selection circuit 203a obtains target data from the first-type storage module 101 according to a first enable signal; and the second selection circuit 203b obtains target data from the second-type storage module 102 according to a second enable signal, wherein the logic level of the first enable signal is opposite to the logic level of the second enable signal. In other words, the first enable signal and the second enable signal can be alternately enabled to complete data output.

[0046] This embodiment arranges multiple storage modules and multiple interface control modules in the storage device, so that each interface control module is coupled to at least two storage modules respectively, and each interface control module responds to a read instruction, outputs the target data read from the at least two storage modules respectively based on the first clock signal to the communication interface according to a second clock signal whose frequency is an integer multiple of the first clock signal. By synchronously reading the data of the at least two storage modules and increasing the frequency of the data output by the interface control module, more data of the storage modules is output to the communication interface using a high-frequency clock signal when the bus remains unchanged, thereby increasing the storage bandwidth of the storage device and improving the data interaction efficiency between the storage device and external devices.

[0047] like Figure 3 and Figure 4 As shown, the first type temporary storage unit 202a is coupled to the first type storage module 101, the second type temporary storage unit 202b is coupled to the second type storage module 102, and the first selection circuit 203a is coupled to the first type temporary storage unit 202a, and is used to obtain target data from the first type storage module 101 according to the first enable signal, and output the target data of the first type storage module 101 temporarily stored in the first type temporary storage unit 202a according to the second clock signal 2*fCLK. Figure 4 DQ0, DQ1, DQ2, and DQ3 represent data output pins. Figure 4 Only DQ0 is taken as an example, but DQ1, DQ2, and DQ3 actually have corresponding connection relationships with the interface control module.

[0048] Similarly, the second selection circuit 203b is coupled to the second type temporary register unit 202b for obtaining target data from the second type storage module 102 according to the second enable signal and outputting the target data of the second type storage module 102 temporarily stored in the second type temporary register unit 202b according to the second clock signal 2*fCLK.

[0049] The logic level of the first enable signal is opposite to the logic level of the second enable signal. For example, if the logic level of the first enable signal is high, the logic level of the second enable signal is low; or if the logic level of the first enable signal is low, the logic level of the second enable signal is high.

[0050] This embodiment provides multiple storage modules and multiple interface control modules in a storage device, such that each interface control module is coupled to at least two storage modules. In response to a read instruction, each interface control module outputs target data read from the at least two storage modules based on a first clock signal to a communication interface using a second clock signal with a frequency that is an integer multiple of the first clock signal. This increases the frequency at which the interface control modules output target data, thereby increasing storage bandwidth.

[0051] Optionally, in some embodiments, the interface control unit 201 may include a phase-locked loop circuit 201a, an input end of the phase-locked loop circuit 201a is used to receive a first clock signal, a first output end of the phase-locked loop circuit 201a is coupled to a first selection circuit 203a, a second output end of the phase-locked loop circuit 201a is coupled to a second selection circuit 203b, and a third output end of the phase-locked loop circuit 201a is coupled to a multiplexer 204; wherein, in response to receiving the first clock signal, the first output end of the phase-locked loop circuit 201a outputs a first enable signal, the second output end of the phase-locked loop circuit 201a outputs a second enable signal, and the third output end of the phase-locked loop circuit 201a outputs a third clock signal.

[0052] The phase-locked loop circuit 201 a is used to prepare and improve the output data timing phase of the interface control module 200 .

[0053] Specifically, if Figure 4 and Figure 5 As shown, a first clock signal 1*fCLK is input to a phase-locked loop circuit 201a, which converts the input first clock signal 1*fCLK into a second clock signal 2*fCLK and a third clock signal 4*fCLK. A first output terminal of the phase-locked loop circuit 201a (i.e., the port corresponding to the second clock signal 2*fCLK) is coupled to a first selection circuit 203a. A second output terminal of the phase-locked loop circuit 201a (i.e., the port corresponding to the second clock signal 2*fCLK) is coupled to a second selection circuit 203b. A third output terminal of the phase-locked loop circuit 201a (i.e., the port corresponding to the third clock signal 4*fCLK) is coupled to a multiplexer 204.

[0054] Among them, there are two ports of the second clock signal 2*f CLK, and the second clock signal 2*f CLK is used as an enable signal. For example, the second clock signal 2*f CLK corresponding to the first output end of the phase-locked loop circuit 201a is used as the first enable signal, and the second clock signal 2*f CLK corresponding to the second output end of the phase-locked loop circuit 201a is used as the second enable signal.

[0055] This embodiment arranges multiple storage modules and multiple interface control modules in the storage device, so that each interface control module is coupled to at least two storage modules respectively, and each interface control module responds to a read instruction, outputs the target data read from the at least two storage modules respectively based on the first clock signal to the communication interface according to a second clock signal whose frequency is an integer multiple of the first clock signal. By synchronously reading the data of the at least two storage modules and increasing the frequency of the data output by the interface control module, more data of the storage modules is output to the communication interface using a high-frequency clock signal when the bus remains unchanged, thereby increasing the storage bandwidth of the storage device and improving the data interaction efficiency between the storage device and external devices.

[0056] Optionally, in some embodiments, the frequency of the second clock signal is twice the frequency of the first clock signal, and the frequency of the third clock signal is four times the frequency of the first clock signal. For example, if the first clock signal is 1*f CLK, then the second clock signal is 2*f CLK, and the third clock signal is 4*f CLK.

[0057] Optionally, in some embodiments, each interface control module is coupled to two storage modules, wherein the wiring lengths between the two storage modules and the interface control module are different.

[0058] For example, the wiring length of the storage module that is closer to the interface control module can be shorter, for example, a shorter wire can be selected for connection; the wiring length of the storage module that is farther from the interface control module can be longer, for example, a longer wire can be selected for connection.

[0059] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules or units is merely a logical functional division. In actual implementation, other division methods may be used. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented.

[0060] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0061] In addition, each functional unit in each embodiment of the present application may be integrated into a processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or software functional units.

[0062] If the integrated units in the other embodiments described above are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0063] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A storage device, characterized in that: The storage device includes: Multiple storage modules; a plurality of interface control modules, each interface control module being coupled to at least two of the storage modules; A communication interface, coupled to the interface control module and used for data exchange with external devices; Each of the interface control modules, in response to a read instruction, reads at least one target data from each of the at least two storage modules based on a first clock signal, sorts the at least two target data according to a positional relationship between the storage modules, and outputs the data to the communication interface based on a second clock signal, wherein a frequency of the second clock signal is an integer multiple of a frequency of the first clock signal; Wherein, each of the interface control modules includes: an interface control unit, coupled to the storage module and the communication interface, respectively, for converting the input first clock signal into the second clock signal and a third clock signal; wherein the second clock signal is used as an enable signal; and the frequency of the third clock signal is an integer multiple of the frequency of the second clock signal; at least two temporary storage units, each of which is coupled to one of the storage modules and is used to temporarily store the at least one target data read from the storage module; a selection unit coupled to the at least two temporary storage units, and responsive to the enable signal, controlling the corresponding temporary storage unit to output the at least one target data; wherein the phase of the enable signal corresponding to each selection unit is different; A multiplexer is coupled to the selection unit and outputs at least two target data to the communication interface according to the third clock signal.

2. The storage device according to claim 1, wherein: The at least two storage modules include a first type storage module and a second type storage module; The first type storage module and the interface control module are arranged close to the communication interface, and the second type storage module is arranged far away from the communication interface; In response to the read instruction, the interface control module reads at least one target data from a first-type storage module and a second-type storage module respectively based on a first clock signal, and controls the output of each target data according to a first enable signal and a second enable signal respectively, wherein the phase of the first enable signal is earlier than the phase of the second enable signal.

3. The storage device according to claim 2, wherein: The frequency of the second clock signal is twice the frequency of the first clock signal, and the frequency of the third clock signal is four times the frequency of the first clock signal.

4. The storage device according to claim 2, wherein: The temporary storage unit includes: A first type temporary storage unit is coupled to the first type storage module, A second type temporary storage unit is coupled to the second type storage module, The selection unit includes: a first selection circuit coupled to the first type of temporary storage unit; a second selection circuit coupled to the second type of temporary storage unit; The first selection circuit obtains the target data from the first type storage module according to the first enable signal; The second selection circuit obtains the target data from the second-type storage module according to the second enable signal, wherein a logic level of the first enable signal is opposite to a logic level of the second enable signal.

5. The storage device according to claim 4, wherein: The interface control unit includes a phase-locked loop circuit, an input end of the phase-locked loop circuit is used to receive the first clock signal, a first output end of the phase-locked loop circuit is coupled to the first selection circuit, a second output end of the phase-locked loop circuit is coupled to the second selection circuit, and a third output end of the phase-locked loop circuit is coupled to the multiplexer; In which, in response to receiving the first clock signal, the first output end of the phase-locked loop circuit outputs a first enable signal, the second output end of the phase-locked loop circuit outputs a second enable signal, and the third output end of the phase-locked loop circuit outputs a third clock signal. The storage device according to claim 1 , wherein: The storage device further includes: The power supply module is respectively coupled to the interface control module and the plurality of storage modules, and is used for providing a direct current power supply.

7. The storage device according to claim 1, wherein: The storage device further includes: The command and address output modules are respectively coupled to the plurality of storage modules and the interface control module, and are used to output a first clock signal, as well as corresponding commands and addresses to the plurality of storage modules and the interface control module.

8. The storage device according to claim 1, wherein: Each interface control module is coupled to two storage modules, wherein the wiring lengths between the two storage modules and the interface control module are different.

9. The storage device according to claim 1, wherein: The storage device is a memory stick.

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