Sub-region for sequential data optimization in a storage device

Abstract

The present disclosure relates to sub-regions optimized for sequential data in a storage device. Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and the second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry to the first portion of the memory array designated for a first use, and assigns a second granularity of a second L2P mapping table entry to the second portion of the memory array designated for a second use, wherein the second granularity is not equal to the first granularity. The memory controller stores the first and second granularities in the memory array and stores at least a portion of the first and second L2P mapping table entries in an L2P cache of the memory controller.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with application number 201980090715.1, application date November 5, 2019, and invention name “Sub-region for sequential data optimization in a storage device”.

[0003] Priority application

[0004] This application claims the benefit of priority to U.S. application serial number 16 / 237,134, filed December 31, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0005] The present disclosure relates to sequential data optimized sub-regions in a storage device. Background Art

[0006] A memory device is a semiconductor circuit that provides electronic storage of data for a host system (e.g., a computer or other electronic device). Memory devices can be volatile or non-volatile. Volatile memory requires power to maintain data and includes, among others, devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM). Non-volatile memory can retain stored data when not powered and includes, among others, devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistive variable memory (e.g., phase change random access memory (PCRAM), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM).

[0007] A host system typically includes a host processor; a first amount of main memory (e.g., typically volatile memory such as DRAM) to support the host processor; and one or more storage systems (e.g., typically non-volatile memory such as flash memory) to provide additional storage for retaining data in addition to or separate from the main memory.

[0008] A storage system, such as a solid-state drive (SSD), may include a memory controller and one or more memory devices, including a plurality of dies or logical units (LUNs). In a specific example, each die may include a plurality of memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller may include interface circuitry configured to communicate with a host device (e.g., a host processor or interface circuitry) via a communication interface (e.g., a bidirectional parallel or serial communication interface). The memory controller may receive commands or operations from the host system in association with memory operations or instructions (e.g., read or write operations) to transfer data (e.g., user data and associated integrity data, such as error data or address data) between the memory devices and the host device, perform erase operations to erase data from the memory devices, and perform drive management operations (e.g., data migration, garbage collection, block retirement). Summary of the Invention

[0009] In one aspect, the present disclosure relates to a storage system comprising: a memory; and a controller configured to perform operations comprising: dividing the memory into a plurality of portions having non-overlapping logical block addressing (LBA) ranges; and assigning a respective performance level to a respective logical-to-physical L2P mapping table entry for each of the plurality of portions of the memory, wherein at least two of the performance levels are different from each other, and wherein the respective L2P mapping table entries include respective granularities.

[0010] On the other hand, the present disclosure relates to a method comprising: dividing, by a controller of the storage system, a memory of the storage system into a plurality of portions having non-overlapping logical block addressing (LBA) ranges; assigning, by the controller, a corresponding performance level to a corresponding logical-to-physical L2P mapping table entry for each of the plurality of portions of the memory, wherein at least two of the performance levels are different from each other; and assigning, by the controller, a corresponding granularity to the corresponding L2P mapping table entry.

[0011] On the other hand, the present disclosure relates to a tangible, non-transitory machine-readable storage medium configured to store instructions that, when executed by a controller of a storage system, cause the controller to: divide the memory of the storage system into multiple portions having non-overlapping logical block addressing (LBA) ranges; assign a respective performance level to a respective logical-to-physical L2P mapping table entry for each of the multiple portions of the memory, wherein at least two of the performance levels are different from each other; and assign a respective granularity to the respective L2P mapping table entries. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same reference numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0013] Figure 1 An example host system including a host device and a storage system is described.

[0014] Figure 2 An example method for providing data optimized sub-regions in a storage system is described.

[0015] Figures 3A to 3D An example of a mapping table area in a storage system is described.

[0016] Figure 4 A schematic diagram illustrating an example of a 3D NAND architecture semiconductor memory array.

[0017] Figure 5 An example block diagram illustrating a memory module.

[0018] Figure 6 A block diagram illustrating an example of an information handling system. DETAILED DESCRIPTION

[0019] Software (e.g., programs), instructions, operating systems (OSs), and other data are typically stored on a storage system and accessed by main memory for use by a host processor. Main memory (e.g., RAM) is typically faster, more expensive, and a different type of memory device (e.g., volatile) than most memory devices of a storage system (e.g., non-volatile, such as SSDs, etc.). In addition to main memory, a host system may also include different levels of volatile memory, such as static memory groups (e.g., cache, typically SRAM). Static memory, in certain instances, is typically faster than main memory and is configured to operate at speeds approaching or exceeding the speed of the host processor, but is less dense and more expensive. In other instances, more or fewer levels or amounts of main memory or static memory may be used depending on the desired host system performance and cost.

[0020] Flash memory devices, such as SSDs, typically include one or more groups of single-transistor floating-gate memory cells. Two common flash memory array architectures include NAND and NOR architectures. The floating-gate memory cells of a memory array are typically arranged in a matrix.

[0021] The performance of NAND storage devices is severely impacted by using a Flash Translation Layer (FTL) to map user data blocks (Logical Block Addressing or LBA) to physical addresses using a logical-to-physical (L2P) table. Current L2P tables use a four-byte physical address for each 4KB block of user data, which results in a large mapping table that cannot fit into the L2P cache at once. The present subject matter provides a storage device that partitions into small sections and operates the partitions at different mapping table granularities based on the partition's designated use. By mapping the partitions at a larger granularity, the random read performance and sequential write performance of that partition will increase (because more mapping tables will fit into the cache at a given time), which will benefit software, such as an operating system, which can load faster and improve the overall user experience.

[0022] Various embodiments provide for partitioning the user area of a storage device into multiple LBA ranges, and customizing the granularity of the L2P mapping table for each LBA range based on a specific use case (or a designated purpose of the partitioned LBA range). In various embodiments, the SRAM within the storage controller is customized for each L2P mapping table to optimize performance for each use case. Thus, the present subject matter defines customized L2P mapping granularity to various LBA ranges to produce customized random write and random read performance, and each LBA range is used for a designated purpose. For example, an operating system (O / S) or critical applications are placed in an area optimized for random read performance to improve boot time or load time, and secondary or less commercially advantageous applications are placed in a general purpose area. Thus, partitions can be tuned for specific designated purposes (such as streaming video or loading an O / S).

[0023] NAND flash-based storage devices require an FTL to map user data blocks (LBAs) to physical addresses. To efficiently support small host writes, the normal granularity of the L2P mapping table is a single physical address entry for a small number of host LBAs, typically holding 4096 bytes of user data. With a 4-byte physical address for each 4KB block of user data, the size of the mapping table is typically quite large. For most devices, having a large mapping table is prohibitive, and typically only a small subset of the mapping table is available within the storage controller in the L2P cache at any one time.

[0024] In various embodiments, there is a tradeoff in the granularity of the mapping between the efficiency of random write operations and the efficiency of the L2P cache. In a first example, a 4KB user data block (containing one or more LBAs) can be mapped to a 4-byte physical address. In a second example, an 8KB user data block (containing twice as many LBAs as a 4KB block) can be mapped to a 4-byte physical address. To perform a 4KB user write in the first example, the data can be written directly and the mapping table updated with the new physical address. To perform a 4KB user write in the second example, another 4KB data block associated with the newly written data must be read from the storage medium, joined to the new 4KB data, and then the newly constructed 8KB block is written to the memory along with a single entry mapping table update. In the second example, the operation is a read-modify-write of the storage device, which is less efficient than the first example (which is only a write). Therefore, the first example has much better performance than the second example described above. However, in the second example, the L2P mapping cache can map twice as much space. For a 32KB L2P cache size, the first example can store 32768 / 4=8192 physical addresses for a total mapped range of 32MB, each of which points to 4KB. For the second example, a 32KB cache is sufficient to hold 8192 physical addresses for a total mapped range of 64MB, each of which points to 8KB.

[0025] In various embodiments, the subject matter partitions the storage system into smaller portions and operates the partitions at different mapping table granularities. In one embodiment, if a 256GB user storage area is available, the first 16GB of data (the first area) can be mapped at 256KB granularity for a single 4-byte physical address, and the remaining 240GB (the second area) can be mapped using 4KB granularity for a single 4-byte physical address. The first area of the storage system mapped at a large granularity will provide poor random write performance because each write less than 256KB involves a 256KB read-modify-write. The second area of the storage system mapped at a smaller granularity will provide better random write performance because there is no read-modify-write penalty for writes as small as 4KB. In another compromise, the entire 16GB range of the first area can be mapped using only 256KB of controller SRAM cache ((16*1024*1024*1024) / (256*1024)), while only 256MB of the user area will be mapped for the second 256KB area. While both the first and second regions offer the same sequential read and write performance, the first region will offer superior random read performance because the entire mapping table for the first region can reside in SRAM at once. Random read performance will be affected for the second region because reads from the second region use a two-read sequence: one read to load the appropriate portion of the mapping table to find the physical address associated with the LBA and a second read to load the data.

[0026] By specifying partition granularity for specific uses, the subject matter provides a significantly improved user experience and more efficient use of the controller's SRAM mapping table resources. For example, the first area is optimal for sequential writes, such as sequential loading of an operating system and critical applications that are updated infrequently, as well as large sequential writes. The first area will provide improved read performance, so that applications in the first area will have excellent load times. In various embodiments, this type of area will be useful for an OS in a mobile device, an automotive device, or the Internet of Things (IoT). Mobile phone manufacturers can take advantage of this by placing proprietary applications in the first area so that they will outperform aftermarket applications that would reside in the second or other areas by default. The second area is optimal for normal write uses, providing the typical experience that users are accustomed to.

[0027] In some embodiments, these advantages can be further enhanced by operating the partitions at different speeds by using faster types of memory for specific partitions. For example, single-level cell (SLC) memory can be used instead of triple-level cell (TLC) NAND, or 3D XPoint type memory can be used for a given partition.

[0028] Various embodiments provide for the definition of one or more regions of a user area in a storage device defined in a table of regions of non-overlapping LBA ranges. By using application-specific selection of mapping table granularity, the subject matter trades controller L2P mapped SRAM resources for random write performance to optimize the user experience for each application and each region of the user area of the storage device. In various embodiments, when an LBA or group of LBAs is written to the storage device, the LBA is checked against the region table to determine the appropriate write granularity for the LBA, the appropriate read-modify-write (if any) is performed, and the appropriate mapping table updates are made depending on the attributes of the selected region. The subject matter also provides for preserving region attributes during junk collection operations. Thus, when junk collection is performed, reads and writes will be performed using the appropriate mapping table chunk size for the region. Due to the limited memory controller resources for L2P mapped data, the granularity can be optimized for specific devices, specific use cases, and / or usage models to achieve market-leading performance.

[0029] In various embodiments of the present subject matter, the variable granularity is permanently stored in a non-volatile memory array. Thus, multiple granularities can be used for regions of the storage device in a permanent operating mode, and the granularity can be accessed by accessing the memory array. In various embodiments, the granularity provides different categories of configurable read services. In various embodiments, multiple regions of the storage device can be assigned different granularities. In one example, two regions of the storage device are assigned different granularities. In another example, three regions of the storage device are assigned different granularities. Without departing from the scope of the present subject matter, other numbers of regions of the storage device can be assigned different granularities. Some embodiments target devices that do not have enough DRAM to hold the entire L2P mapping.

[0030] Aspects of the present disclosure relate to a storage system comprising: a memory array; a random access memory configured to store at least a portion of one or more logical-to-physical (L2P) mapping tables; and a memory controller. The memory controller is programmed to perform operations including: partitioning the memory array into a first portion and a second portion, the first portion and the second portion having non-overlapping logical block addressing (LBA) ranges; assigning a first granularity of a first L2P mapping table entry to the first portion of the memory array designated for a first use; assigning a second granularity of a second L2P mapping table entry to the second portion of the memory array designated for a second use, wherein the second granularity is not equal to the first granularity; and storing at least a portion of the first and second L2P mapping table entries in the random access memory.

[0031] Figure 1An example system (e.g., a host system) 100 is illustrated, which includes a host device 105 and a storage system 110 configured to communicate via a communication interface (I / F) 115 (e.g., a bidirectional parallel or serial communication interface). Host device 105 may include a host processor 106 (e.g., a host central processing unit (CPU) or other processor or processing device) or other host circuitry (e.g., a memory management unit (MMU), interface circuitry, evaluation circuitry 107, etc.). In a specific example, host device 105 may include main memory 108 (e.g., DRAM, etc.) and optionally static memory 109 to support the operation of host processor 106.

[0032] The storage system 110 may include a universal flash storage (UFS) device, an embedded MMC (eMMC TM ) device or one or more other memory devices. For example, if storage system 110 includes a UFS device, communication interface 115 may include a serial bidirectional interface, such as defined in one or more Joint Electron Device Engineering Council (JEDEC) standards (e.g., JEDEC Standard D223D (JESD223D), collectively referred to as JEDEC UFS Host Controller Interface (UFSHCI) 3.0, etc.). In another example, if storage system 110 includes an eMMC device, communication interface 115 may include several parallel bidirectional data lines (e.g., DAT[7:0]) and one or more command lines, such as defined in one or more JEDEC standards (e.g., JEDEC Standard D84-B51 (JESD84-A51), collectively referred to as JEDEC eMMC Standard 5.1, etc.). In other examples, storage system 110 may include one or more other storage devices, or communication interface 115 may include one or more other interfaces depending on host device 105 and storage system 110.

[0033] The storage system 110 may include a memory controller 111, a random access memory (or cache) 113, and a non-volatile memory 112. In an example, the non-volatile memory may include a number of memory devices (e.g., dies or LUNs), such as one or more flash memory devices, each of which includes peripheral circuitry thereon and is controlled by the memory controller 111.

[0034] Flash memory devices typically include one or more groups of single-transistor, floating-gate memory cells. Two common types of flash memory array architectures include NAND and NOR architectures. The floating-gate memory cells of a memory array are typically arranged in a matrix. The gate of each memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a column of the array is coupled together in series, source-to-drain, between a source line and a bit line.

[0035] Each memory cell in a NOR, NAND, 3D crosspoint (Xpoint), holographic RAM (HRAM), MRAM, or one or more other architecture semiconductor memory array can be individually or collectively programmed to one or several programming states. A single-level cell (SLC) can represent one bit of data per cell in one of two programming states (e.g., 1 or 0). A multi-level cell (MLC) can represent data in several programming states (e.g., 2 or 3). n , where n is the bit count of the data). In a specific example, MLC may refer to a memory cell that can store two bits of data in one of four programmed states. A three-level cell (TLC) may represent three bits of data per cell in one of eight programmed states. A four-level cell (QLC) may represent four bits of data per cell in one of 16 programmed states. MLC is used herein in its broader context to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states), including TLC and QLC, among others.

[0036] The storage system 110 may include a MultiMediaCard (MMC) solid-state storage device (e.g., a micro Secure Digital (SD) card, etc.). The MMC device includes several parallel interfaces (e.g., an 8-bit parallel interface) with the host device 105 and is typically a component that is removable from and separate from the host device. In contrast, an embedded MMC (eMMC) device is attached to a circuit board and treated as a component of the host device, with read speeds comparable to Serial ATA (SATA)-based SSD devices. With the increasing demand for mobile device performance, such as to fully enable virtual reality or augmented reality devices and to take advantage of increased network speeds, storage systems have transitioned from parallel to serial communication interfaces. UFS devices (including controllers and firmware) communicate with the host device using a low-voltage differential signaling (LVDS) serial interface with dedicated read / write paths, further improving read / write speeds between the host device and the storage system.

[0037] In three-dimensional (3D) semiconductor memory device technology, vertical floating gate or charge trapping memory structures can be stacked to increase the number of layers, physical pages, and, accordingly, the density of memory cells in a memory device.

[0038] Data is typically stored arbitrarily on a storage system as small units. Even when accessed as a single unit, data can still be received in small, random 4k to 16k single file reads (e.g., 60% to 80% of operations are less than 16k). It is difficult for users and even kernel applications to indicate that data should be stored as a sequential, cohesive unit. File systems are typically designed to optimize space usage rather than sequential retrieval of space.

[0039] The memory controller 111 may receive instructions from the host device 105 and may communicate with the non-volatile memory 112, for example, to transfer (e.g., write or erase) data to or from (e.g., read) one or more memory cells of the non-volatile memory array 112. The memory controller 111 may include, among other things, circuitry or firmware, such as a number of components or integrated circuits. For example, the memory controller 111 may include one or more memory control units, circuits, or components configured to control access across the memory array and provide a translation layer between the host device 105 and the memory system 110.

[0040] The non-volatile memory array 112 (e.g., a 3D NAND architecture semiconductor memory array) may include a number of memory cells arranged in, for example, a number of devices, planes, blocks, or physical pages. As an example, a TLC memory device may include 18,592 bytes (B) of data per page, 1536 pages per block, 548 blocks per plane, and 4 planes per device. As another example, an MLC memory device may include 18,592 bytes (B) of data per page, 1024 pages per block, 548 blocks per plane, and 4 planes per device, but require half the write time and twice the program / erase (P / E) cycles of a corresponding TLC memory device. Other examples may include other numbers or arrangements.

[0041] Figure 2An example method 200 for providing data optimized sub-regions in a storage system is described. The method 200 includes, at 202, partitioning a memory array by a memory controller into a first portion and a second portion, the first portion and the second portion having non-overlapping logical block addressing (LBA) ranges; and, at 204, assigning, by the memory controller, a first granularity of a first L2P mapping table entry for the first portion of the memory array designated for a first use. The method 200 further includes, at 206, assigning, by the memory controller, a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second use, wherein the second granularity is not equal to the first granularity; at 208, storing, by the memory controller, the first granularity and the second granularity in the memory array; and, at 210, storing, by the memory controller, at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

[0042] Figures 3A to 3D An example of a mapping table region in a storage system is described. In various embodiments, a region table mapping is stored at a memory controller and used as a lookup table to determine the granularity of a region to be used for storage or retrieval. In the depicted embodiment, Figure 3D Region 4 is used for O / S or streaming because this region will exhibit the best read performance. Figure 3A Region 1 in the example will exhibit more normal performance and can be used for smaller programs or data that do not have data performance requirements, such as O / S or streaming. In various embodiments, the user can control which type of region data is written to depending on the desired performance and availability. In various embodiments, the subject matter customizes the data regions of the storage system based on the expected workload of the stored data in each region.

[0043] Figure 4 An example schematic diagram illustrating a 3D NAND architecture semiconductor memory array 400 includes an array organized into blocks (e.g., block A 401A, block B 401B, etc.) and sub-blocks (e.g., sub-block A0 401A0, sub-block A1 401B, etc.). n 401A n , sub-block B0 401B0, sub-block B n 401B n etc.) of several memory cell strings (eg, first to third A0 memory strings 405A0 to 407A0, first to third A n Memory string 405A n To 407A n , first to third B0 memory strings 405B0 to 407B0, first to third B n Memory string 405B n to 407B netc.) Memory array 400 represents a portion of a larger number of similar structures that would typically be found in a block, device, or other unit of a memory device.

[0044] Each memory cell string includes source lines (SRC) 435 or source side select gates (SGS) (eg, first to third A0 SGS 431A0 to 433A0, first to third A0 SGS 431A0 to 433A0, first to third A0 SGS 431A0 to 433A0) stacked in a source-to-drain manner along the Z direction. n SGS 431A n To 433A n 、First to third B0 SGS 431B0 to 433B0、First to third B n SGS 431B n to 433B n etc.) and the drain side select gate (SGD) (eg, first to third A0 SGD 426A0 to 428A0, first to third A n SGD 426A n To 428A n , 1st to 3rd B0 SGD 426B0 to 428B0, 1st to 3rd B n SGD 426B n to 428B n Each string of memory cells in the 3D memory array may be arranged as a data line (e.g., bit lines (BL) BL0-BL2 420-422) along the X direction and as a physical page along the Y direction.

[0045] Within a physical page, each layer represents a row of memory cells, and each string of memory cells represents a column. A sub-block may include one or more physical pages. A block may include several sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although illustrated herein as having two blocks, each with two sub-blocks, each sub-block having a single physical page, each physical page having three strings of memory cells, and each string having 8 layers of memory cells, in other examples, the memory array 400 may include more or fewer blocks, sub-blocks, physical pages, strings of memory cells, memory cells, or layers. For example, each string of memory cells may include more or fewer layers (e.g., 16, 32, 64, 128, etc.) as desired, as well as one or more additional layers of semiconductor material above or below the charge storage transistors (e.g., select gates, data lines, etc.). For example, a 48GB TLC NAND memory device may contain 18,592 bytes (B) (16,384 + 2208 bytes) of data per page, 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0046] Each memory cell in the memory array 400 includes a control gate (CG) coupled to (e.g., electrically or otherwise operatively connected to) an access line (e.g., word lines (WL) WL00 through WL70 410A through 417A, WL01 through WL71 410B through 417B, etc.), which can couple the control gates (CG) together across a particular layer or portion of a layer as needed. A particular layer in the 3D memory array, and correspondingly a particular memory cell in a string, can be accessed or controlled using a corresponding access line. Groups of select gates can be accessed using individual select lines. For example, the first through third A0 SGD lines SGDA0 425A0 can be accessed, while the A0 SGD lines SGDA0 426A0 through 428A0 can be accessed using A0 SGD lines SGDA0 427A0. n SGD Line SGDA n 425A n Access 1st to 3rd SGD 426A n To 428A n , the first to third B0 SGDs 426B0 to 428B0 can be accessed using the B0SGD line SGDB0 425B0, and the B n SGD line SGDB n 425B n Access 1st to 3rd B n SGD 426B n to 428B n The first to third A0 SGS431A0 to 433A0 and the first to third A0 SGS431A0 to 433A0 can be accessed using the gate select line SGS0 430A. n SGS 431A n To 433A n , and the first to third B0 SGS 431B0 to 433B0 and the first to third B can be accessed using the gate select line SGS1 430B n SGS 431B n to 433B n .

[0047] In an example, the memory array 400 may include several layers of semiconductor material (e.g., polysilicon, etc.) configured to couple the control gate (CG) of each memory cell or the select gate (or a portion of the CG or select gate) of a corresponding layer of the array. A combination of bit lines (BLs) and select gates, etc., may be used to access, select, or control a particular string of memory cells in the array, and one or more access lines (e.g., word lines) may be used to access, select, or control a particular memory cell at one or more layers in a particular string.

[0048] In a NAND architecture semiconductor memory array, the state of a selected memory cell can be accessed by sensing current or voltage fluctuations associated with a particular data line containing the selected memory cell. The memory array 400 can be accessed using one or more drivers (e.g., by control circuitry, one or more processors, digital logic, etc.). In one example, depending on the type of operation desired to be performed on a particular memory cell or group of memory cells, the one or more drivers can activate a particular memory cell or group of memory cells by driving a particular potential to one or more data lines (e.g., bit lines BL0 to BL2), access lines (e.g., word lines WL0 to WL7), or select gates.

[0049] To program or write data to a memory cell, a programming voltage (Vpgm) (e.g., one or more programming pulses) may be applied to a selected word line (e.g., WL40) and, therefore, to the control gate of each memory cell coupled to the selected word line. The programming pulses may, for example, begin at or near 15V and, in a specific example, may increase in magnitude during each application of the programming pulses. When the programming voltage is applied to the selected word line, a potential (e.g., ground potential (e.g., Vss)) may be applied to the channel between the data line (e.g., bit line) and the substrate (and, therefore, the source and drain) of the memory cell to be programmed, thereby causing charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the channel to the floating gate of the target memory cell.

[0050] In contrast, a pass voltage (Vpass) can be applied to one or more word lines having memory cells not intended for programming, or an inhibit voltage (e.g., Vcc) can be applied to data lines (e.g., bit lines) having memory cells not intended for programming, for example, to inhibit charge transfer from the channel to the floating gates of such non-target memory cells. The pass voltage can be variable, for example, depending on the proximity of the applied pass voltage to the word lines intended for programming. The inhibit voltage can include a supply voltage (Vcc) relative to ground potential (e.g., Vss), such as a voltage from an external source (e.g., a battery, an AC-to-DC converter, etc.).

[0051] As an example, if a programming voltage (e.g., 15V or higher) is applied to a particular word line (e.g., WL40), a 10V pass voltage may be applied to one or more other word lines (e.g., WL30, WL50, etc.) to inhibit programming of non-target memory cells or to preserve the values stored in such memory cells that are not intended to be programmed. As the distance between the applied programming voltage and the non-target memory cells increases, the pass voltage required to avoid programming the non-target memory cells may decrease. For example, if a 15V programming voltage is applied to WL40, a 10V pass voltage may be applied to WL30 and WL50, an 8V pass voltage may be applied to WL20 and WL60, a 7V pass voltage may be applied to WL10 and WL70, and so on. In other examples, the pass voltage, the number of word lines, etc. may be higher or lower, or more or fewer.

[0052] The sense amplifier may be coupled to one or more data lines, such as first, second, or third bit lines (BL0-BL2) 420-422, and may detect the state of each memory cell in the corresponding data line by sensing the voltage or current on the particular data line.

[0053] Between applying one or more programming pulses (e.g., Vpgm), a verify operation may be performed to determine whether the selected memory cell has reached its intended programming state. If the selected memory cell has reached its intended programming state, it may be inhibited from further programming. If the selected memory cell has not yet reached its intended programming state, additional programming pulses may be applied. If the selected memory cell has not reached its intended programming state after a certain number of programming pulses (e.g., a maximum number), the selected memory cell or a string, block, or page associated with the selected memory cell may be marked as defective.

[0054] To erase a memory cell or a group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) may be applied to the substrate (and therefore the channel between the source and drain) of the memory cell to be erased (e.g., using one or more bit lines, select gates, etc.), while the word lines of the target memory cells are maintained at a potential (e.g., ground potential (e.g., Vss)), thereby causing charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the floating gates of the target memory cells to the channel.

[0055] Figure 5An example block diagram illustrates a memory device 500, including a memory array 502 having a plurality of memory cells 504 and one or more circuits or components for providing communication with or performing one or more memory operations on the memory array 502. Although shown with a single memory array 502, in other examples, one or more additional memory arrays, dies, or LUNs may be included. In a specific example, in a memory system having multiple dies or LUNs, the memory device 500 may represent a block diagram of the circuits and components for each die or LUN. The memory device 500 may include a row decoder 512, a column decoder 514, a sense amplifier 520, a page buffer 522, a selector 524, input / output (I / O) circuitry 526, and a memory control unit 530.

[0056] The memory cells 504 of the memory array 502 may be arranged into blocks, such as a first block 502A and a second block 502B. Each block may include sub-blocks. For example, the first block 502A may include a first sub-block 502A0 and a second sub-block 502A n , and the second block 502B may include a first sub-block 502B0 and a second sub-block 502B n Each sub-block may include a number of physical pages, each page including a number of memory cells 504. Although illustrated herein as having two blocks, each block having two sub-blocks, and each sub-block having a number of memory cells 504, in other examples, the memory array 502 may include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, the memory cells 504 may be arranged into a number of rows, columns, pages, sub-blocks, blocks, etc., and accessed, for example, using an access line 506, a first data line 510, or one or more select gates, source lines, etc.

[0057] The memory control unit 530 may control the memory operation of the memory device 500 according to one or more signals or instructions received on the control line 532, including, for example, one or more clock signals or control signals indicating a desired operation (e.g., write, read, erase, etc.), or address signals (A0 to AX) received on one or more address lines 516. One or more devices external to the memory device 500 may control the value of the control signal on the control line 532 or the address signal on the address line 516. Examples of devices external to the memory device 500 may include, but are not limited to, a host, a memory controller, a processor, or a memory controller. Figure 5 One or more circuits or components not described in the specification.

[0058] The memory device 500 can use access lines 506 and first data lines 510 to transfer (e.g., write or erase) data to or transfer (e.g., read) data from one or more memory cells 504. A row decoder 512 and a class decoder 514 can receive and decode address signals (A0 to AX) from address lines 516, can determine which memory cell 504 is to be accessed, and can provide signals to one or more of the access lines 506 (e.g., one or more of the plurality of word lines (WL0 to WLm)) or the first data lines 510 (e.g., one or more of the plurality of bit lines (BL0 to BLn)), such as described above.

[0059] The memory device 500 may include sensing circuitry, such as sense amplifiers 520, configured to determine the value of (e.g., read) data on the memory cell 504 or to determine the value of data to be written to the memory cell 504 using the first data line 510. For example, in a selected string of memory cells 504, one or more of the sense amplifiers 520 may read the logic level in the selected memory cell 504 in response to a read current flowing in the memory array 502 through the selected string to the data line 510.

[0060] One or more devices external to the memory device 500 may communicate with the memory device 500 using the I / O lines (DQ0 through DQN) 508, the address lines 516 (A0 through AX), or the control lines 532. Input / output (I / O) circuitry 526 may use the I / O lines 508, e.g., in accordance with the control lines 532 and the address lines 516, to transfer data values into or out of the memory device 500, e.g., into or out of the page buffer 522 or the memory array 502. The page buffer 522 may store data received from one or more devices external to the memory device 500 before programming the data into the associated portion of the memory array 502, or may store data read from the memory array 502 before transmitting the data to one or more devices external to the memory device 500.

[0061] The column decoder 514 can receive the address signals (A0 to AX) and decode them into one or more column select signals (CSEL1 to CSELn). The selector 524 (e.g., a selection circuit) can receive the column select signals (CSEL1 to CSELn) and select data in the page buffer 522 representing the data value to be read from or programmed into the memory cell 504. The selected data can be transferred between the page buffer 522 and the I / O circuit 526 using the second data line 518.

[0062] The memory control unit 530 may receive positive and negative power signals, such as a power supply voltage (Vcc) 534 and a negative power supply (Vss) 536 (e.g., ground potential), from an external power source (e.g., an internal or external battery, an AC-to-DC converter, etc.). In a specific example, the memory control unit 530 may include a regulator 528 for internally providing the positive or negative power signals.

[0063] Figure 6 A block diagram illustrates an example machine (e.g., a host system) 600 on which any one or more of the techniques (e.g., methodologies) discussed herein may be performed. In alternative embodiments, machine 600 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 600 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 600 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 600 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, an IoT device, an automotive system, or any machine capable of executing instructions (sequentially or otherwise) that specify actions to be taken by that computer. Furthermore, while a single machine is illustrated, the term "machine" should also be construed to include any collection of machines that individually or collectively execute an instruction set (or multiple instruction sets) to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), or other computer cluster configurations.

[0064] As described herein, an example may include or be operable by logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., a group) of circuits implemented in a tangible entity comprising hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system may flexibly change over time and due to potential hardware variability. A circuit system includes components that can perform specific tasks individually or in combination during operation. In an example, the hardware of a circuit system may be invariably designed to perform a specific operation (e.g., hard-wired). In an example, the hardware of a circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), including computer-readable media that is physically modified (e.g., magnetically, electrically, by removably placing particles of constant mass, etc.) to encode instructions for a specific operation. When the physical components are connected, the underlying electrical properties of the hardware components change, for example, from an insulator to a conductor or vice versa. The instructions enable the participating hardware (e.g., execution units or loading mechanisms) to form components of the circuit system in hardware via variable connections to perform a specific task during operation. Accordingly, when the apparatus is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any physical component can be used in more than one member of more than one circuit system. For example, during operation, an execution unit can be used in a first circuit in a first circuit system at one point in time and can be reused by a second circuit in the first circuit system or a third circuit in the second circuit system at a different time.

[0065] The machine (e.g., a computer system, a host system, etc.) 600 may include processing devices 602 (e.g., hardware processors, central processing units (CPUs), graphics processing units (GPUs), hardware processor cores, or any combination thereof), some or all of which may communicate with each other via a communication interface (e.g., a bus) 630, a main memory 604 (e.g., read-only memory (ROM), dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), static memory 606 (e.g., static random access memory (SRAM), etc.), and a storage system 618.

[0066] Processing device 602 may represent one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 602 may be configured to execute instructions 626 to perform the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communicating over a network 620.

[0067] The storage system 618 may include a machine-readable storage medium (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, in whole or in part, within the main memory 604 or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media.

[0068] The term "machine-readable storage medium" should be taken to include a single medium or multiple media that stores one or more sets of instructions, or any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Accordingly, the term "machine-readable storage medium" should be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media. In an example, a massed machine-readable medium includes a machine-readable medium having multiple particles with a constant (e.g., stationary) mass. Accordingly, a massed machine-readable medium is not a transitory propagating signal. Specific examples of massed machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0069] The machine 600 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, one or more of the display unit, input device, or UI navigation device may be a touch screen display. The machine may include a signal generating device (e.g., a speaker) or one or more sensors (e.g., a global positioning system (GPS) sensor, a compass, an accelerometer, or one or more other sensors). The machine 600 may include an output controller, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection) for communicating with or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0070] Instructions 626 (e.g., software, programs, operating system (OS), etc.) or other data are stored on storage system 618 and can be accessed by main memory 604 for use by processing device 602. Main memory 604 (e.g., DRAM) is typically fast but volatile and, therefore, a different type of storage than storage system 618 (e.g., SSD), which is suitable for long-term storage, including when in an "off" state. Instructions 626 or data used by a user or machine 600 are typically loaded into main memory 604 for use by processing device 602. When main memory 604 is full, virtual space from storage system 618 can be allocated to supplement main memory 604; however, because storage system 618 is typically slower than main memory 604, with write speeds typically at least twice as slow as read speeds, the use of virtual memory can significantly reduce the user experience due to storage system latency (compared to main memory 604, such as DRAM). Furthermore, using storage system 618 for virtual memory can significantly reduce the usable lifespan of storage system 618.

[0071] The instructions 624 may also be further transmitted or received over the network 620 using a transmission medium via the network interface device 608 using any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile telephone networks (e.g., cellular networks), plain old telephone (POTS) networks, and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards, known as IEEE 802.16 series of standards, known as ); IEEE 802.15.4 family of standards), point-to-point (P2P) networks. In an example, network interface device 608 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to network 620. In an example, network interface device 608 may include multiple antennas for wireless communication using at least one of single-input, multiple-output (SIMO), multiple-input, multiple-output (MIMO), or multiple-input, single-output (MISO) technology. The term "transmission media" shall be taken to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 600, including digital or analog communication signals or other intangible media used to facilitate communication of such software.

[0072] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Furthermore, the inventors also contemplate examples using any combination or arrangement of those elements shown or described (or one or more aspects thereof) with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0073] All publications, patents, and patent files cited in this file are incorporated herein by reference in their entirety as if individually incorporated by reference. In the event of inconsistent usages between this file and those incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this file; for irreconcilable inconsistencies, the usage in this file controls.

[0074] In this file, as is common in patent files, the terms "a" or "an" are used to include one or more independently of any other instance or usage of "at least one" or "one or more." In this file, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the following claims, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein." Furthermore, in the following claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, objects, or processes that include elements in addition to the elements listed after the term in a claim should still be considered to fall within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0075] In various examples, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including groups of processors or multi-core devices.

[0076] As used in this document, the term "horizontal" is defined as a plane parallel to the conventional plane or surface of a substrate (e.g., the plane beneath a wafer or die), regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "on," "above," and "below" are defined relative to the conventional plane or surface on the top or exposed surface of a substrate, regardless of the orientation of the substrate; and while "on" is intended to imply direct contact of one structure relative to another structure "above" the structure (absent an explicit indication to the contrary), the terms "above" and "below" are expressly intended to identify the relative placement of structures (or layers, features, etc.), which explicitly includes (but is not limited to) direct contact between the identified structures unless specifically identified as such. Similarly, the terms "above" and "below" are not limited to a horizontal orientation, as a structure can be "above" a reference structure if it is the outermost portion of the structure in question at a point in time, even if such structure extends vertically rather than horizontally relative to the reference structure.

[0077] The terms "wafer" and "substrate" are generally used herein to refer to any structure on which an integrated circuit is formed, and also to refer to such structures during the various stages of integrated circuit fabrication. The following detailed description is, therefore, not to be construed in a limiting sense, and the scope of the various embodiments is defined solely by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0078] Various embodiments according to the present disclosure and described herein include memories utilizing a vertical structure of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives will be employed relative to the surface of the substrate on which the memory cells are formed (i.e., a vertical structure will be considered to extend away from the substrate surface, a bottom end of the vertical structure will be considered to be the end closest to the substrate surface, and a top end of the vertical structure will be considered to be the end farthest from the substrate surface).

[0079] As used herein, directional adjectives (e.g., horizontal, vertical, normal, parallel, perpendicular, etc.) may refer to relative orientations and are not intended to require strict adherence to specific geometric properties unless otherwise stated. For example, as used herein, a vertical structure need not be strictly perpendicular to the surface of the substrate, but may be substantially perpendicular to the substrate surface and may form an acute angle (e.g., between 60 and 120 degrees, etc.) with the substrate surface.

[0080] In some embodiments described herein, different doping profiles may be applied to a select gate source (SGS), a control gate (CG), and a select gate drain (SGD), each of which may be formed of or at least include polysilicon in this example. This allows these layers (e.g., polysilicon, etc.) to have different etch rates when exposed to an etching solution. For example, during the formation of a monolithic pillar in a 3D semiconductor device, the SGS and CG may be recessed, while the SGD may remain less recessed or even not recessed at all. Consequently, these doping profiles can be used to selectively etch different layers (e.g., the SGS, CG, and SGD) in a 3D semiconductor device using an etching solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0081] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a desired state is referred to herein as "programming" and can include both writing to the memory cell and erasing from the memory (i.e., the memory cell can be programmed to an erased state).

[0082] It will be understood that when an element is referred to as being “on,” “connected to,” or “coupled to” another element, it can be directly on, directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element, there are no intervening elements or layers present. If two elements are shown in the drawings as having a line connecting them together, then the two elements may be coupled or directly coupled unless otherwise indicated.

[0083] The method examples described herein may be at least partially machine or computer implemented. Some examples may include computer-readable media or machine-readable media encoded with instructions that are operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include program code, such as microcode, assembly language code, high-level language code, or the like. This program code may include computer-readable instructions for performing various methods. The program code may form part of a computer program product. In addition, the program code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., optical disks and digital video disks), magnetic tape cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), and the like.

[0084] Example 1 is a storage system comprising: a memory array; a random access memory configured to store at least a portion of one or more logical-to-physical (L2P) mapping tables; and a memory controller, wherein the memory controller is programmed to perform operations including: partitioning the memory array into a first portion and a second portion, the first portion and the second portion having non-overlapping logical block addressing (LBA) ranges; assigning a first granularity of a first L2P mapping table entry to the first portion of the memory array designated for a first use; assigning a second granularity of a second L2P mapping table entry to the second portion of the memory array designated for a second use, wherein the second granularity is not equal to the first granularity; storing the first granularity and the second granularity in the memory array; and storing at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in the random access memory.

[0085] In Example 2, the subject matter of Example 1 is optionally configured such that the first granularity and the second granularity are stored in a region table in the controller.

[0086] In Example 3, the subject matter of Example 1 is optionally configured such that the first granularity is greater than the second granularity.

[0087] In Example 4, the subject matter of Example 1 is optionally configured such that the second granularity is greater than the first granularity.

[0088] In Example 5, the subject matter of any of Examples 1-4 is optionally configured such that the first portion and the second portion are different memory types.

[0089] In Example 6, the subject matter of any of Examples 1-5 is optionally configured such that partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup.

[0090] In Example 7, the subject matter of any of Examples 1-5 is optionally configured such that partitioning the memory array into a first portion and a second portion includes partitioning the memory array during runtime.

[0091] In Example 8, the subject matter of any of Examples 1-5 is optionally configured such that partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup and repartitioning the memory array during runtime.

[0092] Example 9 is a method comprising: partitioning, by a memory controller, a memory array into a first portion and a second portion, the first portion and the second portion having non-overlapping logical block addressing (LBA) ranges; assigning, by the memory controller, a first granularity of a first logical-to-physical (L2P) mapping table entry to the first portion of the memory array designated for a first use; assigning, by the memory controller, a second granularity of a second L2P mapping table entry to the second portion of the memory array designated for a second use, wherein the second granularity is not equal to the first granularity; storing, by the memory controller, the first granularity and the second granularity in the memory array; and storing, by the memory controller, at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

[0093] In Example 10, the subject matter of Example 9 is optionally configured such that the method further includes: partitioning, by the memory controller, the memory array to include a third portion, the first portion, the second portion, and the third portion having non-overlapping logical block addressing (LBA) ranges; and assigning, by the memory controller, a third granularity of a third L2P mapping table entry to the third portion of the memory array designated for a third use.

[0094] In Example 11, the subject matter of Example 10 is optionally configured such that the third granularity is not equal to the first granularity and the second granularity.

[0095] In Example 12, the subject matter of Example 10 or 11 is optionally configured such that the method further includes: storing, by the memory controller, the third granularity in the memory array; and storing, by the memory controller, at least a portion of the third L2P mapping table entry in the L2P cache of the memory controller.

[0096] In Example 13, the subject matter of any of Examples 10-12 is optionally configured such that the method further includes: partitioning, by the memory controller, the memory array to include a fourth portion, the first portion, the second portion, the third portion, and the fourth portion having non-overlapping logical block addressing (LBA) ranges; and assigning, by the memory controller, a fourth granularity of a fourth L2P mapping table entry to the fourth portion of the memory array designated for a fourth use.

[0097] In Example 14, the subject matter of Example 13 is optionally configured such that the fourth granularity is not equal to the first granularity, the second granularity, and the third granularity.

[0098] In Example 15, the subject matter of Example 13 or 14 is optionally configured such that the method further includes: storing, by the memory controller, the fourth granularity in the memory array; and storing, by the memory controller, at least a portion of the fourth L2P mapping table entry in the L2P cache of the memory controller.

[0099] Example 16 is a device-readable storage medium providing instructions that, when executed by a processor, cause the processor to perform operations comprising: partitioning a memory array into a first portion and a second portion, the first portion and the second portion having non-overlapping logical block addressing (LBA) ranges; assigning a first granularity of a first logical-to-physical (L2P) mapping table entry to the first portion of the memory array designated for a first use; assigning a second granularity of a second L2P mapping table entry to the second portion of the memory array designated for a second use, wherein the second granularity is not equal to the first granularity; storing the first granularity and the second granularity in the memory array; and storing at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache.

[0100] In Example 17, the subject matter of Example 16 is optionally configured such that the first portion and the second portion are different memory types.

[0101] In Example 18, the subject matter of Example 16 or 17 is optionally configured such that partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup.

[0102] In Example 19, the subject matter of Example 16 or 17 is optionally configured such that partitioning the memory array into a first portion and a second portion includes partitioning the memory array during runtime.

[0103] In Example 20, the subject matter of Example 16 or 17 is optionally configured such that partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup and repartitioning the memory array during runtime.

[0104] Example 21 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-20.

[0105] Example 22 is an apparatus comprising means for implementing any one of Examples 1-20.

[0106] Example 23 is a system for implementing any one of Examples 1 to 20.

[0107] Example 24 is a method for implementing any one of Examples 1 to 20.

[0108] The above description is intended to be illustrative and non-restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. After reading the above description, other embodiments can be used by, for example, a person of ordinary skill in the art. The [Abstract] is provided to comply with 37 CFR § 1.72 (b) to allow readers to quickly determine the nature of the technical disclosure. The [Abstract] is submitted based on the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above [Detailed Description], various features can be grouped together to simplify the present disclosure. This should not be interpreted as wishing that unclaimed disclosed features are essential to any claim. On the contrary, the subject matter of the invention may lie in less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the [Implementation], wherein each claim is independently a separate embodiment, and it is expected that such embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the appended claims together with the full scope of equivalents given to this claim.

Claims

1. A storage system comprising: Memory; and A controller configured to perform operations comprising: Dividing the memory into a plurality of portions having non-overlapping logical block addressing (LBA) ranges; assigning a respective performance level to a respective logical-to-physical L2P mapping table entry for each of the plurality of portions of the memory, wherein at least two of the performance levels are different from one another, and wherein the respective L2P mapping table entries include a respective granularity; and Data indicating the size of the corresponding granule is stored in the memory. 2 . The storage system of claim 1 , wherein at least a portion of the L2P mapping table entries are stored in an L2P cache of the controller.

3. The storage system of claim 1, wherein the respective performance levels are assigned according to a respective designated usage of each of the plurality of portions of the memory.

4. The memory system of claim 3, wherein the plurality of portions of memory include multiple types of memory operating at different speeds. 5 . The storage system of claim 1 , wherein the plurality of portions includes a first portion having a first granularity that is greater than a second granularity of a second portion of the plurality of portions. 6 . The storage system of claim 5 , wherein a first write performance corresponding to the first granularity is less than a second write performance corresponding to the second granularity. 7 . The storage system of claim 6 , wherein a first read performance corresponding to the first granularity is better than a second read performance corresponding to the second granularity.

8. The storage system of claim 7, wherein the first portion has better sequential write performance than the second portion.

9. The memory system of claim 1, wherein the memory system comprises a NAND memory device.

10. A method comprising: A controller of the storage system divides a memory of the storage system into a plurality of parts having non-overlapping logical block addressing (LBA) ranges; assigning, by the controller, a respective performance level to a respective logical-to-physical L2P mapping table entry for each of the plurality of portions of the memory, wherein at least two of the performance levels are different from one another; Assigning, by the controller, a corresponding granularity to the corresponding L2P mapping table entry; as well as Data indicating the size of the corresponding granule is stored in the memory.

11. The method of claim 10, wherein the respective performance levels are assigned according to a respective designated usage of each of the plurality of portions of the memory.

12. The method according to claim 10, further comprising: The corresponding granularity is stored in the memory.

13. The method according to claim 12, further comprising: At least a portion of the L2P mapping table entries are stored in an L2P cache of the controller.

14. The method of claim 12, wherein the plurality of portions includes a first portion having a first granularity that is larger than a second granularity of a second portion of the plurality of portions. The method of claim 14 , wherein the first portion has better sequential write performance than the second portion.

16. A tangible, non-transitory, machine-readable storage medium configured to store instructions that, when executed by a controller of a storage system, cause the controller to: Dividing the memory of the storage system into a plurality of portions having non-overlapping logical block addressing (LBA) ranges; assigning a respective performance level to a respective logical-to-physical L2P mapping table entry for each of the plurality of portions of the memory, wherein at least two of the performance levels are different from each other; assigning a corresponding granularity to the corresponding L2P mapping table entry; and Data indicating the size of the corresponding granule is stored in the memory.

17. The tangible, non-transitory, machine-readable storage medium of claim 16, wherein the storage system comprises a NAND memory device.

18. The tangible, non-transitory, machine-readable storage medium of claim 16, wherein the instructions further cause the controller to: storing the corresponding granularity in the memory; and At least a portion of the L2P mapping table entries are stored in an L2P cache of the controller.

19. The tangible, non-transitory machine-readable storage medium of claim 18, wherein the plurality of portions includes a first portion having a first granularity that is larger than a second granularity of a second portion of the plurality of portions, and wherein the first portion has better sequential write performance than the second portion.

Images