An equidistant gate superposition method, device and medium based on FPGA

Abstract

The present application discloses an equidistance gate superposition method, device and medium based on FPGA, which relates to the field of computer technology. The method includes: determining multiple write addresses according to range gate data, judging the same situation of multiple write addresses, the same situation includes that they are not the same, there are two consecutive addresses that are the same, and there is a same address every other address; performing corresponding cache processing on the range gate data according to the same situation. The present application realizes intelligent caching and processing of range gate data by accurately judging the same situation of multiple write addresses. It not only optimizes the data processing process and reduces unnecessary repeated writing, but also further optimizes the data storage structure and improves resource utilization by splitting the RAM address into RAM low bit and RAM high bit. The present application deals with the problem of insufficient BRAM resources, significantly shortens the time for function implementation, and realizes a good match between write and write time, thereby effectively improving system efficiency.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an equidistant gate superposition method, device and medium based on FPGA. Background Art

[0002] In the real-time echo simulation of synthetic aperture radar (SAR), efficiently processing the distance and phase information of all points in the irradiated area is the key to achieving high-precision imaging. For the huge amount of data processing, it is difficult to meet the real-time requirements due to the limitation of computing speed and resource utilization efficiency. For this reason, field programmable gate array (FPGA) is widely used as a processing platform in the market, and its parallel processing capability is used to accelerate the calculation process. Although FPGA can effectively shorten the time required for processing each data point by deploying multiple pipelines for parallel processing, the subsequent data aggregation and accumulation operations become extremely complicated. Specifically, in each clock cycle, each pipeline can generate a data group containing range gate data and phase data. The phase information in these data groups needs to be accumulated according to the range gate to construct a complete echo feature transfer function. Due to the design limitations of the block random access memory (BRAM) inside the FPGA, the same address cannot be read and written in the same clock cycle, which directly hinders the process of directly accumulating phase data. In actual applications, when the phase information corresponding to a range gate needs to be updated, the existing phase value at the address must be read first, added to the newly calculated phase value, and then written back to the same address. This feature of reading first and then writing, and reading and writing cannot be performed at the same time, not only increases the complexity of the processing logic, but may also lead to bottlenecks in processing efficiency, especially in scenarios with high data throughput. In addition, with the increase in the number of pipelines and the improvement in computing accuracy, the consumption of BRAM resources has also increased dramatically, further exacerbating the difficulty of resource allocation and management. Summary of the invention

[0003] In order to solve the above problems, the present application proposes an equidistance gate superposition method based on FPGA, including: determining multiple write addresses according to range gate data, judging the same situation of the multiple write addresses, the same situation includes that they are all different, there are two consecutive addresses that are the same, and there is a same address every other address; according to the same situation, the range gate data is cached accordingly.

[0004] In one example, the method further includes: determining a RAM address, splitting the RAM address to obtain a RAM low bit and a RAM high bit; and storing the range gate data via the RAM low bit and the RAM high bit.

[0005] In one example, the range gate data is cached accordingly according to the same situation, specifically including: if the same situation is not the same, the write address and the range gate data corresponding to the write address are cached according to a preset cycle; the write address after cache processing is read to obtain read data, the read data is superimposed, and the superimposed read data is written.

[0006] In one example, the range gate data is cached accordingly according to the same situation, specifically including: if the same situation is that there are two consecutive addresses that are the same, determining the subsequent data and the first cache data, adding the subsequent data and the first cache data to obtain the added data; and writing the added data into the position corresponding to the first cache data.

[0007] In one example, the range gate data is cached accordingly according to the same situation, specifically including: if the same situation is that there is a sameness with one address left, then the backward data and the second cache data are determined, and the backward data and the second cache data are added to obtain the added data; and the added data is written into the position corresponding to the first cache data.

[0008] In one example, the method further includes: acquiring the first cache data, and writing the first cache data into a location corresponding to the second cache data.

[0009] In one example, the method further includes: determining RAM resources of the FPGA, and packaging the RAM resources to store the range gate data.

[0010] In one example, the method further includes: determining a plurality of parallel processing units through the FPGA, so as to process the range gate data through the plurality of parallel processing units.

[0011] On the other hand, the present application also proposes an equidistant gate superposition device based on FPGA, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the equidistant gate superposition device based on FPGA can execute: determining multiple write addresses based on range gate data, judging the same situation of the multiple write addresses, the same situation including that they are all different, there are two consecutive addresses that are the same, and there is a same address every other address; performing corresponding cache processing on the range gate data according to the same situation.

[0012] On the other hand, the present application also proposes a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured to: determine multiple write addresses based on range gate data, and judge the same situation of the multiple write addresses, wherein the same situation includes that they are not the same, there are two consecutive addresses that are the same, and there is a same address every other address; and perform corresponding cache processing on the range gate data based on the same situation.

[0013] This application realizes intelligent caching and processing of range gate data by accurately judging the same situation of multiple write addresses. It not only optimizes the data processing process and reduces unnecessary repeated writing, but also further optimizes the data storage structure and improves resource utilization by splitting the RAM address into RAM low and RAM high. At the same time, the packaging management of RAM resources inside the FPGA makes data processing more flexible and efficient. This application solves the problem of insufficient BRAM resources, significantly shortens the time for function implementation, and achieves a good match between write and write time, thereby effectively improving system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0015] Figure 1 A schematic diagram of a flow chart of an equidistant gate superposition method based on FPGA in an embodiment of the present application;

[0016] Figure 2 This is a schematic diagram of the real-time SAR echo in the embodiment of the present application;

[0017] Figure 3 This is a schematic diagram of an equidistant gate superposition device based on FPGA in an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0019] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0020] When calculating the echo of a surface target or SAR echo, the concentric circle algorithm is usually used to generate a transfer function, which is then convolved with the original signal to generate an echo signal. In the process of generating the transfer function, it is necessary to calculate which distance unit each point in the map belongs to and to superimpose the complex values ​​of the same distance unit. Using FPGA to complete this requires calling BRAM resources. The first data to arrive is directly written into the BRAM cache. The data of the same range gate that arrives later needs to read out the original data of the same range gate and then add it and write it into the BRAM of the original address for cache until all are written. Read out in sequence. During the writing process, each point needs to go through four processes in sequence: cache waiting, reading data from the same range gate, data superposition, and new data writing. It takes a long time. After writing is completed, the data needs to be read out in sequence, which further increases the time. It can only be used in scenarios where the radar pulse repetition period is relatively large, and BRAM resources are very limited. When there are many points, caching and superposition are more resource-intensive.

[0021] like Figure 1 As shown, in order to solve the above problems, an embodiment of the present application provides an equidistant gate superposition method based on FPGA, the method comprising:

[0022] S101, determining a plurality of write addresses according to range gate data, and judging the sameness of the plurality of write addresses, wherein the sameness includes that they are not the same, two consecutive addresses are the same, and there are two addresses that are the same every other address.

[0023] like Figure 2 As shown in the figure, FPGA technology is used to process trajectory data, which involves reading reference map data from DDR. After solving, the data of different position points are parallelly distributed to different pipelines in the FPGA chip for efficient slant range calculation. Subsequently, for each calculated slant range, the corresponding range gate and its corresponding system function modulation result are determined. These two key data are then sent to the equidistant gate superposition module for fine equidistant gate superposition processing. After this process, superposition within the pipeline and data superposition across different FPGA chips are also performed to achieve a significant improvement in overall processing efficiency and accuracy.

[0024] In the actual FPGA project implementation, in order to efficiently realize the superposition of equidistant gates, the RAM resources inside the FPGA are utilized. In particular, for situations where resources are limited, the URAM resources in the VU series FPGA are used to save precious BRAM resources. URAM resources are encapsulated and instantiated in a large bit width manner to simulate the use of BRAM resources, thereby optimizing resource utilization while ensuring performance. This design ensures that even within the same clock cycle, there will be no simultaneous read and write conflicts for the same address data, and only one clock cycle of waiting time is required when reading data, which effectively improves data processing efficiency and system stability. The RAM structure is shown in Table 1 below:

[0025] Table 1 RAM structure

[0026]

[0027] When storing range gate data, in order to improve data reading efficiency, the data of two adjacent range gates, data0 and data1, are stored in the high and low bits of the same address of RAM, respectively. Specifically, at address 0000 of RAM, data0 of range gate 0000 is stored in the low bit, while data1 of range gate 0001 is stored in the high bit. When reading out the data of 100 range gates in sequence, the time originally required for 100 clock cycles can be reduced to about 50 clock cycles, and each reading can obtain the data of two range gates at the same time, thereby significantly saving the reading time. The correspondence between RAM storage data and range gates is shown in Table 2 below:

[0028] Table 2 Correspondence between RAM storage data and range gate

[0029]

[0030] S102: Perform corresponding cache processing on the range gate data according to the same situation.

[0031] In order to solve the rate mismatch problem caused by the need to superimpose input data, the write and read logic of the range gate is divided into three cases. First, when the input write address, that is, the range gate, is not equal, the input address and the corresponding data are cached for one or two beats, and the data given to the read address at the same time is output from the port and then superimposed and written; second, when two consecutive addresses are the same, the latter data is added to the data that has been cached for one beat, and then written to the data position of the cache for one beat; third, when the address is the same every other time, the latter data is added to the data that has been cached for two beats, and then assigned to the data position of the cache for one beat, and the data originally cached for one beat is given to the cache for two beats. If the second and third cases do not occur in the next clock, that is, when the write addresses are not the same, the first case is used for writing.

[0032] The original 100 random addresses required 400 clock cycles to complete the accumulation. Under the above logic settings, it only takes 103 cycles to complete. When storing the range gate data, one address stores two range gate data. When determining whether they are the same address, 0000 and 0001 are determined as one address, or 0002 and 0003 are determined as one address. After reading the data of the corresponding address, since it is stored according to the high and low bits, for example, if it involves the 0003 range gate, only the data corresponding to the 0003 range gate is processed, and the data of the 0002 range gate read out together keeps the original value.

[0033] In one embodiment, FPGA is configured as multiple independent parallel processing units. These parallel processing units can process the input range gate data simultaneously and independently. Through parallel design, FPGA significantly improves the speed and throughput of data processing, so that more data points can be processed in a limited time, thereby meeting the high requirements of complex radar systems for real-time performance and accuracy.

[0034] like Figure 3 As shown, the embodiment of the present application also provides an equidistant gate superposition device based on FPGA, including:

[0035] at least one processor; and,

[0036] a memory communicatively connected to at least one processor; wherein,

[0037] The memory stores instructions executable by at least one processor, and the instructions are executed by at least one processor to enable an equidistant gate stacking device based on an FPGA to perform:

[0038] Determine multiple write addresses according to the range gate data, and judge the same situation of the multiple write addresses, wherein the same situation includes that all the addresses are different, two consecutive addresses are the same, and there is a same address every other address;

[0039] The range gate data is cached accordingly according to the same situation.

[0040] The embodiment of the present application further provides a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured as follows:

[0041] Determine multiple write addresses according to the range gate data, and judge the same situation of the multiple write addresses, wherein the same situation includes that all the addresses are different, two consecutive addresses are the same, and there is a same address every other address;

[0042] The range gate data is cached accordingly according to the same situation.

[0043] In the 1990s, it was very clear whether the improvement of a technology was hardware improvement (for example, improvement of the circuit structure of diodes, transistors, switches, etc.) or software improvement (improvement of the method flow). However, with the development of technology, many improvements of the method flow today can be regarded as direct improvements of the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that the improvement of a method flow cannot be implemented with hardware entity modules. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask chip manufacturers to design and make dedicated integrated circuit chips. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one kind of HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0044] The controller may be implemented in any suitable manner, for example, the controller may take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) executable by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller may also be implemented as part of the control logic of the memory. It is also known to those skilled in the art that, in addition to implementing the controller in a purely computer-readable program code manner, the controller may be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, such a controller may be considered as a hardware component, and the devices for implementing various functions included therein may also be considered as structures within the hardware component. Or even, the devices for implementing various functions may be considered as both software modules for implementing the method and structures within the hardware component.

[0045] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0046] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0047] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0048] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0049] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0050] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0051] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0052] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0053] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0054] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0055] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0056] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0057] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. An equidistant gate superposition method based on FPGA, characterized in that: include: Determine multiple write addresses according to the range gate data, and judge the same situation of the multiple write addresses, wherein the same situation includes that all the addresses are different, two consecutive addresses are the same, and there is a same address every other address; Perform corresponding cache processing on the range gate data according to the same situation; If the above are not the same, the input address and corresponding data are cached for one or two beats, and the data given to the read address at the same time are output from the port and then superimposed and written; When there are two consecutive addresses that are the same, the latter data is added to the data that has been cached for one beat, and then written into the data position of the cached data for one beat; When there is a same address every other time, the latter data is added to the data that has been cached for two beats before, and the data that has been cached for one beat is assigned to the data position of the cache for one beat, and the data that has been cached for one beat is assigned to the position of the cache for two beats; When the next clock does not occur in the case where two consecutive addresses are identical and the case where every other address is identical, that is, when the write addresses are different, writing is performed in the case where both addresses are different.

2. The method according to claim 1, characterized in that The method further comprises: Determine a RAM address, and split the RAM address to obtain a RAM low bit and a RAM high bit; The range gate data is stored via the RAM low bit and the RAM high bit.

3. The method according to claim 1, characterized in that According to the same situation, the range gate data is cached accordingly, specifically including: If the same situation is that they are not all the same, cache processing is performed on the write address and the range gate data corresponding to the write address according to a preset cycle; The write address after the cache processing is read to obtain read data, the read data is superimposed, and the superimposed read data is written.

4. The method according to claim 1, characterized in that: According to the same situation, the range gate data is cached accordingly, specifically including: If the identical situation is that there are two consecutive identical addresses, determining the subsequent data and the first cache data, and adding the subsequent data and the first cache data to obtain the added data; The added data is written into a position corresponding to the first cache data.

5. The method according to claim 1, characterized in that According to the same situation, the range gate data is cached accordingly, specifically including: If the identical situation is that there is an identical existence at every other address, determining the backward data and the second cache data, and adding the backward data and the second cache data to obtain the added data; The added data is written into a position corresponding to the first cache data.

6. The method according to claim 5, characterized in that The method further comprises: The first cache data is obtained, and the first cache data is written into a position corresponding to the second cache data.

7. The method according to claim 1, characterized in that The method further comprises: The RAM resources of the FPGA are determined, and the RAM resources are packaged to store the range gate data.

8. The method according to claim 1, characterized in that The method further comprises: A plurality of parallel processing units are determined by the FPGA, so as to process the range gate data by the plurality of parallel processing units.

9. An equidistant gate superposition device based on FPGA, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the FPGA-based equidistant gate superposition device to perform: Determine multiple write addresses according to the range gate data, and judge the same situation of the multiple write addresses, wherein the same situation includes that all the addresses are different, two consecutive addresses are the same, and there is a same address every other address; Perform corresponding cache processing on the range gate data according to the same situation; If the above are not the same, the input address and corresponding data are cached for one or two beats, and the data given to the read address at the same time are output from the port and then superimposed and written; When there are two consecutive addresses that are the same, the latter data is added to the data that has been cached for one beat, and then written into the data position of the cached data for one beat; When there is a same address every other time, the latter data is added to the data that has been cached for two beats before, and the data that has been cached for one beat is assigned to the data position of the cache for one beat, and the data that has been cached for one beat is assigned to the position of the cache for two beats; When the next clock does not occur in the case where two consecutive addresses are identical and the case where every other address is identical, that is, when the write addresses are different, writing is performed in the case where both addresses are different.

10. A non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions are configured to: Determine multiple write addresses according to the range gate data, and judge the same situation of the multiple write addresses, wherein the same situation includes that all the addresses are different, two consecutive addresses are the same, and there is a same address every other address; Perform corresponding cache processing on the range gate data according to the same situation; If the above are not the same, the input address and corresponding data are cached for one or two beats, and the data given to the read address at the same time are output from the port and then superimposed and written; When there are two consecutive addresses that are the same, the latter data is added to the data that has been cached for one beat, and then written into the data position of the cached data for one beat; When there is a same address every other time, the latter data is added to the data that has been cached for two beats before, and the data that has been cached for one beat is assigned to the data position of the cache for one beat, and the data that has been cached for one beat is assigned to the position of the cache for two beats; When the next clock does not occur in the case where two consecutive addresses are identical and the case where every other address is identical, that is, when the write addresses are different, writing is performed in the case where both addresses are different.

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