A method for predicting electrical performance degradation of SiC MOSFET

Abstract

The invention relates to a method for predicting electrical performance degradation of SiC MOSFET. The method analyzes three influencing factors of gate-source voltage, temperature and degradation time, and constructs a first degradation characterization model structure of a long channel threshold voltage under zero drain-source voltage, a second degradation characterization model structure of a mobility under a zero bias electric field, and a third degradation characterization model structure of a first-order body effect coefficient of a threshold voltage according to a basic model of SiC MOSFET. Then, a high-temperature gate bias experiment on a target SiC MOSFET device is performed, and model training is performed to obtain a first degradation characterization model, a second degradation characterization model, and a third degradation characterization model. Finally, the three constructed degradation characterization models are embedded in a conventional SiC MOSFET device electrical characteristic SPICE model to obtain a SiC MOSFET model for predicting electrical performance degradation, thereby realizing efficient prediction of electrical performance degradation.

Description

Technical Field

[0001] The invention relates to a method for predicting electrical performance degradation of SiC MOSFET, belonging to the technical field of power semiconductor devices. Background Art

[0002] With the continuous advancement of process technology, traditional Si-based materials can no longer meet people's needs. The development of structures such as superjunction MOS and IGBT has also approached the limit of Si materials. As an important material for the development of third-generation semiconductors, SiC has attracted widespread attention from the scientific community for its large bandgap, high critical breakdown electric field and good high-speed switching characteristics. It is an ideal material for preparing high-temperature, high-voltage and high-frequency devices, and is widely used in power electronics fields such as new energy vehicles, rail transit and smart grids.

[0003] With the widespread application of SiC MOSFET devices, the performance of SiC MOSFET devices has an increasingly greater impact on the entire power electronic system. In actual situations, as the use time increases, the performance of SiC MOSFET devices will degrade. How to predict the degradation of SiC MOSFET devices and better ensure the reliability of the devices has always been the focus of researchers. At present, most of the research on SiC MOSFET focuses on a certain parameter, and the influencing factors considered are relatively single. In this case, the SiC MOSFET model established is difficult to work in actual power electronic systems. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a method for predicting the electrical performance degradation of SiC MOSFET, which can effectively characterize the gate-source voltage V GS , Temperature T a The degradation of the electrical performance of the target SiC MOSFET device under the combined effect of and degradation time t.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solution: The present invention designs a method for predicting the electrical performance degradation of SiC MOSFET, and implements the electrical performance degradation prediction of the target SiC MOSFET device for the application of the target SiC MOSFET device connected to the circuit, comprising the following steps:

[0006] Step A. Create a zero drain-source voltage V for the target SiC MOSFET device DS Lower long channel threshold voltage V TH0 About the gate-source voltage V GS , Temperature T a , the first degradation representation model structure of the degradation duration t;

[0007] Construct the mobility μ0 with respect to the gate-source voltage V under zero bias electric field GS , Temperature T a , the second degradation representation model structure of the degradation time t;

[0008] Construct the threshold voltage first-order body effect coefficient k1 with respect to the gate-source voltage V GS , a third degradation representation model structure with a degradation time t, and then proceeding to step B;

[0009] Step B. Perform a high temperature gate bias experiment on the target SiC MOSFET device, perform data fitting on the first degradation characterization model structure, the second degradation characterization model structure, and the third degradation characterization model structure, respectively, obtain the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model, and then proceed to step C;

[0010] Step C. embedding the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model into the conventional SiC MOSFET device electrical characteristic SPICE model to obtain a SiC MOSFET model corresponding to the target SiC MOSFET device, which is used to predict the electrical performance degradation of the target SiC MOSFET device.

[0011] As a preferred technical solution of the present invention, step A comprises the following:

[0012] According to the Arrhenius model that constitutes the basic model of SiC MOSFET Degradation time model ΔV TH0 =W1t n , Inverse power law model W1=P1V GS n , for the target SiC MOSFET device, build a zero drain-source voltage V DS Lower long channel threshold voltage V TH0 About the gate-source voltage V GS , Temperature T a The structure of the first degradation representation model with degradation duration t is as follows:

[0013]

[0014] Where A and E represent the constants to be fitted, n' represents the temperature T in the first degradation characterization model. a The coefficient to be fitted is n, which represents the coefficient of the first degradation characterization model related to the gate-source voltage V GS and temperature T a The relevant coefficients to be fitted, E arepresents the activation energy required for SiC MOSFET degradation, k represents the Boltzmann constant, W1 represents the electrical parameter under the first degradation characterization model structure, Y1 represents the constant under the first degradation characterization model structure, ΔV TH0 Indicates V TH0 The change in P1 represents the constant under the first degradation characterization model structure.

[0015] As a preferred technical solution of the present invention, step A comprises the following:

[0016] According to the Arrhenius model that constitutes the basic model of SiC MOSFET Degradation time model Δμ0=W2t m , Inverse power law model W2=P2V GS m , for the target SiC MOSFET device, the mobility μ0 under zero bias electric field is constructed with respect to the gate-source voltage V GS , Temperature T a The structure of the second degradation representation model with degradation duration t is as follows:

[0017]

[0018] Where B and D represent the constants to be fitted, and m' represents the temperature T in the second degradation characterization model. a The coefficient to be fitted is related to the gate-source voltage V GS and temperature T a The relevant coefficients to be fitted, E a represents the activation energy required for SiC MOSFET degradation, k represents the Boltzmann constant, W2 represents the electrical parameter under the second degradation characterization model, Y2 represents the constant under the second degradation characterization model, Δμ0 represents the change of μ0, and P2 represents the constant under the second degradation characterization model.

[0019] As a preferred technical solution of the present invention, the step A comprises the following:

[0020] According to the degradation time model Δk1=W3t that constitutes the basic model of SiC MOSFET h , Inverse power law model W3=P3V GS h , for the target SiC MOSFET device, construct the threshold voltage first-order body effect coefficient k1 with respect to the gate-source voltage V GS The structure of the third degradation representation model with degradation duration t is as follows:

[0021] k1=C+(F+GV GS )tw

[0022] Where C, F, and G represent the constants to be fitted, and h represents the gate-source voltage V in the third degradation characterization model. GS The coefficients to be fitted are as follows: h' represents the coefficients of the second degradation characterization model related to temperature T a The relevant coefficients to be fitted, W3 represents the electrical parameters under the third degradation characterization model structure, Δk1 represents the change of k1, and P3 represents the constant under the third degradation characterization model structure.

[0023] As a preferred technical solution of the present invention: the step B includes the following steps B1 to B2;

[0024] Step B1. Based on a preset temperature T a1 ,…,T ai ,…,T aI Respectively with the preset J gate-source voltages V GS1 ,…,V GSj ,…,V GSJ One-to-one combination, respectively, the temperature T in each combination ai and the gate-source voltage V GSj , according to the degradation time t, a high temperature gate bias test is performed on the target SiC MOSFET device, and the target SiC MOSFET device is tested to obtain the output characteristics and transfer characteristics corresponding to the target SiC MOSFET device, and then enter step B2;

[0025] Step B2. Based on the output characteristics and transfer characteristics corresponding to the target SiC MOSFET device, data fitting is performed for the first degradation characterization model structure, the second degradation characterization model structure, and the third degradation characterization model structure, respectively, to obtain the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model, and then proceed to step C.

[0026] As a preferred technical solution of the present invention: the output characteristics and transfer characteristics corresponding to the target SiC MOSFET device include the drain-source current I DS With the drain-source voltage V DS The data changes with the change, and the drain-source current I DS With the gate-source voltage V GS Data that changes.

[0027] The electrical performance degradation prediction method for SiC MOSFET described in the present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0028] (1) The present invention designs a method for predicting the electrical performance degradation of SiC MOSFET, analyzing the gate-source voltage V GS , Temperature T a, degradation time t, and the three influencing factors of the degradation time t. According to the Arrhenius model, degradation time model, and inverse power law model that constitute the basic model of SiC MOSFET, the zero drain-source voltage V DS Lower long channel threshold voltage V TH0 The first degradation characterization model structure of the SiC MOSFET device, the second degradation characterization model structure of the mobility μ0 under zero bias electric field, and the third degradation characterization model structure of the threshold voltage first-order body effect coefficient k1 are constructed, and then a high-temperature gate bias experiment on the target SiC MOSFET device is performed, and model training is performed to obtain the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model respectively; finally, the three constructed degradation characterization models are embedded in the traditional SiC MOSFET device electrical characteristic SPICE model to obtain the SiC MOSFET model for predicting electrical performance degradation, and then the reliability and component life analysis of the target SiC MOSFET device is performed to achieve efficient prediction of electrical performance degradation;

[0029] (2) The electrical performance degradation prediction method designed by the present invention for SiC MOSFET is successfully used in the gate-source voltage V GS , Temperature T a The SiC MOSFET model is established under the combined effect of t and degradation time, which can accurately predict the different gate-source voltages V GS and temperature T a The electrical performance degradation of the target SiC MOSFET device with the degradation time t can effectively evaluate the reliability and life of the target SiC MOSFET device, which has strong practical significance; and the three degradation characterization models constructed are simple in form and have no iterative functions, which are convenient and fast in practical application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a flow chart of a method for predicting electrical performance degradation of SiC MOSFET designed in the present invention;

[0031] Figure 2 It is a flow chart for establishing the first degradation characterization model structure in the design of the present invention;

[0032] Figure 3 It is a flow chart for establishing the second degradation characterization model structure in the design of the present invention;

[0033] Figure 4 It is a flow chart for establishing the third degradation characterization model structure in the design of the present invention;

[0034] Figure 5 It is a schematic diagram of the comparison results of the measured values ​​and the degradation fitting values ​​of the output characteristics and transfer characteristics corresponding to the target SiC MOSFET device under the design and application embodiment of the present invention. DETAILED DESCRIPTION

[0035] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0036] The present invention is a method for predicting the electrical performance degradation of SiC MOSFET. The method predicts the electrical performance degradation of the target SiC MOSFET device for the application of the target SiC MOSFET device connected to the circuit. In practical applications, Figure 1 As shown, the specific implementation includes the following design steps A to C.

[0037] Step A. Create a zero drain-source voltage V for the target SiC MOSFET device DS Lower long channel threshold voltage V TH0 About the gate-source voltage V GS , Temperature T a , the first degradation characterization model structure of the degradation time t; construct the mobility μ0 with respect to the gate-source voltage V under zero bias electric field GS , Temperature T a , the second degradation characterization model structure of the degradation time t; construct the threshold voltage first-order body effect coefficient k1 with respect to the gate-source voltage V GS , the third degradation characterization model structure with a degradation time t, and then enter step B.

[0038] In practical applications, the above step A is specifically based on the Arrhenius model, degradation time model, and inverse power law model that constitute the basic model of SiC MOSFET to construct a zero drain-source voltage V for the target SiC MOSFET device. DS Lower long channel threshold voltage V TH0 The first degradation characterization model structure of , the second degradation characterization model structure of the mobility μ0 under zero bias electric field, and the third degradation characterization model structure of the threshold voltage first-order body effect coefficient k1 are as follows respectively.

[0039] Specific press Figure 2 As shown in the figure, for the target SiC MOSFET device, according to the Arrhenius model that constitutes the basic model of SiC MOSFET Degradation time model ΔV TH0 =W1t n , Inverse power law model W1=P1V GS n , constructing a zero drain-source voltage V DS Lower long channel threshold voltage V TH0 About the gate-source voltage V GS , Temperature T a The structure of the first degradation representation model with degradation duration t is as follows:

[0040]

[0041] Where A and E represent the constants to be fitted, n' represents the temperature T in the first degradation characterization model. a The coefficient to be fitted is n, which represents the coefficient of the first degradation characterization model related to the gate-source voltage V GS and temperature T a The relevant coefficients to be fitted, E a represents the activation energy required for SiC MOSFET degradation, k represents the Boltzmann constant, W1 represents the electrical parameter under the first degradation characterization model structure, Y1 represents the constant under the first degradation characterization model structure, ΔV TH0 Indicates V TH0 The change in P1 represents the constant under the first degradation characterization model structure.

[0042] according to Figure 3 As shown in the figure, for the target SiC MOSFET device, according to the Arrhenius model that constitutes the basic model of SiC MOSFET Degradation time model Δμ0=w2t m , Inverse power law model W2=P2V GS m′ , construct the mobility μ0 with respect to the gate-source voltage V under zero bias electric field GS , Temperature T a The structure of the second degradation representation model with degradation duration t is as follows:

[0043]

[0044] Where B and D represent the constants to be fitted, respectively, and m′ represents the temperature T in the second degradation characterization model. a The coefficient to be fitted is related to the gate-source voltage V GS and temperature T a The relevant coefficients to be fitted, E a represents the activation energy required for SiC MOSFET degradation, k represents the Boltzmann constant, W2 represents the electrical parameter under the second degradation characterization model, Y2 represents the constant under the second degradation characterization model, Δμ0 represents the change of μ0, and P2 represents the constant under the second degradation characterization model.

[0045] according to Figure 4 As shown, for the target SiC MOSFET device, according to the degradation time model Δk1=W3t constituting the basic model of SiC MOSFET h , Inverse power law model W3=P3V GS h′ , construct the threshold voltage first-order body effect coefficient k1 about the gate-source voltage V GS The structure of the third degradation representation model with degradation duration t is as follows:

[0046] k1=C+(F+GV GS )t h

[0047] Where C, F, and G represent the constants to be fitted, and h represents the gate-source voltage V in the third degradation characterization model. GS The coefficients to be fitted are as follows: h' represents the coefficients of the second degradation characterization model related to temperature T a The relevant coefficients to be fitted, W3 represents the electrical parameters under the third degradation characterization model structure, Δk1 represents the change of k1, and P3 represents the constant under the third degradation characterization model structure.

[0048] Step B. Perform a high-temperature gate bias experiment on the target SiC MOSFET device, perform data fitting on the first degradation characterization model structure, the second degradation characterization model structure, and the third degradation characterization model structure, respectively, obtain the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model, and then enter step C.

[0049] In practical application, the above step B is specifically designed to perform the following steps B1 to B2.

[0050] Step B1. Based on a preset temperature T a1 ,…,T ai ,…,T aI Respectively with the preset J gate-source voltages V GS1 ,…,V GSj ,…,V GSJ One-to-one combination, respectively, the temperature T in each combination ai and the gate-source voltage V GSj According to the degradation time t, a high temperature gate bias test is performed on the target SiC MOSFET device, and the target SiC MOSFET device is tested to obtain the output characteristics and transfer characteristics corresponding to the target SiC MOSFET device, including the drain-source current I DS With the drain-source voltage V DS The data changes with the change, and the drain-source current I DS With the gate-source voltage V GS Data that changes, such as Figure 5 As shown, then proceed to step B2;

[0051] Step B2. Based on the output characteristics and transfer characteristics corresponding to the target SiC MOSFET device, data fitting is performed for the first degradation characterization model structure, the second degradation characterization model structure, and the third degradation characterization model structure, respectively, to obtain the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model, and then proceed to step C.

[0052] Step C. embedding the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model into the conventional SiC MOSFET device electrical characteristic SPICE model to obtain a SiC MOSFET model corresponding to the target SiC MOSFET device, which is used to predict the electrical performance degradation of the target SiC MOSFET device.

[0053] The above design is used to predict the electrical performance degradation of SiC MOSFET and is applied in practice, such as Figure 5 As shown, the gate-source voltage V GS =25V, temperature T a =175°C, degradation time t=90H, comparison results of the measured values ​​of the output characteristics and transfer characteristics of the target SiC MOSFET device with the degradation fitting values, wherein the points are the measured values, and the solid lines are the degradation fitting values. The schematic diagram proves that the SiC MOSFET model obtained by the electrical performance degradation prediction method designed by the present invention is highly feasible, and the electrical performance degradation prediction is accurate.

[0054] The above technical solution is designed to predict the electrical performance degradation of SiC MOSFET and analyze the gate-source voltage V GS , Temperature T a , degradation time t, and the three influencing factors of the degradation time t. According to the Arrhenius model, degradation time model, and inverse power law model that constitute the basic model of SiC MOSFET, the zero drain-source voltage V DS Lower long channel threshold voltage V TH0 The first degradation characterization model structure of the SiC MOSFET device, the second degradation characterization model structure of the mobility μ0 under zero bias electric field, and the third degradation characterization model structure of the threshold voltage first-order body effect coefficient k1 are constructed, and then a high-temperature gate bias experiment on the target SiC MOSFET device is performed, and model training is performed to obtain the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model respectively; finally, the three constructed degradation characterization models are embedded in the traditional SiC MOSFET device electrical characteristic SPICE model to obtain a SiC MOSFET model for predicting electrical performance degradation, which can accurately predict different gate-source voltages V GS and temperature T a The electrical performance degradation of the target SiC MOSFET device with the degradation time t can effectively evaluate the reliability and life of the target SiC MOSFET device, which has strong practical significance; and the three degradation characterization models constructed are simple in form and have no iterative functions, which are convenient and fast in practical application.

[0055] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A method for predicting electrical performance degradation of SiC MOSFET, for the application of a target SiC MOSFET device connected to a circuit, predicting electrical performance degradation of the target SiC MOSFET device, characterized in that: The steps include: Step A. Create a zero drain-source voltage V for the target SiC MOSFET device DS Lower long channel threshold voltage V TH0 About the gate-source voltage V GS , Temperature T a , the first degradation representation model structure of the degradation duration t; Construct the mobility μ0 with respect to the gate-source voltage V under zero bias electric field GS , Temperature T a , the second degradation characterization model structure of the degradation time t; construct the threshold voltage first-order body effect coefficient k1 with respect to the gate-source voltage V GS , a third degradation representation model structure with a degradation time t, and then proceeding to step B; Step B. Perform a high temperature gate bias experiment on the target SiC MOSFET device, perform data fitting on the first degradation characterization model structure, the second degradation characterization model structure, and the third degradation characterization model structure, respectively, obtain the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model, and then proceed to step C; Step C. embedding the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model into the conventional SiC MOSFET device electrical characteristic SPICE model to obtain a SiC MOSFET model corresponding to the target SiC MOSFET device, so as to predict the electrical performance degradation of the target SiC MOSFET device; Wherein, step A comprises the following: According to the Arrhenius model that constitutes the basic model of SiC MOSFET Degradation time model ΔV TH0 =W1t n , Inverse power law model W1=P1V GS n' , for the target SiC MOSFET device, build a zero drain-source voltage V DS Lower long channel threshold voltage V TH0 About the gate-source voltage V GS , Temperature T a The structure of the first degradation representation model with degradation duration t is as follows: Where A and E represent the constants to be fitted, n' represents the temperature T in the first degradation characterization model. a The coefficient to be fitted is n, which represents the coefficient of the first degradation characterization model related to the gate-source voltage V GS and temperature T a The relevant coefficients to be fitted, E a represents the activation energy required for SiCMOSFET degradation, k represents the Boltzmann constant, W1 represents the electrical parameters under the first degradation characterization model structure, Y1 represents the constant under the first degradation characterization model structure, ΔV TH0 Indicates V TH0 The change of , P1 represents the constant under the first degradation characterization model structure; According to the Arrhenius model that constitutes the basic model of SiC MOSFET Degradation time model Δμ0=W2t m , Inverse power law model W2=P2V GS m' , for the target SiC MOSFET device, the mobility μ0 under zero bias electric field is constructed with respect to the gate-source voltage V GS , Temperature T a The structure of the second degradation representation model with degradation duration t is as follows: Where B and D represent the constants to be fitted, and m' represents the temperature T in the second degradation characterization model. a The coefficient to be fitted is related to the gate-source voltage V GS and temperature T a The relevant coefficients to be fitted, E a represents the activation energy required for SiCMOSFET degradation, k represents the Boltzmann constant, W2 represents the electrical parameter under the second degradation characterization model, Y2 represents the constant under the second degradation characterization model, Δμ0 represents the change in μ0, and P2 represents the constant under the second degradation characterization model; According to the degradation time model Δk1=W3t that constitutes the basic model of SiC MOSFET h , Inverse power law model W3=P3V GS h' , for the target SiC MOSFET device, construct the threshold voltage first-order body effect coefficient k1 with respect to the gate-source voltage V GS The structure of the third degradation representation model with degradation duration t is as follows: k1=C+(F+GV GS )t h Where C, F, and G represent the constants to be fitted, and h represents the gate-source voltage V in the third degradation characterization model. GS The coefficients to be fitted are as follows: h' represents the coefficients of the second degradation characterization model related to temperature T a The relevant coefficients to be fitted, W3 represents the electrical parameters under the third degradation characterization model structure, Δk1 represents the change of k1, and P3 represents the constant under the third degradation characterization model structure.

2. A method for predicting electrical performance degradation of SiC MOSFET according to claim 1, characterized in that: The step B includes the following steps B1 to B2; Step B1. Based on a preset temperature T a1 ,…,T ai ,…,T al Respectively with the preset J gate-source voltages V GS1 ,…,V GSj ,…,V GSJ One-to-one combination, respectively, the temperature T in each combination ai With the gate-source voltage V GSj , according to the degradation time t, a high temperature gate bias test is performed on the target SiC MOSFET device, and the target SiC MOSFET device is tested to obtain the output characteristics and transfer characteristics corresponding to the target SiC MOSFET device, and then enter step B2; Step B2. Based on the output characteristics and transfer characteristics corresponding to the target SiC MOSFET device, data fitting is performed for the first degradation characterization model structure, the second degradation characterization model structure, and the third degradation characterization model structure, respectively, to obtain the first degradation characterization model, the second degradation characterization model, and the third degradation characterization model, and then proceed to step C.

3. A method for predicting electrical performance degradation of SiC MOSFET according to claim 2, characterized in that: The output characteristics and transfer characteristics of the target SiC MOSFET device include the drain-source current I DS With the drain-source voltage V DS The data changes with the change, and the drain-source current I DS With the gate-source voltage V GS Data that changes.

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