Fan-out packaging structure and method for preparing the fan-out packaging structure

Abstract

The present invention provides a fan-out type packaging structure and a method for preparing the fan-out type packaging structure, and relates to the field of chip packaging technology. The fan-out type packaging structure includes a packaging chip, a plastic package, a pin conductive layer and a redistribution layer, and the two sides of the packaging chip have a functional surface and a non-functional surface respectively; the plastic package is coated outside the packaging chip; the pin conductive layer is arranged on a side surface of the plastic package close to the functional surface, and a first wiring groove is formed in the middle of the pin conductive layer to expose the surface of the plastic package, so that the edge area of ​​the pin conductive layer forms a first pin bump; the redistribution layer is arranged in the first wiring groove; and a pin groove is formed on the edge of the first pin bump away from the redistribution layer. Compared with the prior art, the present invention utilizes the first pin bump to connect with the redistribution layer to realize electrical output, avoids the process of electroplating tin balls on the wiring layer in the conventional technology, avoids the technical problems caused by the tin balls, and can ensure welding reliability at the same time.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging technology, and in particular to a fan-out packaging structure, a preparation method of the fan-out packaging structure and a method thereof. Background Art

[0002] With the rapid development of the semiconductor industry, fan-out wafer level package (FOWLP) is widely used in the semiconductor industry. Fan-out packaging technology generally cuts a single chip from the wafer first, and then packages it on a carrier wafer. Its main advantages are high-density integration, small package product size, superior product performance, and fast signal transmission frequency. In fan-out technology, electroplating is usually used on the rewiring layer to form a tin ball as the output end. The electroplating process usually controls the current density to control the plating uniformity / thickness. The electroplating multi-layer metal layer structure (electroplated copper / nickel tin silver) forms a tin ball. Once the current density is unstable, it is easy to cause the electroplating multi-layer metal layer to delaminate, which in turn causes the tin ball to fall off. At the same time, the existing solder ball soldering bump process has solder bridging and void phenomena.

[0003] At the same time, in the fan-out packaging of the prior art, a high-density wiring layer is usually used to improve the transmission performance of the device. The wiring layer transmits signals through a strong current / strong voltage. As the wiring layer line width design becomes smaller and smaller, and the solder balls are prone to residual electroplating metal ions during the electroplating process, it leads to electron migration and parasitic effects, which in turn lead to electrical failure. In addition, the use of the electroplating solder ball process will make the overall thickness too large, which is not conducive to the miniaturization of the device. Summary of the invention

[0004] The objectives of the present invention include, for example, providing a fan-out packaging structure and a method for preparing a fan-out packaging structure, which can avoid the use of a tin ball electroplating process to achieve output, solve the technical problems caused by the tin ball electroplating process, and ensure the welding effect and electrical connection effect. At the same time, it can reduce the wiring thickness, which is conducive to the miniaturization of the device.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a fan-out packaging structure, comprising:

[0007] A packaged chip, wherein two sides of the packaged chip have a functional surface and a non-functional surface respectively;

[0008] A plastic package body, the plastic package body covering the packaged chip;

[0009] A pin conductive layer, the pin conductive layer is arranged on a side surface of the plastic package body close to the functional surface, and a first wiring groove is formed in the middle of the pin conductive layer to expose the surface of the plastic package body, so that a first pin bump is formed in the edge area of ​​the pin conductive layer;

[0010] A redistribution layer, which is disposed in the first wiring groove and is electrically connected to the pin conductive layer and the packaged chip;

[0011] Wherein, a pin groove is formed on an edge of one side of the first pin bump away from the redistribution layer.

[0012] In an optional implementation, the depth of the pin groove is the same as the thickness of the pin conductive layer, and the pin groove is exposed from the surface of the plastic package body.

[0013] In an optional implementation, the depth of the pin groove is less than the thickness of the pin conductive layer, and the pin conductive layer covers the edge of the plastic package body.

[0014] In an optional embodiment, the first wiring groove includes a first groove and a second groove that are interconnected, the first groove is arranged in the middle of the pin conductive layer, the second groove is arranged on the bottom wall of the first groove and exposes the surface of the plastic package body, and the size of the first groove is larger than that of the second groove, and the redistribution layer is filled and distributed in the first groove and the second groove.

[0015] In an optional embodiment, the redistribution layer includes a first dielectric layer, a conductive wiring layer and a second dielectric layer, the first dielectric layer is filled in the second groove and in contact with the surface of the plastic package body, the second dielectric layer is arranged on a side of the first dielectric layer away from the packaged chip and is filled in the first groove, the conductive wiring layer is arranged in the second dielectric layer and is electrically connected to the packaged chip.

[0016] In an optional embodiment, a surface of a side of the second dielectric layer away from the packaged chip is flush with a surface of a side of the pin conductive layer away from the packaged chip.

[0017] In an optional embodiment, the functional surface is provided with a chip boss, and the chip boss passes through the plastic package body and is in electrical contact with the redistribution layer.

[0018] In an optional embodiment, at least one second wiring groove is further provided on the pin conductive layer, the second wiring groove is arranged around the first wiring groove and spaced apart from the first wiring groove, and the redistribution layer is simultaneously arranged in the first wiring groove and the second wiring groove.

[0019] In an optional embodiment, the first pin bump is arranged on a side of the second wiring groove away from the first wiring groove, the pin conductive layer between the first wiring groove and the second wiring groove is formed with a second pin bump, and the height of the first pin bump relative to the plastic package body is greater than the height of the second pin bump relative to the plastic package body.

[0020] In an optional embodiment, the fan-out packaging structure also includes a stacked chip and a stacked device, the stacked chip is arranged on a side surface of the redistribution layer away from the plastic package body and is electrically connected to the redistribution layer, the stacked device is arranged on a side of the stacked chip away from the plastic package body, and a connecting solder ball is arranged on an edge of the side surface of the stacked device close to the plastic package body, and the connecting solder ball is electrically connected to the first pin bump.

[0021] In an optional embodiment, the fan-out packaging structure also includes a stacked wiring layer, which is arranged on a surface of the plastic package body away from the pin conductive layer, and a conductive column is arranged in the plastic package body, and two sections of the conductive column are respectively electrically connected to the pin conductive layer and the stacked wiring layer.

[0022] In a second aspect, the present invention provides a method for preparing a fan-out packaging structure, which is used to prepare the fan-out packaging structure as described in any one of the aforementioned embodiments, and the preparation method comprises:

[0023] providing a carrier;

[0024] forming a pin conductive layer on the surface of the carrier;

[0025] A packaging chip is attached to the surface of the pin conductive layer;

[0026] Forming a plastic package body on the surface of the pin conductive layer, wherein the plastic package body covers the outside of the packaged chip;

[0027] peeling off the carrier;

[0028] A first wiring groove is formed by etching in the middle of the pin conductive layer to expose the surface of the plastic package body, and the pin conductive layer around the first wiring groove forms a first pin bump;

[0029] forming a redistribution layer in the first wiring groove, wherein the redistribution layer is electrically connected to the pin conductive layer and the packaged chip at the same time;

[0030] Etching a pin groove on the pin conductive layer;

[0031] Cutting is performed along the center line of the pin groove so that the pin groove after cutting is located at an edge of a side of the first pin bump away from the redistribution layer.

[0032] In a third aspect, the present invention provides a method for preparing a fan-out packaging structure, which is used to prepare the fan-out packaging structure as described in any one of the aforementioned embodiments, and the preparation method comprises:

[0033] providing a carrier;

[0034] forming a pin conductive layer on the surface of the carrier;

[0035] A packaging chip is attached to the surface of the pin conductive layer;

[0036] Forming a plastic package body on the surface of the pin conductive layer, wherein the plastic package body covers the outside of the packaged chip;

[0037] peeling off the carrier;

[0038] A first wiring groove and a second wiring groove are formed by etching on the pin conductive layer, the second wiring groove is arranged around the first wiring groove and is spaced apart from the first wiring groove, and the pin conductive layer around the second wiring groove forms a first pin bump, and the pin conductive layer between the first wiring groove and the second wiring groove forms a second pin bump;

[0039] forming a redistribution layer in the first wiring groove and the second wiring groove, wherein the redistribution layer is electrically connected to the pin conductive layer and the packaged chip at the same time;

[0040] Etching a pin groove on the pin conductive layer;

[0041] Cutting is performed along the center line of the pin groove so that the pin groove after cutting is located at an edge of a side of the first pin bump away from the redistribution layer.

[0042] The beneficial effects of the embodiments of the present invention include, for example:

[0043] The fan-out packaging structure and preparation method thereof provided by the embodiment of the present invention wrap the plastic package body outside the package chip, and at the same time, a pin conductive layer is arranged on one side of the plastic package body close to the functional surface of the package chip, and a first wiring groove is formed in the middle of the pin conductive layer to expose the surface of the plastic package body. By setting the first wiring groove, the edge area of ​​the pin conductive layer can form a first pin bump, and a redistribution layer is arranged in the first wiring groove. The redistribution layer is arranged in the first wiring groove and is electrically connected to the pin conductive layer and the package chip at the same time. Among them, a pin groove is formed on the edge of the first pin bump away from the redistribution layer. Compared with the prior art, the embodiment of the present invention utilizes the first pin bump to connect with the redistribution layer to achieve electrical output, avoids the process of electroplating tin balls on the wiring layer in the conventional technology, avoids the problem of tin ball falling and bridging / voids, and also reduces electronic migration and parasitic effects, ensuring electrical connection performance. At the same time, the design of the pin groove can ensure welding reliability. Furthermore, since the redistribution layer is disposed in the first wiring groove, the first pin bump is used to realize partial wiring and transmission functions, and the thickness of the redistribution layer can be reduced, thereby facilitating the miniaturization of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 A schematic diagram of a fan-out packaging structure provided by a first embodiment of the present invention;

[0046] Figure 2 A schematic diagram of another fan-out packaging structure provided by the first embodiment of the present invention;

[0047] Figures 3 to 9 A process flow chart of a method for preparing a fan-out packaging structure provided by the first embodiment of the present invention;

[0048] Fig.10 A schematic diagram of a fan-out packaging structure provided by a second embodiment of the present invention;

[0049] Fig.11 A schematic diagram of a fan-out packaging structure provided by a third embodiment of the present invention;

[0050] Figure 12 to Figure 14 A process flow chart of a method for preparing a fan-out packaging structure provided in a third embodiment of the present invention;

[0051] Fig.15A schematic diagram of a fan-out packaging structure provided in accordance with a fourth embodiment of the present invention.

[0052] Icons: 100-fan-out packaging structure; 110-packaged chip; 111-chip boss; 130-plastic package; 150-pin conductive layer; 151-first wiring groove; 1511-first groove; 1513-second groove; 153-first pin bump; 155-pin groove; 157-second wiring groove; 159-second pin bump; 170-rewiring layer; 171-first dielectric layer; 173-conductive wiring layer; 175-second dielectric layer; 200-carrier; 300-stacked chips; 400-stacked devices; 410-connecting solder balls; 500-stacked wiring layer; 510-conductive pillars. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0056] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0057] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0058] As disclosed in the background technology, the fan-out packaging technology in the prior art usually forms solder balls as output terminals by electroplating on the wiring layer, and there are many problems with electroplating to form solder balls. For example, the current density is usually controlled in the electroplating process to control the uniformity / thickness of the electroplating. The multi-layer metal layer structure (electroplated copper / nickel tin silver) is electroplated to form solder balls. Once the current density is unstable, it is easy to cause the multi-layer metal layer to be delaminated, which in turn causes the solder ball to fall off during welding. At the same time, the existing solder ball welding bump process has solder bridging and void phenomena.

[0059] Furthermore, in the fan-out packaging of the prior art, a high-density wiring layer is usually used to improve the transmission performance of the device. The wiring layer transmits signals through a strong current / strong voltage. As the line width of the wiring layer is designed to be smaller and smaller, and the solder balls are prone to residual electroplating metal ions during the electroplating process, electron migration and parasitic effects are generated, resulting in electrical failure. In addition, the use of the electroplating solder ball process will make the overall thickness too large, which is not conducive to the miniaturization of the device.

[0060] In order to solve the above problems, an embodiment of the present invention provides a novel fan-out packaging structure and a preparation method thereof. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0061] First embodiment

[0062] See also Figure 1 The embodiment of the present invention provides a fan-out packaging structure 100, which can avoid the use of electroplating tin ball process to achieve output, solve the technical problems caused by the electroplating tin ball process, ensure the welding effect and electrical connection effect, and at the same time can reduce the wiring thickness, which is conducive to the miniaturization of the device.

[0063] The fan-out packaging structure 100 provided in this embodiment includes a packaging chip 110, a plastic package body 130, a pin conductive layer 150 and a redistribution layer 170, wherein the two sides of the packaging chip 110 have a functional surface and a non-functional surface respectively; the plastic package body 130 is coated on the outside of the packaging chip 110; the pin conductive layer 150 is arranged on a side surface of the plastic package body 130 close to the functional surface, and a first wiring groove 151 is formed in the middle of the pin conductive layer 150 to expose the surface of the plastic package body 130, so that a first pin bump 153 is formed in the edge area of ​​the pin conductive layer 150; the redistribution layer 170 is arranged in the first wiring groove 151, and is electrically connected to the pin conductive layer 150 and the packaging chip 110 at the same time; wherein a pin groove 155 is formed on the edge of the first pin bump 153 away from the redistribution layer 170.

[0064] In this embodiment, the pin conductive layer 150 can be a sputtered metal layer, and the first wiring groove 151 is formed by etching, and the first pin bump 153 is used to connect with the redistribution layer 170 to achieve electrical output, avoiding the process of electroplating tin balls on the wiring layer in conventional technology, avoiding the problem of tin ball falling and bridging / voids, and reducing electron migration and parasitic effects, ensuring electrical connection performance, while the design of the pin groove 155 can ensure welding reliability. In addition, since the redistribution layer 170 is arranged in the first wiring groove 151, the first pin bump 153 is used to achieve partial wiring and transmission functions, and the thickness of the redistribution layer 170 can be reduced, which is conducive to the miniaturization of the device.

[0065] In this embodiment, the depth of the pin groove 155 is the same as the thickness of the pin conductive layer 150, and the pin groove 155 exposes the surface of the plastic package 130. Specifically, the pin groove 155 can be formed by etching the pin conductive layer 150, and the pin groove 155 exposes the surface of the plastic package 130, so that the edge of the plastic package 130 and the edge of the pin conductive layer 150 are misaligned to form a step. When the board is mounted, since the first pin bump 153 will be welded with the external circuit board or device, the setting of the pin groove 155 can greatly increase the contact area of ​​the solder, thereby ensuring the reliability and stability of the external welding. In addition, since the plastic package 130 is relatively protruding from the pin conductive layer 150 in the horizontal direction, it can play a role in side wall protection and can avoid the generation of cutting burrs.

[0066] See also Figure 2 In other preferred embodiments of the present invention, the depth of the pin groove 155 is less than the thickness of the pin conductive layer 150, and the pin conductive layer 150 covers the edge of the plastic package body 130. Specifically, the depth of the pin groove 155 can be determined by controlling the etching depth, and the etching depth is less than the thickness of the pin conductive layer 150. The pin conductive layer 150 completely covers one side surface of the body, which can play a better protective and insulating role. In addition, when the board is mounted, the contact area between the solder and the pin conductive layer 150 can be further increased, thereby ensuring the reliability and stability of external welding.

[0067] See also Figure 1 and Figure 2In this embodiment, the first wiring groove 151 includes a first groove 1511 and a second groove 1513 that are interconnected. The first groove 1511 is arranged in the middle of the pin conductive layer 150, and the second groove 1513 is arranged on the bottom wall of the first groove 1511, and exposes the surface of the plastic package 130. The size of the first groove 1511 is larger than the size of the second groove 1513, and the redistribution layer 170 is filled and distributed in the first groove 1511 and the second groove 1513. Specifically, the first groove 1511 and the second groove 1513 are formed by etching twice. In the first etching, a first groove 1511 with a larger size can be formed, and the formation area of ​​the first groove 1511 can correspond to the mounting area of ​​the package chip 110. After the first groove 1511 is formed, the bottom wall of the first groove 1511 can be etched twice, and the surface of the plastic package 130 is exposed to form the second groove 1513. The second groove 1513 also corresponds to the package chip 110. Preferably, the second groove 1513 can be located in the middle of the first groove 1511. When preparing the redistribution layer 170 , the redistribution layer 170 can be filled in the first groove 1511 and the second groove 1513 of different sizes, thereby ensuring the wiring effect and improving the bonding force between the wiring layer and the pin conductive layer 150 to avoid delamination.

[0068] Further, the redistribution layer 170 includes a first dielectric layer 171, a conductive wiring layer 173, and a second dielectric layer 175. The first dielectric layer 171 is filled and arranged in the second groove 1513 and contacts the surface of the plastic package body 130. The second dielectric layer 175 is arranged on the side of the first dielectric layer 171 away from the packaged chip 110 and filled and arranged in the first groove 1511. The conductive wiring layer 173 is arranged in the second dielectric layer 175 and is electrically connected to the packaged chip 110. Specifically, the first dielectric layer 171 and the second dielectric layer 175 are both dielectric materials, such as silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. The conductive wiring layer 173 is a conductive metal material, such as a copper layer. The first dielectric layer 171 is filled and arranged in the second groove 1513, and the second dielectric layer 175 is filled in the first groove 1511. The conductive wiring layer 173 can be arranged in the second dielectric layer 175, and pass through the first dielectric layer 171 by local slot electroplating to electrically contact the packaged chip 110 to complete the wiring.

[0069] In this embodiment, the surface of the second dielectric layer 175 on one side away from the packaged chip 110 is flush with the surface of the pin conductive layer 150 on one side away from the packaged chip 110. The overall thickness of the redistribution layer 170 is the same as the overall thickness of the first wiring groove 151, so that the first dielectric layer 171 is in contact with the surface of the plastic package 130, and the second dielectric layer 175 is flush with the pin conductive layer 150, and the first dielectric layer 171 and the second dielectric layer 175 can play a buffering role, thereby avoiding the first pin bump 153 and the plastic package 130 from welding warping during welding.

[0070] In this embodiment, the functional surface is provided with a chip protrusion 111, which passes through the plastic package 130 and is in electrical contact with the redistribution layer 170. Specifically, the functional surface is provided with a soldering pad, on which a chip protrusion 111 is provided. The chip protrusion 111 may be a copper protrusion and is in electrical contact with the conductive wiring layer 173. In some other preferred embodiments, the functional surface may not be provided with a chip protrusion 111, but the surface of the plastic package 130 may be directly grooved to expose the soldering pad of the packaged chip 110, and a copper layer may be formed by electroplating to achieve electrical contact between the conductive wiring layer 173 and the packaged chip 110.

[0071] The embodiment of the present invention further provides a method for preparing a fan-out package structure 100, which is used to prepare the aforementioned fan-out package structure 100. The preparation method comprises the following steps:

[0072] S1: Provide a carrier 200.

[0073] Specifically, a carrier 200 is taken, which may be made of glass, silicon oxide, metal or other materials, and then a film layer is coated on the surface of the carrier 200. The film layer may be a UV adhesive layer, which may serve as a separation layer for the chip packaging structure formed subsequently.

[0074] S2 : forming a pin conductive layer 150 on the surface of the carrier 200 .

[0075] See also Figure 3 Specifically, a metal layer can be formed on the surface of the film layer by physical vapor deposition, chemical vapor deposition or sputtering process. Preferably, a copper layer can be formed on the surface of the film layer by sputtering process, thus constituting the pin conductive layer 150 .

[0076] S3: placing the package chip 110 on the surface of the pin conductive layer 150 .

[0077] See also Figure 4Specifically, the packaged chip 110 can be mounted on the surface of the pin conductive layer 150 through a surface mounting process. It should be noted here that the functional surface of the packaged chip 110 is mounted downward, and a conductive protrusion is provided on the functional surface. The conductive protrusion and the pin conductive layer 150 are welded to realize the Cu-Cu welding process. Compared with the traditional adhesive fixing method, the packaged chip 110 is welded and fixed on the pin conductive layer 150 in this embodiment, thereby achieving a better fixing effect and preventing the chip mounting from being offset due to mold flow impact in the subsequent plastic packaging process.

[0078] S4: forming a plastic package 130 on the surface of the pin conductive layer 150 , and the plastic package 130 covers the outside of the packaged chip 110 .

[0079] See also Figure 5 Specifically, a plastic encapsulation process is adopted to form a plastic encapsulation body 130 by injection molding using a plastic encapsulation mold. The plastic encapsulation body 130 is coated on the outside of the packaged chip 110 to play a good protective role.

[0080] S5: Peeling off the carrier 200 .

[0081] See also Figure 6 Specifically, the adhesive film layer and the carrier 200 may be separated by UV light irradiation, so that the surface of the pin conductive layer 150 is exposed after the carrier 200 is peeled off.

[0082] S6: etching a middle portion of the pin conductive layer 150 to form a first wiring groove 151 that exposes the surface of the plastic package body 130 .

[0083] See also Figure 7 Specifically, a first wiring groove 151 can be formed by partially etching the pin conductive layer 150 , the first wiring groove 151 passes through the pin conductive layer 150 and exposes the surface of the plastic package 130 , and the pin conductive layer 150 around the first wiring groove 151 forms a first pin bump 153 .

[0084] It should be noted that the first wiring groove 151 here is composed of a first groove 1511 and a second groove 1513 , so the first groove 1511 and the second groove 1513 can be formed respectively by two etchings.

[0085] S7 : forming a redistribution layer 170 in the first wiring groove 151 .

[0086] See also Figure 8Specifically, the redistribution layer 170 is electrically connected to the pin conductive layer 150 and the packaged chip 110 at the same time. During the actual wiring, the first dielectric layer 171 can be first formed in the second groove 1513 by spin spraying, physical vapor deposition or chemical vapor deposition, and the conductive wiring layer 173 can be formed by patterning and then electroplating, and then the second dielectric layer 175 can be formed by spin spraying again to fill the first groove 1511, thereby completing the wiring. The first dielectric layer 171 and the second dielectric layer 175 are both made of dielectric materials, such as silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. At the same time, the conductive wiring layer 173 can be an electroplated copper micro wiring layer.

[0087] S8 : etching to form a pin groove 155 on the pin conductive layer 150 .

[0088] See also Fig. 9 Specifically, the pin groove 155 is formed by etching the pin conductive layer 150 at the periphery of the first wiring groove 151 , and preferably, the pin groove 155 can be formed by etching along the edge area of ​​the first pin bump 153 .

[0089] S9: Cut along the center line of the pin groove 155.

[0090] Please continue to see Figure 1 Specifically, through the cutting process, the pin groove 155 after cutting is located at the edge of one side of the first pin bump 153 away from the redistribution layer 170. The cutting process can be mechanical cutting or laser cutting, and the product is cut into single pieces to complete the process.

[0091] In summary, the embodiment of the present invention provides a fan-out type package structure 100 and a preparation method thereof, wherein a plastic package 130 is coated on the outside of a package chip 110, and a pin conductive layer 150 is provided on one side of the plastic package 130 close to the functional surface of the package chip 110, and a first wiring groove 151 is formed in the middle of the pin conductive layer 150 to expose the surface of the plastic package 130. By providing the first wiring groove 151, a first pin bump 153 can be formed in the edge area of ​​the pin conductive layer 150, and a redistribution layer 170 is provided in the first wiring groove 151. The redistribution layer 170 is provided in the first wiring groove 151 and is electrically connected to the pin conductive layer 150 and the package chip 110 at the same time. Among them, a pin groove 155 is formed on the edge of one side of the first pin bump 153 away from the redistribution layer 170. Compared with the prior art, the embodiment of the present invention utilizes the first pin bump 153 to connect with the redistribution layer 170 to achieve electrical output, avoiding the process of electroplating tin balls on the wiring layer in the conventional technology, avoiding the problem of tin ball falling and bridging / voiding, and also reducing electron migration and parasitic effects, ensuring electrical connection performance, while the design of the pin groove 155 can ensure welding reliability. In addition, since the redistribution layer 170 is arranged in the first wiring groove 151, the first pin bump 153 is used to achieve partial wiring and transmission functions, and the thickness of the redistribution layer 170 can be reduced, which is conducive to the miniaturization of the device.

[0092] Second embodiment

[0093] See also Fig.10 The embodiment of the present invention provides a fan-out packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0094] In this embodiment, at least one second wiring groove 157 is further provided on the pin conductive layer 150, and the second wiring groove 157 is provided around the first wiring groove 151 and is spaced apart from the first wiring groove 151, and the redistribution layer 170 is provided in both the first wiring groove 151 and the second wiring groove 157. Specifically, the second wiring groove 157 can be provided between the first wiring groove 151 and the edge of the pin conductive layer 150, and at the same time, the redistribution layer 170 can be distributed in both the first wiring groove 151 and the second wiring groove 157, thereby greatly improving the wiring range.

[0095] It should be noted that the redistribution layer 170 between the first wiring groove 151 and the second wiring groove 157 can be electrically connected to each other through the pin conductive layer 150, so that the redistribution layer 170 is electrically connected as a whole. Similarly, the second wiring groove 157 also adopts a stepped groove structure, and the conductive wiring layer 173 in the second wiring groove 157 is directly in electrical contact with the pin conductive layer 150.

[0096] In this embodiment, the first pin bump 153 is arranged on the side of the second wiring groove 157 away from the first wiring groove 151, and the pin conductive layer 150 between the first wiring groove 151 and the second wiring groove 157 is formed with a second pin bump 159, that is, the first pin bump 153 and the second pin bump 159 form an inner and outer two-circle structure, the first pin bump 153 is located in the outer circle, and the second pin bump 159 is located in the inner circle. The heights of the first pin bump 153 and the second pin bump 159 are flush, and both are exposed in the redistribution layer 170. Thereby, the exposed area of ​​the pin bump is increased, and then the contact area with the solder is increased, and the electrical connection performance is guaranteed.

[0097] It is worth noting that in this embodiment, the redistribution layer 170 may not fill the entire second wiring groove 157, that is, there is a certain gap between the inner wall of the second wiring groove 157 and the redistribution layer 170 therein, thereby forming a groove structure, further increasing the contact area between the solder and the first pin bump 153 and the second pin bump 159 when the board is mounted, ensuring the reliability and stability of welding. At the same time, this gap design can also make the redistribution layer 170 play a buffering role, further reducing the warping phenomenon.

[0098] Third embodiment

[0099] See also Fig.11 The embodiment of the present invention provides a fan-out packaging structure 100, whose basic structure, principle and technical effects are the same as those of the second embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the second embodiment.

[0100] In this embodiment, the first pin bump 153 is arranged on the side of the second wiring groove 157 away from the first wiring groove 151, and the pin conductive layer 150 between the first wiring groove 151 and the second wiring groove 157 is formed with a second pin bump 159, and the height of the first pin bump 153 relative to the plastic package 130 is greater than the height of the second pin bump 159 relative to the plastic package 130, wherein the second pin bump 159 is embedded in the redistribution layer 170 and covered by a dielectric material. In this embodiment, there can be multiple packaged chips 110, and the redistribution layer 170 in the second wiring groove 157 can also be directly connected to the corresponding packaged chip 110.

[0101] It should be noted that the difference between this embodiment and the second embodiment is that when etching the pin conductive layer 150, a first pin bump 153 and a second pin bump 159 of different heights can be formed, wherein the second pin bump 159 can be used as a buried pin and as a bridge structure, thereby improving the welding reliability of the wiring layer and reducing the internal wiring distance of the wiring layer. The second pin bump 159 adopts a raised structure, which can also improve the bonding force of the intermediate dielectric material and play the role of a buffer bump. In addition, the buried pin can increase the thickness of the electrical layer, thereby increasing the current density, and then improving the electrical function and heat dissipation performance.

[0102] It is worth noting that the first pin bump 153, as a high pin, can be used as a pin output terminal, and the height of the first pin bump 153 relative to the plastic package 130 is greater than the thickness of the redistribution layer 170, so that the first pin bump 153 is higher than the redistribution layer 170. On the one hand, it can play a supporting role to avoid the collapse of the solder ball solder when the upper board or other electrical components are connected. On the other hand, it can play a protective role to avoid the stratification of the dielectric layer and prevent the solder ball from overflowing during welding. The first pin bump 153 can be used as a pad for the stacked device 400, thereby playing a role in high-density integration. Moreover, since the size of the first pin bump 153 is large, it is conducive to stacking welding. And the use of the first pin bump 153 here can increase the conductivity and heat dissipation performance, and improve the transmission efficiency.

[0103] The embodiment of the present invention further provides a method for preparing a fan-out package structure 100, which is used to prepare the aforementioned fan-out package structure 100. The method comprises:

[0104] S1: Provide a carrier 200.

[0105] S2 : forming a pin conductive layer 150 on the surface of the carrier 200 .

[0106] S3: placing the package chip 110 on the surface of the pin conductive layer 150 .

[0107] S4: forming a plastic package 130 on the surface of the pin conductive layer 150 , and the plastic package 130 covers the outside of the packaged chip 110 .

[0108] S5: Peeling off the carrier 200 .

[0109] Specifically, the actual preparation process of step S1 to step S5 is the same as that of the first embodiment, and specific reference may be made to step S1 to step S5 in the first embodiment.

[0110] S6: etching the pin conductive layer 150 to form a first wiring groove 151 and a second wiring groove 157 that are exposed on the surface of the plastic package body 130 .

[0111] See also Fig.12 , wherein the second wiring groove 157 is arranged around the first wiring groove 151 and is spaced apart from the first wiring groove 151, and the pin conductive layer 150 around the second wiring groove 157 forms a first pin bump 153, and the pin conductive layer 150 between the first wiring groove 151 and the second wiring groove 157 forms a second pin bump 159.

[0112] It should be noted that, during actual etching, the first wiring groove 151 and the second wiring groove 157 can be formed by etching multiple times, and by controlling the etching depth, the height of the first pin bump 153 can be higher than the height of the second pin bump 159 .

[0113] S7 : forming a redistribution layer 170 in the first wiring groove 151 and the second wiring groove 157 .

[0114] See also Fig.13 Specifically, the redistribution layer 170 is electrically connected to the pin conductive layer 150 and the packaged chip 110 at the same time, and the second dielectric layer 175 of the redistribution layer 170 can cover the second pin bump 159, so that the second pin bump 159 forms an embedded pin.

[0115] S8 : etching to form a pin groove 155 on the pin conductive layer 150 .

[0116] See also Fig.14 Specifically, by etching, a pin groove 155 is formed at the edge of the first pin bump 153 , and the pin groove 155 penetrates to the surface of the plastic package body 130 .

[0117] S9: Cut along the center line of the pin groove 155.

[0118] Please continue to see Fig.11 Specifically, the cut pin groove 155 can be located at an edge of a side of the first pin bump 153 away from the redistribution layer 170 .

[0119] Fourth embodiment

[0120] See also Fig.15 The embodiment of the present invention provides a fan-out packaging structure 100, whose basic structure, principle and technical effects are the same as those of the third embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the third embodiment.

[0121] Furthermore, the fan-out packaging structure 100 also includes a stacked chip 300 and a stacked device 400. The stacked chip 300 is arranged on a side surface of the redistribution layer 170 away from the plastic package 130 and is electrically connected to the redistribution layer 170. The stacked device 400 is arranged on a side of the stacked chip 300 away from the plastic package 130, and a connecting solder ball 410 is arranged on an edge of a side surface of the stacked device 400 close to the plastic package 130. The connecting solder ball 410 is electrically connected to the first pin bump 153. Specifically, a solder pad is also arranged on a side of the redistribution layer 170 away from the packaged chip 110. The solder pad is welded and fixed to the stacked chip 300, and can be arranged at the bottom of the stacked chip 300 as an insulating layer using a dielectric material, and can lead out the solder pad of the packaged chip 110 through the redistribution layer 170 to achieve stacking.

[0122] It should be noted that, in this embodiment, there may be multiple packaged chips 110, for example, three, and there may also be multiple stacked chips 300, for example, two. The specific number can be referred to in the figure.

[0123] It is worth noting that the first pin bump 153, as a high pin, can be used as a pin output terminal, and the height of the first pin bump 153 relative to the plastic package 130 is greater than the thickness of the redistribution layer 170, so that the first pin bump 153 is higher than the redistribution layer 170. On the one hand, it can play a supporting role to avoid the collapse of the solder ball solder when the upper board or other electrical components are connected. On the other hand, it can play a protective role to avoid the stratification of the dielectric layer and prevent the solder ball from overflowing during welding. The first pin bump 153 can be used as a pad for the stacked device 400, thereby playing a role in high-density integration. Moreover, since the size of the first pin bump 153 is large, it is conducive to stacking welding. And the use of the first pin bump 153 here can increase the conductivity and improve the transmission efficiency.

[0124] Furthermore, the fan-out package structure 100 further includes a stacked wiring layer 500, which is disposed on a surface of the plastic package 130 away from the pin conductive layer 150, and a conductive column 510 is disposed in the plastic package 130, and two sections of the conductive column 510 are respectively electrically connected to the pin conductive layer 150 and the stacked wiring layer 500. Specifically, the conductive column 510 can be a copper column, and a solder ball is further disposed on a side of the stacked wiring layer 500 away from the stacked chip 300, which can realize external connection and play a high-density integration function.

[0125] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A fan-out packaging structure, characterized in that: include: A packaged chip, wherein two sides of the packaged chip have a functional surface and a non-functional surface respectively; A plastic package body, the plastic package body covering the packaged chip; A pin conductive layer, the pin conductive layer is arranged on a side surface of the plastic package body close to the functional surface, and a first wiring groove is formed in the middle of the pin conductive layer to expose the surface of the plastic package body, so that a first pin bump is formed in the edge area of ​​the pin conductive layer; A redistribution layer, which is disposed in the first wiring groove and is electrically connected to the pin conductive layer and the packaged chip; Wherein, a pin groove is formed on one side edge of the first pin bump away from the redistribution layer; The first wiring groove comprises a first groove and a second groove which are connected to each other, the first groove is arranged in the middle of the pin conductive layer, the second groove is arranged on the bottom wall of the first groove and exposed to the surface of the plastic package body, and the size of the first groove is larger than that of the second groove, and the redistribution layer is filled and distributed in the first groove and the second groove; The redistribution layer includes a first dielectric layer, a conductive wiring layer and a second dielectric layer. The first dielectric layer is filled in the second groove and contacts the surface of the plastic package body. The second dielectric layer is arranged on a side of the first dielectric layer away from the packaged chip and filled in the first groove. The conductive wiring layer is arranged in the second dielectric layer and is electrically connected to the packaged chip.

2. The fan-out packaging structure according to claim 1, characterized in that: The depth of the pin groove is the same as the thickness of the pin conductive layer, and the pin groove is exposed from the surface of the plastic package body.

3. The fan-out packaging structure according to claim 1, characterized in that: The depth of the pin groove is less than the thickness of the pin conductive layer, and the pin conductive layer covers the edge of the plastic package body.

4. The fan-out packaging structure according to claim 1, characterized in that: A surface of the second dielectric layer on one side away from the packaged chip is flush with a surface of the pin conductive layer on one side away from the packaged chip.

5. The fan-out packaging structure according to claim 1, characterized in that: The functional surface is provided with a chip boss, the chip boss passes through the plastic package body and is in electrical contact with the redistribution layer.

6. The fan-out packaging structure according to claim 1, characterized in that: At least one second wiring groove is also provided on the pin conductive layer. The second wiring groove is arranged around the first wiring groove and spaced apart from the first wiring groove. The redistribution layer is simultaneously arranged in the first wiring groove and the second wiring groove.

7. The fan-out packaging structure according to claim 6, characterized in that: The first pin bump is arranged on a side of the second wiring groove away from the first wiring groove, the pin conductive layer between the first wiring groove and the second wiring groove is formed with a second pin bump, and the height of the first pin bump relative to the plastic package body is greater than the height of the second pin bump relative to the plastic package body.

8. The fan-out packaging structure according to claim 7, characterized in that: The height of the first pin bump relative to the plastic package body is greater than the thickness of the redistribution layer.

9. The fan-out packaging structure according to any one of claims 6 to 8, characterized in that: The fan-out packaging structure also includes a stacked chip and a stacked device. The stacked chip is arranged on a side surface of the redistribution layer away from the plastic package body and is electrically connected to the redistribution layer. The stacked device is arranged on a side of the stacked chip away from the plastic package body, and a connecting solder ball is arranged on an edge of a side surface of the stacked device close to the plastic package body, and the connecting solder ball is electrically connected to the first pin bump.

10. The fan-out packaging structure according to claim 9, characterized in that: The fan-out packaging structure also includes a stacked wiring layer, which is arranged on a side surface of the plastic package away from the pin conductive layer, and a conductive column is arranged in the plastic package, and two sections of the conductive column are electrically connected to the pin conductive layer and the stacked wiring layer respectively.

11. A method for preparing a fan-out packaging structure, used for preparing the fan-out packaging structure according to any one of claims 1 to 10, characterized in that: The preparation method comprises: providing a carrier; forming a pin conductive layer on the surface of the carrier; A packaging chip is attached to the surface of the pin conductive layer; Forming a plastic package body on the surface of the pin conductive layer, wherein the plastic package body covers the outside of the packaged chip; peeling off the carrier; A first wiring groove is formed by etching in the middle of the pin conductive layer to expose the surface of the plastic package body, and the pin conductive layer around the first wiring groove forms a first pin bump; forming a redistribution layer in the first wiring groove, wherein the redistribution layer is electrically connected to the pin conductive layer and the packaged chip at the same time; Etching a pin groove on the pin conductive layer; Cutting is performed along the center line of the pin groove so that the pin groove after cutting is located at an edge of a side of the first pin bump away from the redistribution layer.

12. A method for preparing a fan-out packaging structure, used for preparing the fan-out packaging structure according to any one of claims 1 to 10, characterized in that: The preparation method comprises: providing a carrier; forming a pin conductive layer on the surface of the carrier; A packaging chip is attached to the surface of the pin conductive layer; Forming a plastic package body on the surface of the pin conductive layer, wherein the plastic package body covers the outside of the packaged chip; peeling off the carrier; A first wiring groove and a second wiring groove are formed by etching on the pin conductive layer, the second wiring groove is arranged around the first wiring groove and is spaced apart from the first wiring groove, and the pin conductive layer around the second wiring groove forms a first pin bump, and the pin conductive layer between the first wiring groove and the second wiring groove forms a second pin bump; forming a redistribution layer in the first wiring groove and the second wiring groove, wherein the redistribution layer is electrically connected to the pin conductive layer and the packaged chip at the same time; Etching a pin groove on the pin conductive layer; Cutting is performed along the center line of the pin groove so that the pin groove after cutting is located at an edge of a side of the first pin bump away from the redistribution layer.

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