Germanium-silicon heterojunction bipolar transistor and method of manufacturing the same

Abstract

The application discloses a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and particularly relates to the fields of semiconductor device and integrated circuit process design and manufacturing. The germanium-silicon heterojunction bipolar transistor and the manufacturing method thereof provided by the application can achieve the purpose of exposing the outer base region part sidewall of the polysilicon so as to make necessary space for a germanium-silicon connecting base region which is synchronously grown with an inner base region of a germanium-silicon epitaxial layer in the subsequent process, and realize a recessed germanium-silicon connecting base region structure which can effectively improve the performance of the device. Moreover, the germanium-silicon heterojunction bipolar transistor provided by the application can be manufactured by using a process step which has relatively low process difficulty and complexity, and avoids the process step of using a bottom slit to "dig" the silicon nitride sidewall in the isotropic etching process which is difficult to control in the background art, so that the repeatability, uniformity, controllability and producibility of the related integrated circuit process production can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor device and integrated circuit process design and manufacturing, in particular to a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof. BACKGROUND

[0002] The structure of a germanium-silicon heterojunction bipolar transistor 001 based on selective germanium-silicon epitaxial inner base region self-alignment of isotropic etching silicon nitride inner sidewall is shown in FIG. 1. The key process steps of the heterojunction bipolar transistor 001 are shown in FIGS. 2 and 3 (the device structure schematic diagrams before and after the key process steps are shown in FIGS. 4 and 5, respectively), which are realized by isotropic etching silicon nitride inner sidewall 1, and using the gap 4 reserved at the bottom of the silicon nitride inner sidewall 1 during the growth of the collector region selective silicon epitaxial layer 2 to precisely control the thickness, to etch away part of the silicon nitride inner sidewall 1 and expose part of the outer base region polysilicon layer 3 sidewall. The process complexity and difficulty are quite high, and the process controllability, repeatability and uniformity are relatively poor. Figure 1 Figure 2a and Figure 2b Figure 2a and Figure 2b This part aims to provide background or context for the embodiments of the present application stated in the claims. The description herein is not admitted to be prior art because it is included in this part. SUMMARY

[0003] In order to solve at least one of the above problems in the prior art, the embodiments of the present application provide a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof.

[0004] According to a first aspect of the embodiments of the present application, the present application provides a germanium-silicon heterojunction bipolar transistor, comprising:

[0005] a substrate;

[0006] a heavily doped silicon collector region with a conductive type opposite to that of the substrate, formed on the upper side of the substrate;

[0007] a field region dielectric layer, formed on the upper side of the substrate;

[0008] a first silicon oxide layer, formed on the upper side of the heavily doped silicon collector region and the field region dielectric layer;

[0009] a silicon epitaxial collector region with the same conductive type as the heavily doped silicon collector region, formed on the upper side of the heavily doped silicon collector region;

[0010] a heavily doped polysilicon outer base region with a conductive type opposite to that of the heavily doped silicon collector region, formed on the first silicon oxide layer;

[0011] a second silicon oxide layer, formed on the upper side of the heavily doped polysilicon outer base region;

[0012] ​​a germanium-silicon base region of the same conductivity type as the polysilicon outer base region, including a germanium-silicon epitaxial inner base region formed on the top side of the silicon epitaxial collector region and a germanium-silicon connecting base region formed on the top side of the first silicon oxide layer and between the germanium-silicon epitaxial inner base region and the polysilicon outer base region;

[0013] a second silicon oxide layer formed between the polysilicon outer base region and a silicon nitride layer;

[0014] a silicon nitride layer formed between the second silicon oxide layer and a polysilicon emitter region;

[0015] a silicon nitride inner spacer formed on the top side of the germanium-silicon connecting base region;

[0016] an L-shaped silicon oxide inner spacer formed on the top side of the germanium-silicon epitaxial inner base region and on the inner and top sides of the silicon nitride inner spacer;

[0017] a heavily doped polysilicon emitter region of the same conductivity type as the heavily doped silicon collector region formed on the top side of the silicon nitride layer, the L-shaped silicon oxide inner spacer, and the germanium-silicon epitaxial inner base region;

[0018] a heavily doped single-crystal emitter region of the same conductivity type as the polysilicon emitter region formed in the germanium-silicon epitaxial inner base region between the L-shaped silicon oxide inner spacers; wherein,

[0019] the first silicon oxide layer has a recessed structure near the silicon epitaxial collector region and the polysilicon outer base region, and the germanium-silicon connecting base region is formed on the top side of the recessed structure of the first silicon oxide layer.

[0020] In some embodiments, further comprising:

[0021] a dielectric outer spacer formed on the outside of the first silicon oxide layer, the polysilicon outer base region, the second silicon oxide layer, the silicon nitride layer, and the polysilicon emitter region.

[0022] In some embodiments, further comprising:

[0023] a self-aligned silicide layer formed on the top side of the polysilicon emitter region and the polysilicon outer base region and self-alignedly isolated by the dielectric outer spacer.

[0024] According to a second aspect of the embodiments of the present application, the present application provides a manufacturing method of a germanium-silicon heterojunction bipolar transistor, comprising:

[0025] providing a silicon-based bipolar transistor basic structure, wherein the silicon-based bipolar transistor basic structure includes a substrate and a heavily doped silicon collector region of the opposite conductivity type to the substrate and a field region dielectric layer formed on the substrate;

[0026] Depositing a first silicon oxide layer, a heavily doped polysilicon outer base region of opposite conductivity type to the heavily doped silicon collector region, a second silicon oxide layer and a silicon nitride layer in sequence on the silicon-based bipolar transistor base structure;

[0027] Forming a collector region window along the thickness direction of the silicon nitride layer, the second silicon oxide layer and the polysilicon outer base region to partially expose the first silicon oxide layer;

[0028] Etching the first silicon oxide layer under the collector region window to partially expose the heavily doped silicon collector region;

[0029] Carrying out selective silicon epitaxial collector growth with the exposed heavily doped silicon collector region as a seed crystal, so that the upper surface of the silicon epitaxial collector region is flush with the upper surface of the first silicon oxide layer;

[0030] Forming a third silicon oxide layer on the upper surface of the silicon epitaxial collector region, so that the thickness of the third silicon oxide layer is equal to the thickness of a subsequent silicon-germanium epitaxial inner base region;

[0031] Forming a silicon nitride inner side wall on the inner edge of the collector region window on the upper side of the third silicon oxide layer;

[0032] Etching away the third silicon oxide layer by wet etching and etching away the first silicon oxide layer and the junction between the silicon epitaxial collector region and the polysilicon outer base region by over-etching to form a recess structure;

[0033] Carrying out silicon-germanium base growth with the exposed silicon epitaxial collector region and polysilicon outer base region as a seed crystal, so that the upper side of the silicon epitaxial collector region is a silicon-germanium epitaxial inner base region and the silicon-germanium connecting base region connecting the polysilicon outer base region and the silicon-germanium epitaxial inner base region is formed;

[0034] Forming an L-shaped silicon oxide inner side wall on the inner side of the silicon nitride inner side wall;

[0035] Depositing a polysilicon emitter region of the same conductivity type as the heavily doped silicon collector region;

[0036] Carrying out rapid thermal annealing to diffuse impurities in the polysilicon emitter region into the silicon-germanium epitaxial inner base region to form a heavily doped single-crystal emitter region of the same conductivity type as the polysilicon emitter region.

[0037] In some embodiments, etching the first silicon oxide layer under the collector region window to partially expose the heavily doped silicon collector region comprises:

[0038] First depositing a sacrificial silicon nitride layer and then anisotropically etching the sacrificial silicon nitride layer to form a sacrificial silicon nitride inner side wall on the edge of the collector region window;

[0039] Anisotropic dry etching a first silicon oxide layer using the silicon nitride layer and the sacrificial silicon nitride inner spacer as a mask, leaving a certain thickness of silicon oxide layer at the bottom of the first silicon oxide layer under the collector window;

[0040] Isotropic wet etching the first silicon oxide layer using the silicon nitride layer and the sacrificial silicon nitride inner spacer as a mask, completely etching the remaining silicon oxide layer at the bottom, exposing part of the heavily doped silicon collector region, and simultaneously etching the inner part of the first silicon oxide layer by a corresponding thickness.

[0041] In some embodiments, after performing silicon epitaxial collector growth using the exposed heavily doped silicon collector region as a seed, and making the upper surface of the silicon epitaxial collector region flush with the upper surface of the first silicon oxide layer, before forming a third silicon oxide layer on the upper surface of the silicon epitaxial collector region, the method further comprises:

[0042] Performing selective implant collector ion implantation on the silicon epitaxial collector region using the silicon nitride layer, the second silicon oxide layer, the polysilicon outer base region, and the sacrificial silicon nitride inner spacer as a mask, and implanting impurities of the same conductivity type as the heavily doped silicon collector region.

[0043] In some embodiments, forming a third silicon oxide layer on the upper surface of the silicon epitaxial collector region, and making the thickness of the third silicon oxide layer equal to the thickness of the subsequent germanium-silicon epitaxial inner base region, comprises:

[0044] Wet etching the sacrificial silicon nitride inner spacer;

[0045] Depositing a third silicon oxide layer with a thickness exceeding the total thickness of the polysilicon outer base region, the second silicon oxide layer, and the silicon nitride layer;

[0046] Planarizing and etching back the third silicon oxide layer using the silicon nitride layer as a stop layer;

[0047] Continuing anisotropic dry etching of the third silicon oxide layer using the silicon nitride layer as a mask, making the remaining thickness of the third silicon oxide layer equal to the thickness of the subsequent germanium-silicon epitaxial inner base region.

[0048] In some embodiments, forming an L-shaped silicon oxide inner spacer inside the silicon nitride inner spacer, comprises:

[0049] Depositing a fourth silicon oxide layer;

[0050] Depositing a polysilicon layer on the fourth silicon oxide layer;

[0051] Anisotropic dry etching the polysilicon layer to form a polysilicon inner spacer;

[0052] Wet etching the exposed fourth silicon oxide layer using the polysilicon inner spacer as a mask to form an L-shaped silicon oxide inner spacer.

[0053] In some embodiments, depositing a polysilicon emitter region of the same conductivity type as the heavily doped silicon collector region comprises:

[0054] depositing a polysilicon layer of the same conductivity type as the heavily doped silicon collector region for the emitter region;

[0055] etching the polysilicon layer for the emitter region, the silicon nitride layer, and the second silicon oxide layer using the emitter photoresist as a mask to form a polysilicon emitter region;

[0056] removing the emitter photoresist.

[0057] In some embodiments, after removing the emitter photoresist, prior to performing the rapid thermal anneal, the method further comprises:

[0058] etching the polysilicon outer base region and the first silicon oxide layer using the base photoresist as a mask;

[0059] removing the base photoresist;

[0060] depositing an outer spacer dielectric layer;

[0061] after performing the rapid thermal anneal such that impurities within the polysilicon emitter region diffuse into the germanium silicon epitaxial inner base region to form a single crystalline emitter region, the method further comprises:

[0062] anisotropically etching the outer spacer dielectric layer to form a dielectric outer spacer.

[0063] In some embodiments, after forming the dielectric outer spacer, the method further comprises:

[0064] forming a self-aligned silicide layer on the exposed polysilicon emitter region and polysilicon outer base region, the self-aligned silicide layer being self-aligned from the dielectric outer spacer.

[0065] The germanium silicon heterojunction bipolar transistor and the manufacturing method thereof provided in the present application can achieve the purpose of exposing part of the sidewall of the polysilicon outer base region to provide necessary space for the subsequent germanium silicon connecting base region which is synchronously grown with the germanium silicon epitaxial inner base region, and realize the recessed germanium silicon connecting base region structure which can effectively improve the performance of the device. Moreover, the germanium silicon heterojunction bipolar transistor provided in the present application can be manufactured by using a process step which has relatively low process difficulty and complexity, and avoids the process step of using the bottom slit to "dig" the isotropic etching silicon nitride sidewall which is difficult to control in the background art, thereby effectively improving the repeatability, uniformity, controllability and producibility of the related integrated circuit process production. BRIEF DESCRIPTION OF DRAWINGS

[0066] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor. In the drawings:

[0067] Figure 1 is a structural schematic diagram of a selective GeSi epitaxial inner base self-aligned GeSi heterojunction bipolar transistor based on isotropic etching of a silicon nitride inner sidewall.

[0068] Figure 2a and Figure 2b are structural schematic diagrams of a selective GeSi epitaxial inner base self-aligned GeSi heterojunction bipolar transistor before and after a key process step, respectively, based on isotropic etching of a silicon nitride inner sidewall.

[0069] Figures 3 to 27 are schematic diagrams of semiconductor structures obtained by each process step of a manufacturing method of a GeSi heterojunction bipolar transistor provided by the embodiments of the present application.

[0070] Figure 28 is a flowchart of a manufacturing method of a GeSi heterojunction bipolar transistor provided by the embodiments of the present application.

[0071] Figure 29 is a partial flowchart of a manufacturing method of a GeSi heterojunction bipolar transistor provided by the embodiments of the present application.

[0072] Figure 30 is a partial flowchart of a manufacturing method of a GeSi heterojunction bipolar transistor provided by the embodiments of the present application.

[0073] Figure 31 is a partial flowchart of a manufacturing method of a GeSi heterojunction bipolar transistor provided by the embodiments of the present application.

[0074] Figure 32 is a partial flowchart of a manufacturing method of a GeSi heterojunction bipolar transistor provided by the embodiments of the present application.

[0075] Figure 33 is a partial flowchart of a manufacturing method of a GeSi heterojunction bipolar transistor provided by the embodiments of the present application. DETAILED DESCRIPTION

[0076] With reference to the drawings and the following description, specific embodiments of the application will be described in detail for clarity of understanding. Apparently, the described embodiments are only a part of embodiments of the application, but not all the embodiments. Based on the embodiments in the application, all the other embodiments obtained by a person of ordinary skill in the art without creative work should fall within the protection scope of the application.

[0077] Specific embodiments of the application are disclosed in detail below with reference to the drawings and the following description, indicating the ways in which the principles of the application can be employed. It should be understood that the embodiments of the application are not limited in scope to the described embodiments, but extend their scope to include all changes, modifications and equivalents within the spirit and scope of the appended claims.

[0078] Features described and / or illustrated with respect to one embodiment can be used in the same or similar manner in one or more other embodiments, in combination with or in place of features in other embodiments.

[0079] It should be emphasized that the term "comprises / comprising" when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0080] To solve at least one of the above problems in the prior art, in a first aspect, the application provides a germanium-silicon heterojunction bipolar transistor, as shown in Figure 27 The application provides a germanium-silicon heterojunction bipolar transistor 002, which comprises:

[0081] a substrate 100;

[0082] a heavily doped silicon collector region 200 of a conductivity type opposite to the substrate 100, formed on the upper side of the substrate 100;

[0083] a field region dielectric layer 300, formed on the upper side of the substrate 100;

[0084] a first silicon oxide layer 400, formed on the upper side of the heavily doped silicon collector region 200 and the field region dielectric layer 300;

[0085] a silicon epitaxial collector region 500 of a conductivity type same as the heavily doped silicon collector region 200, formed on the upper side of the heavily doped silicon collector region 200;

[0086] a heavily doped polysilicon base region 600 of a conductivity type opposite to the heavily doped silicon collector region 200, formed on the first silicon oxide layer 400;

[0087] The germanium-silicon base region 700, which has the same conductivity type as the polysilicon outer base region 600, includes a germanium-silicon epitaxial inner base region 700a formed on the upper side of the silicon epitaxial collector region 500 and a germanium-silicon connecting base region 700b formed on the upper side of the first silicon oxide layer 400 and between the germanium-silicon epitaxial inner base region 700a and the polysilicon outer base region 600;

[0088] A second silicon oxide layer 800 is formed between the polysilicon outer base region 600 and a silicon nitride layer 900;

[0089] The silicon nitride layer 900 is formed between the second silicon oxide layer 800 and a polysilicon emitter region 130a;

[0090] A silicon nitride inner sidewall 110 is formed on the upper side of the germanium-silicon connecting base region 700b;

[0091] An L-shaped silicon oxide inner sidewall 120a is formed on the upper side of the germanium-silicon epitaxial inner base region 700a and the inner and upper sides of the silicon nitride inner sidewall 110;

[0092] A heavily doped polysilicon emitter region 130a, which has the same conductivity type as the heavily doped silicon collector region 200, is formed on the upper sides of the silicon nitride layer 900, the L-shaped silicon oxide inner sidewall 120a, and the germanium-silicon epitaxial inner base region 700a;

[0093] A heavily doped single-crystal emitter region 140, which has the same conductivity type as the polysilicon emitter region 130a, is formed in the germanium-silicon epitaxial inner base region 700a between the L-shaped silicon oxide inner sidewalls 120a; wherein,

[0094] The first silicon oxide layer 400 has a recessed structure 400a near the silicon epitaxial collector region 500 and the polysilicon outer base region 600, and the germanium-silicon connecting base region 700b is formed on the upper side of the recessed structure 400a of the first silicon oxide layer 400.

[0095] The germanium-silicon heterojunction bipolar transistor provided by the present application can achieve the purpose of exposing part of the sidewall of the polysilicon outer base region 600 to provide necessary space for the germanium-silicon connecting base region 700b which is synchronously grown with the germanium-silicon epitaxial inner base region 700a, but the germanium-silicon heterojunction bipolar transistor provided by the present application can be manufactured by a process step which has relatively low process difficulty and complexity, avoiding the process step of using a bottom slot to "dig" the isotropic etching silicon nitride sidewall which is difficult to control in the background art, thereby effectively improving the repeatability, uniformity, controllability, and producibility of the related integrated circuit process production.

[0096] In addition, the device structure proposed in the present application also has different features compared with the background art, mainly embodied in that the germanium-silicon connecting base region 700b presents a recessed structure, that is, the germanium-silicon connecting base region 700b is thinnest at one end connecting the polysilicon outer base region 600, gradually thickens from this end to the germanium-silicon epitaxial inner base region 700a, and reaches the thickest at the other end connecting the germanium-silicon epitaxial inner base region 700a. In this way, the overall thickness is larger, so that a smaller parasitic base series resistance can be obtained compared with the background art, which is conducive to improving the radio frequency noise performance of the device. Of course, the increase in the thickness of the germanium-silicon connecting base region 700b of the germanium-silicon heterojunction bipolar transistor in the present application is realized by etching the underlying first silicon oxide layer 400, so that the first silicon oxide layer 400 is inevitably thinned in part, resulting in an increase in the base-collector parasitic capacitance. However, considering that the thinned part of the first silicon oxide layer 400 accounts for a very small proportion of the overall first silicon oxide layer 400, and that the optimal recess degree of the germanium-silicon connecting base region 700b can be comprehensively explored to optimize the trade-off between the parasitic base series resistance and the base-collector parasitic capacitance, the radio frequency power gain performance of the device can be improved to the greatest extent, so that the performance index of the highest oscillation frequency of the device can be actually improved compared with the background art. In addition, the recessed structure of the germanium-silicon connecting base region 700b also results in the formation of a lateral pn junction between the germanium-silicon connecting base region 700b and the silicon epitaxial collector region 500, which has a modulation effect on the related electric potential and electric field of the longitudinal pn junction between the germanium-silicon epitaxial inner base region 700a and the silicon epitaxial collector region 500. Reasonable use of this modulation effect can reduce the electric field strength originally determined by the longitudinal pn junction between the germanium-silicon epitaxial inner base region 700a and the silicon epitaxial collector region 500, thereby effectively improving the breakdown voltage index of the device, and further improving the comprehensive optimization of the speed and frequency response performance index and the withstand voltage index of the device.

[0097] As shown in FIG. 1, in some embodiments, the germanium-silicon heterojunction bipolar transistor 002 further comprises: Figure 27

[0098] A dielectric outer wall 150a is formed outside the first silicon oxide layer 400, the polysilicon outer base region 600, the second silicon oxide layer 800, the silicon nitride layer 900, and the polysilicon emitter region 130a.

[0099] As shown in FIG. 1, in some embodiments, the germanium-silicon heterojunction bipolar transistor 002 further comprises: Figure 27

[0100] A self-aligned silicide layer 160 is formed on the top side of the polysilicon emitter region 130a and the polysilicon outer base region 600, and is self-alignedly isolated by the dielectric outer wall 150a.

[0101] ​​In order to solve at least one of the above problems existing in the prior art, in a second aspect, the present application provides a method for manufacturing a germanium-silicon heterojunction bipolar transistor, such as Figure 28 As shown, the present application provides a method for manufacturing a germanium-silicon heterojunction bipolar transistor, comprising:

[0102] S101. Providing a silicon-based bipolar transistor basic structure, wherein the silicon-based bipolar transistor basic structure includes a substrate, a heavily doped silicon collector region and a field region dielectric layer formed on the substrate and having a conductivity type opposite to that of the substrate;

[0103] In step S101, Figure 3 As shown, the germanium-silicon heterojunction bipolar transistor proposed in the present application starts from a silicon-based bipolar transistor basic structure including a substrate 100, a heavily doped silicon collector region 200 and a field dielectric layer 300, wherein the substrate 100 can be a lightly doped silicon substrate of a first conductivity type, the heavily doped silicon collector region 200 can be a heavily doped buried silicon collector region or a silicon collector well of a second conductivity type (the conductivity type is opposite to that of the substrate 100), and the field dielectric layer 300 can be a field silicon oxide layer.

[0104] S102, depositing a first silicon oxide layer, a heavily doped polysilicon outer base region having a conductivity type opposite to that of the heavily doped silicon collector region, a second silicon oxide layer, and a silicon nitride layer in sequence on the silicon-based bipolar transistor basic structure;

[0105] In step S102, if Figure 4 As shown, a first silicon oxide layer 400, a heavily doped polysilicon external base region 600 having a conductivity type opposite to that of the heavily doped silicon collector region 200, a second silicon oxide layer 800 and a silicon nitride layer 900 are sequentially deposited on the silicon-based bipolar transistor basic structure; wherein the polysilicon external base region 600 can specifically be an in-situ heavily doped polysilicon layer of the first conductivity type.

[0106] S103, forming a collector region window along the thickness direction of the silicon nitride layer, the second silicon oxide layer and the polysilicon external base region, so that the first silicon oxide layer is partially exposed;

[0107] In step S103, Figure 5 and Figure 6 As shown, the silicon nitride layer 900, the second silicon oxide layer 800 and the polysilicon outer base region 600 are etched in sequence using the photoresist 170 as a mask to expose the first silicon oxide layer 400 below, and then the photoresist 170 is removed to form a collector region window 180.

[0108] S104, etching the first silicon oxide layer below the collector region window to partially expose the heavily doped silicon collector region;

[0109] In step S104, as shown in Figure 9 the first silicon oxide layer 400 under the collector window 180 is etched to expose part of the heavily doped silicon collector 200.

[0110] S105, the exposed heavily doped silicon collector is used as a seed to grow a selective silicon epitaxial collector, so that the upper surface of the silicon epitaxial collector is flush with the upper surface of the first silicon oxide layer;

[0111] In step S105, as shown in Figure 10 the exposed heavily doped silicon collector 200 is used as a seed to grow a selective silicon epitaxial collector 500, so that the upper surface of the silicon epitaxial collector 500 is flush with the upper surface of the first silicon oxide layer 400.

[0112] S106, a third silicon oxide layer is formed on the upper surface of the silicon epitaxial collector, and the thickness of the third silicon oxide layer is equal to the thickness of the subsequent germanium-silicon epitaxial intrinsic base;

[0113] In step S106, as shown in Figure 15 a third silicon oxide layer 210 is formed on the upper surface of the silicon epitaxial collector 500, and the thickness of the third silicon oxide layer 210 is equal to the thickness of the subsequent germanium-silicon epitaxial intrinsic base 700a.

[0114] S107, a silicon nitride inner sidewall is formed on the inner edge of the collector window on the upper side of the third silicon oxide layer;

[0115] In step S107, as shown in Figure 16 a silicon nitride inner sidewall 110 is formed by first depositing silicon nitride and then anisotropically etching the silicon nitride by dry etching.

[0116] S108, the third silicon oxide layer is etched away by wet etching, and a certain over-etching is used to etch away the first silicon oxide layer at the junction with the silicon epitaxial collector and the polysilicon extrinsic base, forming a recessed structure;

[0117] In step S108, as shown in Figure 17 the third silicon oxide layer 210 in the collector window 18 is etched away by wet etching, and a certain over-etching is used to etch away part of the underlying first silicon oxide layer 400, forming a recessed structure 400a.

[0118] S109, a germanium-silicon base of the same conductivity type as the polysilicon extrinsic base is grown using the exposed silicon epitaxial collector and polysilicon extrinsic base as a seed, obtaining a germanium-silicon epitaxial intrinsic base on the upper side of the silicon epitaxial collector and a germanium-silicon connecting base connecting the polysilicon extrinsic base and the germanium-silicon epitaxial intrinsic base;

[0119] In step S109, as shown in Figure 18As shown, the exposed silicon epitaxial collector region 500 and the polysilicon outer base region 600 are used as seeds to grow a germanium-silicon base region 700 of the same conductivity type as the polysilicon outer base region 600, and simultaneously grow a germanium-silicon epitaxial inner base region 700a on the silicon epitaxial collector region 500 and a recessed germanium-silicon connecting base region 700b connecting the polysilicon outer base region 600 and the germanium-silicon epitaxial inner base region 700a.

[0120] S110, forming an L-shaped silicon oxide inner wall inside the silicon nitride inner wall;

[0121] In step S110, as shown, an L-shaped silicon oxide inner wall 120a is formed inside the silicon nitride inner wall 110. Figure 21

[0122] S111, depositing a polysilicon emitter region of the same conductivity type as the heavily doped silicon collector region;

[0123] In step S111, as shown, the deposition continues to form a polysilicon emitter region 130a of the same conductivity type as the heavily doped silicon collector region 200. Figure 23

[0124] S112, performing rapid thermal annealing to diffuse impurities in the polysilicon emitter region into the germanium-silicon epitaxial inner base region to form a single-crystal emitter region.

[0125] In step S112, as shown, the semiconductor structure formed in the above steps is subjected to rapid thermal annealing to diffuse impurities in the polysilicon emitter region 130a into the germanium-silicon epitaxial inner base region 700a to form a single-crystal emitter region 140. Figure 25

[0126] The manufacturing method of the germanium-silicon heterojunction bipolar transistor provided by the embodiments of the present application can achieve the purpose of exposing part of the sidewall of the polysilicon outer base region 600 to provide necessary space for the subsequent germanium-silicon connecting base region 700b synchronously grown with the germanium-silicon epitaxial inner base region 700a, and realize the recessed germanium-silicon connecting base region structure that can effectively improve the performance of the device, and the process steps are relatively low in process difficulty and complexity, avoiding the process step of using the bottom slit to "dig" the isotropic etching silicon nitride sidewall, which is difficult to control in the background art, thereby effectively improving the repeatability, uniformity, controllability and producibility of the related integrated circuit process production.

[0127] As shown in some embodiments, the first silicon oxide layer below the collector region window is etched to expose part of the heavily doped silicon collector region, including: Figure 29

[0128] ​​​​S1041, depositing a sacrificial silicon nitride layer, and then anisotropic dry etching the sacrificial silicon nitride layer to form a sacrificial silicon nitride inner wall at the edge of the collector region window;

[0129] In step S1041, as shown in FIG. 10A, a sacrificial silicon nitride layer (not shown in the figure) is first deposited, and then anisotropic dry etching is performed on the sacrificial silicon nitride layer to form a sacrificial silicon nitride inner wall 190 at the edge of the collector region window 180. Figure 7

[0130] S1042, using the silicon nitride layer and the sacrificial silicon nitride inner wall as a mask, anisotropic dry etching is performed on the first silicon oxide layer, so that the bottom of the first silicon oxide layer under the collector region window is left with a certain thickness of silicon oxide layer;

[0131] In step S1042, as shown in FIG. 10B, using the silicon nitride layer 900 and the sacrificial silicon nitride inner wall 190 as a mask, anisotropic dry etching is performed on the first silicon oxide layer 400, but the bottom is left with a thin silicon oxide layer 400b. Figure 8

[0132] S1043, using the silicon nitride layer and the sacrificial silicon nitride inner wall as a mask, isotropic wet etching is performed on the first silicon oxide layer, completely etching the bottom of the remaining silicon oxide layer, so that the part of the heavily doped silicon collector region is exposed, and at the same time, the inner part of the first silicon oxide layer is also etched away by a corresponding thickness.

[0133] In step S1043, as shown in FIG. 10C, using the silicon nitride layer 900 and the sacrificial silicon nitride inner wall 190 as a mask, isotropic wet etching is performed on the first silicon oxide layer 400, completely etching the bottom of the silicon oxide layer 400b, and at the same time, the inner part of the first silicon oxide layer 400 is also etched away by a corresponding thickness. Figure 9 In some embodiments, after the selective silicon epitaxial collector region growth is performed with the exposed heavily doped silicon collector region as a seed, so that the upper surface of the silicon epitaxial collector region is flush with the upper surface of the first silicon oxide layer, and before a third silicon oxide layer is formed on the upper surface of the silicon epitaxial collector region, the method further comprises: using the silicon nitride layer, the second silicon oxide layer, the polycrystalline silicon base region, and the sacrificial silicon nitride inner wall as a mask, performing selective ion implantation of the collector region on the silicon epitaxial collector region, and the conductive type of the implanted impurities is the same as that of the heavily doped silicon collector region.

[0134] Specifically, as shown in FIG. 11A, a third silicon oxide layer 1100 is formed on the upper surface of the silicon epitaxial collector region 1000.

[0135] Figure 11 ​​​As shown, with the silicon nitride layer 900, the second silicon oxide layer 800, the polysilicon outer base region 600 and the sacrificial silicon nitride inner sidewall 190 as masks, a selective ion implantation (SIC) is performed on the silicon epitaxial collector region 500, and the implanted impurity type is the same as that of the heavily doped silicon collector region 200.

[0136] As shown, in some embodiments, a third silicon oxide layer is formed on the upper surface of the silicon epitaxial collector region, and the thickness of the third silicon oxide layer is equal to the thickness of the subsequent silicon germanium epitaxial inner base region, including: Figure 30

[0137] S1061, wet etching the sacrificial silicon nitride inner sidewall;

[0138] As shown, in step S1061, the sacrificial silicon nitride inner sidewall 190 is wet etched, and at the same time, the upper surface of the silicon nitride layer 900 also loses a certain thickness of the silicon nitride layer. Figure 12

[0139] S1062, depositing a third silicon oxide layer with a thickness exceeding the total thickness of the polysilicon outer base region, the second silicon oxide layer and the silicon nitride layer;

[0140] As shown, in step S1062, a third silicon oxide layer 210 is deposited with a thickness exceeding the total thickness of the polysilicon outer base region 600, the second silicon oxide layer 800 and the remaining silicon nitride layer 900. Figure 13

[0141] S1063, planarizing and etching back the third silicon oxide layer with the silicon nitride layer as a stop layer;

[0142] As shown, in step S1063, the third silicon oxide layer 210 above the silicon nitride layer 900 is etched back by planarization with the silicon nitride layer 900 as a stop layer, and the upper surface of the remaining third silicon oxide layer 210 in the collector region window 180 is flush with the upper surface of the silicon nitride layer 900. Figure 14

[0143] S1064, continuing anisotropic dry etching of the third silicon oxide layer with the silicon nitride layer as a mask, so that the remaining thickness of the third silicon oxide layer is equal to the thickness of the subsequent silicon germanium epitaxial inner base region.

[0144] As shown, in step S1064, the third silicon oxide layer 210 is continuously anisotropically dry etched with the silicon nitride layer 900 as a mask, so that the remaining thickness of the third silicon oxide layer 210 is equal to the thickness of the subsequent silicon germanium epitaxial inner base region 700a. Figure 15 As shown, in some embodiments, a third silicon oxide layer is formed on the upper surface of the silicon epitaxial collector region, and the thickness of the third silicon oxide layer is equal to the thickness of the subsequent silicon germanium epitaxial inner base region, including:

[0145] Figure 31 ​​​​​As shown, in some embodiments, an L-shaped silicon oxide inner wall is formed inside the silicon nitride inner wall, comprising:

[0146] S1101, depositing a fourth silicon oxide layer;

[0147] In step S1101, as shown, a fourth silicon oxide layer 120 is deposited. Figure 19

[0148] S1102, depositing a polysilicon layer on the fourth silicon oxide layer;

[0149] S1103, anisotropically dry etching the polysilicon layer to form a polysilicon inner wall;

[0150] In steps S1102 to S1103, as shown, a polysilicon layer (omitted in the figure) is deposited on the fourth silicon oxide layer 120, and the polysilicon layer is anisotropically dry etched to form a polysilicon inner wall 220. Figure 20

[0151] S1104, wet etching away the exposed fourth silicon oxide layer with the polysilicon inner wall as a mask to form an L-shaped silicon oxide inner wall.

[0152] In step S1104, as shown, the exposed fourth silicon oxide layer 120 is wet etched away with the polysilicon inner wall 220 as a mask to form an L-shaped silicon oxide inner wall 120a. Figure 21 As shown, in some embodiments, a polysilicon emitter region of the same conductivity type as the heavily doped silicon collector region is deposited, comprising:

[0153] Figure 32 S1111, depositing an emitter region polysilicon layer of the same conductivity type as the heavily doped silicon collector region;

[0154] In step S1111, as shown, an emitter region polysilicon layer 130 is deposited, where the emitter region polysilicon layer 130 can be a second conductivity type impurity in-situ heavily doped polysilicon layer.

[0155] S1112, etching the emitter region polysilicon layer, the silicon nitride layer, and the second silicon oxide layer with the emitter photoresist as a mask to form a polysilicon emitter region; Figure 22 In step S1112, as shown, the emitter region polysilicon layer 130 and the underlying silicon nitride layer 900 and second silicon oxide layer 800 are then etched away in sequence with the emitter photoresist as a mask to form a polysilicon emitter region 130a.

[0156]

[0157] Figure 23

[0158] ​​​​​​S1113. Remove the emitter photoresist.

[0159] like Figure 33 As shown, in some embodiments, after removing the emitter photoresist and before performing the rapid thermal annealing, the method further includes:

[0160] S113, etching the polysilicon outer base region and the first silicon oxide layer using the base photoresist as a mask;

[0161] In step S113, Figure 24 As shown, the polysilicon outer base region 600 and the first silicon oxide layer 400 thereunder are successively etched away using the base photoresist as a mask.

[0162] S114, removing the base photoresist;

[0163] S115, depositing an outer wall dielectric layer.

[0164] In step S115, Figure 25 As shown, an outer sidewall dielectric layer 150 is deposited.

[0165] In some embodiments, after performing rapid thermal annealing to diffuse impurities in the polysilicon emitter region into the silicon germanium epitaxial inner base region to form a single crystal emitter region, the method further includes: anisotropically dry etching the outer wall dielectric layer to form an outer dielectric wall. Specifically, Figure 26 As shown, the outer sidewall dielectric layer 150 is anisotropically dry-etched to form an outer dielectric sidewall 150a.

[0166] In some embodiments, after forming the dielectric outer sidewall, the method further includes: forming a self-aligned silicide layer on the upper side of the exposed polysilicon emitter region and the polysilicon outer base region, wherein the self-aligned silicide layer is self-aligned and isolated by the dielectric outer sidewall. Figure 27 As shown, a low-resistance self-aligned metal silicide layer 160 can be formed in a self-aligned manner by a silicidation reaction between a refractory metal and the exposed single-crystal silicon and polycrystalline silicon surfaces. The self-aligned silicide layer 160 is isolated in a self-aligned manner by the dielectric outer sidewalls 150a.

[0167] Considering that the present application does not impose any restrictions on the lead-out method of the collector and substrate electrodes of the SiGe heterojunction bipolar transistor, the lead-out electrodes of the collector region and the substrate region are not demonstrated in the process flow chart of the above specific implementation scheme.

[0168] It should be noted that, in the specification, relational terms such as first and second, and the like, can be used solely to distinguish one from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a", "comprising", or "includes" does not, without more constraints, preclude the existence of additional identical elements other than the listed elements. The terms "a", "an", and "the" are used to include one or more than one, independent of any other instances or usages of "at least one" or "one or more". The terms "upper", "lower", and the like, are used only to reflect the orientation of the figures and are not intended to denote specific orientations of the apparatus or elements thereof, and thus should not be construed to limit the present application. Unless otherwise defined, the terms "install", "connect", and "couple" are to be construed in a broad sense and can mean fixedly connected, removably connected, or integrally connected, and can mean mechanically connected, electrically connected, or magnetically connected, and can mean directly connected, or connected through an intermediate medium, or connected internally within two elements. The specific meanings of the above terms in the present application can be understood by those skilled in the art according to the specific circumstances.

[0169] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the specification. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0170] The principles and implementation manners of the present application are described in the specific embodiments in the present application, and the above embodiment descriptions are only used to help understand the method of the present application and its core idea; meanwhile, for the general technical personnel in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed, and the above is not understood as the limitation of the present application.

Claims

1. A silicon-germanium heterojunction bipolar transistor, characterized in that: include: substrate; A heavily doped silicon collector region having a conductivity type opposite to that of the substrate is formed on the upper side of the substrate; A field region dielectric layer is formed on the upper side of the substrate; a first silicon oxide layer formed on the heavily doped silicon collector region and the field region dielectric layer; A silicon epitaxial collector region having the same conductivity type as the heavily doped silicon collector region, formed on an upper side of the heavily doped silicon collector region; a heavily doped polysilicon extrinsic base region having a conductivity type opposite to that of the heavily doped silicon collector region, formed on the first silicon oxide layer; a silicon germanium base region of the same conductivity type as the polysilicon extrinsic base region, comprising a silicon germanium epitaxial intrinsic base region and a silicon germanium connecting base region, wherein the silicon germanium epitaxial intrinsic base region is formed on the upper side of the silicon epitaxial collector region, and the silicon germanium connecting base region is formed on the upper side of the first silicon oxide layer and between the silicon germanium epitaxial intrinsic base region and the polysilicon extrinsic base region; a second silicon oxide layer formed between the polysilicon outer base region and the silicon nitride layer; a silicon nitride layer formed between the second silicon oxide layer and the polysilicon emitter region; A silicon nitride inner sidewall is formed on the upper side of the silicon germanium connection base region; L-shaped silicon oxide inner sidewalls formed on the upper side of the silicon germanium epitaxial base region and the inner side and upper side of the silicon nitride inner sidewalls; A heavily doped polysilicon emitter region of the same conductivity type as the heavily doped silicon collector region is formed on the upper side of the silicon nitride layer, the L-shaped silicon oxide inner sidewall, and the silicon germanium epitaxial inner base region; A heavily doped single crystal emitter region of the same conductivity type as the polysilicon emitter region is formed in the silicon germanium epitaxial base region between the L-shaped silicon oxide inner sidewalls; wherein, A recessed structure is formed in the first silicon oxide layer near the silicon epitaxial collector region and the polysilicon external base region, and the silicon germanium connection base region is formed on the upper side of the recessed structure in the first silicon oxide layer.

2. The silicon-germanium heterojunction bipolar transistor according to claim 1, wherein: Also includes: The dielectric outer wall is formed outside the first silicon oxide layer, the polysilicon outer base region, the second silicon oxide layer, the silicon nitride layer and the polysilicon emitter region.

3. The silicon-germanium heterojunction bipolar transistor according to claim 2, wherein: Also includes: A self-aligned silicide layer is formed on the polysilicon emitter region and the upper side of the polysilicon external base region and is isolated by the dielectric outer sidewall in a self-aligned manner.

4. A method for manufacturing a germanium-silicon heterojunction bipolar transistor, characterized in that: include: A silicon-based bipolar transistor basic structure is provided, wherein the silicon-based bipolar transistor basic structure includes a substrate, a heavily doped silicon collector region and a field region dielectric layer formed on the substrate and having a conductivity type opposite to that of the substrate; Depositing a first silicon oxide layer, a heavily doped polysilicon outer base region having a conductivity type opposite to that of the heavily doped silicon collector region, a second silicon oxide layer, and a silicon nitride layer in sequence on the silicon-based bipolar transistor basic structure; forming a collector region window along the thickness direction of the silicon nitride layer, the second silicon oxide layer and the polysilicon external base region, so that the first silicon oxide layer is partially exposed; Etching the first silicon oxide layer below the collector region window to partially expose the heavily doped silicon collector region; Using the exposed heavily doped silicon collector region as a seed crystal, selectively growing a silicon epitaxial collector region so that the upper surface of the silicon epitaxial collector region is flush with the upper surface of the first silicon oxide layer; forming a third silicon oxide layer on the upper surface of the silicon epitaxial collector region, so that the thickness of the third silicon oxide layer is equal to the thickness of the subsequent silicon germanium epitaxial base region; forming a silicon nitride inner sidewall at the inner edge of the collector region window on the upper side of the third silicon oxide layer; Wet etching the third silicon oxide layer, and etching the junction between the first silicon oxide layer, the silicon epitaxial collector region, and the polysilicon external base region by a certain amount of over-etching to form a recessed structure; Using the exposed silicon epitaxial collector region and the polysilicon external base region as seed crystals, a germanium-silicon base region of the same conductivity type as the polysilicon external base region is grown to obtain a germanium-silicon epitaxial inner base region on the upper side of the silicon epitaxial collector region and a germanium-silicon connecting base region connecting the polysilicon external base region and the germanium-silicon epitaxial inner base region; forming an L-shaped silicon oxide inner sidewall inside the silicon nitride inner sidewall; Depositing a polysilicon emitter region having the same conductivity type as the heavily doped silicon collector region; Rapid thermal annealing is performed to diffuse impurities in the polysilicon emitter region into the silicon germanium epitaxial inner base region to form a heavily doped single crystal emitter region with the same conductivity type as the polysilicon emitter region.

5. The method according to claim 4, characterized in that Etching the first silicon oxide layer below the collector region window to partially expose the heavily doped silicon collector region, comprising: Firstly, a sacrificial silicon nitride layer is deposited, and then the sacrificial silicon nitride layer is anisotropically dry-etched to form a sacrificial silicon nitride inner sidewall at the edge of the collector region window; Anisotropically dry-etching the first silicon oxide layer using the silicon nitride layer and the sacrificial silicon nitride inner sidewall as a mask, so that a certain thickness of silicon oxide layer remains at the bottom of the first silicon oxide layer below the collector region window; The first silicon oxide layer is isotropically wet-etched using the silicon nitride layer and the sacrificial silicon nitride inner sidewall as a mask to completely etch away the remaining silicon oxide layer at the bottom, exposing a portion of the heavily doped silicon collector region. Simultaneously, the inner side of the first silicon oxide layer is also etched away by a corresponding thickness.

6. The method according to claim 5, characterized in that After growing a silicon epitaxial collector region using the exposed heavily doped silicon collector region as a seed crystal so that the upper surface of the silicon epitaxial collector region is flush with the upper surface of the first silicon oxide layer, and before forming a third silicon oxide layer on the upper surface of the silicon epitaxial collector region, the method further includes: Using the silicon nitride layer, the second silicon oxide layer, the polysilicon outer base region and the sacrificial silicon nitride inner sidewall as a mask, the silicon epitaxial collector region is selectively implanted with collector region ions, and the conductivity type of the implanted impurities is the same as that of the heavily doped silicon collector region.

7. The method according to claim 5, characterized in that Forming a third silicon oxide layer on the upper surface of the silicon epitaxial collector region so that the thickness of the third silicon oxide layer is equal to the thickness of the subsequent silicon germanium epitaxial base region comprises: Wet etching the inner sidewall of the sacrificial silicon nitride; Depositing a third silicon oxide layer having a thickness exceeding the total thickness of the polysilicon external base region, the second silicon oxide layer and the silicon nitride layer; Using the silicon nitride layer as a stop layer, planarizing and etching back the third silicon oxide layer; The third silicon oxide layer is continuously anisotropically dry-etched using the silicon nitride layer as a mask, so that the remaining thickness of the third silicon oxide layer is equal to the thickness of the subsequent silicon germanium epitaxial base region.

8. The method according to claim 7, characterized in that An L-shaped silicon oxide inner sidewall is formed inside the silicon nitride inner sidewall, comprising: depositing a fourth silicon oxide layer; depositing a polysilicon layer on the fourth silicon oxide layer; Anisotropically dry etching the polysilicon layer to form polysilicon inner sidewalls; The exposed fourth silicon oxide layer is wet-etched using the polysilicon inner sidewall as a mask to form an L-shaped silicon oxide inner sidewall.

9. The method according to claim 8, characterized in that Deposition to form a polysilicon emitter region of the same conductivity type as the heavily doped silicon collector region, including: Depositing a polysilicon layer in the emitter region having the same conductivity type as that of the heavily doped silicon collector region; Using the emitter photoresist as a mask, etching the emitter region polysilicon layer, silicon nitride layer and second silicon oxide layer to form a polysilicon emitter region; Remove the emitter photoresist.

10. The method according to claim 9, characterized in that After removing the emitter photoresist and before performing the rapid thermal annealing, the method further includes: etching the polysilicon outer base region and the first silicon oxide layer using the base photoresist as a mask; Remove the base photoresist; Depositing an outer wall dielectric layer; After performing rapid thermal annealing to diffuse impurities in the polysilicon emitter region into the silicon germanium epitaxial inner base region to form a single crystal emitter region, the method further includes: The outer sidewall dielectric layer is anisotropically dry-etched to form an outer dielectric sidewall.

11. The method according to claim 10, characterized in that After forming the outer dielectric wall, the method further includes: A self-aligned silicide layer is formed on the upper sides of the exposed polysilicon emitter region and the polysilicon external base region. The self-aligned silicide layer is isolated by the dielectric outer sidewall in a self-aligned manner.

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