Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a first semiconductor layer, a second semiconductor layer, a first insulating layer, a gate dielectric layer and a gate. The first semiconductor layer extends in a first direction, and the second semiconductor layer is located on the first semiconductor layer and extends in a second direction perpendicular to the first direction. The first semiconductor layer and the second semiconductor layer are integrally formed. The first insulating layer is arranged on the first semiconductor layer. The gate dielectric layer is arranged on the sidewall of the second semiconductor layer and partially arranged on the first insulating layer. The gate is arranged on the gate dielectric layer. In this way, the first semiconductor layer and the second semiconductor layer can be synchronously formed and respectively serve as a source and a channel structure of the semiconductor device, so that the structural stability of the semiconductor device is improved and the operation performance of the semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having a vertical channel structure and a method for manufacturing the same. Background Technology

[0002] Semiconductor integrated circuit technology continues to advance over time, with each new generation of manufacturing processes producing products that are smaller and more complex in circuit design than the previous generation. The number and density of functional components on each wafer area must continuously increase due to product innovation demands, which in turn necessitates smaller and smaller geometric dimensions for each component. Because traditional planar metal-oxide-semiconductor (MOS) transistor manufacturing processes are difficult to miniaturize continuously, the industry has proposed replacing traditional planar transistor components with 3D or non-planar transistor components, thereby reducing the geometric dimensions of transistor components and / or improving the operational performance of transistor devices. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device in which a first semiconductor layer and a second semiconductor layer are integrally formed on a first direction and a second direction that are perpendicular to each other, respectively, so that the first semiconductor layer and the second semiconductor layer can serve as the source and channel structure of the semiconductor device, respectively, thereby improving the structural stability of the semiconductor device and enhancing its operational performance.

[0004] The purpose of this invention is to provide a method for fabricating a semiconductor device, in which a first semiconductor layer and a second semiconductor layer are simultaneously and integrally formed in a first direction and a second direction that are perpendicular to each other, serving as the source and channel structure of the semiconductor device, respectively, and a gate is subsequently formed on the channel structure. In this way, a semiconductor device with a robust structure and optimized operational performance can be formed through a post-gate process while simplifying the manufacturing process.

[0005] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including a substrate, a first semiconductor layer, a second semiconductor layer, a first insulating layer, a gate dielectric layer, and a gate. The first semiconductor layer extends in a first direction, and the second semiconductor layer is located on the first semiconductor layer and extends in a second direction, the first direction being perpendicular to the second direction. The first semiconductor layer and the second semiconductor layer are integrally formed. The first insulating layer is disposed on the first semiconductor layer. The gate dielectric layer is disposed on a sidewall of the second semiconductor layer and partially located on the first insulating layer. The gate is disposed on the gate dielectric layer.

[0006] To achieve the above objectives, one embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: providing a substrate, forming a first semiconductor layer extending in a first direction on the substrate; forming a second semiconductor layer extending in a second direction on the first semiconductor layer, wherein the first direction is perpendicular to the second direction; wherein the first semiconductor layer and the second semiconductor layer are integrally formed; forming a first insulating layer on the first semiconductor layer; forming a gate dielectric layer on the first insulating layer, located on the sidewall of the second semiconductor layer; and forming a gate on the gate dielectric layer.

[0007] The semiconductor device and its fabrication method of the present invention pre-form a channel structure before fabricating the gate, and fabricate the source and the channel structure of the semiconductor device together in the same process, such that the channel structure has a columnar cross-section extending in the vertical direction and is integrally formed with the source and comprises the same material. In this way, the fabrication of the semiconductor device can be effectively simplified, resulting in a semiconductor device with a simplified structure and optimized operational performance, achieving effects similar to dual-gate or gate-all-around devices. Attached Figure Description

[0008] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to the first embodiment of the present invention;

[0010] Figure 2 This is a top view of a semiconductor device after the formation of the first and second semiconductor layers.

[0011] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device after the formation of the first and second semiconductor layers.

[0012] Figure 4 A top view of a semiconductor device after the first insulating material layer has been formed.

[0013] Figure 5 This is a schematic cross-sectional view of a semiconductor device after the formation of an insulating material layer.

[0014] Figure 6 This is a schematic cross-sectional view of a semiconductor device after the metal material layer has been formed.

[0015] Figure 7 This is a top view of a semiconductor device after the gate has been formed.

[0016] Figure 8 This is a schematic cross-sectional view of a semiconductor device after the gate has been formed.

[0017] Figure 9 This is a top view of a semiconductor device after the formation of the second insulating layer.

[0018] Figure 10 This is a schematic cross-sectional view of a semiconductor device after the formation of the second insulating layer.

[0019] Figure 11 This is a top view of a semiconductor device after the formation of a conductive material layer.

[0020] Figure 12 This is a schematic cross-sectional view of a semiconductor device after the formation of a conductive material layer.

[0021] Figure 13 This is another cross-sectional schematic diagram of a semiconductor device after the formation of a conductive material layer;

[0022] Figure 14 This is a top view of a semiconductor device after the formation of the second insulating layer.

[0023] Figure 15 This is a schematic cross-sectional view of a semiconductor device after the formation of the second insulating layer.

[0024] Figure 16 This is a schematic cross-sectional view of a semiconductor device after the drain electrode has been formed.

[0025] Explanation of reference numerals in the attached figures:

[0026] 10, 20 Semiconductor devices

[0027] 100 substrate

[0028] 102 Conductive Structure

[0029] 104, 108, 118, 124 metal barrier layers

[0030] 106, 120, 126 conductive layers

[0031] 110 First Semiconductor Layer

[0032] 112 Second Semiconductor Layer

[0033] 113 Insulation layer

[0034] 114 First Insulation Layer

[0035] 114a First insulating material layer

[0036] 116, 216 gate dielectric layer

[0037] 116a Gate dielectric material layer

[0038] 118a Metal barrier material layer

[0039] 120a conductive material layer

[0040] 122 Second Insulation Layer

[0041] 128 Insulation Layer

[0042] 216a Gate Dielectric Material Layer

[0043] 218a Metal barrier material layer

[0044] 218 Metal Barrier Layer

[0045] 220a conductive material layer

[0046] 220 conductive layer

[0047] CP contact pad

[0048] CW metal wire

[0049] D1 First Direction

[0050] D2 Second Direction

[0051] D3 third direction

[0052] GE gate

[0053] IS insulation gap

[0054] OP1, OP2, OP3 perforations

[0055] R1 Depression

[0056] S1 First Surface

[0057] S2 Second Surface

[0058] SE Source

[0059] SS channel structure Detailed Implementation

[0060] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, along with accompanying drawings, to explain in detail the technical solutions and desired effects of this invention. Those skilled in the art can, without departing from the spirit of this invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0061] Please refer to Figure 1 As shown, Figure 1 This is a schematic cross-sectional view of the semiconductor device 10 according to the first embodiment of the present invention. Figure 1 As shown, the semiconductor device 10 includes a substrate 100, a first semiconductor layer 110, a second semiconductor layer 112, a first insulating layer 114, a gate dielectric layer 116, and a gate GE. The substrate 100 may include, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials. Those skilled in the art will readily understand that various required active and / or passive components may be further formed on or within the substrate 100 according to actual device requirements, such as... Figure 1 The conductive structure 102 shown is not limited thereto.

[0062] A first semiconductor layer 110 and a second semiconductor layer 112 are disposed on a substrate 100 and extend in mutually perpendicular first directions D1 and second directions D2, respectively. A first insulating layer 114 is disposed on the top surface of the first semiconductor layer 110, and a gate dielectric layer 116 is disposed on the sidewall of the second semiconductor layer 112 and partially located on the first insulating layer 114. In one embodiment, the first insulating layer 114 and the gate dielectric layer 116 may each comprise different dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable materials, but are not limited thereto. The gate electrode GE is also disposed on the sidewall of the second semiconductor layer 112 and located on the gate dielectric layer 116. It should be noted that the second semiconductor layer 112 is located on the first semiconductor layer 110 and is integrally formed with the first semiconductor layer 110. In one embodiment, the first semiconductor layer 110 and the second semiconductor layer 112 both comprise semiconductor materials, such as doped polycrystalline silicon, doped amorphous silicon, indium zinc oxide (IZO), aluminum zinc oxide (AZO), or indium gallium zinc oxide (IGZO), but are not limited thereto. In this configuration, the first semiconductor layer 110 and the second semiconductor layer 112 can respectively serve as the source SE and channel structure SS of the semiconductor device 10, such that the channel structure SS exhibits a columnar cross-section extending along the second direction D2, and simultaneously physically contacts the lower source SE and the upper contact pad CP. Thus, when a threshold voltage is applied to the gate GE, the channel structure SS can electrically connect the source SE and the contact pad CP as a vertical channel structure, and the gate dielectric layer 116, the gate GE, the channel structure SS, and the source SE together form a three-dimensional transistor assembly, achieving an effect similar to a dual-gate transistor. Therefore, by setting an integrally formed first semiconductor layer 110 and a second semiconductor layer 112 made of the same material, the component structure of the semiconductor device 10 can be effectively simplified and its stability improved, thereby improving the operational performance of the semiconductor device 10.

[0063] In detail, the gate dielectric layer 116 extends, for example, partially in the first direction D1 and partially in the second direction D2, and has the following characteristics: Figure 1The L-shaped cross-section is shown. The top surface of the gate dielectric layer 116 is coplanar with the top surface of the gate GE. The side surface of the gate dielectric layer 116 extending in the second direction D2 physically contacts the sidewall of the second semiconductor layer 112, while the bottom surface of the gate dielectric layer 116 extending in the first direction D1 physically contacts the top surface of the first insulating layer 114. The first insulating layer 114 is located below the gate dielectric layer 116. The bottom surface of the first insulating layer 114 physically contacts the top surface of the first semiconductor layer 110, while the side surface of the first insulating layer 114 is flush with the side surface of the gate dielectric layer 116 and physically contacts part of the sidewall of the second semiconductor layer 112. The first insulating layer 114 also has a recess R1 that is recessed downwards from the top surface, wherein one side of the recess R1, for example, is flush with the sidewall of the gate GE. Figure 1 As shown. On the other hand, the gate GE is disposed on the gate dielectric layer 116 and simultaneously physically contacts the first surface S1 of the gate dielectric layer 116 in the first direction D1 and the second surface S2 in the second direction D2.

[0064] For example Figure 1 As shown, the semiconductor device 10 further includes a metal wire CW, a second insulating layer 122, and an insulating layer 128 disposed on the substrate 100. The metal wire CW is disposed between the first semiconductor layer 110 and the substrate 100, and simultaneously physically contacts the first semiconductor layer 110 and the conductive structure 102 disposed within the substrate 100. The metal wire CW, the gate GE, and the contact pad CP each comprise a composite layer structure, for example. For instance, the metal wire CW includes, for example, a metal barrier layer 104, a conductive layer 106, and a metal barrier layer 108 sequentially stacked in the second direction D2; the gate GE includes, for example, a metal barrier layer 118 and a conductive layer 120 sequentially stacked in the first direction D1; and the contact pad CP includes a metal barrier layer 124 and a conductive layer 126 sequentially stacked in the second direction D2. In one embodiment, the metal barrier layers 104, 118, and 124 all include the same metal barrier material, such as titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or other suitable metal barrier materials, while the conductive layers 106, 120, and 126 all include the same metal material, such as copper, aluminum, tungsten, or other suitable low-resistivity metal materials, but are not limited thereto.

[0065] The second insulating layer 122 is disposed on the first insulating layer 114, and the insulating layer 128 is further disposed on the second insulating layer 122. The contact pad CP is disposed within the insulating layer 128 to physically contact the top surface of the second semiconductor layer 112. It should be noted that in this embodiment, a portion of the second insulating layer 122 also covers the gate dielectric layer 116 and the gate GE, and is sandwiched between the contact pad CP and the gate GE. In one embodiment, the second insulating layer 122 and the insulating layer 128 may comprise different dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable materials. The second insulating layer 122 preferably comprises the same dielectric material as the first insulating layer 114, but is not limited thereto. Thus, the sequentially disposed first insulating layer 114 and second insulating layer 122 can together form the insulating space IS of the semiconductor device 10, surrounding the gate GE to effectively isolate the gate GE from its adjacent components, optimizing the structure and function of the gate GE.

[0066] In other words, by using an integrally formed first semiconductor layer 110 and a second semiconductor layer 112 as the source (SE) and channel structure (SS) respectively, the semiconductor device 10 in this embodiment can be assembled into a three-dimensional transistor assembly with a simplified and more stable component structure. Thus, the channel structure (SS) of the semiconductor device 10 achieves a similar effect to a dual-gate structure and possesses optimized operational performance.

[0067] To enable those skilled in the art to easily understand and implement the semiconductor device of the present invention, the following will further describe the manufacturing method of the semiconductor device 10 of the present invention.

[0068] Please see Figures 2 to 11 The diagram shown is a schematic representation of a method for fabricating a semiconductor device 10 according to an embodiment of the present invention. First, as... Figure 2 and Figure 3 As shown, a film-forming process, such as chemical vapor deposition, physical vapor deposition, or other suitable methods, is performed to sequentially form a metal barrier layer 104, a conductive layer 106, a metal barrier layer 108, and a semiconductor material layer (not shown) on a substrate 100. The metal barrier layer 104, conductive layer 106, and metal barrier layer 108 together form a metal wire CW, which physically contacts the conductive structure 102 within the substrate 100 through the metal barrier layer 104. The semiconductor material layer extends, for example, in a first direction D1, and is alternately disposed on the metal barrier layer 108 with an insulating layer 113 in a third direction D3 perpendicular to the first direction D1. In one embodiment, the semiconductor material layer includes, for example, doped polycrystalline silicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide, while the insulating layer 113 includes, for example, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, but is not limited thereto.

[0069] Next, a patterning process is performed using a mask (not shown) to form multiple channels (not shown) on the third-direction D3 that simultaneously penetrate the semiconductor material layer and the insulating layer 113, while within the semiconductor material layer, a pattern is formed as shown in the diagram. Figure 2 and Figure 3 The multiple perforations OP1 are shown. Then, the mask is removed. In detail, as... Figure 3 As shown, the semiconductor material layer penetrated by the through-hole OP1 is such that the semiconductor material layer not penetrated by the through-hole OP1 is completely covered on the metal barrier layer 108, forming the first semiconductor layer 110. The semiconductor material layer penetrated by the through-hole OP1 is located on the first semiconductor layer 110, forming the second semiconductor layer 112 extending in the second direction D2. In this way, the first semiconductor layer 110 and the second semiconductor layer 112 are integrally formed and include the same material, and in subsequent processes, they serve as the source SE and channel structure SS of the semiconductor device 10, respectively.

[0070] like Figure 4 and Figure 5 As shown, a deposition and etch-back fabrication process is performed on the substrate 100 to form a first insulating material layer 114a in the trench, such that the first insulating material layer 114a is formed at the bottom of the via OP1 and partially fills the via OP1.

[0071] like Figure 6 As shown, a film-forming process is performed again, such as by chemical vapor deposition, physical vapor deposition, or other suitable methods, to sequentially form a gate dielectric material layer 116a, a metal barrier material layer 118a, and a conductive material layer 120a, partially formed within and partially outside the through-hole OP1. The conductive material layer 120a fills the through-hole OP1 and partially covers the top surface of the second semiconductor layer 112. In one embodiment, the gate dielectric material layer 116a includes, for example, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, preferably a material different from the first insulating material layer 114a, but is not limited thereto.

[0072] like Figure 7 and Figure 8As shown, a planarization process, such as chemical mechanical polishing or other suitable methods, is first performed to remove the conductive material layer 120a, the metal barrier material layer 118a, and the gate dielectric material layer 116a formed outside the via OP1. Then, a dry etching process is performed using another mask (not shown) to partially remove the conductive material layer 120a, the metal barrier material layer 118a, and the gate dielectric material layer 116a again, and to remove part of the first insulating material layer 114a below the gate dielectric material layer 116a, forming a via OP2 with a bottom surface lower than the first insulating material layer 114a. Furthermore, during the formation of the via OP2, an L-shaped gate dielectric layer 116, an L-shaped metal barrier layer 118, and a conductive layer 120 located on both sides of the via OP2 are simultaneously formed, and a first insulating layer 114 is formed below the via OP2. Thus, the metal barrier layer 118 and the conductive layer 120 together form the gate GE of the semiconductor device 10, and are located on the sidewall of the second semiconductor layer 112 together with the gate dielectric layer 116. Then, the other mask is completely removed. It should be noted that since the aforementioned metal barrier material layer 118a and gate dielectric material layer 116a are integrally disposed in the channel, the formed gate GE, as Figure 7 The top view shown presents a long strip shape and allows simultaneous contact with multiple channel structures SS.

[0073] like Figure 9 and Figure 10 As shown, a deposition and etch-back process is performed again to form a second insulating layer 122 filling the via OP2. In one embodiment, the second insulating layer 122 preferably includes a dielectric material similar to the first insulating layer 114, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., but is not limited thereto. Thus, the first insulating layer 114 and the second insulating layer 122 sequentially formed between the gates GE can together form an insulating space IS, effectively isolating the gate GE from its adjacent components and optimizing the structure and function of the gate GE. Then, a contact pad CP and an insulating layer 128 are formed on the second semiconductor layer 112, such that the bottom surface of the contact pad CP physically contacts the top surface of the second semiconductor layer 112. Under this operation, a structure is formed as shown in the figure. Figure 1 The semiconductor device 10 shown completes the fabrication of the semiconductor device 10 in this embodiment.

[0074] According to the fabrication method of this embodiment, a first semiconductor layer 110 extending in the first direction D1 and a second semiconductor layer 112 extending in the second direction D2 are simultaneously formed through a patterning process of semiconductor material layers. These serve as the source SE and channel structure SS of the semiconductor device 10, respectively. The channel structure SS exhibits a columnar cross-section extending along the second direction D2, and simultaneously makes physical contact between the lower source SE and the upper contact pad CP. In this way, the source SE and channel structure SS of the semiconductor device 10 can be completed in the same process, having an integral structure and the same semiconductor material. The gate dielectric layer 116, the gate GE, the channel structure SS, and the source SE together form a three-dimensional transistor assembly, achieving an effect similar to a dual-gate transistor. Therefore, the fabrication of the semiconductor device 10 can be effectively simplified, resulting in a semiconductor device 10 with a simplified structure and optimized operational performance.

[0075] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device and its fabrication method of this invention may have other forms or be achieved by other means, and are not limited to the foregoing. The following will further describe other embodiments or variations of the semiconductor device and its fabrication method of this invention. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0076] Please refer to Figures 11 to 16 The diagram shown illustrates a method for fabricating a semiconductor device 20 according to a second embodiment of the present invention. The structure and fabrication method of the semiconductor device 20 in this embodiment are generally the same as those of the semiconductor device 10 in the first embodiment described above; the similarities will not be repeated here. The main difference between the fabrication method of the semiconductor device 20 in this embodiment and that in the first embodiment is the formation of a gate dielectric layer 216 with its top surface higher than the gate GE.

[0077] In detail, such as Figures 11 to 13 As shown, in the formation of the aforementioned embodiments Figure 6Before the conductive material layer and the metal barrier material layer shown, the insulating layer 113 located on both sides of the second semiconductor layer 112 on the third-direction D3 is further partially removed. Then, a film formation process is performed, such as by chemical vapor deposition, physical vapor deposition, or other suitable methods, to form a gate dielectric material layer 216a, a metal barrier material layer (not shown), and a conductive material layer (not shown) sequentially surrounding the second semiconductor layer 112. The gate dielectric material layer 216a, the metal barrier material layer, and the conductive material layer are partially formed within and partially outside the via OP1. A dry etching process is performed to partially remove the conductive material layer and the metal barrier layer, and a metal barrier material layer 218a and a conductive material layer 220 are formed on the gate dielectric material layer 216a, located only within the via OP1. Then, with the aid of a mask (not shown), the conductive material layer 220a, the metal barrier material layer 218a, the gate dielectric material layer 216a, and the portion of the first insulating material layer 114a below the gate dielectric material layer 216a are partially removed again to form the via OP3, and then the mask is completely removed. Thus, when the via OP3 is formed, the metal barrier layer 118 and the conductive layer 120 located on the gate dielectric material layer 216a are simultaneously formed, and the metal barrier layer 118 and the conductive layer 120 together form the gate GE of the semiconductor device 10.

[0078] like Figures 14 to 15As shown, the conductive material layer 220a and the metal barrier material layer 218a are partially removed again until the via OP1 is not completely filled. This simultaneously forms the metal barrier layer 218 and the conductive layer 220 on the gate dielectric material layer 216a, together forming the gate GE of the semiconductor device 20. It should be noted that the gate GE is simultaneously disposed on both opposite sides of the second semiconductor layer 112 in the first direction D1 and the third direction D3, allowing the gate GE to be formed around a portion of the sidewalls of the second semiconductor layer 112, achieving a gate-all-around effect. Then, a film fabrication process is performed, such as chemical vapor deposition, physical vapor deposition, or other suitable methods, to form a second insulating material layer (not shown) on the gate dielectric material layer 216a, such that the second insulating material layer is partially formed within and outside the vias OP3 and OP1. Next, a planarization process, such as chemical mechanical polishing or other suitable methods, is performed to remove the second insulating material layer and gate dielectric material layer 216a formed outside the vias OP3 and OP1, while simultaneously forming the second insulating layer 122 and the gate dielectric layer 216. Specifically, the second insulating layer 122 is also formed on the first insulating layer 114 and is located together with the first insulating layer 114 between the gates GE, forming an insulating space IS to isolate the gate GE from its adjacent components and optimize the structure and function of the gate GE. The gate dielectric layer 216 is formed between the gate GE and the second semiconductor layer 112, and the top surface of the gate dielectric layer 216 is coplanar with the top surface of the second insulating layer 122 and the top surface of the second semiconductor layer 112.

[0079] Then, as Figure 16 As shown, a contact pad CP and an insulating layer 128 are formed on the second semiconductor layer 112, such that the bottom surface of the contact pad CP physically contacts the top surface of the second semiconductor layer 112. This operation completes the fabrication of the semiconductor device 20 in this embodiment. The structure of the semiconductor device 20 in this embodiment is generally the same as that of the semiconductor device 10 in the first embodiment described above, also including a substrate 100, a first semiconductor layer 110, a second semiconductor layer 112, a first insulating layer 114, and a gate GE. The main difference between the semiconductor device 20 in this embodiment and the first embodiment is that the bottom surface of the contact pad CP also physically contacts the top surface of the gate dielectric layer 216. That is, in this embodiment, the sidewall portion of the second semiconductor layer 112 in the second direction is covered by the first insulating layer 114, and partially covered by the gate dielectric layer 216. Under this configuration, even if the fabrication of the channel structure SS takes precedence over the fabrication of other components such as the gate GE, the channel structure SS fabricated first will not be damaged in subsequent fabrication processes.

[0080] According to the semiconductor device 20 of this embodiment, the first semiconductor layer 110 and the second semiconductor layer 112, which are integrally formed, serve as the source (SE) and the channel structure (SS), respectively. This allows the source (SE) and the channel structure (SS) of the semiconductor device 20 to be completed in the same process, achieving a simplified process. Furthermore, the gate dielectric layer 116, the gate (GE), the channel structure (SS), and the source (SE) of the semiconductor device 20 can also jointly form a three-dimensional transistor assembly, achieving a similar effect to an all-gate transistor. Thus, the semiconductor device 20 of this embodiment achieves more optimized operational performance while maintaining a simplified and more stable assembly structure.

[0081] In summary, the semiconductor device and its fabrication method of the present invention form a channel structure before fabricating the gate, and fabricate the source and channel structure of the semiconductor device in the same process, so that the channel structure has a columnar cross-section extending in the vertical direction and is integrally formed with the source and includes the same material. In this way, the fabrication of the semiconductor device can be effectively simplified, resulting in a semiconductor device with a simplified structure and more optimized operation performance, achieving effects similar to dual-gate or all-gate devices.

[0082] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A first semiconductor layer extends in a first direction; The second semiconductor layer is located on the first semiconductor layer and extends in a second direction, the first direction being perpendicular to the second direction, and the first semiconductor layer and the second semiconductor layer are integrally formed. A first insulating layer is disposed on the first semiconductor layer; A gate dielectric layer is disposed on the sidewall of the second semiconductor layer and partially located on the first insulating layer; as well as A gate is disposed on the gate dielectric layer; A contact pad is disposed on the second semiconductor layer, and the bottom surface of the contact pad contacts the top surface of the second semiconductor layer; A second insulating layer is disposed on the first insulating layer and physically contacts the gate dielectric layer and the gate. It also includes a metal wire disposed below the first semiconductor layer, wherein the metal wire, the gate, and the contact pad each comprise: The conductive layer, the metal wire, the gate, and the conductive layer of the contact pad all comprise the same metallic material; and A metal barrier layer is disposed below the conductive layer, and the metal barrier layer of the metal wire, the gate and the contact pad comprises the same metal barrier material; The first semiconductor layer and the second semiconductor layer comprise the same semiconductor material.

2. The semiconductor device according to claim 1, characterized in that, The bottom surface of the first insulating layer contacts the top surface of the first semiconductor layer.

3. The semiconductor device according to claim 1, characterized in that, The side of the first insulating layer contacts the sidewall of the second semiconductor layer.

4. The semiconductor device according to claim 1, characterized in that, The bottom surface of the gate dielectric layer contacts the top surface of the first insulating layer, and the side surface of the gate dielectric layer contacts the side surface of the second semiconductor layer.

5. The semiconductor device according to claim 1, characterized in that, The gate contact and the gate dielectric layer are respectively located on the first surface and the second surface in the first direction and the second direction.

6. The semiconductor device according to claim 1, characterized in that, The top surface of the gate dielectric layer contacts the bottom surface of the contact pad.

7. A method for manufacturing a semiconductor device, used to manufacture the semiconductor device according to any one of claims 1-6, characterized in that, include: Provide substrate; A first semiconductor layer extending in a first direction is formed on the substrate; A second semiconductor layer extending in a second direction is formed on the first semiconductor layer, the first direction being perpendicular to the second direction, and the first semiconductor layer and the second semiconductor layer are integrally formed. A first insulating layer is formed on the first semiconductor layer; A gate dielectric layer is formed on the first insulating layer and located on the sidewall of the second semiconductor layer; as well as A gate is formed on the gate dielectric layer; The formation of the first semiconductor layer and the second semiconductor layer further includes: Forming a semiconductor material layer; Multiple through-holes are formed partially through the semiconductor material layer to simultaneously form the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are simultaneously formed and comprise the same semiconductor material; and A first insulating material layer is formed within the perforation, partially filling the perforation; forming the gate and gate dielectric layer further includes: A gate dielectric material layer, a metal barrier material layer, and a conductive material layer are sequentially formed within the perforation, conformally covering the second semiconductor layer and the first insulating material layer; Partial removal of the conductive material layer, the metal barrier material layer, and the gate dielectric material layer to form a conductive layer, a metal barrier layer, and a gate dielectric layer, wherein the conductive layer and the metal barrier layer together form the gate; and Partial removal of the first insulating material layer to form the first insulating layer, wherein the top surface of the first insulating layer is lower than the bottom surface of the gate dielectric layer; or... The formation of the gate and the gate dielectric layer further includes: A gate dielectric material layer, a metal barrier material layer, and a conductive material layer are sequentially formed within the perforation, conformally covering at least one channel structure and the first insulating material layer; Partial removal of the conductive material layer and the metal barrier material layer forms a conductive layer and a metal barrier layer, which together form the gate. A second insulating material layer is formed on the gate dielectric material layer; and Partial removal of the second insulating material layer and the gate dielectric material layer, forming a second insulating layer and the gate dielectric layer on the first insulating layer, wherein the second insulating layer physically contacts the gate dielectric layer and the gate.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, Also includes: A second insulating layer is formed on the first insulating layer, wherein the second insulating layer physically contacts the gate dielectric layer, the gate, and the second semiconductor layer.

9. The method for fabricating a semiconductor device according to claim 7, characterized in that, The top surface of the gate dielectric layer is coplanar with the top surface of the gate.

10. The method for fabricating a semiconductor device according to claim 7, characterized in that, The top surface of the gate dielectric layer is coplanar with the top surface of the second semiconductor layer.

11. The method for fabricating a semiconductor device according to claim 7, characterized in that, Also includes: A contact pad is formed on the second semiconductor layer, the bottom surface of the contact pad contacting the top surface of the second semiconductor layer, and the top surface of the gate dielectric layer contacting the bottom surface of the contact pad.

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